1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/datadir.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "hw/sysbus.h" 37 #include "hw/arm/boot.h" 38 #include "hw/arm/primecell.h" 39 #include "hw/arm/virt.h" 40 #include "hw/block/flash.h" 41 #include "hw/vfio/vfio-calxeda-xgmac.h" 42 #include "hw/vfio/vfio-amd-xgbe.h" 43 #include "hw/display/ramfb.h" 44 #include "net/net.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/numa.h" 47 #include "sysemu/runstate.h" 48 #include "sysemu/tpm.h" 49 #include "sysemu/tcg.h" 50 #include "sysemu/kvm.h" 51 #include "sysemu/hvf.h" 52 #include "sysemu/qtest.h" 53 #include "hw/loader.h" 54 #include "qapi/error.h" 55 #include "qemu/bitops.h" 56 #include "qemu/error-report.h" 57 #include "qemu/module.h" 58 #include "hw/pci-host/gpex.h" 59 #include "hw/virtio/virtio-pci.h" 60 #include "hw/core/sysbus-fdt.h" 61 #include "hw/platform-bus.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/arm/fdt.h" 64 #include "hw/intc/arm_gic.h" 65 #include "hw/intc/arm_gicv3_common.h" 66 #include "hw/intc/arm_gicv3_its_common.h" 67 #include "hw/irq.h" 68 #include "kvm_arm.h" 69 #include "hw/firmware/smbios.h" 70 #include "qapi/visitor.h" 71 #include "qapi/qapi-visit-common.h" 72 #include "standard-headers/linux/input.h" 73 #include "hw/arm/smmuv3.h" 74 #include "hw/acpi/acpi.h" 75 #include "target/arm/internals.h" 76 #include "hw/mem/pc-dimm.h" 77 #include "hw/mem/nvdimm.h" 78 #include "hw/acpi/generic_event_device.h" 79 #include "hw/virtio/virtio-md-pci.h" 80 #include "hw/virtio/virtio-iommu.h" 81 #include "hw/char/pl011.h" 82 #include "qemu/guest-random.h" 83 84 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 85 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 86 void *data) \ 87 { \ 88 MachineClass *mc = MACHINE_CLASS(oc); \ 89 virt_machine_##major##_##minor##_options(mc); \ 90 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 91 if (latest) { \ 92 mc->alias = "virt"; \ 93 } \ 94 } \ 95 static const TypeInfo machvirt_##major##_##minor##_info = { \ 96 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 97 .parent = TYPE_VIRT_MACHINE, \ 98 .class_init = virt_##major##_##minor##_class_init, \ 99 }; \ 100 static void machvirt_machine_##major##_##minor##_init(void) \ 101 { \ 102 type_register_static(&machvirt_##major##_##minor##_info); \ 103 } \ 104 type_init(machvirt_machine_##major##_##minor##_init); 105 106 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 107 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 108 #define DEFINE_VIRT_MACHINE(major, minor) \ 109 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 110 111 112 /* Number of external interrupt lines to configure the GIC with */ 113 #define NUM_IRQS 256 114 115 #define PLATFORM_BUS_NUM_IRQS 64 116 117 /* Legacy RAM limit in GB (< version 4.0) */ 118 #define LEGACY_RAMLIMIT_GB 255 119 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 120 121 /* Addresses and sizes of our components. 122 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 123 * 128MB..256MB is used for miscellaneous device I/O. 124 * 256MB..1GB is reserved for possible future PCI support (ie where the 125 * PCI memory window will go if we add a PCI host controller). 126 * 1GB and up is RAM (which may happily spill over into the 127 * high memory region beyond 4GB). 128 * This represents a compromise between how much RAM can be given to 129 * a 32 bit VM and leaving space for expansion and in particular for PCI. 130 * Note that devices should generally be placed at multiples of 0x10000, 131 * to accommodate guests using 64K pages. 132 */ 133 static const MemMapEntry base_memmap[] = { 134 /* Space up to 0x8000000 is reserved for a boot ROM */ 135 [VIRT_FLASH] = { 0, 0x08000000 }, 136 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 137 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 138 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 139 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 140 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 141 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 142 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 143 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 144 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 145 /* This redistributor space allows up to 2*64kB*123 CPUs */ 146 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 147 [VIRT_UART] = { 0x09000000, 0x00001000 }, 148 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 149 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 150 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 151 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 152 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 153 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 154 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 155 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 156 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, 157 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, 158 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 159 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 160 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 161 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 162 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 163 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 164 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 165 /* Actual RAM size depends on initial RAM and device memory settings */ 166 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 167 }; 168 169 /* 170 * Highmem IO Regions: This memory map is floating, located after the RAM. 171 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 172 * top of the RAM, so that its base get the same alignment as the size, 173 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 174 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 175 * Note the extended_memmap is sized so that it eventually also includes the 176 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 177 * index of base_memmap). 178 * 179 * The memory map for these Highmem IO Regions can be in legacy or compact 180 * layout, depending on 'compact-highmem' property. With legacy layout, the 181 * PA space for one specific region is always reserved, even if the region 182 * has been disabled or doesn't fit into the PA space. However, the PA space 183 * for the region won't be reserved in these circumstances with compact layout. 184 */ 185 static MemMapEntry extended_memmap[] = { 186 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 187 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 188 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 189 /* Second PCIe window */ 190 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 191 }; 192 193 static const int a15irqmap[] = { 194 [VIRT_UART] = 1, 195 [VIRT_RTC] = 2, 196 [VIRT_PCIE] = 3, /* ... to 6 */ 197 [VIRT_GPIO] = 7, 198 [VIRT_SECURE_UART] = 8, 199 [VIRT_ACPI_GED] = 9, 200 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 201 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 202 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 203 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 204 }; 205 206 static const char *valid_cpus[] = { 207 #ifdef CONFIG_TCG 208 ARM_CPU_TYPE_NAME("cortex-a7"), 209 ARM_CPU_TYPE_NAME("cortex-a15"), 210 ARM_CPU_TYPE_NAME("cortex-a35"), 211 ARM_CPU_TYPE_NAME("cortex-a55"), 212 ARM_CPU_TYPE_NAME("cortex-a72"), 213 ARM_CPU_TYPE_NAME("cortex-a76"), 214 ARM_CPU_TYPE_NAME("cortex-a710"), 215 ARM_CPU_TYPE_NAME("a64fx"), 216 ARM_CPU_TYPE_NAME("neoverse-n1"), 217 ARM_CPU_TYPE_NAME("neoverse-v1"), 218 #endif 219 ARM_CPU_TYPE_NAME("cortex-a53"), 220 ARM_CPU_TYPE_NAME("cortex-a57"), 221 ARM_CPU_TYPE_NAME("host"), 222 ARM_CPU_TYPE_NAME("max"), 223 }; 224 225 static bool cpu_type_valid(const char *cpu) 226 { 227 int i; 228 229 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 230 if (strcmp(cpu, valid_cpus[i]) == 0) { 231 return true; 232 } 233 } 234 return false; 235 } 236 237 static void create_randomness(MachineState *ms, const char *node) 238 { 239 struct { 240 uint64_t kaslr; 241 uint8_t rng[32]; 242 } seed; 243 244 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { 245 return; 246 } 247 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr); 248 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); 249 } 250 251 static void create_fdt(VirtMachineState *vms) 252 { 253 MachineState *ms = MACHINE(vms); 254 int nb_numa_nodes = ms->numa_state->num_nodes; 255 void *fdt = create_device_tree(&vms->fdt_size); 256 257 if (!fdt) { 258 error_report("create_device_tree() failed"); 259 exit(1); 260 } 261 262 ms->fdt = fdt; 263 264 /* Header */ 265 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 266 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 267 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 268 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt"); 269 270 /* /chosen must exist for load_dtb to fill in necessary properties later */ 271 qemu_fdt_add_subnode(fdt, "/chosen"); 272 if (vms->dtb_randomness) { 273 create_randomness(ms, "/chosen"); 274 } 275 276 if (vms->secure) { 277 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 278 if (vms->dtb_randomness) { 279 create_randomness(ms, "/secure-chosen"); 280 } 281 } 282 283 /* Clock node, for the benefit of the UART. The kernel device tree 284 * binding documentation claims the PL011 node clock properties are 285 * optional but in practice if you omit them the kernel refuses to 286 * probe for the device. 287 */ 288 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 289 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 290 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 291 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 292 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 293 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 294 "clk24mhz"); 295 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 296 297 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 298 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 299 uint32_t *matrix = g_malloc0(size); 300 int idx, i, j; 301 302 for (i = 0; i < nb_numa_nodes; i++) { 303 for (j = 0; j < nb_numa_nodes; j++) { 304 idx = (i * nb_numa_nodes + j) * 3; 305 matrix[idx + 0] = cpu_to_be32(i); 306 matrix[idx + 1] = cpu_to_be32(j); 307 matrix[idx + 2] = 308 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 309 } 310 } 311 312 qemu_fdt_add_subnode(fdt, "/distance-map"); 313 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 314 "numa-distance-map-v1"); 315 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 316 matrix, size); 317 g_free(matrix); 318 } 319 } 320 321 static void fdt_add_timer_nodes(const VirtMachineState *vms) 322 { 323 /* On real hardware these interrupts are level-triggered. 324 * On KVM they were edge-triggered before host kernel version 4.4, 325 * and level-triggered afterwards. 326 * On emulated QEMU they are level-triggered. 327 * 328 * Getting the DTB info about them wrong is awkward for some 329 * guest kernels: 330 * pre-4.8 ignore the DT and leave the interrupt configured 331 * with whatever the GIC reset value (or the bootloader) left it at 332 * 4.8 before rc6 honour the incorrect data by programming it back 333 * into the GIC, causing problems 334 * 4.8rc6 and later ignore the DT and always write "level triggered" 335 * into the GIC 336 * 337 * For backwards-compatibility, virt-2.8 and earlier will continue 338 * to say these are edge-triggered, but later machines will report 339 * the correct information. 340 */ 341 ARMCPU *armcpu; 342 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 343 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 344 MachineState *ms = MACHINE(vms); 345 346 if (vmc->claim_edge_triggered_timers) { 347 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 348 } 349 350 if (vms->gic_version == VIRT_GIC_VERSION_2) { 351 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 352 GIC_FDT_IRQ_PPI_CPU_WIDTH, 353 (1 << MACHINE(vms)->smp.cpus) - 1); 354 } 355 356 qemu_fdt_add_subnode(ms->fdt, "/timer"); 357 358 armcpu = ARM_CPU(qemu_get_cpu(0)); 359 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 360 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 361 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", 362 compat, sizeof(compat)); 363 } else { 364 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", 365 "arm,armv7-timer"); 366 } 367 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); 368 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 369 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 370 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 371 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 372 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 373 } 374 375 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 376 { 377 int cpu; 378 int addr_cells = 1; 379 const MachineState *ms = MACHINE(vms); 380 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 381 int smp_cpus = ms->smp.cpus; 382 383 /* 384 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml 385 * On ARM v8 64-bit systems value should be set to 2, 386 * that corresponds to the MPIDR_EL1 register size. 387 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 388 * in the system, #address-cells can be set to 1, since 389 * MPIDR_EL1[63:32] bits are not used for CPUs 390 * identification. 391 * 392 * Here we actually don't know whether our system is 32- or 64-bit one. 393 * The simplest way to go is to examine affinity IDs of all our CPUs. If 394 * at least one of them has Aff3 populated, we set #address-cells to 2. 395 */ 396 for (cpu = 0; cpu < smp_cpus; cpu++) { 397 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 398 399 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 400 addr_cells = 2; 401 break; 402 } 403 } 404 405 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 406 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); 407 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 408 409 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 410 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 411 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 412 CPUState *cs = CPU(armcpu); 413 414 qemu_fdt_add_subnode(ms->fdt, nodename); 415 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 416 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 417 armcpu->dtb_compatible); 418 419 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { 420 qemu_fdt_setprop_string(ms->fdt, nodename, 421 "enable-method", "psci"); 422 } 423 424 if (addr_cells == 2) { 425 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", 426 armcpu->mp_affinity); 427 } else { 428 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", 429 armcpu->mp_affinity); 430 } 431 432 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 433 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 434 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 435 } 436 437 if (!vmc->no_cpu_topology) { 438 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 439 qemu_fdt_alloc_phandle(ms->fdt)); 440 } 441 442 g_free(nodename); 443 } 444 445 if (!vmc->no_cpu_topology) { 446 /* 447 * Add vCPU topology description through fdt node cpu-map. 448 * 449 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt 450 * In a SMP system, the hierarchy of CPUs can be defined through 451 * four entities that are used to describe the layout of CPUs in 452 * the system: socket/cluster/core/thread. 453 * 454 * A socket node represents the boundary of system physical package 455 * and its child nodes must be one or more cluster nodes. A system 456 * can contain several layers of clustering within a single physical 457 * package and cluster nodes can be contained in parent cluster nodes. 458 * 459 * Note: currently we only support one layer of clustering within 460 * each physical package. 461 */ 462 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 463 464 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 465 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); 466 char *map_path; 467 468 if (ms->smp.threads > 1) { 469 map_path = g_strdup_printf( 470 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", 471 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), 472 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, 473 (cpu / ms->smp.threads) % ms->smp.cores, 474 cpu % ms->smp.threads); 475 } else { 476 map_path = g_strdup_printf( 477 "/cpus/cpu-map/socket%d/cluster%d/core%d", 478 cpu / (ms->smp.clusters * ms->smp.cores), 479 (cpu / ms->smp.cores) % ms->smp.clusters, 480 cpu % ms->smp.cores); 481 } 482 qemu_fdt_add_path(ms->fdt, map_path); 483 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 484 485 g_free(map_path); 486 g_free(cpu_path); 487 } 488 } 489 } 490 491 static void fdt_add_its_gic_node(VirtMachineState *vms) 492 { 493 char *nodename; 494 MachineState *ms = MACHINE(vms); 495 496 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 497 nodename = g_strdup_printf("/intc/its@%" PRIx64, 498 vms->memmap[VIRT_GIC_ITS].base); 499 qemu_fdt_add_subnode(ms->fdt, nodename); 500 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 501 "arm,gic-v3-its"); 502 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 503 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1); 504 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 505 2, vms->memmap[VIRT_GIC_ITS].base, 506 2, vms->memmap[VIRT_GIC_ITS].size); 507 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 508 g_free(nodename); 509 } 510 511 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 512 { 513 MachineState *ms = MACHINE(vms); 514 char *nodename; 515 516 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 517 vms->memmap[VIRT_GIC_V2M].base); 518 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 519 qemu_fdt_add_subnode(ms->fdt, nodename); 520 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 521 "arm,gic-v2m-frame"); 522 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 523 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 524 2, vms->memmap[VIRT_GIC_V2M].base, 525 2, vms->memmap[VIRT_GIC_V2M].size); 526 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 527 g_free(nodename); 528 } 529 530 static void fdt_add_gic_node(VirtMachineState *vms) 531 { 532 MachineState *ms = MACHINE(vms); 533 char *nodename; 534 535 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 536 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); 537 538 nodename = g_strdup_printf("/intc@%" PRIx64, 539 vms->memmap[VIRT_GIC_DIST].base); 540 qemu_fdt_add_subnode(ms->fdt, nodename); 541 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 542 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 543 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 544 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 545 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 546 if (vms->gic_version != VIRT_GIC_VERSION_2) { 547 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 548 549 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 550 "arm,gic-v3"); 551 552 qemu_fdt_setprop_cell(ms->fdt, nodename, 553 "#redistributor-regions", nb_redist_regions); 554 555 if (nb_redist_regions == 1) { 556 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 557 2, vms->memmap[VIRT_GIC_DIST].base, 558 2, vms->memmap[VIRT_GIC_DIST].size, 559 2, vms->memmap[VIRT_GIC_REDIST].base, 560 2, vms->memmap[VIRT_GIC_REDIST].size); 561 } else { 562 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 563 2, vms->memmap[VIRT_GIC_DIST].base, 564 2, vms->memmap[VIRT_GIC_DIST].size, 565 2, vms->memmap[VIRT_GIC_REDIST].base, 566 2, vms->memmap[VIRT_GIC_REDIST].size, 567 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 568 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 569 } 570 571 if (vms->virt) { 572 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 573 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 574 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 575 } 576 } else { 577 /* 'cortex-a15-gic' means 'GIC v2' */ 578 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 579 "arm,cortex-a15-gic"); 580 if (!vms->virt) { 581 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 582 2, vms->memmap[VIRT_GIC_DIST].base, 583 2, vms->memmap[VIRT_GIC_DIST].size, 584 2, vms->memmap[VIRT_GIC_CPU].base, 585 2, vms->memmap[VIRT_GIC_CPU].size); 586 } else { 587 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 588 2, vms->memmap[VIRT_GIC_DIST].base, 589 2, vms->memmap[VIRT_GIC_DIST].size, 590 2, vms->memmap[VIRT_GIC_CPU].base, 591 2, vms->memmap[VIRT_GIC_CPU].size, 592 2, vms->memmap[VIRT_GIC_HYP].base, 593 2, vms->memmap[VIRT_GIC_HYP].size, 594 2, vms->memmap[VIRT_GIC_VCPU].base, 595 2, vms->memmap[VIRT_GIC_VCPU].size); 596 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 597 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 598 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 599 } 600 } 601 602 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); 603 g_free(nodename); 604 } 605 606 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 607 { 608 ARMCPU *armcpu = ARM_CPU(first_cpu); 609 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 610 MachineState *ms = MACHINE(vms); 611 612 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 613 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); 614 return; 615 } 616 617 if (vms->gic_version == VIRT_GIC_VERSION_2) { 618 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 619 GIC_FDT_IRQ_PPI_CPU_WIDTH, 620 (1 << MACHINE(vms)->smp.cpus) - 1); 621 } 622 623 qemu_fdt_add_subnode(ms->fdt, "/pmu"); 624 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 625 const char compat[] = "arm,armv8-pmuv3"; 626 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", 627 compat, sizeof(compat)); 628 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", 629 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 630 } 631 } 632 633 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 634 { 635 DeviceState *dev; 636 MachineState *ms = MACHINE(vms); 637 int irq = vms->irqmap[VIRT_ACPI_GED]; 638 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 639 640 if (ms->ram_slots) { 641 event |= ACPI_GED_MEM_HOTPLUG_EVT; 642 } 643 644 if (ms->nvdimms_state->is_enabled) { 645 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 646 } 647 648 dev = qdev_new(TYPE_ACPI_GED); 649 qdev_prop_set_uint32(dev, "ged-event", event); 650 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 651 652 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 653 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 654 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 655 656 return dev; 657 } 658 659 static void create_its(VirtMachineState *vms) 660 { 661 const char *itsclass = its_class_name(); 662 DeviceState *dev; 663 664 if (!strcmp(itsclass, "arm-gicv3-its")) { 665 if (!vms->tcg_its) { 666 itsclass = NULL; 667 } 668 } 669 670 if (!itsclass) { 671 /* Do nothing if not supported */ 672 return; 673 } 674 675 dev = qdev_new(itsclass); 676 677 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 678 &error_abort); 679 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 680 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 681 682 fdt_add_its_gic_node(vms); 683 vms->msi_controller = VIRT_MSI_CTRL_ITS; 684 } 685 686 static void create_v2m(VirtMachineState *vms) 687 { 688 int i; 689 int irq = vms->irqmap[VIRT_GIC_V2M]; 690 DeviceState *dev; 691 692 dev = qdev_new("arm-gicv2m"); 693 qdev_prop_set_uint32(dev, "base-spi", irq); 694 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 695 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 696 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 697 698 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 699 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 700 qdev_get_gpio_in(vms->gic, irq + i)); 701 } 702 703 fdt_add_v2m_gic_node(vms); 704 vms->msi_controller = VIRT_MSI_CTRL_GICV2M; 705 } 706 707 static void create_gic(VirtMachineState *vms, MemoryRegion *mem) 708 { 709 MachineState *ms = MACHINE(vms); 710 /* We create a standalone GIC */ 711 SysBusDevice *gicbusdev; 712 const char *gictype; 713 int i; 714 unsigned int smp_cpus = ms->smp.cpus; 715 uint32_t nb_redist_regions = 0; 716 int revision; 717 718 if (vms->gic_version == VIRT_GIC_VERSION_2) { 719 gictype = gic_class_name(); 720 } else { 721 gictype = gicv3_class_name(); 722 } 723 724 switch (vms->gic_version) { 725 case VIRT_GIC_VERSION_2: 726 revision = 2; 727 break; 728 case VIRT_GIC_VERSION_3: 729 revision = 3; 730 break; 731 case VIRT_GIC_VERSION_4: 732 revision = 4; 733 break; 734 default: 735 g_assert_not_reached(); 736 } 737 vms->gic = qdev_new(gictype); 738 qdev_prop_set_uint32(vms->gic, "revision", revision); 739 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 740 /* Note that the num-irq property counts both internal and external 741 * interrupts; there are always 32 of the former (mandated by GIC spec). 742 */ 743 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 744 if (!kvm_irqchip_in_kernel()) { 745 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 746 } 747 748 if (vms->gic_version != VIRT_GIC_VERSION_2) { 749 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); 750 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 751 752 nb_redist_regions = virt_gicv3_redist_region_count(vms); 753 754 qdev_prop_set_uint32(vms->gic, "len-redist-region-count", 755 nb_redist_regions); 756 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count); 757 758 if (!kvm_irqchip_in_kernel()) { 759 if (vms->tcg_its) { 760 object_property_set_link(OBJECT(vms->gic), "sysmem", 761 OBJECT(mem), &error_fatal); 762 qdev_prop_set_bit(vms->gic, "has-lpi", true); 763 } 764 } 765 766 if (nb_redist_regions == 2) { 767 uint32_t redist1_capacity = 768 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 769 770 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", 771 MIN(smp_cpus - redist0_count, redist1_capacity)); 772 } 773 } else { 774 if (!kvm_irqchip_in_kernel()) { 775 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 776 vms->virt); 777 } 778 } 779 gicbusdev = SYS_BUS_DEVICE(vms->gic); 780 sysbus_realize_and_unref(gicbusdev, &error_fatal); 781 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 782 if (vms->gic_version != VIRT_GIC_VERSION_2) { 783 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 784 if (nb_redist_regions == 2) { 785 sysbus_mmio_map(gicbusdev, 2, 786 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 787 } 788 } else { 789 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 790 if (vms->virt) { 791 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 792 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 793 } 794 } 795 796 /* Wire the outputs from each CPU's generic timer and the GICv3 797 * maintenance interrupt signal to the appropriate GIC PPI inputs, 798 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 799 */ 800 for (i = 0; i < smp_cpus; i++) { 801 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 802 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 803 /* Mapping from the output timer irq lines from the CPU to the 804 * GIC PPI inputs we use for the virt board. 805 */ 806 const int timer_irq[] = { 807 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 808 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 809 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 810 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 811 }; 812 813 for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 814 qdev_connect_gpio_out(cpudev, irq, 815 qdev_get_gpio_in(vms->gic, 816 ppibase + timer_irq[irq])); 817 } 818 819 if (vms->gic_version != VIRT_GIC_VERSION_2) { 820 qemu_irq irq = qdev_get_gpio_in(vms->gic, 821 ppibase + ARCH_GIC_MAINT_IRQ); 822 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 823 0, irq); 824 } else if (vms->virt) { 825 qemu_irq irq = qdev_get_gpio_in(vms->gic, 826 ppibase + ARCH_GIC_MAINT_IRQ); 827 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 828 } 829 830 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 831 qdev_get_gpio_in(vms->gic, ppibase 832 + VIRTUAL_PMU_IRQ)); 833 834 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 835 sysbus_connect_irq(gicbusdev, i + smp_cpus, 836 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 837 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 838 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 839 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 840 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 841 } 842 843 fdt_add_gic_node(vms); 844 845 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) { 846 create_its(vms); 847 } else if (vms->gic_version == VIRT_GIC_VERSION_2) { 848 create_v2m(vms); 849 } 850 } 851 852 static void create_uart(const VirtMachineState *vms, int uart, 853 MemoryRegion *mem, Chardev *chr) 854 { 855 char *nodename; 856 hwaddr base = vms->memmap[uart].base; 857 hwaddr size = vms->memmap[uart].size; 858 int irq = vms->irqmap[uart]; 859 const char compat[] = "arm,pl011\0arm,primecell"; 860 const char clocknames[] = "uartclk\0apb_pclk"; 861 DeviceState *dev = qdev_new(TYPE_PL011); 862 SysBusDevice *s = SYS_BUS_DEVICE(dev); 863 MachineState *ms = MACHINE(vms); 864 865 qdev_prop_set_chr(dev, "chardev", chr); 866 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 867 memory_region_add_subregion(mem, base, 868 sysbus_mmio_get_region(s, 0)); 869 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 870 871 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 872 qemu_fdt_add_subnode(ms->fdt, nodename); 873 /* Note that we can't use setprop_string because of the embedded NUL */ 874 qemu_fdt_setprop(ms->fdt, nodename, "compatible", 875 compat, sizeof(compat)); 876 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 877 2, base, 2, size); 878 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 879 GIC_FDT_IRQ_TYPE_SPI, irq, 880 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 881 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", 882 vms->clock_phandle, vms->clock_phandle); 883 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", 884 clocknames, sizeof(clocknames)); 885 886 if (uart == VIRT_UART) { 887 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 888 } else { 889 /* Mark as not usable by the normal world */ 890 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 891 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 892 893 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", 894 nodename); 895 } 896 897 g_free(nodename); 898 } 899 900 static void create_rtc(const VirtMachineState *vms) 901 { 902 char *nodename; 903 hwaddr base = vms->memmap[VIRT_RTC].base; 904 hwaddr size = vms->memmap[VIRT_RTC].size; 905 int irq = vms->irqmap[VIRT_RTC]; 906 const char compat[] = "arm,pl031\0arm,primecell"; 907 MachineState *ms = MACHINE(vms); 908 909 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 910 911 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 912 qemu_fdt_add_subnode(ms->fdt, nodename); 913 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 914 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 915 2, base, 2, size); 916 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 917 GIC_FDT_IRQ_TYPE_SPI, irq, 918 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 919 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 920 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 921 g_free(nodename); 922 } 923 924 static DeviceState *gpio_key_dev; 925 static void virt_powerdown_req(Notifier *n, void *opaque) 926 { 927 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 928 929 if (s->acpi_dev) { 930 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 931 } else { 932 /* use gpio Pin 3 for power button event */ 933 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 934 } 935 } 936 937 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, 938 uint32_t phandle) 939 { 940 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 941 qdev_get_gpio_in(pl061_dev, 3)); 942 943 qemu_fdt_add_subnode(fdt, "/gpio-keys"); 944 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); 945 946 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); 947 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", 948 "label", "GPIO Key Poweroff"); 949 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", 950 KEY_POWER); 951 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", 952 "gpios", phandle, 3, 0); 953 } 954 955 #define SECURE_GPIO_POWEROFF 0 956 #define SECURE_GPIO_RESET 1 957 958 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, 959 uint32_t phandle) 960 { 961 DeviceState *gpio_pwr_dev; 962 963 /* gpio-pwr */ 964 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); 965 966 /* connect secure pl061 to gpio-pwr */ 967 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, 968 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); 969 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, 970 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); 971 972 qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); 973 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", 974 "gpio-poweroff"); 975 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", 976 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); 977 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); 978 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", 979 "okay"); 980 981 qemu_fdt_add_subnode(fdt, "/gpio-restart"); 982 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", 983 "gpio-restart"); 984 qemu_fdt_setprop_cells(fdt, "/gpio-restart", 985 "gpios", phandle, SECURE_GPIO_RESET, 0); 986 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); 987 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", 988 "okay"); 989 } 990 991 static void create_gpio_devices(const VirtMachineState *vms, int gpio, 992 MemoryRegion *mem) 993 { 994 char *nodename; 995 DeviceState *pl061_dev; 996 hwaddr base = vms->memmap[gpio].base; 997 hwaddr size = vms->memmap[gpio].size; 998 int irq = vms->irqmap[gpio]; 999 const char compat[] = "arm,pl061\0arm,primecell"; 1000 SysBusDevice *s; 1001 MachineState *ms = MACHINE(vms); 1002 1003 pl061_dev = qdev_new("pl061"); 1004 /* Pull lines down to 0 if not driven by the PL061 */ 1005 qdev_prop_set_uint32(pl061_dev, "pullups", 0); 1006 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); 1007 s = SYS_BUS_DEVICE(pl061_dev); 1008 sysbus_realize_and_unref(s, &error_fatal); 1009 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); 1010 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 1011 1012 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); 1013 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 1014 qemu_fdt_add_subnode(ms->fdt, nodename); 1015 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1016 2, base, 2, size); 1017 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 1018 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); 1019 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); 1020 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1021 GIC_FDT_IRQ_TYPE_SPI, irq, 1022 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1023 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1024 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1025 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); 1026 1027 if (gpio != VIRT_GPIO) { 1028 /* Mark as not usable by the normal world */ 1029 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1030 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1031 } 1032 g_free(nodename); 1033 1034 /* Child gpio devices */ 1035 if (gpio == VIRT_GPIO) { 1036 create_gpio_keys(ms->fdt, pl061_dev, phandle); 1037 } else { 1038 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); 1039 } 1040 } 1041 1042 static void create_virtio_devices(const VirtMachineState *vms) 1043 { 1044 int i; 1045 hwaddr size = vms->memmap[VIRT_MMIO].size; 1046 MachineState *ms = MACHINE(vms); 1047 1048 /* We create the transports in forwards order. Since qbus_realize() 1049 * prepends (not appends) new child buses, the incrementing loop below will 1050 * create a list of virtio-mmio buses with decreasing base addresses. 1051 * 1052 * When a -device option is processed from the command line, 1053 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 1054 * order. The upshot is that -device options in increasing command line 1055 * order are mapped to virtio-mmio buses with decreasing base addresses. 1056 * 1057 * When this code was originally written, that arrangement ensured that the 1058 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 1059 * the first -device on the command line. (The end-to-end order is a 1060 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 1061 * guest kernel's name-to-address assignment strategy.) 1062 * 1063 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 1064 * the message, if not necessarily the code, of commit 70161ff336. 1065 * Therefore the loop now establishes the inverse of the original intent. 1066 * 1067 * Unfortunately, we can't counteract the kernel change by reversing the 1068 * loop; it would break existing command lines. 1069 * 1070 * In any case, the kernel makes no guarantee about the stability of 1071 * enumeration order of virtio devices (as demonstrated by it changing 1072 * between kernel versions). For reliable and stable identification 1073 * of disks users must use UUIDs or similar mechanisms. 1074 */ 1075 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 1076 int irq = vms->irqmap[VIRT_MMIO] + i; 1077 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1078 1079 sysbus_create_simple("virtio-mmio", base, 1080 qdev_get_gpio_in(vms->gic, irq)); 1081 } 1082 1083 /* We add dtb nodes in reverse order so that they appear in the finished 1084 * device tree lowest address first. 1085 * 1086 * Note that this mapping is independent of the loop above. The previous 1087 * loop influences virtio device to virtio transport assignment, whereas 1088 * this loop controls how virtio transports are laid out in the dtb. 1089 */ 1090 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 1091 char *nodename; 1092 int irq = vms->irqmap[VIRT_MMIO] + i; 1093 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1094 1095 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 1096 qemu_fdt_add_subnode(ms->fdt, nodename); 1097 qemu_fdt_setprop_string(ms->fdt, nodename, 1098 "compatible", "virtio,mmio"); 1099 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1100 2, base, 2, size); 1101 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1102 GIC_FDT_IRQ_TYPE_SPI, irq, 1103 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1104 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1105 g_free(nodename); 1106 } 1107 } 1108 1109 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 1110 1111 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 1112 const char *name, 1113 const char *alias_prop_name) 1114 { 1115 /* 1116 * Create a single flash device. We use the same parameters as 1117 * the flash devices on the Versatile Express board. 1118 */ 1119 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 1120 1121 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 1122 qdev_prop_set_uint8(dev, "width", 4); 1123 qdev_prop_set_uint8(dev, "device-width", 2); 1124 qdev_prop_set_bit(dev, "big-endian", false); 1125 qdev_prop_set_uint16(dev, "id0", 0x89); 1126 qdev_prop_set_uint16(dev, "id1", 0x18); 1127 qdev_prop_set_uint16(dev, "id2", 0x00); 1128 qdev_prop_set_uint16(dev, "id3", 0x00); 1129 qdev_prop_set_string(dev, "name", name); 1130 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 1131 object_property_add_alias(OBJECT(vms), alias_prop_name, 1132 OBJECT(dev), "drive"); 1133 return PFLASH_CFI01(dev); 1134 } 1135 1136 static void virt_flash_create(VirtMachineState *vms) 1137 { 1138 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 1139 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 1140 } 1141 1142 static void virt_flash_map1(PFlashCFI01 *flash, 1143 hwaddr base, hwaddr size, 1144 MemoryRegion *sysmem) 1145 { 1146 DeviceState *dev = DEVICE(flash); 1147 1148 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 1149 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 1150 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 1151 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1152 1153 memory_region_add_subregion(sysmem, base, 1154 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1155 0)); 1156 } 1157 1158 static void virt_flash_map(VirtMachineState *vms, 1159 MemoryRegion *sysmem, 1160 MemoryRegion *secure_sysmem) 1161 { 1162 /* 1163 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 1164 * sysmem is the system memory space. secure_sysmem is the secure view 1165 * of the system, and the first flash device should be made visible only 1166 * there. The second flash device is visible to both secure and nonsecure. 1167 * If sysmem == secure_sysmem this means there is no separate Secure 1168 * address space and both flash devices are generally visible. 1169 */ 1170 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1171 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1172 1173 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1174 secure_sysmem); 1175 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1176 sysmem); 1177 } 1178 1179 static void virt_flash_fdt(VirtMachineState *vms, 1180 MemoryRegion *sysmem, 1181 MemoryRegion *secure_sysmem) 1182 { 1183 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1184 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1185 MachineState *ms = MACHINE(vms); 1186 char *nodename; 1187 1188 if (sysmem == secure_sysmem) { 1189 /* Report both flash devices as a single node in the DT */ 1190 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1191 qemu_fdt_add_subnode(ms->fdt, nodename); 1192 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1193 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1194 2, flashbase, 2, flashsize, 1195 2, flashbase + flashsize, 2, flashsize); 1196 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1197 g_free(nodename); 1198 } else { 1199 /* 1200 * Report the devices as separate nodes so we can mark one as 1201 * only visible to the secure world. 1202 */ 1203 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1204 qemu_fdt_add_subnode(ms->fdt, nodename); 1205 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1206 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1207 2, flashbase, 2, flashsize); 1208 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1209 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1210 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1211 g_free(nodename); 1212 1213 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize); 1214 qemu_fdt_add_subnode(ms->fdt, nodename); 1215 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1216 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1217 2, flashbase + flashsize, 2, flashsize); 1218 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1219 g_free(nodename); 1220 } 1221 } 1222 1223 static bool virt_firmware_init(VirtMachineState *vms, 1224 MemoryRegion *sysmem, 1225 MemoryRegion *secure_sysmem) 1226 { 1227 int i; 1228 const char *bios_name; 1229 BlockBackend *pflash_blk0; 1230 1231 /* Map legacy -drive if=pflash to machine properties */ 1232 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1233 pflash_cfi01_legacy_drive(vms->flash[i], 1234 drive_get(IF_PFLASH, 0, i)); 1235 } 1236 1237 virt_flash_map(vms, sysmem, secure_sysmem); 1238 1239 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1240 1241 bios_name = MACHINE(vms)->firmware; 1242 if (bios_name) { 1243 char *fname; 1244 MemoryRegion *mr; 1245 int image_size; 1246 1247 if (pflash_blk0) { 1248 error_report("The contents of the first flash device may be " 1249 "specified with -bios or with -drive if=pflash... " 1250 "but you cannot use both options at once"); 1251 exit(1); 1252 } 1253 1254 /* Fall back to -bios */ 1255 1256 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1257 if (!fname) { 1258 error_report("Could not find ROM image '%s'", bios_name); 1259 exit(1); 1260 } 1261 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1262 image_size = load_image_mr(fname, mr); 1263 g_free(fname); 1264 if (image_size < 0) { 1265 error_report("Could not load ROM image '%s'", bios_name); 1266 exit(1); 1267 } 1268 } 1269 1270 return pflash_blk0 || bios_name; 1271 } 1272 1273 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1274 { 1275 MachineState *ms = MACHINE(vms); 1276 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1277 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1278 FWCfgState *fw_cfg; 1279 char *nodename; 1280 1281 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1282 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1283 1284 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1285 qemu_fdt_add_subnode(ms->fdt, nodename); 1286 qemu_fdt_setprop_string(ms->fdt, nodename, 1287 "compatible", "qemu,fw-cfg-mmio"); 1288 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1289 2, base, 2, size); 1290 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1291 g_free(nodename); 1292 return fw_cfg; 1293 } 1294 1295 static void create_pcie_irq_map(const MachineState *ms, 1296 uint32_t gic_phandle, 1297 int first_irq, const char *nodename) 1298 { 1299 int devfn, pin; 1300 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1301 uint32_t *irq_map = full_irq_map; 1302 1303 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1304 for (pin = 0; pin < 4; pin++) { 1305 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1306 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1307 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1308 int i; 1309 1310 uint32_t map[] = { 1311 devfn << 8, 0, 0, /* devfn */ 1312 pin + 1, /* PCI pin */ 1313 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1314 1315 /* Convert map to big endian */ 1316 for (i = 0; i < 10; i++) { 1317 irq_map[i] = cpu_to_be32(map[i]); 1318 } 1319 irq_map += 10; 1320 } 1321 } 1322 1323 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", 1324 full_irq_map, sizeof(full_irq_map)); 1325 1326 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 1327 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ 1328 0, 0, 1329 0x7 /* PCI irq */); 1330 } 1331 1332 static void create_smmu(const VirtMachineState *vms, 1333 PCIBus *bus) 1334 { 1335 char *node; 1336 const char compat[] = "arm,smmu-v3"; 1337 int irq = vms->irqmap[VIRT_SMMU]; 1338 int i; 1339 hwaddr base = vms->memmap[VIRT_SMMU].base; 1340 hwaddr size = vms->memmap[VIRT_SMMU].size; 1341 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1342 DeviceState *dev; 1343 MachineState *ms = MACHINE(vms); 1344 1345 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1346 return; 1347 } 1348 1349 dev = qdev_new(TYPE_ARM_SMMUV3); 1350 1351 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1352 &error_abort); 1353 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1354 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1355 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1356 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1357 qdev_get_gpio_in(vms->gic, irq + i)); 1358 } 1359 1360 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1361 qemu_fdt_add_subnode(ms->fdt, node); 1362 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1363 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); 1364 1365 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", 1366 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1367 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1368 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1369 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1370 1371 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, 1372 sizeof(irq_names)); 1373 1374 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); 1375 1376 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1377 1378 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1379 g_free(node); 1380 } 1381 1382 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1383 { 1384 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1385 uint16_t bdf = vms->virtio_iommu_bdf; 1386 MachineState *ms = MACHINE(vms); 1387 char *node; 1388 1389 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1390 1391 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename, 1392 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1393 qemu_fdt_add_subnode(ms->fdt, node); 1394 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1395 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 1396 1, bdf << 8, 1, 0, 1, 0, 1397 1, 0, 1, 0); 1398 1399 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1400 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1401 g_free(node); 1402 1403 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", 1404 0x0, vms->iommu_phandle, 0x0, bdf, 1405 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1406 } 1407 1408 static void create_pcie(VirtMachineState *vms) 1409 { 1410 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1411 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1412 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1413 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1414 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1415 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1416 hwaddr base_ecam, size_ecam; 1417 hwaddr base = base_mmio; 1418 int nr_pcie_buses; 1419 int irq = vms->irqmap[VIRT_PCIE]; 1420 MemoryRegion *mmio_alias; 1421 MemoryRegion *mmio_reg; 1422 MemoryRegion *ecam_alias; 1423 MemoryRegion *ecam_reg; 1424 DeviceState *dev; 1425 char *nodename; 1426 int i, ecam_id; 1427 PCIHostState *pci; 1428 MachineState *ms = MACHINE(vms); 1429 MachineClass *mc = MACHINE_GET_CLASS(ms); 1430 1431 dev = qdev_new(TYPE_GPEX_HOST); 1432 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1433 1434 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1435 base_ecam = vms->memmap[ecam_id].base; 1436 size_ecam = vms->memmap[ecam_id].size; 1437 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1438 /* Map only the first size_ecam bytes of ECAM space */ 1439 ecam_alias = g_new0(MemoryRegion, 1); 1440 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1441 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1442 ecam_reg, 0, size_ecam); 1443 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1444 1445 /* Map the MMIO window into system address space so as to expose 1446 * the section of PCI MMIO space which starts at the same base address 1447 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1448 * the window). 1449 */ 1450 mmio_alias = g_new0(MemoryRegion, 1); 1451 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1452 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1453 mmio_reg, base_mmio, size_mmio); 1454 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1455 1456 if (vms->highmem_mmio) { 1457 /* Map high MMIO space */ 1458 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1459 1460 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1461 mmio_reg, base_mmio_high, size_mmio_high); 1462 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1463 high_mmio_alias); 1464 } 1465 1466 /* Map IO port space */ 1467 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1468 1469 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1470 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1471 qdev_get_gpio_in(vms->gic, irq + i)); 1472 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1473 } 1474 1475 pci = PCI_HOST_BRIDGE(dev); 1476 pci->bypass_iommu = vms->default_bus_bypass_iommu; 1477 vms->bus = pci->bus; 1478 if (vms->bus) { 1479 for (i = 0; i < nb_nics; i++) { 1480 pci_nic_init_nofail(&nd_table[i], pci->bus, mc->default_nic, NULL); 1481 } 1482 } 1483 1484 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1485 qemu_fdt_add_subnode(ms->fdt, nodename); 1486 qemu_fdt_setprop_string(ms->fdt, nodename, 1487 "compatible", "pci-host-ecam-generic"); 1488 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 1489 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 1490 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 1491 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 1492 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 1493 nr_pcie_buses - 1); 1494 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1495 1496 if (vms->msi_phandle) { 1497 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 1498 0, vms->msi_phandle, 0, 0x10000); 1499 } 1500 1501 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1502 2, base_ecam, 2, size_ecam); 1503 1504 if (vms->highmem_mmio) { 1505 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1506 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1507 2, base_pio, 2, size_pio, 1508 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1509 2, base_mmio, 2, size_mmio, 1510 1, FDT_PCI_RANGE_MMIO_64BIT, 1511 2, base_mmio_high, 1512 2, base_mmio_high, 2, size_mmio_high); 1513 } else { 1514 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1515 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1516 2, base_pio, 2, size_pio, 1517 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1518 2, base_mmio, 2, size_mmio); 1519 } 1520 1521 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 1522 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); 1523 1524 if (vms->iommu) { 1525 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1526 1527 switch (vms->iommu) { 1528 case VIRT_IOMMU_SMMUV3: 1529 create_smmu(vms, vms->bus); 1530 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 1531 0x0, vms->iommu_phandle, 0x0, 0x10000); 1532 break; 1533 default: 1534 g_assert_not_reached(); 1535 } 1536 } 1537 } 1538 1539 static void create_platform_bus(VirtMachineState *vms) 1540 { 1541 DeviceState *dev; 1542 SysBusDevice *s; 1543 int i; 1544 MemoryRegion *sysmem = get_system_memory(); 1545 1546 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1547 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1548 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1549 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1550 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1551 vms->platform_bus_dev = dev; 1552 1553 s = SYS_BUS_DEVICE(dev); 1554 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1555 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1556 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1557 } 1558 1559 memory_region_add_subregion(sysmem, 1560 vms->memmap[VIRT_PLATFORM_BUS].base, 1561 sysbus_mmio_get_region(s, 0)); 1562 } 1563 1564 static void create_tag_ram(MemoryRegion *tag_sysmem, 1565 hwaddr base, hwaddr size, 1566 const char *name) 1567 { 1568 MemoryRegion *tagram = g_new(MemoryRegion, 1); 1569 1570 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); 1571 memory_region_add_subregion(tag_sysmem, base / 32, tagram); 1572 } 1573 1574 static void create_secure_ram(VirtMachineState *vms, 1575 MemoryRegion *secure_sysmem, 1576 MemoryRegion *secure_tag_sysmem) 1577 { 1578 MemoryRegion *secram = g_new(MemoryRegion, 1); 1579 char *nodename; 1580 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1581 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1582 MachineState *ms = MACHINE(vms); 1583 1584 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1585 &error_fatal); 1586 memory_region_add_subregion(secure_sysmem, base, secram); 1587 1588 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1589 qemu_fdt_add_subnode(ms->fdt, nodename); 1590 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 1591 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 1592 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1593 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1594 1595 if (secure_tag_sysmem) { 1596 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); 1597 } 1598 1599 g_free(nodename); 1600 } 1601 1602 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1603 { 1604 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1605 bootinfo); 1606 MachineState *ms = MACHINE(board); 1607 1608 1609 *fdt_size = board->fdt_size; 1610 return ms->fdt; 1611 } 1612 1613 static void virt_build_smbios(VirtMachineState *vms) 1614 { 1615 MachineClass *mc = MACHINE_GET_CLASS(vms); 1616 MachineState *ms = MACHINE(vms); 1617 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1618 uint8_t *smbios_tables, *smbios_anchor; 1619 size_t smbios_tables_len, smbios_anchor_len; 1620 struct smbios_phys_mem_area mem_array; 1621 const char *product = "QEMU Virtual Machine"; 1622 1623 if (kvm_enabled()) { 1624 product = "KVM Virtual Machine"; 1625 } 1626 1627 smbios_set_defaults("QEMU", product, 1628 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1629 true, SMBIOS_ENTRY_POINT_TYPE_64); 1630 1631 /* build the array of physical mem area from base_memmap */ 1632 mem_array.address = vms->memmap[VIRT_MEM].base; 1633 mem_array.length = ms->ram_size; 1634 1635 smbios_get_tables(ms, &mem_array, 1, 1636 &smbios_tables, &smbios_tables_len, 1637 &smbios_anchor, &smbios_anchor_len, 1638 &error_fatal); 1639 1640 if (smbios_anchor) { 1641 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1642 smbios_tables, smbios_tables_len); 1643 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1644 smbios_anchor, smbios_anchor_len); 1645 } 1646 } 1647 1648 static 1649 void virt_machine_done(Notifier *notifier, void *data) 1650 { 1651 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1652 machine_done); 1653 MachineState *ms = MACHINE(vms); 1654 ARMCPU *cpu = ARM_CPU(first_cpu); 1655 struct arm_boot_info *info = &vms->bootinfo; 1656 AddressSpace *as = arm_boot_address_space(cpu, info); 1657 1658 /* 1659 * If the user provided a dtb, we assume the dynamic sysbus nodes 1660 * already are integrated there. This corresponds to a use case where 1661 * the dynamic sysbus nodes are complex and their generation is not yet 1662 * supported. In that case the user can take charge of the guest dt 1663 * while qemu takes charge of the qom stuff. 1664 */ 1665 if (info->dtb_filename == NULL) { 1666 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", 1667 vms->memmap[VIRT_PLATFORM_BUS].base, 1668 vms->memmap[VIRT_PLATFORM_BUS].size, 1669 vms->irqmap[VIRT_PLATFORM_BUS]); 1670 } 1671 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1672 exit(1); 1673 } 1674 1675 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg); 1676 1677 virt_acpi_setup(vms); 1678 virt_build_smbios(vms); 1679 } 1680 1681 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1682 { 1683 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1684 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1685 1686 if (!vmc->disallow_affinity_adjustment) { 1687 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1688 * GIC's target-list limitations. 32-bit KVM hosts currently 1689 * always create clusters of 4 CPUs, but that is expected to 1690 * change when they gain support for gicv3. When KVM is enabled 1691 * it will override the changes we make here, therefore our 1692 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1693 * and to improve SGI efficiency. 1694 */ 1695 if (vms->gic_version == VIRT_GIC_VERSION_2) { 1696 clustersz = GIC_TARGETLIST_BITS; 1697 } else { 1698 clustersz = GICV3_TARGETLIST_BITS; 1699 } 1700 } 1701 return arm_cpu_mp_affinity(idx, clustersz); 1702 } 1703 1704 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, 1705 int index) 1706 { 1707 bool *enabled_array[] = { 1708 &vms->highmem_redists, 1709 &vms->highmem_ecam, 1710 &vms->highmem_mmio, 1711 }; 1712 1713 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST == 1714 ARRAY_SIZE(enabled_array)); 1715 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array)); 1716 1717 return enabled_array[index - VIRT_LOWMEMMAP_LAST]; 1718 } 1719 1720 static void virt_set_high_memmap(VirtMachineState *vms, 1721 hwaddr base, int pa_bits) 1722 { 1723 hwaddr region_base, region_size; 1724 bool *region_enabled, fits; 1725 int i; 1726 1727 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1728 region_enabled = virt_get_high_memmap_enabled(vms, i); 1729 region_base = ROUND_UP(base, extended_memmap[i].size); 1730 region_size = extended_memmap[i].size; 1731 1732 vms->memmap[i].base = region_base; 1733 vms->memmap[i].size = region_size; 1734 1735 /* 1736 * Check each device to see if it fits in the PA space, 1737 * moving highest_gpa as we go. For compatibility, move 1738 * highest_gpa for disabled fitting devices as well, if 1739 * the compact layout has been disabled. 1740 * 1741 * For each device that doesn't fit, disable it. 1742 */ 1743 fits = (region_base + region_size) <= BIT_ULL(pa_bits); 1744 *region_enabled &= fits; 1745 if (vms->highmem_compact && !*region_enabled) { 1746 continue; 1747 } 1748 1749 base = region_base + region_size; 1750 if (fits) { 1751 vms->highest_gpa = base - 1; 1752 } 1753 } 1754 } 1755 1756 static void virt_set_memmap(VirtMachineState *vms, int pa_bits) 1757 { 1758 MachineState *ms = MACHINE(vms); 1759 hwaddr base, device_memory_base, device_memory_size, memtop; 1760 int i; 1761 1762 vms->memmap = extended_memmap; 1763 1764 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1765 vms->memmap[i] = base_memmap[i]; 1766 } 1767 1768 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1769 error_report("unsupported number of memory slots: %"PRIu64, 1770 ms->ram_slots); 1771 exit(EXIT_FAILURE); 1772 } 1773 1774 /* 1775 * !highmem is exactly the same as limiting the PA space to 32bit, 1776 * irrespective of the underlying capabilities of the HW. 1777 */ 1778 if (!vms->highmem) { 1779 pa_bits = 32; 1780 } 1781 1782 /* 1783 * We compute the base of the high IO region depending on the 1784 * amount of initial and device memory. The device memory start/size 1785 * is aligned on 1GiB. We never put the high IO region below 256GiB 1786 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1787 * The device region size assumes 1GiB page max alignment per slot. 1788 */ 1789 device_memory_base = 1790 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1791 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1792 1793 /* Base address of the high IO region */ 1794 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1795 if (memtop > BIT_ULL(pa_bits)) { 1796 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n", 1797 pa_bits, memtop - BIT_ULL(pa_bits)); 1798 exit(EXIT_FAILURE); 1799 } 1800 if (base < device_memory_base) { 1801 error_report("maxmem/slots too huge"); 1802 exit(EXIT_FAILURE); 1803 } 1804 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1805 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1806 } 1807 1808 /* We know for sure that at least the memory fits in the PA space */ 1809 vms->highest_gpa = memtop - 1; 1810 1811 virt_set_high_memmap(vms, base, pa_bits); 1812 1813 if (device_memory_size > 0) { 1814 machine_memory_devices_init(ms, device_memory_base, device_memory_size); 1815 } 1816 } 1817 1818 static VirtGICType finalize_gic_version_do(const char *accel_name, 1819 VirtGICType gic_version, 1820 int gics_supported, 1821 unsigned int max_cpus) 1822 { 1823 /* Convert host/max/nosel to GIC version number */ 1824 switch (gic_version) { 1825 case VIRT_GIC_VERSION_HOST: 1826 if (!kvm_enabled()) { 1827 error_report("gic-version=host requires KVM"); 1828 exit(1); 1829 } 1830 1831 /* For KVM, gic-version=host means gic-version=max */ 1832 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX, 1833 gics_supported, max_cpus); 1834 case VIRT_GIC_VERSION_MAX: 1835 if (gics_supported & VIRT_GIC_VERSION_4_MASK) { 1836 gic_version = VIRT_GIC_VERSION_4; 1837 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1838 gic_version = VIRT_GIC_VERSION_3; 1839 } else { 1840 gic_version = VIRT_GIC_VERSION_2; 1841 } 1842 break; 1843 case VIRT_GIC_VERSION_NOSEL: 1844 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) && 1845 max_cpus <= GIC_NCPU) { 1846 gic_version = VIRT_GIC_VERSION_2; 1847 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1848 /* 1849 * in case the host does not support v2 emulation or 1850 * the end-user requested more than 8 VCPUs we now default 1851 * to v3. In any case defaulting to v2 would be broken. 1852 */ 1853 gic_version = VIRT_GIC_VERSION_3; 1854 } else if (max_cpus > GIC_NCPU) { 1855 error_report("%s only supports GICv2 emulation but more than 8 " 1856 "vcpus are requested", accel_name); 1857 exit(1); 1858 } 1859 break; 1860 case VIRT_GIC_VERSION_2: 1861 case VIRT_GIC_VERSION_3: 1862 case VIRT_GIC_VERSION_4: 1863 break; 1864 } 1865 1866 /* Check chosen version is effectively supported */ 1867 switch (gic_version) { 1868 case VIRT_GIC_VERSION_2: 1869 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) { 1870 error_report("%s does not support GICv2 emulation", accel_name); 1871 exit(1); 1872 } 1873 break; 1874 case VIRT_GIC_VERSION_3: 1875 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) { 1876 error_report("%s does not support GICv3 emulation", accel_name); 1877 exit(1); 1878 } 1879 break; 1880 case VIRT_GIC_VERSION_4: 1881 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) { 1882 error_report("%s does not support GICv4 emulation, is virtualization=on?", 1883 accel_name); 1884 exit(1); 1885 } 1886 break; 1887 default: 1888 error_report("logic error in finalize_gic_version"); 1889 exit(1); 1890 break; 1891 } 1892 1893 return gic_version; 1894 } 1895 1896 /* 1897 * finalize_gic_version - Determines the final gic_version 1898 * according to the gic-version property 1899 * 1900 * Default GIC type is v2 1901 */ 1902 static void finalize_gic_version(VirtMachineState *vms) 1903 { 1904 const char *accel_name = current_accel_name(); 1905 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 1906 int gics_supported = 0; 1907 1908 /* Determine which GIC versions the current environment supports */ 1909 if (kvm_enabled() && kvm_irqchip_in_kernel()) { 1910 int probe_bitmap = kvm_arm_vgic_probe(); 1911 1912 if (!probe_bitmap) { 1913 error_report("Unable to determine GIC version supported by host"); 1914 exit(1); 1915 } 1916 1917 if (probe_bitmap & KVM_ARM_VGIC_V2) { 1918 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1919 } 1920 if (probe_bitmap & KVM_ARM_VGIC_V3) { 1921 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1922 } 1923 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) { 1924 /* KVM w/o kernel irqchip can only deal with GICv2 */ 1925 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1926 accel_name = "KVM with kernel-irqchip=off"; 1927 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { 1928 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1929 if (module_object_class_by_name("arm-gicv3")) { 1930 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1931 if (vms->virt) { 1932 /* GICv4 only makes sense if CPU has EL2 */ 1933 gics_supported |= VIRT_GIC_VERSION_4_MASK; 1934 } 1935 } 1936 } else { 1937 error_report("Unsupported accelerator, can not determine GIC support"); 1938 exit(1); 1939 } 1940 1941 /* 1942 * Then convert helpers like host/max to concrete GIC versions and ensure 1943 * the desired version is supported 1944 */ 1945 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version, 1946 gics_supported, max_cpus); 1947 } 1948 1949 /* 1950 * virt_cpu_post_init() must be called after the CPUs have 1951 * been realized and the GIC has been created. 1952 */ 1953 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) 1954 { 1955 int max_cpus = MACHINE(vms)->smp.max_cpus; 1956 bool aarch64, pmu, steal_time; 1957 CPUState *cpu; 1958 1959 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); 1960 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); 1961 steal_time = object_property_get_bool(OBJECT(first_cpu), 1962 "kvm-steal-time", NULL); 1963 1964 if (kvm_enabled()) { 1965 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; 1966 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; 1967 1968 if (steal_time) { 1969 MemoryRegion *pvtime = g_new(MemoryRegion, 1); 1970 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; 1971 1972 /* The memory region size must be a multiple of host page size. */ 1973 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); 1974 1975 if (pvtime_size > pvtime_reg_size) { 1976 error_report("pvtime requires a %" HWADDR_PRId 1977 " byte memory region for %d CPUs," 1978 " but only %" HWADDR_PRId " has been reserved", 1979 pvtime_size, max_cpus, pvtime_reg_size); 1980 exit(1); 1981 } 1982 1983 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); 1984 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); 1985 } 1986 1987 CPU_FOREACH(cpu) { 1988 if (pmu) { 1989 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); 1990 if (kvm_irqchip_in_kernel()) { 1991 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 1992 } 1993 kvm_arm_pmu_init(cpu); 1994 } 1995 if (steal_time) { 1996 kvm_arm_pvtime_init(cpu, pvtime_reg_base + 1997 cpu->cpu_index * PVTIME_SIZE_PER_CPU); 1998 } 1999 } 2000 } else { 2001 if (aarch64 && vms->highmem) { 2002 int requested_pa_size = 64 - clz64(vms->highest_gpa); 2003 int pamax = arm_pamax(ARM_CPU(first_cpu)); 2004 2005 if (pamax < requested_pa_size) { 2006 error_report("VCPU supports less PA bits (%d) than " 2007 "requested by the memory map (%d)", 2008 pamax, requested_pa_size); 2009 exit(1); 2010 } 2011 } 2012 } 2013 } 2014 2015 static void machvirt_init(MachineState *machine) 2016 { 2017 VirtMachineState *vms = VIRT_MACHINE(machine); 2018 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 2019 MachineClass *mc = MACHINE_GET_CLASS(machine); 2020 const CPUArchIdList *possible_cpus; 2021 MemoryRegion *sysmem = get_system_memory(); 2022 MemoryRegion *secure_sysmem = NULL; 2023 MemoryRegion *tag_sysmem = NULL; 2024 MemoryRegion *secure_tag_sysmem = NULL; 2025 int n, virt_max_cpus; 2026 bool firmware_loaded; 2027 bool aarch64 = true; 2028 bool has_ged = !vmc->no_ged; 2029 unsigned int smp_cpus = machine->smp.cpus; 2030 unsigned int max_cpus = machine->smp.max_cpus; 2031 2032 if (!cpu_type_valid(machine->cpu_type)) { 2033 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 2034 exit(1); 2035 } 2036 2037 possible_cpus = mc->possible_cpu_arch_ids(machine); 2038 2039 /* 2040 * In accelerated mode, the memory map is computed earlier in kvm_type() 2041 * to create a VM with the right number of IPA bits. 2042 */ 2043 if (!vms->memmap) { 2044 Object *cpuobj; 2045 ARMCPU *armcpu; 2046 int pa_bits; 2047 2048 /* 2049 * Instantiate a temporary CPU object to find out about what 2050 * we are about to deal with. Once this is done, get rid of 2051 * the object. 2052 */ 2053 cpuobj = object_new(possible_cpus->cpus[0].type); 2054 armcpu = ARM_CPU(cpuobj); 2055 2056 pa_bits = arm_pamax(armcpu); 2057 2058 object_unref(cpuobj); 2059 2060 virt_set_memmap(vms, pa_bits); 2061 } 2062 2063 /* We can probe only here because during property set 2064 * KVM is not available yet 2065 */ 2066 finalize_gic_version(vms); 2067 2068 if (vms->secure) { 2069 /* 2070 * The Secure view of the world is the same as the NonSecure, 2071 * but with a few extra devices. Create it as a container region 2072 * containing the system memory at low priority; any secure-only 2073 * devices go in at higher priority and take precedence. 2074 */ 2075 secure_sysmem = g_new(MemoryRegion, 1); 2076 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 2077 UINT64_MAX); 2078 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 2079 } 2080 2081 firmware_loaded = virt_firmware_init(vms, sysmem, 2082 secure_sysmem ?: sysmem); 2083 2084 /* If we have an EL3 boot ROM then the assumption is that it will 2085 * implement PSCI itself, so disable QEMU's internal implementation 2086 * so it doesn't get in the way. Instead of starting secondary 2087 * CPUs in PSCI powerdown state we will start them all running and 2088 * let the boot ROM sort them out. 2089 * The usual case is that we do use QEMU's PSCI implementation; 2090 * if the guest has EL2 then we will use SMC as the conduit, 2091 * and otherwise we will use HVC (for backwards compatibility and 2092 * because if we're using KVM then we must use HVC). 2093 */ 2094 if (vms->secure && firmware_loaded) { 2095 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 2096 } else if (vms->virt) { 2097 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 2098 } else { 2099 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 2100 } 2101 2102 /* 2103 * The maximum number of CPUs depends on the GIC version, or on how 2104 * many redistributors we can fit into the memory map (which in turn 2105 * depends on whether this is a GICv3 or v4). 2106 */ 2107 if (vms->gic_version == VIRT_GIC_VERSION_2) { 2108 virt_max_cpus = GIC_NCPU; 2109 } else { 2110 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST); 2111 if (vms->highmem_redists) { 2112 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 2113 } 2114 } 2115 2116 if (max_cpus > virt_max_cpus) { 2117 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 2118 "supported by machine 'mach-virt' (%d)", 2119 max_cpus, virt_max_cpus); 2120 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) { 2121 error_printf("Try 'highmem-redists=on' for more CPUs\n"); 2122 } 2123 2124 exit(1); 2125 } 2126 2127 if (vms->secure && (kvm_enabled() || hvf_enabled())) { 2128 error_report("mach-virt: %s does not support providing " 2129 "Security extensions (TrustZone) to the guest CPU", 2130 current_accel_name()); 2131 exit(1); 2132 } 2133 2134 if (vms->virt && (kvm_enabled() || hvf_enabled())) { 2135 error_report("mach-virt: %s does not support providing " 2136 "Virtualization extensions to the guest CPU", 2137 current_accel_name()); 2138 exit(1); 2139 } 2140 2141 if (vms->mte && (kvm_enabled() || hvf_enabled())) { 2142 error_report("mach-virt: %s does not support providing " 2143 "MTE to the guest CPU", 2144 current_accel_name()); 2145 exit(1); 2146 } 2147 2148 create_fdt(vms); 2149 2150 assert(possible_cpus->len == max_cpus); 2151 for (n = 0; n < possible_cpus->len; n++) { 2152 Object *cpuobj; 2153 CPUState *cs; 2154 2155 if (n >= smp_cpus) { 2156 break; 2157 } 2158 2159 cpuobj = object_new(possible_cpus->cpus[n].type); 2160 object_property_set_int(cpuobj, "mp-affinity", 2161 possible_cpus->cpus[n].arch_id, NULL); 2162 2163 cs = CPU(cpuobj); 2164 cs->cpu_index = n; 2165 2166 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 2167 &error_fatal); 2168 2169 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 2170 2171 if (!vms->secure) { 2172 object_property_set_bool(cpuobj, "has_el3", false, NULL); 2173 } 2174 2175 if (!vms->virt && object_property_find(cpuobj, "has_el2")) { 2176 object_property_set_bool(cpuobj, "has_el2", false, NULL); 2177 } 2178 2179 if (vmc->kvm_no_adjvtime && 2180 object_property_find(cpuobj, "kvm-no-adjvtime")) { 2181 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 2182 } 2183 2184 if (vmc->no_kvm_steal_time && 2185 object_property_find(cpuobj, "kvm-steal-time")) { 2186 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); 2187 } 2188 2189 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { 2190 object_property_set_bool(cpuobj, "pmu", false, NULL); 2191 } 2192 2193 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { 2194 object_property_set_bool(cpuobj, "lpa2", false, NULL); 2195 } 2196 2197 if (object_property_find(cpuobj, "reset-cbar")) { 2198 object_property_set_int(cpuobj, "reset-cbar", 2199 vms->memmap[VIRT_CPUPERIPHS].base, 2200 &error_abort); 2201 } 2202 2203 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 2204 &error_abort); 2205 if (vms->secure) { 2206 object_property_set_link(cpuobj, "secure-memory", 2207 OBJECT(secure_sysmem), &error_abort); 2208 } 2209 2210 if (vms->mte) { 2211 /* Create the memory region only once, but link to all cpus. */ 2212 if (!tag_sysmem) { 2213 /* 2214 * The property exists only if MemTag is supported. 2215 * If it is, we must allocate the ram to back that up. 2216 */ 2217 if (!object_property_find(cpuobj, "tag-memory")) { 2218 error_report("MTE requested, but not supported " 2219 "by the guest CPU"); 2220 exit(1); 2221 } 2222 2223 tag_sysmem = g_new(MemoryRegion, 1); 2224 memory_region_init(tag_sysmem, OBJECT(machine), 2225 "tag-memory", UINT64_MAX / 32); 2226 2227 if (vms->secure) { 2228 secure_tag_sysmem = g_new(MemoryRegion, 1); 2229 memory_region_init(secure_tag_sysmem, OBJECT(machine), 2230 "secure-tag-memory", UINT64_MAX / 32); 2231 2232 /* As with ram, secure-tag takes precedence over tag. */ 2233 memory_region_add_subregion_overlap(secure_tag_sysmem, 0, 2234 tag_sysmem, -1); 2235 } 2236 } 2237 2238 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem), 2239 &error_abort); 2240 if (vms->secure) { 2241 object_property_set_link(cpuobj, "secure-tag-memory", 2242 OBJECT(secure_tag_sysmem), 2243 &error_abort); 2244 } 2245 } 2246 2247 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 2248 object_unref(cpuobj); 2249 } 2250 fdt_add_timer_nodes(vms); 2251 fdt_add_cpu_nodes(vms); 2252 2253 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 2254 machine->ram); 2255 2256 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 2257 2258 create_gic(vms, sysmem); 2259 2260 virt_cpu_post_init(vms, sysmem); 2261 2262 fdt_add_pmu_nodes(vms); 2263 2264 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 2265 2266 if (vms->secure) { 2267 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); 2268 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 2269 } 2270 2271 if (tag_sysmem) { 2272 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, 2273 machine->ram_size, "mach-virt.tag"); 2274 } 2275 2276 vms->highmem_ecam &= (!firmware_loaded || aarch64); 2277 2278 create_rtc(vms); 2279 2280 create_pcie(vms); 2281 2282 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 2283 vms->acpi_dev = create_acpi_ged(vms); 2284 } else { 2285 create_gpio_devices(vms, VIRT_GPIO, sysmem); 2286 } 2287 2288 if (vms->secure && !vmc->no_secure_gpio) { 2289 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); 2290 } 2291 2292 /* connect powerdown request */ 2293 vms->powerdown_notifier.notify = virt_powerdown_req; 2294 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 2295 2296 /* Create mmio transports, so the user can create virtio backends 2297 * (which will be automatically plugged in to the transports). If 2298 * no backend is created the transport will just sit harmlessly idle. 2299 */ 2300 create_virtio_devices(vms); 2301 2302 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 2303 rom_set_fw(vms->fw_cfg); 2304 2305 create_platform_bus(vms); 2306 2307 if (machine->nvdimms_state->is_enabled) { 2308 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 2309 .space_id = AML_AS_SYSTEM_MEMORY, 2310 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 2311 .bit_width = NVDIMM_ACPI_IO_LEN << 3 2312 }; 2313 2314 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 2315 arm_virt_nvdimm_acpi_dsmio, 2316 vms->fw_cfg, OBJECT(vms)); 2317 } 2318 2319 vms->bootinfo.ram_size = machine->ram_size; 2320 vms->bootinfo.board_id = -1; 2321 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 2322 vms->bootinfo.get_dtb = machvirt_dtb; 2323 vms->bootinfo.skip_dtb_autoload = true; 2324 vms->bootinfo.firmware_loaded = firmware_loaded; 2325 vms->bootinfo.psci_conduit = vms->psci_conduit; 2326 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 2327 2328 vms->machine_done.notify = virt_machine_done; 2329 qemu_add_machine_init_done_notifier(&vms->machine_done); 2330 } 2331 2332 static bool virt_get_secure(Object *obj, Error **errp) 2333 { 2334 VirtMachineState *vms = VIRT_MACHINE(obj); 2335 2336 return vms->secure; 2337 } 2338 2339 static void virt_set_secure(Object *obj, bool value, Error **errp) 2340 { 2341 VirtMachineState *vms = VIRT_MACHINE(obj); 2342 2343 vms->secure = value; 2344 } 2345 2346 static bool virt_get_virt(Object *obj, Error **errp) 2347 { 2348 VirtMachineState *vms = VIRT_MACHINE(obj); 2349 2350 return vms->virt; 2351 } 2352 2353 static void virt_set_virt(Object *obj, bool value, Error **errp) 2354 { 2355 VirtMachineState *vms = VIRT_MACHINE(obj); 2356 2357 vms->virt = value; 2358 } 2359 2360 static bool virt_get_highmem(Object *obj, Error **errp) 2361 { 2362 VirtMachineState *vms = VIRT_MACHINE(obj); 2363 2364 return vms->highmem; 2365 } 2366 2367 static void virt_set_highmem(Object *obj, bool value, Error **errp) 2368 { 2369 VirtMachineState *vms = VIRT_MACHINE(obj); 2370 2371 vms->highmem = value; 2372 } 2373 2374 static bool virt_get_compact_highmem(Object *obj, Error **errp) 2375 { 2376 VirtMachineState *vms = VIRT_MACHINE(obj); 2377 2378 return vms->highmem_compact; 2379 } 2380 2381 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp) 2382 { 2383 VirtMachineState *vms = VIRT_MACHINE(obj); 2384 2385 vms->highmem_compact = value; 2386 } 2387 2388 static bool virt_get_highmem_redists(Object *obj, Error **errp) 2389 { 2390 VirtMachineState *vms = VIRT_MACHINE(obj); 2391 2392 return vms->highmem_redists; 2393 } 2394 2395 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp) 2396 { 2397 VirtMachineState *vms = VIRT_MACHINE(obj); 2398 2399 vms->highmem_redists = value; 2400 } 2401 2402 static bool virt_get_highmem_ecam(Object *obj, Error **errp) 2403 { 2404 VirtMachineState *vms = VIRT_MACHINE(obj); 2405 2406 return vms->highmem_ecam; 2407 } 2408 2409 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp) 2410 { 2411 VirtMachineState *vms = VIRT_MACHINE(obj); 2412 2413 vms->highmem_ecam = value; 2414 } 2415 2416 static bool virt_get_highmem_mmio(Object *obj, Error **errp) 2417 { 2418 VirtMachineState *vms = VIRT_MACHINE(obj); 2419 2420 return vms->highmem_mmio; 2421 } 2422 2423 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp) 2424 { 2425 VirtMachineState *vms = VIRT_MACHINE(obj); 2426 2427 vms->highmem_mmio = value; 2428 } 2429 2430 2431 static bool virt_get_its(Object *obj, Error **errp) 2432 { 2433 VirtMachineState *vms = VIRT_MACHINE(obj); 2434 2435 return vms->its; 2436 } 2437 2438 static void virt_set_its(Object *obj, bool value, Error **errp) 2439 { 2440 VirtMachineState *vms = VIRT_MACHINE(obj); 2441 2442 vms->its = value; 2443 } 2444 2445 static bool virt_get_dtb_randomness(Object *obj, Error **errp) 2446 { 2447 VirtMachineState *vms = VIRT_MACHINE(obj); 2448 2449 return vms->dtb_randomness; 2450 } 2451 2452 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp) 2453 { 2454 VirtMachineState *vms = VIRT_MACHINE(obj); 2455 2456 vms->dtb_randomness = value; 2457 } 2458 2459 static char *virt_get_oem_id(Object *obj, Error **errp) 2460 { 2461 VirtMachineState *vms = VIRT_MACHINE(obj); 2462 2463 return g_strdup(vms->oem_id); 2464 } 2465 2466 static void virt_set_oem_id(Object *obj, const char *value, Error **errp) 2467 { 2468 VirtMachineState *vms = VIRT_MACHINE(obj); 2469 size_t len = strlen(value); 2470 2471 if (len > 6) { 2472 error_setg(errp, 2473 "User specified oem-id value is bigger than 6 bytes in size"); 2474 return; 2475 } 2476 2477 strncpy(vms->oem_id, value, 6); 2478 } 2479 2480 static char *virt_get_oem_table_id(Object *obj, Error **errp) 2481 { 2482 VirtMachineState *vms = VIRT_MACHINE(obj); 2483 2484 return g_strdup(vms->oem_table_id); 2485 } 2486 2487 static void virt_set_oem_table_id(Object *obj, const char *value, 2488 Error **errp) 2489 { 2490 VirtMachineState *vms = VIRT_MACHINE(obj); 2491 size_t len = strlen(value); 2492 2493 if (len > 8) { 2494 error_setg(errp, 2495 "User specified oem-table-id value is bigger than 8 bytes in size"); 2496 return; 2497 } 2498 strncpy(vms->oem_table_id, value, 8); 2499 } 2500 2501 2502 bool virt_is_acpi_enabled(VirtMachineState *vms) 2503 { 2504 if (vms->acpi == ON_OFF_AUTO_OFF) { 2505 return false; 2506 } 2507 return true; 2508 } 2509 2510 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 2511 void *opaque, Error **errp) 2512 { 2513 VirtMachineState *vms = VIRT_MACHINE(obj); 2514 OnOffAuto acpi = vms->acpi; 2515 2516 visit_type_OnOffAuto(v, name, &acpi, errp); 2517 } 2518 2519 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 2520 void *opaque, Error **errp) 2521 { 2522 VirtMachineState *vms = VIRT_MACHINE(obj); 2523 2524 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 2525 } 2526 2527 static bool virt_get_ras(Object *obj, Error **errp) 2528 { 2529 VirtMachineState *vms = VIRT_MACHINE(obj); 2530 2531 return vms->ras; 2532 } 2533 2534 static void virt_set_ras(Object *obj, bool value, Error **errp) 2535 { 2536 VirtMachineState *vms = VIRT_MACHINE(obj); 2537 2538 vms->ras = value; 2539 } 2540 2541 static bool virt_get_mte(Object *obj, Error **errp) 2542 { 2543 VirtMachineState *vms = VIRT_MACHINE(obj); 2544 2545 return vms->mte; 2546 } 2547 2548 static void virt_set_mte(Object *obj, bool value, Error **errp) 2549 { 2550 VirtMachineState *vms = VIRT_MACHINE(obj); 2551 2552 vms->mte = value; 2553 } 2554 2555 static char *virt_get_gic_version(Object *obj, Error **errp) 2556 { 2557 VirtMachineState *vms = VIRT_MACHINE(obj); 2558 const char *val; 2559 2560 switch (vms->gic_version) { 2561 case VIRT_GIC_VERSION_4: 2562 val = "4"; 2563 break; 2564 case VIRT_GIC_VERSION_3: 2565 val = "3"; 2566 break; 2567 default: 2568 val = "2"; 2569 break; 2570 } 2571 return g_strdup(val); 2572 } 2573 2574 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2575 { 2576 VirtMachineState *vms = VIRT_MACHINE(obj); 2577 2578 if (!strcmp(value, "4")) { 2579 vms->gic_version = VIRT_GIC_VERSION_4; 2580 } else if (!strcmp(value, "3")) { 2581 vms->gic_version = VIRT_GIC_VERSION_3; 2582 } else if (!strcmp(value, "2")) { 2583 vms->gic_version = VIRT_GIC_VERSION_2; 2584 } else if (!strcmp(value, "host")) { 2585 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2586 } else if (!strcmp(value, "max")) { 2587 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2588 } else { 2589 error_setg(errp, "Invalid gic-version value"); 2590 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2591 } 2592 } 2593 2594 static char *virt_get_iommu(Object *obj, Error **errp) 2595 { 2596 VirtMachineState *vms = VIRT_MACHINE(obj); 2597 2598 switch (vms->iommu) { 2599 case VIRT_IOMMU_NONE: 2600 return g_strdup("none"); 2601 case VIRT_IOMMU_SMMUV3: 2602 return g_strdup("smmuv3"); 2603 default: 2604 g_assert_not_reached(); 2605 } 2606 } 2607 2608 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2609 { 2610 VirtMachineState *vms = VIRT_MACHINE(obj); 2611 2612 if (!strcmp(value, "smmuv3")) { 2613 vms->iommu = VIRT_IOMMU_SMMUV3; 2614 } else if (!strcmp(value, "none")) { 2615 vms->iommu = VIRT_IOMMU_NONE; 2616 } else { 2617 error_setg(errp, "Invalid iommu value"); 2618 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2619 } 2620 } 2621 2622 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp) 2623 { 2624 VirtMachineState *vms = VIRT_MACHINE(obj); 2625 2626 return vms->default_bus_bypass_iommu; 2627 } 2628 2629 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value, 2630 Error **errp) 2631 { 2632 VirtMachineState *vms = VIRT_MACHINE(obj); 2633 2634 vms->default_bus_bypass_iommu = value; 2635 } 2636 2637 static CpuInstanceProperties 2638 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2639 { 2640 MachineClass *mc = MACHINE_GET_CLASS(ms); 2641 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2642 2643 assert(cpu_index < possible_cpus->len); 2644 return possible_cpus->cpus[cpu_index].props; 2645 } 2646 2647 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2648 { 2649 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 2650 2651 return socket_id % ms->numa_state->num_nodes; 2652 } 2653 2654 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2655 { 2656 int n; 2657 unsigned int max_cpus = ms->smp.max_cpus; 2658 VirtMachineState *vms = VIRT_MACHINE(ms); 2659 MachineClass *mc = MACHINE_GET_CLASS(vms); 2660 2661 if (ms->possible_cpus) { 2662 assert(ms->possible_cpus->len == max_cpus); 2663 return ms->possible_cpus; 2664 } 2665 2666 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2667 sizeof(CPUArchId) * max_cpus); 2668 ms->possible_cpus->len = max_cpus; 2669 for (n = 0; n < ms->possible_cpus->len; n++) { 2670 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2671 ms->possible_cpus->cpus[n].arch_id = 2672 virt_cpu_mp_affinity(vms, n); 2673 2674 assert(!mc->smp_props.dies_supported); 2675 ms->possible_cpus->cpus[n].props.has_socket_id = true; 2676 ms->possible_cpus->cpus[n].props.socket_id = 2677 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); 2678 ms->possible_cpus->cpus[n].props.has_cluster_id = true; 2679 ms->possible_cpus->cpus[n].props.cluster_id = 2680 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; 2681 ms->possible_cpus->cpus[n].props.has_core_id = true; 2682 ms->possible_cpus->cpus[n].props.core_id = 2683 (n / ms->smp.threads) % ms->smp.cores; 2684 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2685 ms->possible_cpus->cpus[n].props.thread_id = 2686 n % ms->smp.threads; 2687 } 2688 return ms->possible_cpus; 2689 } 2690 2691 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2692 Error **errp) 2693 { 2694 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2695 const MachineState *ms = MACHINE(hotplug_dev); 2696 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2697 2698 if (!vms->acpi_dev) { 2699 error_setg(errp, 2700 "memory hotplug is not enabled: missing acpi-ged device"); 2701 return; 2702 } 2703 2704 if (vms->mte) { 2705 error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); 2706 return; 2707 } 2708 2709 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2710 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2711 return; 2712 } 2713 2714 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 2715 } 2716 2717 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2718 DeviceState *dev, Error **errp) 2719 { 2720 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2721 MachineState *ms = MACHINE(hotplug_dev); 2722 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2723 2724 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); 2725 2726 if (is_nvdimm) { 2727 nvdimm_plug(ms->nvdimms_state); 2728 } 2729 2730 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2731 dev, &error_abort); 2732 } 2733 2734 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2735 DeviceState *dev, Error **errp) 2736 { 2737 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2738 2739 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2740 virt_memory_pre_plug(hotplug_dev, dev, errp); 2741 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2742 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2743 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2744 hwaddr db_start = 0, db_end = 0; 2745 char *resv_prop_str; 2746 2747 if (vms->iommu != VIRT_IOMMU_NONE) { 2748 error_setg(errp, "virt machine does not support multiple IOMMUs"); 2749 return; 2750 } 2751 2752 switch (vms->msi_controller) { 2753 case VIRT_MSI_CTRL_NONE: 2754 return; 2755 case VIRT_MSI_CTRL_ITS: 2756 /* GITS_TRANSLATER page */ 2757 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; 2758 db_end = base_memmap[VIRT_GIC_ITS].base + 2759 base_memmap[VIRT_GIC_ITS].size - 1; 2760 break; 2761 case VIRT_MSI_CTRL_GICV2M: 2762 /* MSI_SETSPI_NS page */ 2763 db_start = base_memmap[VIRT_GIC_V2M].base; 2764 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; 2765 break; 2766 } 2767 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", 2768 db_start, db_end, 2769 VIRTIO_IOMMU_RESV_MEM_T_MSI); 2770 2771 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 2772 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 2773 resv_prop_str, errp); 2774 g_free(resv_prop_str); 2775 } 2776 } 2777 2778 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2779 DeviceState *dev, Error **errp) 2780 { 2781 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2782 2783 if (vms->platform_bus_dev) { 2784 MachineClass *mc = MACHINE_GET_CLASS(vms); 2785 2786 if (device_is_dynamic_sysbus(mc, dev)) { 2787 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2788 SYS_BUS_DEVICE(dev)); 2789 } 2790 } 2791 2792 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2793 virt_memory_plug(hotplug_dev, dev, errp); 2794 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2795 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2796 } 2797 2798 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2799 PCIDevice *pdev = PCI_DEVICE(dev); 2800 2801 vms->iommu = VIRT_IOMMU_VIRTIO; 2802 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2803 create_virtio_iommu_dt_bindings(vms); 2804 } 2805 } 2806 2807 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, 2808 DeviceState *dev, Error **errp) 2809 { 2810 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2811 2812 if (!vms->acpi_dev) { 2813 error_setg(errp, 2814 "memory hotplug is not enabled: missing acpi-ged device"); 2815 return; 2816 } 2817 2818 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2819 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 2820 return; 2821 } 2822 2823 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, 2824 errp); 2825 } 2826 2827 static void virt_dimm_unplug(HotplugHandler *hotplug_dev, 2828 DeviceState *dev, Error **errp) 2829 { 2830 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2831 Error *local_err = NULL; 2832 2833 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); 2834 if (local_err) { 2835 goto out; 2836 } 2837 2838 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); 2839 qdev_unrealize(dev); 2840 2841 out: 2842 error_propagate(errp, local_err); 2843 } 2844 2845 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2846 DeviceState *dev, Error **errp) 2847 { 2848 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2849 virt_dimm_unplug_request(hotplug_dev, dev, errp); 2850 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2851 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 2852 errp); 2853 } else { 2854 error_setg(errp, "device unplug request for unsupported device" 2855 " type: %s", object_get_typename(OBJECT(dev))); 2856 } 2857 } 2858 2859 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2860 DeviceState *dev, Error **errp) 2861 { 2862 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2863 virt_dimm_unplug(hotplug_dev, dev, errp); 2864 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2865 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2866 } else { 2867 error_setg(errp, "virt: device unplug for unsupported device" 2868 " type: %s", object_get_typename(OBJECT(dev))); 2869 } 2870 } 2871 2872 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2873 DeviceState *dev) 2874 { 2875 MachineClass *mc = MACHINE_GET_CLASS(machine); 2876 2877 if (device_is_dynamic_sysbus(mc, dev) || 2878 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2879 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 2880 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2881 return HOTPLUG_HANDLER(machine); 2882 } 2883 return NULL; 2884 } 2885 2886 /* 2887 * for arm64 kvm_type [7-0] encodes the requested number of bits 2888 * in the IPA address space 2889 */ 2890 static int virt_kvm_type(MachineState *ms, const char *type_str) 2891 { 2892 VirtMachineState *vms = VIRT_MACHINE(ms); 2893 int max_vm_pa_size, requested_pa_size; 2894 bool fixed_ipa; 2895 2896 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 2897 2898 /* we freeze the memory map to compute the highest gpa */ 2899 virt_set_memmap(vms, max_vm_pa_size); 2900 2901 requested_pa_size = 64 - clz64(vms->highest_gpa); 2902 2903 /* 2904 * KVM requires the IPA size to be at least 32 bits. 2905 */ 2906 if (requested_pa_size < 32) { 2907 requested_pa_size = 32; 2908 } 2909 2910 if (requested_pa_size > max_vm_pa_size) { 2911 error_report("-m and ,maxmem option values " 2912 "require an IPA range (%d bits) larger than " 2913 "the one supported by the host (%d bits)", 2914 requested_pa_size, max_vm_pa_size); 2915 return -1; 2916 } 2917 /* 2918 * We return the requested PA log size, unless KVM only supports 2919 * the implicit legacy 40b IPA setting, in which case the kvm_type 2920 * must be 0. 2921 */ 2922 return fixed_ipa ? 0 : requested_pa_size; 2923 } 2924 2925 static void virt_machine_class_init(ObjectClass *oc, void *data) 2926 { 2927 MachineClass *mc = MACHINE_CLASS(oc); 2928 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2929 2930 mc->init = machvirt_init; 2931 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 2932 * The value may be reduced later when we have more information about the 2933 * configuration of the particular instance. 2934 */ 2935 mc->max_cpus = 512; 2936 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 2937 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 2938 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 2939 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 2940 #ifdef CONFIG_TPM 2941 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 2942 #endif 2943 mc->block_default_type = IF_VIRTIO; 2944 mc->no_cdrom = 1; 2945 mc->pci_allow_0_address = true; 2946 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 2947 mc->minimum_page_bits = 12; 2948 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 2949 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 2950 #ifdef CONFIG_TCG 2951 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 2952 #else 2953 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); 2954 #endif 2955 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 2956 mc->kvm_type = virt_kvm_type; 2957 assert(!mc->get_hotplug_handler); 2958 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 2959 hc->pre_plug = virt_machine_device_pre_plug_cb; 2960 hc->plug = virt_machine_device_plug_cb; 2961 hc->unplug_request = virt_machine_device_unplug_request_cb; 2962 hc->unplug = virt_machine_device_unplug_cb; 2963 mc->nvdimm_supported = true; 2964 mc->smp_props.clusters_supported = true; 2965 mc->auto_enable_numa_with_memhp = true; 2966 mc->auto_enable_numa_with_memdev = true; 2967 /* platform instead of architectural choice */ 2968 mc->cpu_cluster_has_numa_boundary = true; 2969 mc->default_ram_id = "mach-virt.ram"; 2970 mc->default_nic = "virtio-net-pci"; 2971 2972 object_class_property_add(oc, "acpi", "OnOffAuto", 2973 virt_get_acpi, virt_set_acpi, 2974 NULL, NULL); 2975 object_class_property_set_description(oc, "acpi", 2976 "Enable ACPI"); 2977 object_class_property_add_bool(oc, "secure", virt_get_secure, 2978 virt_set_secure); 2979 object_class_property_set_description(oc, "secure", 2980 "Set on/off to enable/disable the ARM " 2981 "Security Extensions (TrustZone)"); 2982 2983 object_class_property_add_bool(oc, "virtualization", virt_get_virt, 2984 virt_set_virt); 2985 object_class_property_set_description(oc, "virtualization", 2986 "Set on/off to enable/disable emulating a " 2987 "guest CPU which implements the ARM " 2988 "Virtualization Extensions"); 2989 2990 object_class_property_add_bool(oc, "highmem", virt_get_highmem, 2991 virt_set_highmem); 2992 object_class_property_set_description(oc, "highmem", 2993 "Set on/off to enable/disable using " 2994 "physical address space above 32 bits"); 2995 2996 object_class_property_add_bool(oc, "compact-highmem", 2997 virt_get_compact_highmem, 2998 virt_set_compact_highmem); 2999 object_class_property_set_description(oc, "compact-highmem", 3000 "Set on/off to enable/disable compact " 3001 "layout for high memory regions"); 3002 3003 object_class_property_add_bool(oc, "highmem-redists", 3004 virt_get_highmem_redists, 3005 virt_set_highmem_redists); 3006 object_class_property_set_description(oc, "highmem-redists", 3007 "Set on/off to enable/disable high " 3008 "memory region for GICv3 or GICv4 " 3009 "redistributor"); 3010 3011 object_class_property_add_bool(oc, "highmem-ecam", 3012 virt_get_highmem_ecam, 3013 virt_set_highmem_ecam); 3014 object_class_property_set_description(oc, "highmem-ecam", 3015 "Set on/off to enable/disable high " 3016 "memory region for PCI ECAM"); 3017 3018 object_class_property_add_bool(oc, "highmem-mmio", 3019 virt_get_highmem_mmio, 3020 virt_set_highmem_mmio); 3021 object_class_property_set_description(oc, "highmem-mmio", 3022 "Set on/off to enable/disable high " 3023 "memory region for PCI MMIO"); 3024 3025 object_class_property_add_str(oc, "gic-version", virt_get_gic_version, 3026 virt_set_gic_version); 3027 object_class_property_set_description(oc, "gic-version", 3028 "Set GIC version. " 3029 "Valid values are 2, 3, 4, host and max"); 3030 3031 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); 3032 object_class_property_set_description(oc, "iommu", 3033 "Set the IOMMU type. " 3034 "Valid values are none and smmuv3"); 3035 3036 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 3037 virt_get_default_bus_bypass_iommu, 3038 virt_set_default_bus_bypass_iommu); 3039 object_class_property_set_description(oc, "default-bus-bypass-iommu", 3040 "Set on/off to enable/disable " 3041 "bypass_iommu for default root bus"); 3042 3043 object_class_property_add_bool(oc, "ras", virt_get_ras, 3044 virt_set_ras); 3045 object_class_property_set_description(oc, "ras", 3046 "Set on/off to enable/disable reporting host memory errors " 3047 "to a KVM guest using ACPI and guest external abort exceptions"); 3048 3049 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); 3050 object_class_property_set_description(oc, "mte", 3051 "Set on/off to enable/disable emulating a " 3052 "guest CPU which implements the ARM " 3053 "Memory Tagging Extension"); 3054 3055 object_class_property_add_bool(oc, "its", virt_get_its, 3056 virt_set_its); 3057 object_class_property_set_description(oc, "its", 3058 "Set on/off to enable/disable " 3059 "ITS instantiation"); 3060 3061 object_class_property_add_bool(oc, "dtb-randomness", 3062 virt_get_dtb_randomness, 3063 virt_set_dtb_randomness); 3064 object_class_property_set_description(oc, "dtb-randomness", 3065 "Set off to disable passing random or " 3066 "non-deterministic dtb nodes to guest"); 3067 3068 object_class_property_add_bool(oc, "dtb-kaslr-seed", 3069 virt_get_dtb_randomness, 3070 virt_set_dtb_randomness); 3071 object_class_property_set_description(oc, "dtb-kaslr-seed", 3072 "Deprecated synonym of dtb-randomness"); 3073 3074 object_class_property_add_str(oc, "x-oem-id", 3075 virt_get_oem_id, 3076 virt_set_oem_id); 3077 object_class_property_set_description(oc, "x-oem-id", 3078 "Override the default value of field OEMID " 3079 "in ACPI table header." 3080 "The string may be up to 6 bytes in size"); 3081 3082 3083 object_class_property_add_str(oc, "x-oem-table-id", 3084 virt_get_oem_table_id, 3085 virt_set_oem_table_id); 3086 object_class_property_set_description(oc, "x-oem-table-id", 3087 "Override the default value of field OEM Table ID " 3088 "in ACPI table header." 3089 "The string may be up to 8 bytes in size"); 3090 3091 } 3092 3093 static void virt_instance_init(Object *obj) 3094 { 3095 VirtMachineState *vms = VIRT_MACHINE(obj); 3096 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 3097 3098 /* EL3 is disabled by default on virt: this makes us consistent 3099 * between KVM and TCG for this board, and it also allows us to 3100 * boot UEFI blobs which assume no TrustZone support. 3101 */ 3102 vms->secure = false; 3103 3104 /* EL2 is also disabled by default, for similar reasons */ 3105 vms->virt = false; 3106 3107 /* High memory is enabled by default */ 3108 vms->highmem = true; 3109 vms->highmem_compact = !vmc->no_highmem_compact; 3110 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 3111 3112 vms->highmem_ecam = !vmc->no_highmem_ecam; 3113 vms->highmem_mmio = true; 3114 vms->highmem_redists = true; 3115 3116 if (vmc->no_its) { 3117 vms->its = false; 3118 } else { 3119 /* Default allows ITS instantiation */ 3120 vms->its = true; 3121 3122 if (vmc->no_tcg_its) { 3123 vms->tcg_its = false; 3124 } else { 3125 vms->tcg_its = true; 3126 } 3127 } 3128 3129 /* Default disallows iommu instantiation */ 3130 vms->iommu = VIRT_IOMMU_NONE; 3131 3132 /* The default root bus is attached to iommu by default */ 3133 vms->default_bus_bypass_iommu = false; 3134 3135 /* Default disallows RAS instantiation */ 3136 vms->ras = false; 3137 3138 /* MTE is disabled by default. */ 3139 vms->mte = false; 3140 3141 /* Supply kaslr-seed and rng-seed by default */ 3142 vms->dtb_randomness = true; 3143 3144 vms->irqmap = a15irqmap; 3145 3146 virt_flash_create(vms); 3147 3148 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 3149 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 3150 } 3151 3152 static const TypeInfo virt_machine_info = { 3153 .name = TYPE_VIRT_MACHINE, 3154 .parent = TYPE_MACHINE, 3155 .abstract = true, 3156 .instance_size = sizeof(VirtMachineState), 3157 .class_size = sizeof(VirtMachineClass), 3158 .class_init = virt_machine_class_init, 3159 .instance_init = virt_instance_init, 3160 .interfaces = (InterfaceInfo[]) { 3161 { TYPE_HOTPLUG_HANDLER }, 3162 { } 3163 }, 3164 }; 3165 3166 static void machvirt_machine_init(void) 3167 { 3168 type_register_static(&virt_machine_info); 3169 } 3170 type_init(machvirt_machine_init); 3171 3172 static void virt_machine_8_2_options(MachineClass *mc) 3173 { 3174 } 3175 DEFINE_VIRT_MACHINE_AS_LATEST(8, 2) 3176 3177 static void virt_machine_8_1_options(MachineClass *mc) 3178 { 3179 virt_machine_8_2_options(mc); 3180 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len); 3181 } 3182 DEFINE_VIRT_MACHINE(8, 1) 3183 3184 static void virt_machine_8_0_options(MachineClass *mc) 3185 { 3186 virt_machine_8_1_options(mc); 3187 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 3188 } 3189 DEFINE_VIRT_MACHINE(8, 0) 3190 3191 static void virt_machine_7_2_options(MachineClass *mc) 3192 { 3193 virt_machine_8_0_options(mc); 3194 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 3195 } 3196 DEFINE_VIRT_MACHINE(7, 2) 3197 3198 static void virt_machine_7_1_options(MachineClass *mc) 3199 { 3200 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3201 3202 virt_machine_7_2_options(mc); 3203 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 3204 /* Compact layout for high memory regions was introduced with 7.2 */ 3205 vmc->no_highmem_compact = true; 3206 } 3207 DEFINE_VIRT_MACHINE(7, 1) 3208 3209 static void virt_machine_7_0_options(MachineClass *mc) 3210 { 3211 virt_machine_7_1_options(mc); 3212 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 3213 } 3214 DEFINE_VIRT_MACHINE(7, 0) 3215 3216 static void virt_machine_6_2_options(MachineClass *mc) 3217 { 3218 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3219 3220 virt_machine_7_0_options(mc); 3221 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 3222 vmc->no_tcg_lpa2 = true; 3223 } 3224 DEFINE_VIRT_MACHINE(6, 2) 3225 3226 static void virt_machine_6_1_options(MachineClass *mc) 3227 { 3228 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3229 3230 virt_machine_6_2_options(mc); 3231 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 3232 mc->smp_props.prefer_sockets = true; 3233 vmc->no_cpu_topology = true; 3234 3235 /* qemu ITS was introduced with 6.2 */ 3236 vmc->no_tcg_its = true; 3237 } 3238 DEFINE_VIRT_MACHINE(6, 1) 3239 3240 static void virt_machine_6_0_options(MachineClass *mc) 3241 { 3242 virt_machine_6_1_options(mc); 3243 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 3244 } 3245 DEFINE_VIRT_MACHINE(6, 0) 3246 3247 static void virt_machine_5_2_options(MachineClass *mc) 3248 { 3249 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3250 3251 virt_machine_6_0_options(mc); 3252 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 3253 vmc->no_secure_gpio = true; 3254 } 3255 DEFINE_VIRT_MACHINE(5, 2) 3256 3257 static void virt_machine_5_1_options(MachineClass *mc) 3258 { 3259 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3260 3261 virt_machine_5_2_options(mc); 3262 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 3263 vmc->no_kvm_steal_time = true; 3264 } 3265 DEFINE_VIRT_MACHINE(5, 1) 3266 3267 static void virt_machine_5_0_options(MachineClass *mc) 3268 { 3269 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3270 3271 virt_machine_5_1_options(mc); 3272 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 3273 mc->numa_mem_supported = true; 3274 vmc->acpi_expose_flash = true; 3275 mc->auto_enable_numa_with_memdev = false; 3276 } 3277 DEFINE_VIRT_MACHINE(5, 0) 3278 3279 static void virt_machine_4_2_options(MachineClass *mc) 3280 { 3281 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3282 3283 virt_machine_5_0_options(mc); 3284 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 3285 vmc->kvm_no_adjvtime = true; 3286 } 3287 DEFINE_VIRT_MACHINE(4, 2) 3288 3289 static void virt_machine_4_1_options(MachineClass *mc) 3290 { 3291 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3292 3293 virt_machine_4_2_options(mc); 3294 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 3295 vmc->no_ged = true; 3296 mc->auto_enable_numa_with_memhp = false; 3297 } 3298 DEFINE_VIRT_MACHINE(4, 1) 3299 3300 static void virt_machine_4_0_options(MachineClass *mc) 3301 { 3302 virt_machine_4_1_options(mc); 3303 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 3304 } 3305 DEFINE_VIRT_MACHINE(4, 0) 3306 3307 static void virt_machine_3_1_options(MachineClass *mc) 3308 { 3309 virt_machine_4_0_options(mc); 3310 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 3311 } 3312 DEFINE_VIRT_MACHINE(3, 1) 3313 3314 static void virt_machine_3_0_options(MachineClass *mc) 3315 { 3316 virt_machine_3_1_options(mc); 3317 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 3318 } 3319 DEFINE_VIRT_MACHINE(3, 0) 3320 3321 static void virt_machine_2_12_options(MachineClass *mc) 3322 { 3323 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3324 3325 virt_machine_3_0_options(mc); 3326 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 3327 vmc->no_highmem_ecam = true; 3328 mc->max_cpus = 255; 3329 } 3330 DEFINE_VIRT_MACHINE(2, 12) 3331 3332 static void virt_machine_2_11_options(MachineClass *mc) 3333 { 3334 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3335 3336 virt_machine_2_12_options(mc); 3337 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 3338 vmc->smbios_old_sys_ver = true; 3339 } 3340 DEFINE_VIRT_MACHINE(2, 11) 3341 3342 static void virt_machine_2_10_options(MachineClass *mc) 3343 { 3344 virt_machine_2_11_options(mc); 3345 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 3346 /* before 2.11 we never faulted accesses to bad addresses */ 3347 mc->ignore_memory_transaction_failures = true; 3348 } 3349 DEFINE_VIRT_MACHINE(2, 10) 3350 3351 static void virt_machine_2_9_options(MachineClass *mc) 3352 { 3353 virt_machine_2_10_options(mc); 3354 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 3355 } 3356 DEFINE_VIRT_MACHINE(2, 9) 3357 3358 static void virt_machine_2_8_options(MachineClass *mc) 3359 { 3360 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3361 3362 virt_machine_2_9_options(mc); 3363 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 3364 /* For 2.8 and earlier we falsely claimed in the DT that 3365 * our timers were edge-triggered, not level-triggered. 3366 */ 3367 vmc->claim_edge_triggered_timers = true; 3368 } 3369 DEFINE_VIRT_MACHINE(2, 8) 3370 3371 static void virt_machine_2_7_options(MachineClass *mc) 3372 { 3373 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3374 3375 virt_machine_2_8_options(mc); 3376 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 3377 /* ITS was introduced with 2.8 */ 3378 vmc->no_its = true; 3379 /* Stick with 1K pages for migration compatibility */ 3380 mc->minimum_page_bits = 0; 3381 } 3382 DEFINE_VIRT_MACHINE(2, 7) 3383 3384 static void virt_machine_2_6_options(MachineClass *mc) 3385 { 3386 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3387 3388 virt_machine_2_7_options(mc); 3389 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 3390 vmc->disallow_affinity_adjustment = true; 3391 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 3392 vmc->no_pmu = true; 3393 } 3394 DEFINE_VIRT_MACHINE(2, 6) 3395