1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qapi/error.h" 33 #include "hw/sysbus.h" 34 #include "hw/arm/arm.h" 35 #include "hw/arm/primecell.h" 36 #include "hw/arm/virt.h" 37 #include "hw/vfio/vfio-calxeda-xgmac.h" 38 #include "hw/vfio/vfio-amd-xgbe.h" 39 #include "hw/devices.h" 40 #include "net/net.h" 41 #include "sysemu/block-backend.h" 42 #include "sysemu/device_tree.h" 43 #include "sysemu/numa.h" 44 #include "sysemu/sysemu.h" 45 #include "sysemu/kvm.h" 46 #include "hw/compat.h" 47 #include "hw/loader.h" 48 #include "exec/address-spaces.h" 49 #include "qemu/bitops.h" 50 #include "qemu/error-report.h" 51 #include "hw/pci-host/gpex.h" 52 #include "hw/arm/sysbus-fdt.h" 53 #include "hw/platform-bus.h" 54 #include "hw/arm/fdt.h" 55 #include "hw/intc/arm_gic.h" 56 #include "hw/intc/arm_gicv3_common.h" 57 #include "kvm_arm.h" 58 #include "hw/smbios/smbios.h" 59 #include "qapi/visitor.h" 60 #include "standard-headers/linux/input.h" 61 62 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 63 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 64 void *data) \ 65 { \ 66 MachineClass *mc = MACHINE_CLASS(oc); \ 67 virt_machine_##major##_##minor##_options(mc); \ 68 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 69 if (latest) { \ 70 mc->alias = "virt"; \ 71 } \ 72 } \ 73 static const TypeInfo machvirt_##major##_##minor##_info = { \ 74 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 75 .parent = TYPE_VIRT_MACHINE, \ 76 .instance_init = virt_##major##_##minor##_instance_init, \ 77 .class_init = virt_##major##_##minor##_class_init, \ 78 }; \ 79 static void machvirt_machine_##major##_##minor##_init(void) \ 80 { \ 81 type_register_static(&machvirt_##major##_##minor##_info); \ 82 } \ 83 type_init(machvirt_machine_##major##_##minor##_init); 84 85 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 86 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 87 #define DEFINE_VIRT_MACHINE(major, minor) \ 88 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 89 90 91 /* Number of external interrupt lines to configure the GIC with */ 92 #define NUM_IRQS 256 93 94 #define PLATFORM_BUS_NUM_IRQS 64 95 96 static ARMPlatformBusSystemParams platform_bus_params; 97 98 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means 99 * RAM can go up to the 256GB mark, leaving 256GB of the physical 100 * address space unallocated and free for future use between 256G and 512G. 101 * If we need to provide more RAM to VMs in the future then we need to: 102 * * allocate a second bank of RAM starting at 2TB and working up 103 * * fix the DT and ACPI table generation code in QEMU to correctly 104 * report two split lumps of RAM to the guest 105 * * fix KVM in the host kernel to allow guests with >40 bit address spaces 106 * (We don't want to fill all the way up to 512GB with RAM because 107 * we might want it for non-RAM purposes later. Conversely it seems 108 * reasonable to assume that anybody configuring a VM with a quarter 109 * of a terabyte of RAM will be doing it on a host with more than a 110 * terabyte of physical address space.) 111 */ 112 #define RAMLIMIT_GB 255 113 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) 114 115 /* Addresses and sizes of our components. 116 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 117 * 128MB..256MB is used for miscellaneous device I/O. 118 * 256MB..1GB is reserved for possible future PCI support (ie where the 119 * PCI memory window will go if we add a PCI host controller). 120 * 1GB and up is RAM (which may happily spill over into the 121 * high memory region beyond 4GB). 122 * This represents a compromise between how much RAM can be given to 123 * a 32 bit VM and leaving space for expansion and in particular for PCI. 124 * Note that devices should generally be placed at multiples of 0x10000, 125 * to accommodate guests using 64K pages. 126 */ 127 static const MemMapEntry a15memmap[] = { 128 /* Space up to 0x8000000 is reserved for a boot ROM */ 129 [VIRT_FLASH] = { 0, 0x08000000 }, 130 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 131 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 132 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 133 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 134 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 135 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 136 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 137 /* This redistributor space allows up to 2*64kB*123 CPUs */ 138 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 139 [VIRT_UART] = { 0x09000000, 0x00001000 }, 140 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 141 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 142 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 143 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 144 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 145 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 146 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 147 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 148 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 149 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 150 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 151 [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES }, 152 /* Second PCIe window, 512GB wide at the 512GB boundary */ 153 [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL }, 154 }; 155 156 static const int a15irqmap[] = { 157 [VIRT_UART] = 1, 158 [VIRT_RTC] = 2, 159 [VIRT_PCIE] = 3, /* ... to 6 */ 160 [VIRT_GPIO] = 7, 161 [VIRT_SECURE_UART] = 8, 162 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 163 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 164 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 165 }; 166 167 static const char *valid_cpus[] = { 168 ARM_CPU_TYPE_NAME("cortex-a15"), 169 ARM_CPU_TYPE_NAME("cortex-a53"), 170 ARM_CPU_TYPE_NAME("cortex-a57"), 171 ARM_CPU_TYPE_NAME("host"), 172 ARM_CPU_TYPE_NAME("max"), 173 }; 174 175 static bool cpu_type_valid(const char *cpu) 176 { 177 int i; 178 179 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 180 if (strcmp(cpu, valid_cpus[i]) == 0) { 181 return true; 182 } 183 } 184 return false; 185 } 186 187 static void create_fdt(VirtMachineState *vms) 188 { 189 void *fdt = create_device_tree(&vms->fdt_size); 190 191 if (!fdt) { 192 error_report("create_device_tree() failed"); 193 exit(1); 194 } 195 196 vms->fdt = fdt; 197 198 /* Header */ 199 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 200 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 201 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 202 203 /* 204 * /chosen and /memory nodes must exist for load_dtb 205 * to fill in necessary properties later 206 */ 207 qemu_fdt_add_subnode(fdt, "/chosen"); 208 qemu_fdt_add_subnode(fdt, "/memory"); 209 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 210 211 /* Clock node, for the benefit of the UART. The kernel device tree 212 * binding documentation claims the PL011 node clock properties are 213 * optional but in practice if you omit them the kernel refuses to 214 * probe for the device. 215 */ 216 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 217 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 218 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 219 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 220 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 221 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 222 "clk24mhz"); 223 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 224 225 if (have_numa_distance) { 226 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 227 uint32_t *matrix = g_malloc0(size); 228 int idx, i, j; 229 230 for (i = 0; i < nb_numa_nodes; i++) { 231 for (j = 0; j < nb_numa_nodes; j++) { 232 idx = (i * nb_numa_nodes + j) * 3; 233 matrix[idx + 0] = cpu_to_be32(i); 234 matrix[idx + 1] = cpu_to_be32(j); 235 matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]); 236 } 237 } 238 239 qemu_fdt_add_subnode(fdt, "/distance-map"); 240 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 241 "numa-distance-map-v1"); 242 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 243 matrix, size); 244 g_free(matrix); 245 } 246 } 247 248 static void fdt_add_timer_nodes(const VirtMachineState *vms) 249 { 250 /* On real hardware these interrupts are level-triggered. 251 * On KVM they were edge-triggered before host kernel version 4.4, 252 * and level-triggered afterwards. 253 * On emulated QEMU they are level-triggered. 254 * 255 * Getting the DTB info about them wrong is awkward for some 256 * guest kernels: 257 * pre-4.8 ignore the DT and leave the interrupt configured 258 * with whatever the GIC reset value (or the bootloader) left it at 259 * 4.8 before rc6 honour the incorrect data by programming it back 260 * into the GIC, causing problems 261 * 4.8rc6 and later ignore the DT and always write "level triggered" 262 * into the GIC 263 * 264 * For backwards-compatibility, virt-2.8 and earlier will continue 265 * to say these are edge-triggered, but later machines will report 266 * the correct information. 267 */ 268 ARMCPU *armcpu; 269 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 270 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 271 272 if (vmc->claim_edge_triggered_timers) { 273 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 274 } 275 276 if (vms->gic_version == 2) { 277 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 278 GIC_FDT_IRQ_PPI_CPU_WIDTH, 279 (1 << vms->smp_cpus) - 1); 280 } 281 282 qemu_fdt_add_subnode(vms->fdt, "/timer"); 283 284 armcpu = ARM_CPU(qemu_get_cpu(0)); 285 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 286 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 287 qemu_fdt_setprop(vms->fdt, "/timer", "compatible", 288 compat, sizeof(compat)); 289 } else { 290 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible", 291 "arm,armv7-timer"); 292 } 293 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0); 294 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts", 295 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 296 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 297 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 298 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 299 } 300 301 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 302 { 303 int cpu; 304 int addr_cells = 1; 305 const MachineState *ms = MACHINE(vms); 306 307 /* 308 * From Documentation/devicetree/bindings/arm/cpus.txt 309 * On ARM v8 64-bit systems value should be set to 2, 310 * that corresponds to the MPIDR_EL1 register size. 311 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 312 * in the system, #address-cells can be set to 1, since 313 * MPIDR_EL1[63:32] bits are not used for CPUs 314 * identification. 315 * 316 * Here we actually don't know whether our system is 32- or 64-bit one. 317 * The simplest way to go is to examine affinity IDs of all our CPUs. If 318 * at least one of them has Aff3 populated, we set #address-cells to 2. 319 */ 320 for (cpu = 0; cpu < vms->smp_cpus; cpu++) { 321 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 322 323 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 324 addr_cells = 2; 325 break; 326 } 327 } 328 329 qemu_fdt_add_subnode(vms->fdt, "/cpus"); 330 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); 331 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); 332 333 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { 334 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 335 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 336 CPUState *cs = CPU(armcpu); 337 338 qemu_fdt_add_subnode(vms->fdt, nodename); 339 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); 340 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 341 armcpu->dtb_compatible); 342 343 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED 344 && vms->smp_cpus > 1) { 345 qemu_fdt_setprop_string(vms->fdt, nodename, 346 "enable-method", "psci"); 347 } 348 349 if (addr_cells == 2) { 350 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", 351 armcpu->mp_affinity); 352 } else { 353 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", 354 armcpu->mp_affinity); 355 } 356 357 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 358 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", 359 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 360 } 361 362 g_free(nodename); 363 } 364 } 365 366 static void fdt_add_its_gic_node(VirtMachineState *vms) 367 { 368 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 369 qemu_fdt_add_subnode(vms->fdt, "/intc/its"); 370 qemu_fdt_setprop_string(vms->fdt, "/intc/its", "compatible", 371 "arm,gic-v3-its"); 372 qemu_fdt_setprop(vms->fdt, "/intc/its", "msi-controller", NULL, 0); 373 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/its", "reg", 374 2, vms->memmap[VIRT_GIC_ITS].base, 375 2, vms->memmap[VIRT_GIC_ITS].size); 376 qemu_fdt_setprop_cell(vms->fdt, "/intc/its", "phandle", vms->msi_phandle); 377 } 378 379 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 380 { 381 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 382 qemu_fdt_add_subnode(vms->fdt, "/intc/v2m"); 383 qemu_fdt_setprop_string(vms->fdt, "/intc/v2m", "compatible", 384 "arm,gic-v2m-frame"); 385 qemu_fdt_setprop(vms->fdt, "/intc/v2m", "msi-controller", NULL, 0); 386 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/v2m", "reg", 387 2, vms->memmap[VIRT_GIC_V2M].base, 388 2, vms->memmap[VIRT_GIC_V2M].size); 389 qemu_fdt_setprop_cell(vms->fdt, "/intc/v2m", "phandle", vms->msi_phandle); 390 } 391 392 static void fdt_add_gic_node(VirtMachineState *vms) 393 { 394 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt); 395 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle); 396 397 qemu_fdt_add_subnode(vms->fdt, "/intc"); 398 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#interrupt-cells", 3); 399 qemu_fdt_setprop(vms->fdt, "/intc", "interrupt-controller", NULL, 0); 400 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#address-cells", 0x2); 401 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#size-cells", 0x2); 402 qemu_fdt_setprop(vms->fdt, "/intc", "ranges", NULL, 0); 403 if (vms->gic_version == 3) { 404 qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", 405 "arm,gic-v3"); 406 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", 407 2, vms->memmap[VIRT_GIC_DIST].base, 408 2, vms->memmap[VIRT_GIC_DIST].size, 409 2, vms->memmap[VIRT_GIC_REDIST].base, 410 2, vms->memmap[VIRT_GIC_REDIST].size); 411 if (vms->virt) { 412 qemu_fdt_setprop_cells(vms->fdt, "/intc", "interrupts", 413 GIC_FDT_IRQ_TYPE_PPI, ARCH_GICV3_MAINT_IRQ, 414 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 415 } 416 } else { 417 /* 'cortex-a15-gic' means 'GIC v2' */ 418 qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", 419 "arm,cortex-a15-gic"); 420 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", 421 2, vms->memmap[VIRT_GIC_DIST].base, 422 2, vms->memmap[VIRT_GIC_DIST].size, 423 2, vms->memmap[VIRT_GIC_CPU].base, 424 2, vms->memmap[VIRT_GIC_CPU].size); 425 } 426 427 qemu_fdt_setprop_cell(vms->fdt, "/intc", "phandle", vms->gic_phandle); 428 } 429 430 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 431 { 432 CPUState *cpu; 433 ARMCPU *armcpu; 434 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 435 436 CPU_FOREACH(cpu) { 437 armcpu = ARM_CPU(cpu); 438 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 439 return; 440 } 441 if (kvm_enabled()) { 442 if (kvm_irqchip_in_kernel()) { 443 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 444 } 445 kvm_arm_pmu_init(cpu); 446 } 447 } 448 449 if (vms->gic_version == 2) { 450 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 451 GIC_FDT_IRQ_PPI_CPU_WIDTH, 452 (1 << vms->smp_cpus) - 1); 453 } 454 455 armcpu = ARM_CPU(qemu_get_cpu(0)); 456 qemu_fdt_add_subnode(vms->fdt, "/pmu"); 457 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 458 const char compat[] = "arm,armv8-pmuv3"; 459 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible", 460 compat, sizeof(compat)); 461 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts", 462 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 463 } 464 } 465 466 static void create_its(VirtMachineState *vms, DeviceState *gicdev) 467 { 468 const char *itsclass = its_class_name(); 469 DeviceState *dev; 470 471 if (!itsclass) { 472 /* Do nothing if not supported */ 473 return; 474 } 475 476 dev = qdev_create(NULL, itsclass); 477 478 object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3", 479 &error_abort); 480 qdev_init_nofail(dev); 481 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 482 483 fdt_add_its_gic_node(vms); 484 } 485 486 static void create_v2m(VirtMachineState *vms, qemu_irq *pic) 487 { 488 int i; 489 int irq = vms->irqmap[VIRT_GIC_V2M]; 490 DeviceState *dev; 491 492 dev = qdev_create(NULL, "arm-gicv2m"); 493 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 494 qdev_prop_set_uint32(dev, "base-spi", irq); 495 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 496 qdev_init_nofail(dev); 497 498 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 499 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 500 } 501 502 fdt_add_v2m_gic_node(vms); 503 } 504 505 static void create_gic(VirtMachineState *vms, qemu_irq *pic) 506 { 507 /* We create a standalone GIC */ 508 DeviceState *gicdev; 509 SysBusDevice *gicbusdev; 510 const char *gictype; 511 int type = vms->gic_version, i; 512 513 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 514 515 gicdev = qdev_create(NULL, gictype); 516 qdev_prop_set_uint32(gicdev, "revision", type); 517 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 518 /* Note that the num-irq property counts both internal and external 519 * interrupts; there are always 32 of the former (mandated by GIC spec). 520 */ 521 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 522 if (!kvm_irqchip_in_kernel()) { 523 qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure); 524 } 525 qdev_init_nofail(gicdev); 526 gicbusdev = SYS_BUS_DEVICE(gicdev); 527 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 528 if (type == 3) { 529 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 530 } else { 531 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 532 } 533 534 /* Wire the outputs from each CPU's generic timer and the GICv3 535 * maintenance interrupt signal to the appropriate GIC PPI inputs, 536 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 537 */ 538 for (i = 0; i < smp_cpus; i++) { 539 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 540 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 541 int irq; 542 /* Mapping from the output timer irq lines from the CPU to the 543 * GIC PPI inputs we use for the virt board. 544 */ 545 const int timer_irq[] = { 546 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 547 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 548 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 549 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 550 }; 551 552 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 553 qdev_connect_gpio_out(cpudev, irq, 554 qdev_get_gpio_in(gicdev, 555 ppibase + timer_irq[irq])); 556 } 557 558 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 559 qdev_get_gpio_in(gicdev, ppibase 560 + ARCH_GICV3_MAINT_IRQ)); 561 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 562 qdev_get_gpio_in(gicdev, ppibase 563 + VIRTUAL_PMU_IRQ)); 564 565 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 566 sysbus_connect_irq(gicbusdev, i + smp_cpus, 567 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 568 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 569 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 570 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 571 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 572 } 573 574 for (i = 0; i < NUM_IRQS; i++) { 575 pic[i] = qdev_get_gpio_in(gicdev, i); 576 } 577 578 fdt_add_gic_node(vms); 579 580 if (type == 3 && vms->its) { 581 create_its(vms, gicdev); 582 } else if (type == 2) { 583 create_v2m(vms, pic); 584 } 585 } 586 587 static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart, 588 MemoryRegion *mem, Chardev *chr) 589 { 590 char *nodename; 591 hwaddr base = vms->memmap[uart].base; 592 hwaddr size = vms->memmap[uart].size; 593 int irq = vms->irqmap[uart]; 594 const char compat[] = "arm,pl011\0arm,primecell"; 595 const char clocknames[] = "uartclk\0apb_pclk"; 596 DeviceState *dev = qdev_create(NULL, "pl011"); 597 SysBusDevice *s = SYS_BUS_DEVICE(dev); 598 599 qdev_prop_set_chr(dev, "chardev", chr); 600 qdev_init_nofail(dev); 601 memory_region_add_subregion(mem, base, 602 sysbus_mmio_get_region(s, 0)); 603 sysbus_connect_irq(s, 0, pic[irq]); 604 605 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 606 qemu_fdt_add_subnode(vms->fdt, nodename); 607 /* Note that we can't use setprop_string because of the embedded NUL */ 608 qemu_fdt_setprop(vms->fdt, nodename, "compatible", 609 compat, sizeof(compat)); 610 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 611 2, base, 2, size); 612 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 613 GIC_FDT_IRQ_TYPE_SPI, irq, 614 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 615 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks", 616 vms->clock_phandle, vms->clock_phandle); 617 qemu_fdt_setprop(vms->fdt, nodename, "clock-names", 618 clocknames, sizeof(clocknames)); 619 620 if (uart == VIRT_UART) { 621 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); 622 } else { 623 /* Mark as not usable by the normal world */ 624 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 625 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 626 } 627 628 g_free(nodename); 629 } 630 631 static void create_rtc(const VirtMachineState *vms, qemu_irq *pic) 632 { 633 char *nodename; 634 hwaddr base = vms->memmap[VIRT_RTC].base; 635 hwaddr size = vms->memmap[VIRT_RTC].size; 636 int irq = vms->irqmap[VIRT_RTC]; 637 const char compat[] = "arm,pl031\0arm,primecell"; 638 639 sysbus_create_simple("pl031", base, pic[irq]); 640 641 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 642 qemu_fdt_add_subnode(vms->fdt, nodename); 643 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 644 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 645 2, base, 2, size); 646 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 647 GIC_FDT_IRQ_TYPE_SPI, irq, 648 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 649 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 650 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 651 g_free(nodename); 652 } 653 654 static DeviceState *gpio_key_dev; 655 static void virt_powerdown_req(Notifier *n, void *opaque) 656 { 657 /* use gpio Pin 3 for power button event */ 658 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 659 } 660 661 static Notifier virt_system_powerdown_notifier = { 662 .notify = virt_powerdown_req 663 }; 664 665 static void create_gpio(const VirtMachineState *vms, qemu_irq *pic) 666 { 667 char *nodename; 668 DeviceState *pl061_dev; 669 hwaddr base = vms->memmap[VIRT_GPIO].base; 670 hwaddr size = vms->memmap[VIRT_GPIO].size; 671 int irq = vms->irqmap[VIRT_GPIO]; 672 const char compat[] = "arm,pl061\0arm,primecell"; 673 674 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); 675 676 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); 677 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 678 qemu_fdt_add_subnode(vms->fdt, nodename); 679 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 680 2, base, 2, size); 681 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 682 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); 683 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); 684 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 685 GIC_FDT_IRQ_TYPE_SPI, irq, 686 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 687 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 688 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 689 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); 690 691 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 692 qdev_get_gpio_in(pl061_dev, 3)); 693 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); 694 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); 695 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); 696 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); 697 698 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); 699 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", 700 "label", "GPIO Key Poweroff"); 701 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", 702 KEY_POWER); 703 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", 704 "gpios", phandle, 3, 0); 705 706 /* connect powerdown request */ 707 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier); 708 709 g_free(nodename); 710 } 711 712 static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic) 713 { 714 int i; 715 hwaddr size = vms->memmap[VIRT_MMIO].size; 716 717 /* We create the transports in forwards order. Since qbus_realize() 718 * prepends (not appends) new child buses, the incrementing loop below will 719 * create a list of virtio-mmio buses with decreasing base addresses. 720 * 721 * When a -device option is processed from the command line, 722 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 723 * order. The upshot is that -device options in increasing command line 724 * order are mapped to virtio-mmio buses with decreasing base addresses. 725 * 726 * When this code was originally written, that arrangement ensured that the 727 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 728 * the first -device on the command line. (The end-to-end order is a 729 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 730 * guest kernel's name-to-address assignment strategy.) 731 * 732 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 733 * the message, if not necessarily the code, of commit 70161ff336. 734 * Therefore the loop now establishes the inverse of the original intent. 735 * 736 * Unfortunately, we can't counteract the kernel change by reversing the 737 * loop; it would break existing command lines. 738 * 739 * In any case, the kernel makes no guarantee about the stability of 740 * enumeration order of virtio devices (as demonstrated by it changing 741 * between kernel versions). For reliable and stable identification 742 * of disks users must use UUIDs or similar mechanisms. 743 */ 744 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 745 int irq = vms->irqmap[VIRT_MMIO] + i; 746 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 747 748 sysbus_create_simple("virtio-mmio", base, pic[irq]); 749 } 750 751 /* We add dtb nodes in reverse order so that they appear in the finished 752 * device tree lowest address first. 753 * 754 * Note that this mapping is independent of the loop above. The previous 755 * loop influences virtio device to virtio transport assignment, whereas 756 * this loop controls how virtio transports are laid out in the dtb. 757 */ 758 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 759 char *nodename; 760 int irq = vms->irqmap[VIRT_MMIO] + i; 761 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 762 763 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 764 qemu_fdt_add_subnode(vms->fdt, nodename); 765 qemu_fdt_setprop_string(vms->fdt, nodename, 766 "compatible", "virtio,mmio"); 767 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 768 2, base, 2, size); 769 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 770 GIC_FDT_IRQ_TYPE_SPI, irq, 771 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 772 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 773 g_free(nodename); 774 } 775 } 776 777 static void create_one_flash(const char *name, hwaddr flashbase, 778 hwaddr flashsize, const char *file, 779 MemoryRegion *sysmem) 780 { 781 /* Create and map a single flash device. We use the same 782 * parameters as the flash devices on the Versatile Express board. 783 */ 784 DriveInfo *dinfo = drive_get_next(IF_PFLASH); 785 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 786 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 787 const uint64_t sectorlength = 256 * 1024; 788 789 if (dinfo) { 790 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 791 &error_abort); 792 } 793 794 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); 795 qdev_prop_set_uint64(dev, "sector-length", sectorlength); 796 qdev_prop_set_uint8(dev, "width", 4); 797 qdev_prop_set_uint8(dev, "device-width", 2); 798 qdev_prop_set_bit(dev, "big-endian", false); 799 qdev_prop_set_uint16(dev, "id0", 0x89); 800 qdev_prop_set_uint16(dev, "id1", 0x18); 801 qdev_prop_set_uint16(dev, "id2", 0x00); 802 qdev_prop_set_uint16(dev, "id3", 0x00); 803 qdev_prop_set_string(dev, "name", name); 804 qdev_init_nofail(dev); 805 806 memory_region_add_subregion(sysmem, flashbase, 807 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 808 809 if (file) { 810 char *fn; 811 int image_size; 812 813 if (drive_get(IF_PFLASH, 0, 0)) { 814 error_report("The contents of the first flash device may be " 815 "specified with -bios or with -drive if=pflash... " 816 "but you cannot use both options at once"); 817 exit(1); 818 } 819 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file); 820 if (!fn) { 821 error_report("Could not find ROM image '%s'", file); 822 exit(1); 823 } 824 image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0)); 825 g_free(fn); 826 if (image_size < 0) { 827 error_report("Could not load ROM image '%s'", file); 828 exit(1); 829 } 830 } 831 } 832 833 static void create_flash(const VirtMachineState *vms, 834 MemoryRegion *sysmem, 835 MemoryRegion *secure_sysmem) 836 { 837 /* Create two flash devices to fill the VIRT_FLASH space in the memmap. 838 * Any file passed via -bios goes in the first of these. 839 * sysmem is the system memory space. secure_sysmem is the secure view 840 * of the system, and the first flash device should be made visible only 841 * there. The second flash device is visible to both secure and nonsecure. 842 * If sysmem == secure_sysmem this means there is no separate Secure 843 * address space and both flash devices are generally visible. 844 */ 845 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 846 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 847 char *nodename; 848 849 create_one_flash("virt.flash0", flashbase, flashsize, 850 bios_name, secure_sysmem); 851 create_one_flash("virt.flash1", flashbase + flashsize, flashsize, 852 NULL, sysmem); 853 854 if (sysmem == secure_sysmem) { 855 /* Report both flash devices as a single node in the DT */ 856 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 857 qemu_fdt_add_subnode(vms->fdt, nodename); 858 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 859 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 860 2, flashbase, 2, flashsize, 861 2, flashbase + flashsize, 2, flashsize); 862 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 863 g_free(nodename); 864 } else { 865 /* Report the devices as separate nodes so we can mark one as 866 * only visible to the secure world. 867 */ 868 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 869 qemu_fdt_add_subnode(vms->fdt, nodename); 870 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 871 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 872 2, flashbase, 2, flashsize); 873 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 874 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 875 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 876 g_free(nodename); 877 878 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 879 qemu_fdt_add_subnode(vms->fdt, nodename); 880 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 881 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 882 2, flashbase + flashsize, 2, flashsize); 883 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 884 g_free(nodename); 885 } 886 } 887 888 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 889 { 890 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 891 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 892 FWCfgState *fw_cfg; 893 char *nodename; 894 895 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 896 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 897 898 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 899 qemu_fdt_add_subnode(vms->fdt, nodename); 900 qemu_fdt_setprop_string(vms->fdt, nodename, 901 "compatible", "qemu,fw-cfg-mmio"); 902 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 903 2, base, 2, size); 904 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 905 g_free(nodename); 906 return fw_cfg; 907 } 908 909 static void create_pcie_irq_map(const VirtMachineState *vms, 910 uint32_t gic_phandle, 911 int first_irq, const char *nodename) 912 { 913 int devfn, pin; 914 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 915 uint32_t *irq_map = full_irq_map; 916 917 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 918 for (pin = 0; pin < 4; pin++) { 919 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 920 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 921 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 922 int i; 923 924 uint32_t map[] = { 925 devfn << 8, 0, 0, /* devfn */ 926 pin + 1, /* PCI pin */ 927 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 928 929 /* Convert map to big endian */ 930 for (i = 0; i < 10; i++) { 931 irq_map[i] = cpu_to_be32(map[i]); 932 } 933 irq_map += 10; 934 } 935 } 936 937 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map", 938 full_irq_map, sizeof(full_irq_map)); 939 940 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask", 941 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 942 0x7 /* PCI irq */); 943 } 944 945 static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) 946 { 947 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 948 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 949 hwaddr base_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].base; 950 hwaddr size_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].size; 951 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 952 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 953 hwaddr base_ecam = vms->memmap[VIRT_PCIE_ECAM].base; 954 hwaddr size_ecam = vms->memmap[VIRT_PCIE_ECAM].size; 955 hwaddr base = base_mmio; 956 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 957 int irq = vms->irqmap[VIRT_PCIE]; 958 MemoryRegion *mmio_alias; 959 MemoryRegion *mmio_reg; 960 MemoryRegion *ecam_alias; 961 MemoryRegion *ecam_reg; 962 DeviceState *dev; 963 char *nodename; 964 int i; 965 PCIHostState *pci; 966 967 dev = qdev_create(NULL, TYPE_GPEX_HOST); 968 qdev_init_nofail(dev); 969 970 /* Map only the first size_ecam bytes of ECAM space */ 971 ecam_alias = g_new0(MemoryRegion, 1); 972 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 973 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 974 ecam_reg, 0, size_ecam); 975 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 976 977 /* Map the MMIO window into system address space so as to expose 978 * the section of PCI MMIO space which starts at the same base address 979 * (ie 1:1 mapping for that part of PCI MMIO space visible through 980 * the window). 981 */ 982 mmio_alias = g_new0(MemoryRegion, 1); 983 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 984 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 985 mmio_reg, base_mmio, size_mmio); 986 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 987 988 if (vms->highmem) { 989 /* Map high MMIO space */ 990 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 991 992 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 993 mmio_reg, base_mmio_high, size_mmio_high); 994 memory_region_add_subregion(get_system_memory(), base_mmio_high, 995 high_mmio_alias); 996 } 997 998 /* Map IO port space */ 999 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1000 1001 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1002 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 1003 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1004 } 1005 1006 pci = PCI_HOST_BRIDGE(dev); 1007 if (pci->bus) { 1008 for (i = 0; i < nb_nics; i++) { 1009 NICInfo *nd = &nd_table[i]; 1010 1011 if (!nd->model) { 1012 nd->model = g_strdup("virtio"); 1013 } 1014 1015 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1016 } 1017 } 1018 1019 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1020 qemu_fdt_add_subnode(vms->fdt, nodename); 1021 qemu_fdt_setprop_string(vms->fdt, nodename, 1022 "compatible", "pci-host-ecam-generic"); 1023 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci"); 1024 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3); 1025 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2); 1026 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0, 1027 nr_pcie_buses - 1); 1028 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1029 1030 if (vms->msi_phandle) { 1031 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", 1032 vms->msi_phandle); 1033 } 1034 1035 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1036 2, base_ecam, 2, size_ecam); 1037 1038 if (vms->highmem) { 1039 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1040 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1041 2, base_pio, 2, size_pio, 1042 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1043 2, base_mmio, 2, size_mmio, 1044 1, FDT_PCI_RANGE_MMIO_64BIT, 1045 2, base_mmio_high, 1046 2, base_mmio_high, 2, size_mmio_high); 1047 } else { 1048 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1049 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1050 2, base_pio, 2, size_pio, 1051 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1052 2, base_mmio, 2, size_mmio); 1053 } 1054 1055 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); 1056 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); 1057 1058 g_free(nodename); 1059 } 1060 1061 static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic) 1062 { 1063 DeviceState *dev; 1064 SysBusDevice *s; 1065 int i; 1066 ARMPlatformBusFDTParams *fdt_params = g_new(ARMPlatformBusFDTParams, 1); 1067 MemoryRegion *sysmem = get_system_memory(); 1068 1069 platform_bus_params.platform_bus_base = vms->memmap[VIRT_PLATFORM_BUS].base; 1070 platform_bus_params.platform_bus_size = vms->memmap[VIRT_PLATFORM_BUS].size; 1071 platform_bus_params.platform_bus_first_irq = vms->irqmap[VIRT_PLATFORM_BUS]; 1072 platform_bus_params.platform_bus_num_irqs = PLATFORM_BUS_NUM_IRQS; 1073 1074 fdt_params->system_params = &platform_bus_params; 1075 fdt_params->binfo = &vms->bootinfo; 1076 fdt_params->intc = "/intc"; 1077 /* 1078 * register a machine init done notifier that creates the device tree 1079 * nodes of the platform bus and its children dynamic sysbus devices 1080 */ 1081 arm_register_platform_bus_fdt_creator(fdt_params); 1082 1083 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1084 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1085 qdev_prop_set_uint32(dev, "num_irqs", 1086 platform_bus_params.platform_bus_num_irqs); 1087 qdev_prop_set_uint32(dev, "mmio_size", 1088 platform_bus_params.platform_bus_size); 1089 qdev_init_nofail(dev); 1090 s = SYS_BUS_DEVICE(dev); 1091 1092 for (i = 0; i < platform_bus_params.platform_bus_num_irqs; i++) { 1093 int irqn = platform_bus_params.platform_bus_first_irq + i; 1094 sysbus_connect_irq(s, i, pic[irqn]); 1095 } 1096 1097 memory_region_add_subregion(sysmem, 1098 platform_bus_params.platform_bus_base, 1099 sysbus_mmio_get_region(s, 0)); 1100 } 1101 1102 static void create_secure_ram(VirtMachineState *vms, 1103 MemoryRegion *secure_sysmem) 1104 { 1105 MemoryRegion *secram = g_new(MemoryRegion, 1); 1106 char *nodename; 1107 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1108 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1109 1110 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1111 &error_fatal); 1112 memory_region_add_subregion(secure_sysmem, base, secram); 1113 1114 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1115 qemu_fdt_add_subnode(vms->fdt, nodename); 1116 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory"); 1117 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size); 1118 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1119 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1120 1121 g_free(nodename); 1122 } 1123 1124 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1125 { 1126 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1127 bootinfo); 1128 1129 *fdt_size = board->fdt_size; 1130 return board->fdt; 1131 } 1132 1133 static void virt_build_smbios(VirtMachineState *vms) 1134 { 1135 uint8_t *smbios_tables, *smbios_anchor; 1136 size_t smbios_tables_len, smbios_anchor_len; 1137 const char *product = "QEMU Virtual Machine"; 1138 1139 if (!vms->fw_cfg) { 1140 return; 1141 } 1142 1143 if (kvm_enabled()) { 1144 product = "KVM Virtual Machine"; 1145 } 1146 1147 smbios_set_defaults("QEMU", product, 1148 "1.0", false, true, SMBIOS_ENTRY_POINT_30); 1149 1150 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, 1151 &smbios_anchor, &smbios_anchor_len); 1152 1153 if (smbios_anchor) { 1154 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1155 smbios_tables, smbios_tables_len); 1156 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1157 smbios_anchor, smbios_anchor_len); 1158 } 1159 } 1160 1161 static 1162 void virt_machine_done(Notifier *notifier, void *data) 1163 { 1164 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1165 machine_done); 1166 1167 virt_acpi_setup(vms); 1168 virt_build_smbios(vms); 1169 } 1170 1171 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1172 { 1173 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1174 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1175 1176 if (!vmc->disallow_affinity_adjustment) { 1177 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1178 * GIC's target-list limitations. 32-bit KVM hosts currently 1179 * always create clusters of 4 CPUs, but that is expected to 1180 * change when they gain support for gicv3. When KVM is enabled 1181 * it will override the changes we make here, therefore our 1182 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1183 * and to improve SGI efficiency. 1184 */ 1185 if (vms->gic_version == 3) { 1186 clustersz = GICV3_TARGETLIST_BITS; 1187 } else { 1188 clustersz = GIC_TARGETLIST_BITS; 1189 } 1190 } 1191 return arm_cpu_mp_affinity(idx, clustersz); 1192 } 1193 1194 static void machvirt_init(MachineState *machine) 1195 { 1196 VirtMachineState *vms = VIRT_MACHINE(machine); 1197 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1198 MachineClass *mc = MACHINE_GET_CLASS(machine); 1199 const CPUArchIdList *possible_cpus; 1200 qemu_irq pic[NUM_IRQS]; 1201 MemoryRegion *sysmem = get_system_memory(); 1202 MemoryRegion *secure_sysmem = NULL; 1203 int n, virt_max_cpus; 1204 MemoryRegion *ram = g_new(MemoryRegion, 1); 1205 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); 1206 1207 /* We can probe only here because during property set 1208 * KVM is not available yet 1209 */ 1210 if (vms->gic_version <= 0) { 1211 /* "host" or "max" */ 1212 if (!kvm_enabled()) { 1213 if (vms->gic_version == 0) { 1214 error_report("gic-version=host requires KVM"); 1215 exit(1); 1216 } else { 1217 /* "max": currently means 3 for TCG */ 1218 vms->gic_version = 3; 1219 } 1220 } else { 1221 vms->gic_version = kvm_arm_vgic_probe(); 1222 if (!vms->gic_version) { 1223 error_report( 1224 "Unable to determine GIC version supported by host"); 1225 exit(1); 1226 } 1227 } 1228 } 1229 1230 if (!cpu_type_valid(machine->cpu_type)) { 1231 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 1232 exit(1); 1233 } 1234 1235 /* If we have an EL3 boot ROM then the assumption is that it will 1236 * implement PSCI itself, so disable QEMU's internal implementation 1237 * so it doesn't get in the way. Instead of starting secondary 1238 * CPUs in PSCI powerdown state we will start them all running and 1239 * let the boot ROM sort them out. 1240 * The usual case is that we do use QEMU's PSCI implementation; 1241 * if the guest has EL2 then we will use SMC as the conduit, 1242 * and otherwise we will use HVC (for backwards compatibility and 1243 * because if we're using KVM then we must use HVC). 1244 */ 1245 if (vms->secure && firmware_loaded) { 1246 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1247 } else if (vms->virt) { 1248 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 1249 } else { 1250 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 1251 } 1252 1253 /* The maximum number of CPUs depends on the GIC version, or on how 1254 * many redistributors we can fit into the memory map. 1255 */ 1256 if (vms->gic_version == 3) { 1257 virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / 0x20000; 1258 } else { 1259 virt_max_cpus = GIC_NCPU; 1260 } 1261 1262 if (max_cpus > virt_max_cpus) { 1263 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1264 "supported by machine 'mach-virt' (%d)", 1265 max_cpus, virt_max_cpus); 1266 exit(1); 1267 } 1268 1269 vms->smp_cpus = smp_cpus; 1270 1271 if (machine->ram_size > vms->memmap[VIRT_MEM].size) { 1272 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB); 1273 exit(1); 1274 } 1275 1276 if (vms->virt && kvm_enabled()) { 1277 error_report("mach-virt: KVM does not support providing " 1278 "Virtualization extensions to the guest CPU"); 1279 exit(1); 1280 } 1281 1282 if (vms->secure) { 1283 if (kvm_enabled()) { 1284 error_report("mach-virt: KVM does not support Security extensions"); 1285 exit(1); 1286 } 1287 1288 /* The Secure view of the world is the same as the NonSecure, 1289 * but with a few extra devices. Create it as a container region 1290 * containing the system memory at low priority; any secure-only 1291 * devices go in at higher priority and take precedence. 1292 */ 1293 secure_sysmem = g_new(MemoryRegion, 1); 1294 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1295 UINT64_MAX); 1296 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1297 } 1298 1299 create_fdt(vms); 1300 1301 possible_cpus = mc->possible_cpu_arch_ids(machine); 1302 for (n = 0; n < possible_cpus->len; n++) { 1303 Object *cpuobj; 1304 CPUState *cs; 1305 1306 if (n >= smp_cpus) { 1307 break; 1308 } 1309 1310 cpuobj = object_new(possible_cpus->cpus[n].type); 1311 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 1312 "mp-affinity", NULL); 1313 1314 cs = CPU(cpuobj); 1315 cs->cpu_index = n; 1316 1317 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 1318 &error_fatal); 1319 1320 if (!vms->secure) { 1321 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1322 } 1323 1324 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { 1325 object_property_set_bool(cpuobj, false, "has_el2", NULL); 1326 } 1327 1328 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1329 object_property_set_int(cpuobj, vms->psci_conduit, 1330 "psci-conduit", NULL); 1331 1332 /* Secondary CPUs start in PSCI powered-down state */ 1333 if (n > 0) { 1334 object_property_set_bool(cpuobj, true, 1335 "start-powered-off", NULL); 1336 } 1337 } 1338 1339 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { 1340 object_property_set_bool(cpuobj, false, "pmu", NULL); 1341 } 1342 1343 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1344 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, 1345 "reset-cbar", &error_abort); 1346 } 1347 1348 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1349 &error_abort); 1350 if (vms->secure) { 1351 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1352 "secure-memory", &error_abort); 1353 } 1354 1355 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 1356 object_unref(cpuobj); 1357 } 1358 fdt_add_timer_nodes(vms); 1359 fdt_add_cpu_nodes(vms); 1360 1361 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", 1362 machine->ram_size); 1363 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); 1364 1365 create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem); 1366 1367 create_gic(vms, pic); 1368 1369 fdt_add_pmu_nodes(vms); 1370 1371 create_uart(vms, pic, VIRT_UART, sysmem, serial_hds[0]); 1372 1373 if (vms->secure) { 1374 create_secure_ram(vms, secure_sysmem); 1375 create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hds[1]); 1376 } 1377 1378 create_rtc(vms, pic); 1379 1380 create_pcie(vms, pic); 1381 1382 create_gpio(vms, pic); 1383 1384 /* Create mmio transports, so the user can create virtio backends 1385 * (which will be automatically plugged in to the transports). If 1386 * no backend is created the transport will just sit harmlessly idle. 1387 */ 1388 create_virtio_devices(vms, pic); 1389 1390 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 1391 rom_set_fw(vms->fw_cfg); 1392 1393 vms->machine_done.notify = virt_machine_done; 1394 qemu_add_machine_init_done_notifier(&vms->machine_done); 1395 1396 vms->bootinfo.ram_size = machine->ram_size; 1397 vms->bootinfo.kernel_filename = machine->kernel_filename; 1398 vms->bootinfo.kernel_cmdline = machine->kernel_cmdline; 1399 vms->bootinfo.initrd_filename = machine->initrd_filename; 1400 vms->bootinfo.nb_cpus = smp_cpus; 1401 vms->bootinfo.board_id = -1; 1402 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 1403 vms->bootinfo.get_dtb = machvirt_dtb; 1404 vms->bootinfo.firmware_loaded = firmware_loaded; 1405 arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo); 1406 1407 /* 1408 * arm_load_kernel machine init done notifier registration must 1409 * happen before the platform_bus_create call. In this latter, 1410 * another notifier is registered which adds platform bus nodes. 1411 * Notifiers are executed in registration reverse order. 1412 */ 1413 create_platform_bus(vms, pic); 1414 } 1415 1416 static bool virt_get_secure(Object *obj, Error **errp) 1417 { 1418 VirtMachineState *vms = VIRT_MACHINE(obj); 1419 1420 return vms->secure; 1421 } 1422 1423 static void virt_set_secure(Object *obj, bool value, Error **errp) 1424 { 1425 VirtMachineState *vms = VIRT_MACHINE(obj); 1426 1427 vms->secure = value; 1428 } 1429 1430 static bool virt_get_virt(Object *obj, Error **errp) 1431 { 1432 VirtMachineState *vms = VIRT_MACHINE(obj); 1433 1434 return vms->virt; 1435 } 1436 1437 static void virt_set_virt(Object *obj, bool value, Error **errp) 1438 { 1439 VirtMachineState *vms = VIRT_MACHINE(obj); 1440 1441 vms->virt = value; 1442 } 1443 1444 static bool virt_get_highmem(Object *obj, Error **errp) 1445 { 1446 VirtMachineState *vms = VIRT_MACHINE(obj); 1447 1448 return vms->highmem; 1449 } 1450 1451 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1452 { 1453 VirtMachineState *vms = VIRT_MACHINE(obj); 1454 1455 vms->highmem = value; 1456 } 1457 1458 static bool virt_get_its(Object *obj, Error **errp) 1459 { 1460 VirtMachineState *vms = VIRT_MACHINE(obj); 1461 1462 return vms->its; 1463 } 1464 1465 static void virt_set_its(Object *obj, bool value, Error **errp) 1466 { 1467 VirtMachineState *vms = VIRT_MACHINE(obj); 1468 1469 vms->its = value; 1470 } 1471 1472 static char *virt_get_gic_version(Object *obj, Error **errp) 1473 { 1474 VirtMachineState *vms = VIRT_MACHINE(obj); 1475 const char *val = vms->gic_version == 3 ? "3" : "2"; 1476 1477 return g_strdup(val); 1478 } 1479 1480 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 1481 { 1482 VirtMachineState *vms = VIRT_MACHINE(obj); 1483 1484 if (!strcmp(value, "3")) { 1485 vms->gic_version = 3; 1486 } else if (!strcmp(value, "2")) { 1487 vms->gic_version = 2; 1488 } else if (!strcmp(value, "host")) { 1489 vms->gic_version = 0; /* Will probe later */ 1490 } else if (!strcmp(value, "max")) { 1491 vms->gic_version = -1; /* Will probe later */ 1492 } else { 1493 error_setg(errp, "Invalid gic-version value"); 1494 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 1495 } 1496 } 1497 1498 static CpuInstanceProperties 1499 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1500 { 1501 MachineClass *mc = MACHINE_GET_CLASS(ms); 1502 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1503 1504 assert(cpu_index < possible_cpus->len); 1505 return possible_cpus->cpus[cpu_index].props; 1506 } 1507 1508 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1509 { 1510 return idx % nb_numa_nodes; 1511 } 1512 1513 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1514 { 1515 int n; 1516 VirtMachineState *vms = VIRT_MACHINE(ms); 1517 1518 if (ms->possible_cpus) { 1519 assert(ms->possible_cpus->len == max_cpus); 1520 return ms->possible_cpus; 1521 } 1522 1523 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1524 sizeof(CPUArchId) * max_cpus); 1525 ms->possible_cpus->len = max_cpus; 1526 for (n = 0; n < ms->possible_cpus->len; n++) { 1527 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1528 ms->possible_cpus->cpus[n].arch_id = 1529 virt_cpu_mp_affinity(vms, n); 1530 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1531 ms->possible_cpus->cpus[n].props.thread_id = n; 1532 } 1533 return ms->possible_cpus; 1534 } 1535 1536 static void virt_machine_class_init(ObjectClass *oc, void *data) 1537 { 1538 MachineClass *mc = MACHINE_CLASS(oc); 1539 1540 mc->init = machvirt_init; 1541 /* Start max_cpus at the maximum QEMU supports. We'll further restrict 1542 * it later in machvirt_init, where we have more information about the 1543 * configuration of the particular instance. 1544 */ 1545 mc->max_cpus = 255; 1546 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 1547 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 1548 mc->block_default_type = IF_VIRTIO; 1549 mc->no_cdrom = 1; 1550 mc->pci_allow_0_address = true; 1551 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 1552 mc->minimum_page_bits = 12; 1553 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1554 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1555 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 1556 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1557 } 1558 1559 static const TypeInfo virt_machine_info = { 1560 .name = TYPE_VIRT_MACHINE, 1561 .parent = TYPE_MACHINE, 1562 .abstract = true, 1563 .instance_size = sizeof(VirtMachineState), 1564 .class_size = sizeof(VirtMachineClass), 1565 .class_init = virt_machine_class_init, 1566 }; 1567 1568 static void machvirt_machine_init(void) 1569 { 1570 type_register_static(&virt_machine_info); 1571 } 1572 type_init(machvirt_machine_init); 1573 1574 static void virt_2_12_instance_init(Object *obj) 1575 { 1576 VirtMachineState *vms = VIRT_MACHINE(obj); 1577 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1578 1579 /* EL3 is disabled by default on virt: this makes us consistent 1580 * between KVM and TCG for this board, and it also allows us to 1581 * boot UEFI blobs which assume no TrustZone support. 1582 */ 1583 vms->secure = false; 1584 object_property_add_bool(obj, "secure", virt_get_secure, 1585 virt_set_secure, NULL); 1586 object_property_set_description(obj, "secure", 1587 "Set on/off to enable/disable the ARM " 1588 "Security Extensions (TrustZone)", 1589 NULL); 1590 1591 /* EL2 is also disabled by default, for similar reasons */ 1592 vms->virt = false; 1593 object_property_add_bool(obj, "virtualization", virt_get_virt, 1594 virt_set_virt, NULL); 1595 object_property_set_description(obj, "virtualization", 1596 "Set on/off to enable/disable emulating a " 1597 "guest CPU which implements the ARM " 1598 "Virtualization Extensions", 1599 NULL); 1600 1601 /* High memory is enabled by default */ 1602 vms->highmem = true; 1603 object_property_add_bool(obj, "highmem", virt_get_highmem, 1604 virt_set_highmem, NULL); 1605 object_property_set_description(obj, "highmem", 1606 "Set on/off to enable/disable using " 1607 "physical address space above 32 bits", 1608 NULL); 1609 /* Default GIC type is v2 */ 1610 vms->gic_version = 2; 1611 object_property_add_str(obj, "gic-version", virt_get_gic_version, 1612 virt_set_gic_version, NULL); 1613 object_property_set_description(obj, "gic-version", 1614 "Set GIC version. " 1615 "Valid values are 2, 3 and host", NULL); 1616 1617 if (vmc->no_its) { 1618 vms->its = false; 1619 } else { 1620 /* Default allows ITS instantiation */ 1621 vms->its = true; 1622 object_property_add_bool(obj, "its", virt_get_its, 1623 virt_set_its, NULL); 1624 object_property_set_description(obj, "its", 1625 "Set on/off to enable/disable " 1626 "ITS instantiation", 1627 NULL); 1628 } 1629 1630 vms->memmap = a15memmap; 1631 vms->irqmap = a15irqmap; 1632 } 1633 1634 static void virt_machine_2_12_options(MachineClass *mc) 1635 { 1636 } 1637 DEFINE_VIRT_MACHINE_AS_LATEST(2, 12) 1638 1639 #define VIRT_COMPAT_2_11 \ 1640 HW_COMPAT_2_11 1641 1642 static void virt_2_11_instance_init(Object *obj) 1643 { 1644 virt_2_12_instance_init(obj); 1645 } 1646 1647 static void virt_machine_2_11_options(MachineClass *mc) 1648 { 1649 virt_machine_2_12_options(mc); 1650 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_11); 1651 } 1652 DEFINE_VIRT_MACHINE(2, 11) 1653 1654 #define VIRT_COMPAT_2_10 \ 1655 HW_COMPAT_2_10 1656 1657 static void virt_2_10_instance_init(Object *obj) 1658 { 1659 virt_2_11_instance_init(obj); 1660 } 1661 1662 static void virt_machine_2_10_options(MachineClass *mc) 1663 { 1664 virt_machine_2_11_options(mc); 1665 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_10); 1666 } 1667 DEFINE_VIRT_MACHINE(2, 10) 1668 1669 #define VIRT_COMPAT_2_9 \ 1670 HW_COMPAT_2_9 1671 1672 static void virt_2_9_instance_init(Object *obj) 1673 { 1674 virt_2_10_instance_init(obj); 1675 } 1676 1677 static void virt_machine_2_9_options(MachineClass *mc) 1678 { 1679 virt_machine_2_10_options(mc); 1680 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_9); 1681 } 1682 DEFINE_VIRT_MACHINE(2, 9) 1683 1684 #define VIRT_COMPAT_2_8 \ 1685 HW_COMPAT_2_8 1686 1687 static void virt_2_8_instance_init(Object *obj) 1688 { 1689 virt_2_9_instance_init(obj); 1690 } 1691 1692 static void virt_machine_2_8_options(MachineClass *mc) 1693 { 1694 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1695 1696 virt_machine_2_9_options(mc); 1697 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_8); 1698 /* For 2.8 and earlier we falsely claimed in the DT that 1699 * our timers were edge-triggered, not level-triggered. 1700 */ 1701 vmc->claim_edge_triggered_timers = true; 1702 } 1703 DEFINE_VIRT_MACHINE(2, 8) 1704 1705 #define VIRT_COMPAT_2_7 \ 1706 HW_COMPAT_2_7 1707 1708 static void virt_2_7_instance_init(Object *obj) 1709 { 1710 virt_2_8_instance_init(obj); 1711 } 1712 1713 static void virt_machine_2_7_options(MachineClass *mc) 1714 { 1715 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1716 1717 virt_machine_2_8_options(mc); 1718 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_7); 1719 /* ITS was introduced with 2.8 */ 1720 vmc->no_its = true; 1721 /* Stick with 1K pages for migration compatibility */ 1722 mc->minimum_page_bits = 0; 1723 } 1724 DEFINE_VIRT_MACHINE(2, 7) 1725 1726 #define VIRT_COMPAT_2_6 \ 1727 HW_COMPAT_2_6 1728 1729 static void virt_2_6_instance_init(Object *obj) 1730 { 1731 virt_2_7_instance_init(obj); 1732 } 1733 1734 static void virt_machine_2_6_options(MachineClass *mc) 1735 { 1736 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1737 1738 virt_machine_2_7_options(mc); 1739 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6); 1740 vmc->disallow_affinity_adjustment = true; 1741 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 1742 vmc->no_pmu = true; 1743 } 1744 DEFINE_VIRT_MACHINE(2, 6) 1745