1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/datadir.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "hw/sysbus.h" 37 #include "hw/arm/boot.h" 38 #include "hw/arm/primecell.h" 39 #include "hw/arm/virt.h" 40 #include "hw/block/flash.h" 41 #include "hw/vfio/vfio-calxeda-xgmac.h" 42 #include "hw/vfio/vfio-amd-xgbe.h" 43 #include "hw/display/ramfb.h" 44 #include "net/net.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/numa.h" 47 #include "sysemu/runstate.h" 48 #include "sysemu/tpm.h" 49 #include "sysemu/tcg.h" 50 #include "sysemu/kvm.h" 51 #include "sysemu/hvf.h" 52 #include "sysemu/qtest.h" 53 #include "hw/loader.h" 54 #include "qapi/error.h" 55 #include "qemu/bitops.h" 56 #include "qemu/error-report.h" 57 #include "qemu/module.h" 58 #include "hw/pci-host/gpex.h" 59 #include "hw/virtio/virtio-pci.h" 60 #include "hw/core/sysbus-fdt.h" 61 #include "hw/platform-bus.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/arm/fdt.h" 64 #include "hw/intc/arm_gic.h" 65 #include "hw/intc/arm_gicv3_common.h" 66 #include "hw/intc/arm_gicv3_its_common.h" 67 #include "hw/irq.h" 68 #include "kvm_arm.h" 69 #include "hw/firmware/smbios.h" 70 #include "qapi/visitor.h" 71 #include "qapi/qapi-visit-common.h" 72 #include "qapi/qmp/qlist.h" 73 #include "standard-headers/linux/input.h" 74 #include "hw/arm/smmuv3.h" 75 #include "hw/acpi/acpi.h" 76 #include "target/arm/cpu-qom.h" 77 #include "target/arm/internals.h" 78 #include "target/arm/multiprocessing.h" 79 #include "target/arm/gtimer.h" 80 #include "hw/mem/pc-dimm.h" 81 #include "hw/mem/nvdimm.h" 82 #include "hw/acpi/generic_event_device.h" 83 #include "hw/virtio/virtio-md-pci.h" 84 #include "hw/virtio/virtio-iommu.h" 85 #include "hw/char/pl011.h" 86 #include "qemu/guest-random.h" 87 88 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 89 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 90 void *data) \ 91 { \ 92 MachineClass *mc = MACHINE_CLASS(oc); \ 93 virt_machine_##major##_##minor##_options(mc); \ 94 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 95 if (latest) { \ 96 mc->alias = "virt"; \ 97 } \ 98 } \ 99 static const TypeInfo machvirt_##major##_##minor##_info = { \ 100 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 101 .parent = TYPE_VIRT_MACHINE, \ 102 .class_init = virt_##major##_##minor##_class_init, \ 103 }; \ 104 static void machvirt_machine_##major##_##minor##_init(void) \ 105 { \ 106 type_register_static(&machvirt_##major##_##minor##_info); \ 107 } \ 108 type_init(machvirt_machine_##major##_##minor##_init); 109 110 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 111 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 112 #define DEFINE_VIRT_MACHINE(major, minor) \ 113 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 114 115 116 /* Number of external interrupt lines to configure the GIC with */ 117 #define NUM_IRQS 256 118 119 #define PLATFORM_BUS_NUM_IRQS 64 120 121 /* Legacy RAM limit in GB (< version 4.0) */ 122 #define LEGACY_RAMLIMIT_GB 255 123 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 124 125 /* Addresses and sizes of our components. 126 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 127 * 128MB..256MB is used for miscellaneous device I/O. 128 * 256MB..1GB is reserved for possible future PCI support (ie where the 129 * PCI memory window will go if we add a PCI host controller). 130 * 1GB and up is RAM (which may happily spill over into the 131 * high memory region beyond 4GB). 132 * This represents a compromise between how much RAM can be given to 133 * a 32 bit VM and leaving space for expansion and in particular for PCI. 134 * Note that devices should generally be placed at multiples of 0x10000, 135 * to accommodate guests using 64K pages. 136 */ 137 static const MemMapEntry base_memmap[] = { 138 /* Space up to 0x8000000 is reserved for a boot ROM */ 139 [VIRT_FLASH] = { 0, 0x08000000 }, 140 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 141 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 142 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 143 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 144 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 145 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 146 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 147 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 148 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 149 /* This redistributor space allows up to 2*64kB*123 CPUs */ 150 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 151 [VIRT_UART] = { 0x09000000, 0x00001000 }, 152 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 153 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 154 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 155 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 156 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 157 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 158 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 159 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 160 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, 161 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, 162 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 163 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 164 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 165 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 166 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 167 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 168 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 169 /* Actual RAM size depends on initial RAM and device memory settings */ 170 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 171 }; 172 173 /* 174 * Highmem IO Regions: This memory map is floating, located after the RAM. 175 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 176 * top of the RAM, so that its base get the same alignment as the size, 177 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 178 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 179 * Note the extended_memmap is sized so that it eventually also includes the 180 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 181 * index of base_memmap). 182 * 183 * The memory map for these Highmem IO Regions can be in legacy or compact 184 * layout, depending on 'compact-highmem' property. With legacy layout, the 185 * PA space for one specific region is always reserved, even if the region 186 * has been disabled or doesn't fit into the PA space. However, the PA space 187 * for the region won't be reserved in these circumstances with compact layout. 188 */ 189 static MemMapEntry extended_memmap[] = { 190 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 191 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 192 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 193 /* Second PCIe window */ 194 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 195 }; 196 197 static const int a15irqmap[] = { 198 [VIRT_UART] = 1, 199 [VIRT_RTC] = 2, 200 [VIRT_PCIE] = 3, /* ... to 6 */ 201 [VIRT_GPIO] = 7, 202 [VIRT_SECURE_UART] = 8, 203 [VIRT_ACPI_GED] = 9, 204 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 205 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 206 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 207 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 208 }; 209 210 static void create_randomness(MachineState *ms, const char *node) 211 { 212 struct { 213 uint64_t kaslr; 214 uint8_t rng[32]; 215 } seed; 216 217 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { 218 return; 219 } 220 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr); 221 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); 222 } 223 224 /* 225 * The CPU object always exposes the NS EL2 virt timer IRQ line, 226 * but we don't want to advertise it to the guest in the dtb or ACPI 227 * table unless it's really going to do something. 228 */ 229 static bool ns_el2_virt_timer_present(void) 230 { 231 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0)); 232 CPUARMState *env = &cpu->env; 233 234 return arm_feature(env, ARM_FEATURE_AARCH64) && 235 arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu); 236 } 237 238 static void create_fdt(VirtMachineState *vms) 239 { 240 MachineState *ms = MACHINE(vms); 241 int nb_numa_nodes = ms->numa_state->num_nodes; 242 void *fdt = create_device_tree(&vms->fdt_size); 243 244 if (!fdt) { 245 error_report("create_device_tree() failed"); 246 exit(1); 247 } 248 249 ms->fdt = fdt; 250 251 /* Header */ 252 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 253 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 254 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 255 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt"); 256 257 /* /chosen must exist for load_dtb to fill in necessary properties later */ 258 qemu_fdt_add_subnode(fdt, "/chosen"); 259 if (vms->dtb_randomness) { 260 create_randomness(ms, "/chosen"); 261 } 262 263 if (vms->secure) { 264 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 265 if (vms->dtb_randomness) { 266 create_randomness(ms, "/secure-chosen"); 267 } 268 } 269 270 /* Clock node, for the benefit of the UART. The kernel device tree 271 * binding documentation claims the PL011 node clock properties are 272 * optional but in practice if you omit them the kernel refuses to 273 * probe for the device. 274 */ 275 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 276 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 277 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 278 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 279 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 280 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 281 "clk24mhz"); 282 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 283 284 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 285 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 286 uint32_t *matrix = g_malloc0(size); 287 int idx, i, j; 288 289 for (i = 0; i < nb_numa_nodes; i++) { 290 for (j = 0; j < nb_numa_nodes; j++) { 291 idx = (i * nb_numa_nodes + j) * 3; 292 matrix[idx + 0] = cpu_to_be32(i); 293 matrix[idx + 1] = cpu_to_be32(j); 294 matrix[idx + 2] = 295 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 296 } 297 } 298 299 qemu_fdt_add_subnode(fdt, "/distance-map"); 300 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 301 "numa-distance-map-v1"); 302 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 303 matrix, size); 304 g_free(matrix); 305 } 306 } 307 308 static void fdt_add_timer_nodes(const VirtMachineState *vms) 309 { 310 /* On real hardware these interrupts are level-triggered. 311 * On KVM they were edge-triggered before host kernel version 4.4, 312 * and level-triggered afterwards. 313 * On emulated QEMU they are level-triggered. 314 * 315 * Getting the DTB info about them wrong is awkward for some 316 * guest kernels: 317 * pre-4.8 ignore the DT and leave the interrupt configured 318 * with whatever the GIC reset value (or the bootloader) left it at 319 * 4.8 before rc6 honour the incorrect data by programming it back 320 * into the GIC, causing problems 321 * 4.8rc6 and later ignore the DT and always write "level triggered" 322 * into the GIC 323 * 324 * For backwards-compatibility, virt-2.8 and earlier will continue 325 * to say these are edge-triggered, but later machines will report 326 * the correct information. 327 */ 328 ARMCPU *armcpu; 329 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 330 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 331 MachineState *ms = MACHINE(vms); 332 333 if (vmc->claim_edge_triggered_timers) { 334 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 335 } 336 337 if (vms->gic_version == VIRT_GIC_VERSION_2) { 338 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 339 GIC_FDT_IRQ_PPI_CPU_WIDTH, 340 (1 << MACHINE(vms)->smp.cpus) - 1); 341 } 342 343 qemu_fdt_add_subnode(ms->fdt, "/timer"); 344 345 armcpu = ARM_CPU(qemu_get_cpu(0)); 346 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 347 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 348 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", 349 compat, sizeof(compat)); 350 } else { 351 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", 352 "arm,armv7-timer"); 353 } 354 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); 355 if (vms->ns_el2_virt_timer_irq) { 356 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 357 GIC_FDT_IRQ_TYPE_PPI, 358 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, 359 GIC_FDT_IRQ_TYPE_PPI, 360 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, 361 GIC_FDT_IRQ_TYPE_PPI, 362 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, 363 GIC_FDT_IRQ_TYPE_PPI, 364 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags, 365 GIC_FDT_IRQ_TYPE_PPI, 366 INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags); 367 } else { 368 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 369 GIC_FDT_IRQ_TYPE_PPI, 370 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, 371 GIC_FDT_IRQ_TYPE_PPI, 372 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, 373 GIC_FDT_IRQ_TYPE_PPI, 374 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, 375 GIC_FDT_IRQ_TYPE_PPI, 376 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags); 377 } 378 } 379 380 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 381 { 382 int cpu; 383 int addr_cells = 1; 384 const MachineState *ms = MACHINE(vms); 385 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 386 int smp_cpus = ms->smp.cpus; 387 388 /* 389 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml 390 * On ARM v8 64-bit systems value should be set to 2, 391 * that corresponds to the MPIDR_EL1 register size. 392 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 393 * in the system, #address-cells can be set to 1, since 394 * MPIDR_EL1[63:32] bits are not used for CPUs 395 * identification. 396 * 397 * Here we actually don't know whether our system is 32- or 64-bit one. 398 * The simplest way to go is to examine affinity IDs of all our CPUs. If 399 * at least one of them has Aff3 populated, we set #address-cells to 2. 400 */ 401 for (cpu = 0; cpu < smp_cpus; cpu++) { 402 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 403 404 if (arm_cpu_mp_affinity(armcpu) & ARM_AFF3_MASK) { 405 addr_cells = 2; 406 break; 407 } 408 } 409 410 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 411 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); 412 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 413 414 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 415 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 416 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 417 CPUState *cs = CPU(armcpu); 418 419 qemu_fdt_add_subnode(ms->fdt, nodename); 420 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 421 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 422 armcpu->dtb_compatible); 423 424 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { 425 qemu_fdt_setprop_string(ms->fdt, nodename, 426 "enable-method", "psci"); 427 } 428 429 if (addr_cells == 2) { 430 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", 431 arm_cpu_mp_affinity(armcpu)); 432 } else { 433 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", 434 arm_cpu_mp_affinity(armcpu)); 435 } 436 437 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 438 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 439 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 440 } 441 442 if (!vmc->no_cpu_topology) { 443 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 444 qemu_fdt_alloc_phandle(ms->fdt)); 445 } 446 447 g_free(nodename); 448 } 449 450 if (!vmc->no_cpu_topology) { 451 /* 452 * Add vCPU topology description through fdt node cpu-map. 453 * 454 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt 455 * In a SMP system, the hierarchy of CPUs can be defined through 456 * four entities that are used to describe the layout of CPUs in 457 * the system: socket/cluster/core/thread. 458 * 459 * A socket node represents the boundary of system physical package 460 * and its child nodes must be one or more cluster nodes. A system 461 * can contain several layers of clustering within a single physical 462 * package and cluster nodes can be contained in parent cluster nodes. 463 * 464 * Note: currently we only support one layer of clustering within 465 * each physical package. 466 */ 467 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 468 469 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 470 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); 471 char *map_path; 472 473 if (ms->smp.threads > 1) { 474 map_path = g_strdup_printf( 475 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", 476 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), 477 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, 478 (cpu / ms->smp.threads) % ms->smp.cores, 479 cpu % ms->smp.threads); 480 } else { 481 map_path = g_strdup_printf( 482 "/cpus/cpu-map/socket%d/cluster%d/core%d", 483 cpu / (ms->smp.clusters * ms->smp.cores), 484 (cpu / ms->smp.cores) % ms->smp.clusters, 485 cpu % ms->smp.cores); 486 } 487 qemu_fdt_add_path(ms->fdt, map_path); 488 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 489 490 g_free(map_path); 491 g_free(cpu_path); 492 } 493 } 494 } 495 496 static void fdt_add_its_gic_node(VirtMachineState *vms) 497 { 498 char *nodename; 499 MachineState *ms = MACHINE(vms); 500 501 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 502 nodename = g_strdup_printf("/intc/its@%" PRIx64, 503 vms->memmap[VIRT_GIC_ITS].base); 504 qemu_fdt_add_subnode(ms->fdt, nodename); 505 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 506 "arm,gic-v3-its"); 507 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 508 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1); 509 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 510 2, vms->memmap[VIRT_GIC_ITS].base, 511 2, vms->memmap[VIRT_GIC_ITS].size); 512 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 513 g_free(nodename); 514 } 515 516 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 517 { 518 MachineState *ms = MACHINE(vms); 519 char *nodename; 520 521 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 522 vms->memmap[VIRT_GIC_V2M].base); 523 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 524 qemu_fdt_add_subnode(ms->fdt, nodename); 525 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 526 "arm,gic-v2m-frame"); 527 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 528 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 529 2, vms->memmap[VIRT_GIC_V2M].base, 530 2, vms->memmap[VIRT_GIC_V2M].size); 531 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 532 g_free(nodename); 533 } 534 535 static void fdt_add_gic_node(VirtMachineState *vms) 536 { 537 MachineState *ms = MACHINE(vms); 538 char *nodename; 539 540 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 541 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); 542 543 nodename = g_strdup_printf("/intc@%" PRIx64, 544 vms->memmap[VIRT_GIC_DIST].base); 545 qemu_fdt_add_subnode(ms->fdt, nodename); 546 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 547 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 548 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 549 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 550 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 551 if (vms->gic_version != VIRT_GIC_VERSION_2) { 552 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 553 554 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 555 "arm,gic-v3"); 556 557 qemu_fdt_setprop_cell(ms->fdt, nodename, 558 "#redistributor-regions", nb_redist_regions); 559 560 if (nb_redist_regions == 1) { 561 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 562 2, vms->memmap[VIRT_GIC_DIST].base, 563 2, vms->memmap[VIRT_GIC_DIST].size, 564 2, vms->memmap[VIRT_GIC_REDIST].base, 565 2, vms->memmap[VIRT_GIC_REDIST].size); 566 } else { 567 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 568 2, vms->memmap[VIRT_GIC_DIST].base, 569 2, vms->memmap[VIRT_GIC_DIST].size, 570 2, vms->memmap[VIRT_GIC_REDIST].base, 571 2, vms->memmap[VIRT_GIC_REDIST].size, 572 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 573 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 574 } 575 576 if (vms->virt) { 577 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 578 GIC_FDT_IRQ_TYPE_PPI, 579 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), 580 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 581 } 582 } else { 583 /* 'cortex-a15-gic' means 'GIC v2' */ 584 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 585 "arm,cortex-a15-gic"); 586 if (!vms->virt) { 587 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 588 2, vms->memmap[VIRT_GIC_DIST].base, 589 2, vms->memmap[VIRT_GIC_DIST].size, 590 2, vms->memmap[VIRT_GIC_CPU].base, 591 2, vms->memmap[VIRT_GIC_CPU].size); 592 } else { 593 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 594 2, vms->memmap[VIRT_GIC_DIST].base, 595 2, vms->memmap[VIRT_GIC_DIST].size, 596 2, vms->memmap[VIRT_GIC_CPU].base, 597 2, vms->memmap[VIRT_GIC_CPU].size, 598 2, vms->memmap[VIRT_GIC_HYP].base, 599 2, vms->memmap[VIRT_GIC_HYP].size, 600 2, vms->memmap[VIRT_GIC_VCPU].base, 601 2, vms->memmap[VIRT_GIC_VCPU].size); 602 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 603 GIC_FDT_IRQ_TYPE_PPI, 604 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), 605 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 606 } 607 } 608 609 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); 610 g_free(nodename); 611 } 612 613 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 614 { 615 ARMCPU *armcpu = ARM_CPU(first_cpu); 616 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 617 MachineState *ms = MACHINE(vms); 618 619 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 620 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); 621 return; 622 } 623 624 if (vms->gic_version == VIRT_GIC_VERSION_2) { 625 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 626 GIC_FDT_IRQ_PPI_CPU_WIDTH, 627 (1 << MACHINE(vms)->smp.cpus) - 1); 628 } 629 630 qemu_fdt_add_subnode(ms->fdt, "/pmu"); 631 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 632 const char compat[] = "arm,armv8-pmuv3"; 633 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", 634 compat, sizeof(compat)); 635 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", 636 GIC_FDT_IRQ_TYPE_PPI, 637 INTID_TO_PPI(VIRTUAL_PMU_IRQ), irqflags); 638 } 639 } 640 641 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 642 { 643 DeviceState *dev; 644 MachineState *ms = MACHINE(vms); 645 int irq = vms->irqmap[VIRT_ACPI_GED]; 646 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 647 648 if (ms->ram_slots) { 649 event |= ACPI_GED_MEM_HOTPLUG_EVT; 650 } 651 652 if (ms->nvdimms_state->is_enabled) { 653 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 654 } 655 656 dev = qdev_new(TYPE_ACPI_GED); 657 qdev_prop_set_uint32(dev, "ged-event", event); 658 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 659 660 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 661 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 662 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 663 664 return dev; 665 } 666 667 static void create_its(VirtMachineState *vms) 668 { 669 const char *itsclass = its_class_name(); 670 DeviceState *dev; 671 672 if (!strcmp(itsclass, "arm-gicv3-its")) { 673 if (!vms->tcg_its) { 674 itsclass = NULL; 675 } 676 } 677 678 if (!itsclass) { 679 /* Do nothing if not supported */ 680 return; 681 } 682 683 dev = qdev_new(itsclass); 684 685 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 686 &error_abort); 687 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 688 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 689 690 fdt_add_its_gic_node(vms); 691 vms->msi_controller = VIRT_MSI_CTRL_ITS; 692 } 693 694 static void create_v2m(VirtMachineState *vms) 695 { 696 int i; 697 int irq = vms->irqmap[VIRT_GIC_V2M]; 698 DeviceState *dev; 699 700 dev = qdev_new("arm-gicv2m"); 701 qdev_prop_set_uint32(dev, "base-spi", irq); 702 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 703 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 704 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 705 706 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 707 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 708 qdev_get_gpio_in(vms->gic, irq + i)); 709 } 710 711 fdt_add_v2m_gic_node(vms); 712 vms->msi_controller = VIRT_MSI_CTRL_GICV2M; 713 } 714 715 static void create_gic(VirtMachineState *vms, MemoryRegion *mem) 716 { 717 MachineState *ms = MACHINE(vms); 718 /* We create a standalone GIC */ 719 SysBusDevice *gicbusdev; 720 const char *gictype; 721 int i; 722 unsigned int smp_cpus = ms->smp.cpus; 723 uint32_t nb_redist_regions = 0; 724 int revision; 725 726 if (vms->gic_version == VIRT_GIC_VERSION_2) { 727 gictype = gic_class_name(); 728 } else { 729 gictype = gicv3_class_name(); 730 } 731 732 switch (vms->gic_version) { 733 case VIRT_GIC_VERSION_2: 734 revision = 2; 735 break; 736 case VIRT_GIC_VERSION_3: 737 revision = 3; 738 break; 739 case VIRT_GIC_VERSION_4: 740 revision = 4; 741 break; 742 default: 743 g_assert_not_reached(); 744 } 745 vms->gic = qdev_new(gictype); 746 qdev_prop_set_uint32(vms->gic, "revision", revision); 747 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 748 /* Note that the num-irq property counts both internal and external 749 * interrupts; there are always 32 of the former (mandated by GIC spec). 750 */ 751 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 752 if (!kvm_irqchip_in_kernel()) { 753 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 754 } 755 756 if (vms->gic_version != VIRT_GIC_VERSION_2) { 757 QList *redist_region_count; 758 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); 759 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 760 761 nb_redist_regions = virt_gicv3_redist_region_count(vms); 762 763 redist_region_count = qlist_new(); 764 qlist_append_int(redist_region_count, redist0_count); 765 if (nb_redist_regions == 2) { 766 uint32_t redist1_capacity = 767 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 768 769 qlist_append_int(redist_region_count, 770 MIN(smp_cpus - redist0_count, redist1_capacity)); 771 } 772 qdev_prop_set_array(vms->gic, "redist-region-count", 773 redist_region_count); 774 775 if (!kvm_irqchip_in_kernel()) { 776 if (vms->tcg_its) { 777 object_property_set_link(OBJECT(vms->gic), "sysmem", 778 OBJECT(mem), &error_fatal); 779 qdev_prop_set_bit(vms->gic, "has-lpi", true); 780 } 781 } 782 } else { 783 if (!kvm_irqchip_in_kernel()) { 784 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 785 vms->virt); 786 } 787 } 788 gicbusdev = SYS_BUS_DEVICE(vms->gic); 789 sysbus_realize_and_unref(gicbusdev, &error_fatal); 790 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 791 if (vms->gic_version != VIRT_GIC_VERSION_2) { 792 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 793 if (nb_redist_regions == 2) { 794 sysbus_mmio_map(gicbusdev, 2, 795 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 796 } 797 } else { 798 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 799 if (vms->virt) { 800 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 801 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 802 } 803 } 804 805 /* Wire the outputs from each CPU's generic timer and the GICv3 806 * maintenance interrupt signal to the appropriate GIC PPI inputs, 807 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 808 */ 809 for (i = 0; i < smp_cpus; i++) { 810 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 811 int intidbase = NUM_IRQS + i * GIC_INTERNAL; 812 /* Mapping from the output timer irq lines from the CPU to the 813 * GIC PPI inputs we use for the virt board. 814 */ 815 const int timer_irq[] = { 816 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 817 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 818 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 819 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 820 [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, 821 }; 822 823 for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 824 qdev_connect_gpio_out(cpudev, irq, 825 qdev_get_gpio_in(vms->gic, 826 intidbase + timer_irq[irq])); 827 } 828 829 if (vms->gic_version != VIRT_GIC_VERSION_2) { 830 qemu_irq irq = qdev_get_gpio_in(vms->gic, 831 intidbase + ARCH_GIC_MAINT_IRQ); 832 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 833 0, irq); 834 } else if (vms->virt) { 835 qemu_irq irq = qdev_get_gpio_in(vms->gic, 836 intidbase + ARCH_GIC_MAINT_IRQ); 837 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 838 } 839 840 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 841 qdev_get_gpio_in(vms->gic, intidbase 842 + VIRTUAL_PMU_IRQ)); 843 844 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 845 sysbus_connect_irq(gicbusdev, i + smp_cpus, 846 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 847 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 848 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 849 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 850 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 851 } 852 853 fdt_add_gic_node(vms); 854 855 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) { 856 create_its(vms); 857 } else if (vms->gic_version == VIRT_GIC_VERSION_2) { 858 create_v2m(vms); 859 } 860 } 861 862 static void create_uart(const VirtMachineState *vms, int uart, 863 MemoryRegion *mem, Chardev *chr) 864 { 865 char *nodename; 866 hwaddr base = vms->memmap[uart].base; 867 hwaddr size = vms->memmap[uart].size; 868 int irq = vms->irqmap[uart]; 869 const char compat[] = "arm,pl011\0arm,primecell"; 870 const char clocknames[] = "uartclk\0apb_pclk"; 871 DeviceState *dev = qdev_new(TYPE_PL011); 872 SysBusDevice *s = SYS_BUS_DEVICE(dev); 873 MachineState *ms = MACHINE(vms); 874 875 qdev_prop_set_chr(dev, "chardev", chr); 876 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 877 memory_region_add_subregion(mem, base, 878 sysbus_mmio_get_region(s, 0)); 879 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 880 881 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 882 qemu_fdt_add_subnode(ms->fdt, nodename); 883 /* Note that we can't use setprop_string because of the embedded NUL */ 884 qemu_fdt_setprop(ms->fdt, nodename, "compatible", 885 compat, sizeof(compat)); 886 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 887 2, base, 2, size); 888 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 889 GIC_FDT_IRQ_TYPE_SPI, irq, 890 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 891 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", 892 vms->clock_phandle, vms->clock_phandle); 893 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", 894 clocknames, sizeof(clocknames)); 895 896 if (uart == VIRT_UART) { 897 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 898 } else { 899 /* Mark as not usable by the normal world */ 900 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 901 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 902 903 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", 904 nodename); 905 } 906 907 g_free(nodename); 908 } 909 910 static void create_rtc(const VirtMachineState *vms) 911 { 912 char *nodename; 913 hwaddr base = vms->memmap[VIRT_RTC].base; 914 hwaddr size = vms->memmap[VIRT_RTC].size; 915 int irq = vms->irqmap[VIRT_RTC]; 916 const char compat[] = "arm,pl031\0arm,primecell"; 917 MachineState *ms = MACHINE(vms); 918 919 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 920 921 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 922 qemu_fdt_add_subnode(ms->fdt, nodename); 923 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 924 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 925 2, base, 2, size); 926 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 927 GIC_FDT_IRQ_TYPE_SPI, irq, 928 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 929 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 930 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 931 g_free(nodename); 932 } 933 934 static DeviceState *gpio_key_dev; 935 static void virt_powerdown_req(Notifier *n, void *opaque) 936 { 937 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 938 939 if (s->acpi_dev) { 940 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 941 } else { 942 /* use gpio Pin 3 for power button event */ 943 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 944 } 945 } 946 947 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, 948 uint32_t phandle) 949 { 950 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 951 qdev_get_gpio_in(pl061_dev, 3)); 952 953 qemu_fdt_add_subnode(fdt, "/gpio-keys"); 954 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); 955 956 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); 957 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", 958 "label", "GPIO Key Poweroff"); 959 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", 960 KEY_POWER); 961 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", 962 "gpios", phandle, 3, 0); 963 } 964 965 #define SECURE_GPIO_POWEROFF 0 966 #define SECURE_GPIO_RESET 1 967 968 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, 969 uint32_t phandle) 970 { 971 DeviceState *gpio_pwr_dev; 972 973 /* gpio-pwr */ 974 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); 975 976 /* connect secure pl061 to gpio-pwr */ 977 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, 978 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); 979 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, 980 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); 981 982 qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); 983 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", 984 "gpio-poweroff"); 985 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", 986 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); 987 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); 988 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", 989 "okay"); 990 991 qemu_fdt_add_subnode(fdt, "/gpio-restart"); 992 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", 993 "gpio-restart"); 994 qemu_fdt_setprop_cells(fdt, "/gpio-restart", 995 "gpios", phandle, SECURE_GPIO_RESET, 0); 996 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); 997 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", 998 "okay"); 999 } 1000 1001 static void create_gpio_devices(const VirtMachineState *vms, int gpio, 1002 MemoryRegion *mem) 1003 { 1004 char *nodename; 1005 DeviceState *pl061_dev; 1006 hwaddr base = vms->memmap[gpio].base; 1007 hwaddr size = vms->memmap[gpio].size; 1008 int irq = vms->irqmap[gpio]; 1009 const char compat[] = "arm,pl061\0arm,primecell"; 1010 SysBusDevice *s; 1011 MachineState *ms = MACHINE(vms); 1012 1013 pl061_dev = qdev_new("pl061"); 1014 /* Pull lines down to 0 if not driven by the PL061 */ 1015 qdev_prop_set_uint32(pl061_dev, "pullups", 0); 1016 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); 1017 s = SYS_BUS_DEVICE(pl061_dev); 1018 sysbus_realize_and_unref(s, &error_fatal); 1019 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); 1020 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 1021 1022 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); 1023 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 1024 qemu_fdt_add_subnode(ms->fdt, nodename); 1025 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1026 2, base, 2, size); 1027 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 1028 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); 1029 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); 1030 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1031 GIC_FDT_IRQ_TYPE_SPI, irq, 1032 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1033 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1034 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1035 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); 1036 1037 if (gpio != VIRT_GPIO) { 1038 /* Mark as not usable by the normal world */ 1039 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1040 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1041 } 1042 g_free(nodename); 1043 1044 /* Child gpio devices */ 1045 if (gpio == VIRT_GPIO) { 1046 create_gpio_keys(ms->fdt, pl061_dev, phandle); 1047 } else { 1048 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); 1049 } 1050 } 1051 1052 static void create_virtio_devices(const VirtMachineState *vms) 1053 { 1054 int i; 1055 hwaddr size = vms->memmap[VIRT_MMIO].size; 1056 MachineState *ms = MACHINE(vms); 1057 1058 /* We create the transports in forwards order. Since qbus_realize() 1059 * prepends (not appends) new child buses, the incrementing loop below will 1060 * create a list of virtio-mmio buses with decreasing base addresses. 1061 * 1062 * When a -device option is processed from the command line, 1063 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 1064 * order. The upshot is that -device options in increasing command line 1065 * order are mapped to virtio-mmio buses with decreasing base addresses. 1066 * 1067 * When this code was originally written, that arrangement ensured that the 1068 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 1069 * the first -device on the command line. (The end-to-end order is a 1070 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 1071 * guest kernel's name-to-address assignment strategy.) 1072 * 1073 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 1074 * the message, if not necessarily the code, of commit 70161ff336. 1075 * Therefore the loop now establishes the inverse of the original intent. 1076 * 1077 * Unfortunately, we can't counteract the kernel change by reversing the 1078 * loop; it would break existing command lines. 1079 * 1080 * In any case, the kernel makes no guarantee about the stability of 1081 * enumeration order of virtio devices (as demonstrated by it changing 1082 * between kernel versions). For reliable and stable identification 1083 * of disks users must use UUIDs or similar mechanisms. 1084 */ 1085 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 1086 int irq = vms->irqmap[VIRT_MMIO] + i; 1087 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1088 1089 sysbus_create_simple("virtio-mmio", base, 1090 qdev_get_gpio_in(vms->gic, irq)); 1091 } 1092 1093 /* We add dtb nodes in reverse order so that they appear in the finished 1094 * device tree lowest address first. 1095 * 1096 * Note that this mapping is independent of the loop above. The previous 1097 * loop influences virtio device to virtio transport assignment, whereas 1098 * this loop controls how virtio transports are laid out in the dtb. 1099 */ 1100 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 1101 char *nodename; 1102 int irq = vms->irqmap[VIRT_MMIO] + i; 1103 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1104 1105 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 1106 qemu_fdt_add_subnode(ms->fdt, nodename); 1107 qemu_fdt_setprop_string(ms->fdt, nodename, 1108 "compatible", "virtio,mmio"); 1109 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1110 2, base, 2, size); 1111 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1112 GIC_FDT_IRQ_TYPE_SPI, irq, 1113 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1114 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1115 g_free(nodename); 1116 } 1117 } 1118 1119 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 1120 1121 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 1122 const char *name, 1123 const char *alias_prop_name) 1124 { 1125 /* 1126 * Create a single flash device. We use the same parameters as 1127 * the flash devices on the Versatile Express board. 1128 */ 1129 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 1130 1131 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 1132 qdev_prop_set_uint8(dev, "width", 4); 1133 qdev_prop_set_uint8(dev, "device-width", 2); 1134 qdev_prop_set_bit(dev, "big-endian", false); 1135 qdev_prop_set_uint16(dev, "id0", 0x89); 1136 qdev_prop_set_uint16(dev, "id1", 0x18); 1137 qdev_prop_set_uint16(dev, "id2", 0x00); 1138 qdev_prop_set_uint16(dev, "id3", 0x00); 1139 qdev_prop_set_string(dev, "name", name); 1140 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 1141 object_property_add_alias(OBJECT(vms), alias_prop_name, 1142 OBJECT(dev), "drive"); 1143 return PFLASH_CFI01(dev); 1144 } 1145 1146 static void virt_flash_create(VirtMachineState *vms) 1147 { 1148 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 1149 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 1150 } 1151 1152 static void virt_flash_map1(PFlashCFI01 *flash, 1153 hwaddr base, hwaddr size, 1154 MemoryRegion *sysmem) 1155 { 1156 DeviceState *dev = DEVICE(flash); 1157 1158 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 1159 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 1160 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 1161 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1162 1163 memory_region_add_subregion(sysmem, base, 1164 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1165 0)); 1166 } 1167 1168 static void virt_flash_map(VirtMachineState *vms, 1169 MemoryRegion *sysmem, 1170 MemoryRegion *secure_sysmem) 1171 { 1172 /* 1173 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 1174 * sysmem is the system memory space. secure_sysmem is the secure view 1175 * of the system, and the first flash device should be made visible only 1176 * there. The second flash device is visible to both secure and nonsecure. 1177 * If sysmem == secure_sysmem this means there is no separate Secure 1178 * address space and both flash devices are generally visible. 1179 */ 1180 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1181 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1182 1183 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1184 secure_sysmem); 1185 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1186 sysmem); 1187 } 1188 1189 static void virt_flash_fdt(VirtMachineState *vms, 1190 MemoryRegion *sysmem, 1191 MemoryRegion *secure_sysmem) 1192 { 1193 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1194 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1195 MachineState *ms = MACHINE(vms); 1196 char *nodename; 1197 1198 if (sysmem == secure_sysmem) { 1199 /* Report both flash devices as a single node in the DT */ 1200 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1201 qemu_fdt_add_subnode(ms->fdt, nodename); 1202 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1203 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1204 2, flashbase, 2, flashsize, 1205 2, flashbase + flashsize, 2, flashsize); 1206 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1207 g_free(nodename); 1208 } else { 1209 /* 1210 * Report the devices as separate nodes so we can mark one as 1211 * only visible to the secure world. 1212 */ 1213 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1214 qemu_fdt_add_subnode(ms->fdt, nodename); 1215 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1216 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1217 2, flashbase, 2, flashsize); 1218 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1219 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1220 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1221 g_free(nodename); 1222 1223 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize); 1224 qemu_fdt_add_subnode(ms->fdt, nodename); 1225 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1226 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1227 2, flashbase + flashsize, 2, flashsize); 1228 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1229 g_free(nodename); 1230 } 1231 } 1232 1233 static bool virt_firmware_init(VirtMachineState *vms, 1234 MemoryRegion *sysmem, 1235 MemoryRegion *secure_sysmem) 1236 { 1237 int i; 1238 const char *bios_name; 1239 BlockBackend *pflash_blk0; 1240 1241 /* Map legacy -drive if=pflash to machine properties */ 1242 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1243 pflash_cfi01_legacy_drive(vms->flash[i], 1244 drive_get(IF_PFLASH, 0, i)); 1245 } 1246 1247 virt_flash_map(vms, sysmem, secure_sysmem); 1248 1249 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1250 1251 bios_name = MACHINE(vms)->firmware; 1252 if (bios_name) { 1253 char *fname; 1254 MemoryRegion *mr; 1255 int image_size; 1256 1257 if (pflash_blk0) { 1258 error_report("The contents of the first flash device may be " 1259 "specified with -bios or with -drive if=pflash... " 1260 "but you cannot use both options at once"); 1261 exit(1); 1262 } 1263 1264 /* Fall back to -bios */ 1265 1266 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1267 if (!fname) { 1268 error_report("Could not find ROM image '%s'", bios_name); 1269 exit(1); 1270 } 1271 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1272 image_size = load_image_mr(fname, mr); 1273 g_free(fname); 1274 if (image_size < 0) { 1275 error_report("Could not load ROM image '%s'", bios_name); 1276 exit(1); 1277 } 1278 } 1279 1280 return pflash_blk0 || bios_name; 1281 } 1282 1283 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1284 { 1285 MachineState *ms = MACHINE(vms); 1286 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1287 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1288 FWCfgState *fw_cfg; 1289 char *nodename; 1290 1291 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1292 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1293 1294 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1295 qemu_fdt_add_subnode(ms->fdt, nodename); 1296 qemu_fdt_setprop_string(ms->fdt, nodename, 1297 "compatible", "qemu,fw-cfg-mmio"); 1298 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1299 2, base, 2, size); 1300 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1301 g_free(nodename); 1302 return fw_cfg; 1303 } 1304 1305 static void create_pcie_irq_map(const MachineState *ms, 1306 uint32_t gic_phandle, 1307 int first_irq, const char *nodename) 1308 { 1309 int devfn, pin; 1310 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1311 uint32_t *irq_map = full_irq_map; 1312 1313 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1314 for (pin = 0; pin < 4; pin++) { 1315 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1316 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1317 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1318 int i; 1319 1320 uint32_t map[] = { 1321 devfn << 8, 0, 0, /* devfn */ 1322 pin + 1, /* PCI pin */ 1323 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1324 1325 /* Convert map to big endian */ 1326 for (i = 0; i < 10; i++) { 1327 irq_map[i] = cpu_to_be32(map[i]); 1328 } 1329 irq_map += 10; 1330 } 1331 } 1332 1333 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", 1334 full_irq_map, sizeof(full_irq_map)); 1335 1336 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 1337 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ 1338 0, 0, 1339 0x7 /* PCI irq */); 1340 } 1341 1342 static void create_smmu(const VirtMachineState *vms, 1343 PCIBus *bus) 1344 { 1345 char *node; 1346 const char compat[] = "arm,smmu-v3"; 1347 int irq = vms->irqmap[VIRT_SMMU]; 1348 int i; 1349 hwaddr base = vms->memmap[VIRT_SMMU].base; 1350 hwaddr size = vms->memmap[VIRT_SMMU].size; 1351 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1352 DeviceState *dev; 1353 MachineState *ms = MACHINE(vms); 1354 1355 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1356 return; 1357 } 1358 1359 dev = qdev_new(TYPE_ARM_SMMUV3); 1360 1361 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1362 &error_abort); 1363 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1364 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1365 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1366 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1367 qdev_get_gpio_in(vms->gic, irq + i)); 1368 } 1369 1370 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1371 qemu_fdt_add_subnode(ms->fdt, node); 1372 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1373 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); 1374 1375 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", 1376 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1377 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1378 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1379 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1380 1381 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, 1382 sizeof(irq_names)); 1383 1384 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); 1385 1386 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1387 1388 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1389 g_free(node); 1390 } 1391 1392 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1393 { 1394 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1395 uint16_t bdf = vms->virtio_iommu_bdf; 1396 MachineState *ms = MACHINE(vms); 1397 char *node; 1398 1399 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1400 1401 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename, 1402 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1403 qemu_fdt_add_subnode(ms->fdt, node); 1404 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1405 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 1406 1, bdf << 8, 1, 0, 1, 0, 1407 1, 0, 1, 0); 1408 1409 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1410 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1411 g_free(node); 1412 1413 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", 1414 0x0, vms->iommu_phandle, 0x0, bdf, 1415 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1416 } 1417 1418 static void create_pcie(VirtMachineState *vms) 1419 { 1420 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1421 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1422 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1423 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1424 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1425 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1426 hwaddr base_ecam, size_ecam; 1427 hwaddr base = base_mmio; 1428 int nr_pcie_buses; 1429 int irq = vms->irqmap[VIRT_PCIE]; 1430 MemoryRegion *mmio_alias; 1431 MemoryRegion *mmio_reg; 1432 MemoryRegion *ecam_alias; 1433 MemoryRegion *ecam_reg; 1434 DeviceState *dev; 1435 char *nodename; 1436 int i, ecam_id; 1437 PCIHostState *pci; 1438 MachineState *ms = MACHINE(vms); 1439 MachineClass *mc = MACHINE_GET_CLASS(ms); 1440 1441 dev = qdev_new(TYPE_GPEX_HOST); 1442 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1443 1444 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1445 base_ecam = vms->memmap[ecam_id].base; 1446 size_ecam = vms->memmap[ecam_id].size; 1447 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1448 /* Map only the first size_ecam bytes of ECAM space */ 1449 ecam_alias = g_new0(MemoryRegion, 1); 1450 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1451 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1452 ecam_reg, 0, size_ecam); 1453 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1454 1455 /* Map the MMIO window into system address space so as to expose 1456 * the section of PCI MMIO space which starts at the same base address 1457 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1458 * the window). 1459 */ 1460 mmio_alias = g_new0(MemoryRegion, 1); 1461 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1462 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1463 mmio_reg, base_mmio, size_mmio); 1464 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1465 1466 if (vms->highmem_mmio) { 1467 /* Map high MMIO space */ 1468 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1469 1470 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1471 mmio_reg, base_mmio_high, size_mmio_high); 1472 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1473 high_mmio_alias); 1474 } 1475 1476 /* Map IO port space */ 1477 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1478 1479 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1480 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1481 qdev_get_gpio_in(vms->gic, irq + i)); 1482 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1483 } 1484 1485 pci = PCI_HOST_BRIDGE(dev); 1486 pci->bypass_iommu = vms->default_bus_bypass_iommu; 1487 vms->bus = pci->bus; 1488 if (vms->bus) { 1489 pci_init_nic_devices(pci->bus, mc->default_nic); 1490 } 1491 1492 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1493 qemu_fdt_add_subnode(ms->fdt, nodename); 1494 qemu_fdt_setprop_string(ms->fdt, nodename, 1495 "compatible", "pci-host-ecam-generic"); 1496 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 1497 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 1498 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 1499 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 1500 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 1501 nr_pcie_buses - 1); 1502 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1503 1504 if (vms->msi_phandle) { 1505 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 1506 0, vms->msi_phandle, 0, 0x10000); 1507 } 1508 1509 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1510 2, base_ecam, 2, size_ecam); 1511 1512 if (vms->highmem_mmio) { 1513 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1514 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1515 2, base_pio, 2, size_pio, 1516 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1517 2, base_mmio, 2, size_mmio, 1518 1, FDT_PCI_RANGE_MMIO_64BIT, 1519 2, base_mmio_high, 1520 2, base_mmio_high, 2, size_mmio_high); 1521 } else { 1522 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1523 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1524 2, base_pio, 2, size_pio, 1525 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1526 2, base_mmio, 2, size_mmio); 1527 } 1528 1529 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 1530 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); 1531 1532 if (vms->iommu) { 1533 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1534 1535 switch (vms->iommu) { 1536 case VIRT_IOMMU_SMMUV3: 1537 create_smmu(vms, vms->bus); 1538 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 1539 0x0, vms->iommu_phandle, 0x0, 0x10000); 1540 break; 1541 default: 1542 g_assert_not_reached(); 1543 } 1544 } 1545 } 1546 1547 static void create_platform_bus(VirtMachineState *vms) 1548 { 1549 DeviceState *dev; 1550 SysBusDevice *s; 1551 int i; 1552 MemoryRegion *sysmem = get_system_memory(); 1553 1554 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1555 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1556 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1557 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1558 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1559 vms->platform_bus_dev = dev; 1560 1561 s = SYS_BUS_DEVICE(dev); 1562 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1563 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1564 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1565 } 1566 1567 memory_region_add_subregion(sysmem, 1568 vms->memmap[VIRT_PLATFORM_BUS].base, 1569 sysbus_mmio_get_region(s, 0)); 1570 } 1571 1572 static void create_tag_ram(MemoryRegion *tag_sysmem, 1573 hwaddr base, hwaddr size, 1574 const char *name) 1575 { 1576 MemoryRegion *tagram = g_new(MemoryRegion, 1); 1577 1578 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); 1579 memory_region_add_subregion(tag_sysmem, base / 32, tagram); 1580 } 1581 1582 static void create_secure_ram(VirtMachineState *vms, 1583 MemoryRegion *secure_sysmem, 1584 MemoryRegion *secure_tag_sysmem) 1585 { 1586 MemoryRegion *secram = g_new(MemoryRegion, 1); 1587 char *nodename; 1588 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1589 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1590 MachineState *ms = MACHINE(vms); 1591 1592 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1593 &error_fatal); 1594 memory_region_add_subregion(secure_sysmem, base, secram); 1595 1596 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1597 qemu_fdt_add_subnode(ms->fdt, nodename); 1598 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 1599 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 1600 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1601 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1602 1603 if (secure_tag_sysmem) { 1604 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); 1605 } 1606 1607 g_free(nodename); 1608 } 1609 1610 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1611 { 1612 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1613 bootinfo); 1614 MachineState *ms = MACHINE(board); 1615 1616 1617 *fdt_size = board->fdt_size; 1618 return ms->fdt; 1619 } 1620 1621 static void virt_build_smbios(VirtMachineState *vms) 1622 { 1623 MachineClass *mc = MACHINE_GET_CLASS(vms); 1624 MachineState *ms = MACHINE(vms); 1625 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1626 uint8_t *smbios_tables, *smbios_anchor; 1627 size_t smbios_tables_len, smbios_anchor_len; 1628 struct smbios_phys_mem_area mem_array; 1629 const char *product = "QEMU Virtual Machine"; 1630 1631 if (kvm_enabled()) { 1632 product = "KVM Virtual Machine"; 1633 } 1634 1635 smbios_set_defaults("QEMU", product, 1636 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1637 true, SMBIOS_ENTRY_POINT_TYPE_64); 1638 1639 /* build the array of physical mem area from base_memmap */ 1640 mem_array.address = vms->memmap[VIRT_MEM].base; 1641 mem_array.length = ms->ram_size; 1642 1643 smbios_get_tables(ms, &mem_array, 1, 1644 &smbios_tables, &smbios_tables_len, 1645 &smbios_anchor, &smbios_anchor_len, 1646 &error_fatal); 1647 1648 if (smbios_anchor) { 1649 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1650 smbios_tables, smbios_tables_len); 1651 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1652 smbios_anchor, smbios_anchor_len); 1653 } 1654 } 1655 1656 static 1657 void virt_machine_done(Notifier *notifier, void *data) 1658 { 1659 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1660 machine_done); 1661 MachineState *ms = MACHINE(vms); 1662 ARMCPU *cpu = ARM_CPU(first_cpu); 1663 struct arm_boot_info *info = &vms->bootinfo; 1664 AddressSpace *as = arm_boot_address_space(cpu, info); 1665 1666 /* 1667 * If the user provided a dtb, we assume the dynamic sysbus nodes 1668 * already are integrated there. This corresponds to a use case where 1669 * the dynamic sysbus nodes are complex and their generation is not yet 1670 * supported. In that case the user can take charge of the guest dt 1671 * while qemu takes charge of the qom stuff. 1672 */ 1673 if (info->dtb_filename == NULL) { 1674 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", 1675 vms->memmap[VIRT_PLATFORM_BUS].base, 1676 vms->memmap[VIRT_PLATFORM_BUS].size, 1677 vms->irqmap[VIRT_PLATFORM_BUS]); 1678 } 1679 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1680 exit(1); 1681 } 1682 1683 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg); 1684 1685 virt_acpi_setup(vms); 1686 virt_build_smbios(vms); 1687 } 1688 1689 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1690 { 1691 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1692 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1693 1694 if (!vmc->disallow_affinity_adjustment) { 1695 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1696 * GIC's target-list limitations. 32-bit KVM hosts currently 1697 * always create clusters of 4 CPUs, but that is expected to 1698 * change when they gain support for gicv3. When KVM is enabled 1699 * it will override the changes we make here, therefore our 1700 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1701 * and to improve SGI efficiency. 1702 */ 1703 if (vms->gic_version == VIRT_GIC_VERSION_2) { 1704 clustersz = GIC_TARGETLIST_BITS; 1705 } else { 1706 clustersz = GICV3_TARGETLIST_BITS; 1707 } 1708 } 1709 return arm_build_mp_affinity(idx, clustersz); 1710 } 1711 1712 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, 1713 int index) 1714 { 1715 bool *enabled_array[] = { 1716 &vms->highmem_redists, 1717 &vms->highmem_ecam, 1718 &vms->highmem_mmio, 1719 }; 1720 1721 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST == 1722 ARRAY_SIZE(enabled_array)); 1723 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array)); 1724 1725 return enabled_array[index - VIRT_LOWMEMMAP_LAST]; 1726 } 1727 1728 static void virt_set_high_memmap(VirtMachineState *vms, 1729 hwaddr base, int pa_bits) 1730 { 1731 hwaddr region_base, region_size; 1732 bool *region_enabled, fits; 1733 int i; 1734 1735 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1736 region_enabled = virt_get_high_memmap_enabled(vms, i); 1737 region_base = ROUND_UP(base, extended_memmap[i].size); 1738 region_size = extended_memmap[i].size; 1739 1740 vms->memmap[i].base = region_base; 1741 vms->memmap[i].size = region_size; 1742 1743 /* 1744 * Check each device to see if it fits in the PA space, 1745 * moving highest_gpa as we go. For compatibility, move 1746 * highest_gpa for disabled fitting devices as well, if 1747 * the compact layout has been disabled. 1748 * 1749 * For each device that doesn't fit, disable it. 1750 */ 1751 fits = (region_base + region_size) <= BIT_ULL(pa_bits); 1752 *region_enabled &= fits; 1753 if (vms->highmem_compact && !*region_enabled) { 1754 continue; 1755 } 1756 1757 base = region_base + region_size; 1758 if (fits) { 1759 vms->highest_gpa = base - 1; 1760 } 1761 } 1762 } 1763 1764 static void virt_set_memmap(VirtMachineState *vms, int pa_bits) 1765 { 1766 MachineState *ms = MACHINE(vms); 1767 hwaddr base, device_memory_base, device_memory_size, memtop; 1768 int i; 1769 1770 vms->memmap = extended_memmap; 1771 1772 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1773 vms->memmap[i] = base_memmap[i]; 1774 } 1775 1776 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1777 error_report("unsupported number of memory slots: %"PRIu64, 1778 ms->ram_slots); 1779 exit(EXIT_FAILURE); 1780 } 1781 1782 /* 1783 * !highmem is exactly the same as limiting the PA space to 32bit, 1784 * irrespective of the underlying capabilities of the HW. 1785 */ 1786 if (!vms->highmem) { 1787 pa_bits = 32; 1788 } 1789 1790 /* 1791 * We compute the base of the high IO region depending on the 1792 * amount of initial and device memory. The device memory start/size 1793 * is aligned on 1GiB. We never put the high IO region below 256GiB 1794 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1795 * The device region size assumes 1GiB page max alignment per slot. 1796 */ 1797 device_memory_base = 1798 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1799 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1800 1801 /* Base address of the high IO region */ 1802 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1803 if (memtop > BIT_ULL(pa_bits)) { 1804 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes", 1805 pa_bits, memtop - BIT_ULL(pa_bits)); 1806 exit(EXIT_FAILURE); 1807 } 1808 if (base < device_memory_base) { 1809 error_report("maxmem/slots too huge"); 1810 exit(EXIT_FAILURE); 1811 } 1812 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1813 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1814 } 1815 1816 /* We know for sure that at least the memory fits in the PA space */ 1817 vms->highest_gpa = memtop - 1; 1818 1819 virt_set_high_memmap(vms, base, pa_bits); 1820 1821 if (device_memory_size > 0) { 1822 machine_memory_devices_init(ms, device_memory_base, device_memory_size); 1823 } 1824 } 1825 1826 static VirtGICType finalize_gic_version_do(const char *accel_name, 1827 VirtGICType gic_version, 1828 int gics_supported, 1829 unsigned int max_cpus) 1830 { 1831 /* Convert host/max/nosel to GIC version number */ 1832 switch (gic_version) { 1833 case VIRT_GIC_VERSION_HOST: 1834 if (!kvm_enabled()) { 1835 error_report("gic-version=host requires KVM"); 1836 exit(1); 1837 } 1838 1839 /* For KVM, gic-version=host means gic-version=max */ 1840 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX, 1841 gics_supported, max_cpus); 1842 case VIRT_GIC_VERSION_MAX: 1843 if (gics_supported & VIRT_GIC_VERSION_4_MASK) { 1844 gic_version = VIRT_GIC_VERSION_4; 1845 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1846 gic_version = VIRT_GIC_VERSION_3; 1847 } else { 1848 gic_version = VIRT_GIC_VERSION_2; 1849 } 1850 break; 1851 case VIRT_GIC_VERSION_NOSEL: 1852 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) && 1853 max_cpus <= GIC_NCPU) { 1854 gic_version = VIRT_GIC_VERSION_2; 1855 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1856 /* 1857 * in case the host does not support v2 emulation or 1858 * the end-user requested more than 8 VCPUs we now default 1859 * to v3. In any case defaulting to v2 would be broken. 1860 */ 1861 gic_version = VIRT_GIC_VERSION_3; 1862 } else if (max_cpus > GIC_NCPU) { 1863 error_report("%s only supports GICv2 emulation but more than 8 " 1864 "vcpus are requested", accel_name); 1865 exit(1); 1866 } 1867 break; 1868 case VIRT_GIC_VERSION_2: 1869 case VIRT_GIC_VERSION_3: 1870 case VIRT_GIC_VERSION_4: 1871 break; 1872 } 1873 1874 /* Check chosen version is effectively supported */ 1875 switch (gic_version) { 1876 case VIRT_GIC_VERSION_2: 1877 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) { 1878 error_report("%s does not support GICv2 emulation", accel_name); 1879 exit(1); 1880 } 1881 break; 1882 case VIRT_GIC_VERSION_3: 1883 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) { 1884 error_report("%s does not support GICv3 emulation", accel_name); 1885 exit(1); 1886 } 1887 break; 1888 case VIRT_GIC_VERSION_4: 1889 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) { 1890 error_report("%s does not support GICv4 emulation, is virtualization=on?", 1891 accel_name); 1892 exit(1); 1893 } 1894 break; 1895 default: 1896 error_report("logic error in finalize_gic_version"); 1897 exit(1); 1898 break; 1899 } 1900 1901 return gic_version; 1902 } 1903 1904 /* 1905 * finalize_gic_version - Determines the final gic_version 1906 * according to the gic-version property 1907 * 1908 * Default GIC type is v2 1909 */ 1910 static void finalize_gic_version(VirtMachineState *vms) 1911 { 1912 const char *accel_name = current_accel_name(); 1913 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 1914 int gics_supported = 0; 1915 1916 /* Determine which GIC versions the current environment supports */ 1917 if (kvm_enabled() && kvm_irqchip_in_kernel()) { 1918 int probe_bitmap = kvm_arm_vgic_probe(); 1919 1920 if (!probe_bitmap) { 1921 error_report("Unable to determine GIC version supported by host"); 1922 exit(1); 1923 } 1924 1925 if (probe_bitmap & KVM_ARM_VGIC_V2) { 1926 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1927 } 1928 if (probe_bitmap & KVM_ARM_VGIC_V3) { 1929 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1930 } 1931 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) { 1932 /* KVM w/o kernel irqchip can only deal with GICv2 */ 1933 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1934 accel_name = "KVM with kernel-irqchip=off"; 1935 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { 1936 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1937 if (module_object_class_by_name("arm-gicv3")) { 1938 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1939 if (vms->virt) { 1940 /* GICv4 only makes sense if CPU has EL2 */ 1941 gics_supported |= VIRT_GIC_VERSION_4_MASK; 1942 } 1943 } 1944 } else { 1945 error_report("Unsupported accelerator, can not determine GIC support"); 1946 exit(1); 1947 } 1948 1949 /* 1950 * Then convert helpers like host/max to concrete GIC versions and ensure 1951 * the desired version is supported 1952 */ 1953 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version, 1954 gics_supported, max_cpus); 1955 } 1956 1957 /* 1958 * virt_cpu_post_init() must be called after the CPUs have 1959 * been realized and the GIC has been created. 1960 */ 1961 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) 1962 { 1963 int max_cpus = MACHINE(vms)->smp.max_cpus; 1964 bool aarch64, pmu, steal_time; 1965 CPUState *cpu; 1966 1967 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); 1968 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); 1969 steal_time = object_property_get_bool(OBJECT(first_cpu), 1970 "kvm-steal-time", NULL); 1971 1972 if (kvm_enabled()) { 1973 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; 1974 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; 1975 1976 if (steal_time) { 1977 MemoryRegion *pvtime = g_new(MemoryRegion, 1); 1978 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; 1979 1980 /* The memory region size must be a multiple of host page size. */ 1981 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); 1982 1983 if (pvtime_size > pvtime_reg_size) { 1984 error_report("pvtime requires a %" HWADDR_PRId 1985 " byte memory region for %d CPUs," 1986 " but only %" HWADDR_PRId " has been reserved", 1987 pvtime_size, max_cpus, pvtime_reg_size); 1988 exit(1); 1989 } 1990 1991 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); 1992 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); 1993 } 1994 1995 CPU_FOREACH(cpu) { 1996 if (pmu) { 1997 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); 1998 if (kvm_irqchip_in_kernel()) { 1999 kvm_arm_pmu_set_irq(ARM_CPU(cpu), VIRTUAL_PMU_IRQ); 2000 } 2001 kvm_arm_pmu_init(ARM_CPU(cpu)); 2002 } 2003 if (steal_time) { 2004 kvm_arm_pvtime_init(ARM_CPU(cpu), pvtime_reg_base 2005 + cpu->cpu_index 2006 * PVTIME_SIZE_PER_CPU); 2007 } 2008 } 2009 } else { 2010 if (aarch64 && vms->highmem) { 2011 int requested_pa_size = 64 - clz64(vms->highest_gpa); 2012 int pamax = arm_pamax(ARM_CPU(first_cpu)); 2013 2014 if (pamax < requested_pa_size) { 2015 error_report("VCPU supports less PA bits (%d) than " 2016 "requested by the memory map (%d)", 2017 pamax, requested_pa_size); 2018 exit(1); 2019 } 2020 } 2021 } 2022 } 2023 2024 static void machvirt_init(MachineState *machine) 2025 { 2026 VirtMachineState *vms = VIRT_MACHINE(machine); 2027 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 2028 MachineClass *mc = MACHINE_GET_CLASS(machine); 2029 const CPUArchIdList *possible_cpus; 2030 MemoryRegion *sysmem = get_system_memory(); 2031 MemoryRegion *secure_sysmem = NULL; 2032 MemoryRegion *tag_sysmem = NULL; 2033 MemoryRegion *secure_tag_sysmem = NULL; 2034 int n, virt_max_cpus; 2035 bool firmware_loaded; 2036 bool aarch64 = true; 2037 bool has_ged = !vmc->no_ged; 2038 unsigned int smp_cpus = machine->smp.cpus; 2039 unsigned int max_cpus = machine->smp.max_cpus; 2040 2041 possible_cpus = mc->possible_cpu_arch_ids(machine); 2042 2043 /* 2044 * In accelerated mode, the memory map is computed earlier in kvm_type() 2045 * to create a VM with the right number of IPA bits. 2046 */ 2047 if (!vms->memmap) { 2048 Object *cpuobj; 2049 ARMCPU *armcpu; 2050 int pa_bits; 2051 2052 /* 2053 * Instantiate a temporary CPU object to find out about what 2054 * we are about to deal with. Once this is done, get rid of 2055 * the object. 2056 */ 2057 cpuobj = object_new(possible_cpus->cpus[0].type); 2058 armcpu = ARM_CPU(cpuobj); 2059 2060 pa_bits = arm_pamax(armcpu); 2061 2062 object_unref(cpuobj); 2063 2064 virt_set_memmap(vms, pa_bits); 2065 } 2066 2067 /* We can probe only here because during property set 2068 * KVM is not available yet 2069 */ 2070 finalize_gic_version(vms); 2071 2072 if (vms->secure) { 2073 /* 2074 * The Secure view of the world is the same as the NonSecure, 2075 * but with a few extra devices. Create it as a container region 2076 * containing the system memory at low priority; any secure-only 2077 * devices go in at higher priority and take precedence. 2078 */ 2079 secure_sysmem = g_new(MemoryRegion, 1); 2080 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 2081 UINT64_MAX); 2082 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 2083 } 2084 2085 firmware_loaded = virt_firmware_init(vms, sysmem, 2086 secure_sysmem ?: sysmem); 2087 2088 /* If we have an EL3 boot ROM then the assumption is that it will 2089 * implement PSCI itself, so disable QEMU's internal implementation 2090 * so it doesn't get in the way. Instead of starting secondary 2091 * CPUs in PSCI powerdown state we will start them all running and 2092 * let the boot ROM sort them out. 2093 * The usual case is that we do use QEMU's PSCI implementation; 2094 * if the guest has EL2 then we will use SMC as the conduit, 2095 * and otherwise we will use HVC (for backwards compatibility and 2096 * because if we're using KVM then we must use HVC). 2097 */ 2098 if (vms->secure && firmware_loaded) { 2099 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 2100 } else if (vms->virt) { 2101 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 2102 } else { 2103 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 2104 } 2105 2106 /* 2107 * The maximum number of CPUs depends on the GIC version, or on how 2108 * many redistributors we can fit into the memory map (which in turn 2109 * depends on whether this is a GICv3 or v4). 2110 */ 2111 if (vms->gic_version == VIRT_GIC_VERSION_2) { 2112 virt_max_cpus = GIC_NCPU; 2113 } else { 2114 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST); 2115 if (vms->highmem_redists) { 2116 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 2117 } 2118 } 2119 2120 if (max_cpus > virt_max_cpus) { 2121 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 2122 "supported by machine 'mach-virt' (%d)", 2123 max_cpus, virt_max_cpus); 2124 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) { 2125 error_printf("Try 'highmem-redists=on' for more CPUs\n"); 2126 } 2127 2128 exit(1); 2129 } 2130 2131 if (vms->secure && (kvm_enabled() || hvf_enabled())) { 2132 error_report("mach-virt: %s does not support providing " 2133 "Security extensions (TrustZone) to the guest CPU", 2134 current_accel_name()); 2135 exit(1); 2136 } 2137 2138 if (vms->virt && (kvm_enabled() || hvf_enabled())) { 2139 error_report("mach-virt: %s does not support providing " 2140 "Virtualization extensions to the guest CPU", 2141 current_accel_name()); 2142 exit(1); 2143 } 2144 2145 if (vms->mte && (kvm_enabled() || hvf_enabled())) { 2146 error_report("mach-virt: %s does not support providing " 2147 "MTE to the guest CPU", 2148 current_accel_name()); 2149 exit(1); 2150 } 2151 2152 create_fdt(vms); 2153 2154 assert(possible_cpus->len == max_cpus); 2155 for (n = 0; n < possible_cpus->len; n++) { 2156 Object *cpuobj; 2157 CPUState *cs; 2158 2159 if (n >= smp_cpus) { 2160 break; 2161 } 2162 2163 cpuobj = object_new(possible_cpus->cpus[n].type); 2164 object_property_set_int(cpuobj, "mp-affinity", 2165 possible_cpus->cpus[n].arch_id, NULL); 2166 2167 cs = CPU(cpuobj); 2168 cs->cpu_index = n; 2169 2170 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 2171 &error_fatal); 2172 2173 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 2174 2175 if (!vms->secure) { 2176 object_property_set_bool(cpuobj, "has_el3", false, NULL); 2177 } 2178 2179 if (!vms->virt && object_property_find(cpuobj, "has_el2")) { 2180 object_property_set_bool(cpuobj, "has_el2", false, NULL); 2181 } 2182 2183 if (vmc->kvm_no_adjvtime && 2184 object_property_find(cpuobj, "kvm-no-adjvtime")) { 2185 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 2186 } 2187 2188 if (vmc->no_kvm_steal_time && 2189 object_property_find(cpuobj, "kvm-steal-time")) { 2190 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); 2191 } 2192 2193 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { 2194 object_property_set_bool(cpuobj, "pmu", false, NULL); 2195 } 2196 2197 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { 2198 object_property_set_bool(cpuobj, "lpa2", false, NULL); 2199 } 2200 2201 if (object_property_find(cpuobj, "reset-cbar")) { 2202 object_property_set_int(cpuobj, "reset-cbar", 2203 vms->memmap[VIRT_CPUPERIPHS].base, 2204 &error_abort); 2205 } 2206 2207 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 2208 &error_abort); 2209 if (vms->secure) { 2210 object_property_set_link(cpuobj, "secure-memory", 2211 OBJECT(secure_sysmem), &error_abort); 2212 } 2213 2214 if (vms->mte) { 2215 /* Create the memory region only once, but link to all cpus. */ 2216 if (!tag_sysmem) { 2217 /* 2218 * The property exists only if MemTag is supported. 2219 * If it is, we must allocate the ram to back that up. 2220 */ 2221 if (!object_property_find(cpuobj, "tag-memory")) { 2222 error_report("MTE requested, but not supported " 2223 "by the guest CPU"); 2224 exit(1); 2225 } 2226 2227 tag_sysmem = g_new(MemoryRegion, 1); 2228 memory_region_init(tag_sysmem, OBJECT(machine), 2229 "tag-memory", UINT64_MAX / 32); 2230 2231 if (vms->secure) { 2232 secure_tag_sysmem = g_new(MemoryRegion, 1); 2233 memory_region_init(secure_tag_sysmem, OBJECT(machine), 2234 "secure-tag-memory", UINT64_MAX / 32); 2235 2236 /* As with ram, secure-tag takes precedence over tag. */ 2237 memory_region_add_subregion_overlap(secure_tag_sysmem, 0, 2238 tag_sysmem, -1); 2239 } 2240 } 2241 2242 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem), 2243 &error_abort); 2244 if (vms->secure) { 2245 object_property_set_link(cpuobj, "secure-tag-memory", 2246 OBJECT(secure_tag_sysmem), 2247 &error_abort); 2248 } 2249 } 2250 2251 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 2252 object_unref(cpuobj); 2253 } 2254 2255 /* Now we've created the CPUs we can see if they have the hypvirt timer */ 2256 vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() && 2257 !vmc->no_ns_el2_virt_timer_irq; 2258 2259 fdt_add_timer_nodes(vms); 2260 fdt_add_cpu_nodes(vms); 2261 2262 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 2263 machine->ram); 2264 2265 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 2266 2267 create_gic(vms, sysmem); 2268 2269 virt_cpu_post_init(vms, sysmem); 2270 2271 fdt_add_pmu_nodes(vms); 2272 2273 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 2274 2275 if (vms->secure) { 2276 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); 2277 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 2278 } 2279 2280 if (tag_sysmem) { 2281 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, 2282 machine->ram_size, "mach-virt.tag"); 2283 } 2284 2285 vms->highmem_ecam &= (!firmware_loaded || aarch64); 2286 2287 create_rtc(vms); 2288 2289 create_pcie(vms); 2290 2291 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 2292 vms->acpi_dev = create_acpi_ged(vms); 2293 } else { 2294 create_gpio_devices(vms, VIRT_GPIO, sysmem); 2295 } 2296 2297 if (vms->secure && !vmc->no_secure_gpio) { 2298 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); 2299 } 2300 2301 /* connect powerdown request */ 2302 vms->powerdown_notifier.notify = virt_powerdown_req; 2303 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 2304 2305 /* Create mmio transports, so the user can create virtio backends 2306 * (which will be automatically plugged in to the transports). If 2307 * no backend is created the transport will just sit harmlessly idle. 2308 */ 2309 create_virtio_devices(vms); 2310 2311 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 2312 rom_set_fw(vms->fw_cfg); 2313 2314 create_platform_bus(vms); 2315 2316 if (machine->nvdimms_state->is_enabled) { 2317 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 2318 .space_id = AML_AS_SYSTEM_MEMORY, 2319 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 2320 .bit_width = NVDIMM_ACPI_IO_LEN << 3 2321 }; 2322 2323 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 2324 arm_virt_nvdimm_acpi_dsmio, 2325 vms->fw_cfg, OBJECT(vms)); 2326 } 2327 2328 vms->bootinfo.ram_size = machine->ram_size; 2329 vms->bootinfo.board_id = -1; 2330 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 2331 vms->bootinfo.get_dtb = machvirt_dtb; 2332 vms->bootinfo.skip_dtb_autoload = true; 2333 vms->bootinfo.firmware_loaded = firmware_loaded; 2334 vms->bootinfo.psci_conduit = vms->psci_conduit; 2335 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 2336 2337 vms->machine_done.notify = virt_machine_done; 2338 qemu_add_machine_init_done_notifier(&vms->machine_done); 2339 } 2340 2341 static bool virt_get_secure(Object *obj, Error **errp) 2342 { 2343 VirtMachineState *vms = VIRT_MACHINE(obj); 2344 2345 return vms->secure; 2346 } 2347 2348 static void virt_set_secure(Object *obj, bool value, Error **errp) 2349 { 2350 VirtMachineState *vms = VIRT_MACHINE(obj); 2351 2352 vms->secure = value; 2353 } 2354 2355 static bool virt_get_virt(Object *obj, Error **errp) 2356 { 2357 VirtMachineState *vms = VIRT_MACHINE(obj); 2358 2359 return vms->virt; 2360 } 2361 2362 static void virt_set_virt(Object *obj, bool value, Error **errp) 2363 { 2364 VirtMachineState *vms = VIRT_MACHINE(obj); 2365 2366 vms->virt = value; 2367 } 2368 2369 static bool virt_get_highmem(Object *obj, Error **errp) 2370 { 2371 VirtMachineState *vms = VIRT_MACHINE(obj); 2372 2373 return vms->highmem; 2374 } 2375 2376 static void virt_set_highmem(Object *obj, bool value, Error **errp) 2377 { 2378 VirtMachineState *vms = VIRT_MACHINE(obj); 2379 2380 vms->highmem = value; 2381 } 2382 2383 static bool virt_get_compact_highmem(Object *obj, Error **errp) 2384 { 2385 VirtMachineState *vms = VIRT_MACHINE(obj); 2386 2387 return vms->highmem_compact; 2388 } 2389 2390 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp) 2391 { 2392 VirtMachineState *vms = VIRT_MACHINE(obj); 2393 2394 vms->highmem_compact = value; 2395 } 2396 2397 static bool virt_get_highmem_redists(Object *obj, Error **errp) 2398 { 2399 VirtMachineState *vms = VIRT_MACHINE(obj); 2400 2401 return vms->highmem_redists; 2402 } 2403 2404 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp) 2405 { 2406 VirtMachineState *vms = VIRT_MACHINE(obj); 2407 2408 vms->highmem_redists = value; 2409 } 2410 2411 static bool virt_get_highmem_ecam(Object *obj, Error **errp) 2412 { 2413 VirtMachineState *vms = VIRT_MACHINE(obj); 2414 2415 return vms->highmem_ecam; 2416 } 2417 2418 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp) 2419 { 2420 VirtMachineState *vms = VIRT_MACHINE(obj); 2421 2422 vms->highmem_ecam = value; 2423 } 2424 2425 static bool virt_get_highmem_mmio(Object *obj, Error **errp) 2426 { 2427 VirtMachineState *vms = VIRT_MACHINE(obj); 2428 2429 return vms->highmem_mmio; 2430 } 2431 2432 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp) 2433 { 2434 VirtMachineState *vms = VIRT_MACHINE(obj); 2435 2436 vms->highmem_mmio = value; 2437 } 2438 2439 2440 static bool virt_get_its(Object *obj, Error **errp) 2441 { 2442 VirtMachineState *vms = VIRT_MACHINE(obj); 2443 2444 return vms->its; 2445 } 2446 2447 static void virt_set_its(Object *obj, bool value, Error **errp) 2448 { 2449 VirtMachineState *vms = VIRT_MACHINE(obj); 2450 2451 vms->its = value; 2452 } 2453 2454 static bool virt_get_dtb_randomness(Object *obj, Error **errp) 2455 { 2456 VirtMachineState *vms = VIRT_MACHINE(obj); 2457 2458 return vms->dtb_randomness; 2459 } 2460 2461 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp) 2462 { 2463 VirtMachineState *vms = VIRT_MACHINE(obj); 2464 2465 vms->dtb_randomness = value; 2466 } 2467 2468 static char *virt_get_oem_id(Object *obj, Error **errp) 2469 { 2470 VirtMachineState *vms = VIRT_MACHINE(obj); 2471 2472 return g_strdup(vms->oem_id); 2473 } 2474 2475 static void virt_set_oem_id(Object *obj, const char *value, Error **errp) 2476 { 2477 VirtMachineState *vms = VIRT_MACHINE(obj); 2478 size_t len = strlen(value); 2479 2480 if (len > 6) { 2481 error_setg(errp, 2482 "User specified oem-id value is bigger than 6 bytes in size"); 2483 return; 2484 } 2485 2486 strncpy(vms->oem_id, value, 6); 2487 } 2488 2489 static char *virt_get_oem_table_id(Object *obj, Error **errp) 2490 { 2491 VirtMachineState *vms = VIRT_MACHINE(obj); 2492 2493 return g_strdup(vms->oem_table_id); 2494 } 2495 2496 static void virt_set_oem_table_id(Object *obj, const char *value, 2497 Error **errp) 2498 { 2499 VirtMachineState *vms = VIRT_MACHINE(obj); 2500 size_t len = strlen(value); 2501 2502 if (len > 8) { 2503 error_setg(errp, 2504 "User specified oem-table-id value is bigger than 8 bytes in size"); 2505 return; 2506 } 2507 strncpy(vms->oem_table_id, value, 8); 2508 } 2509 2510 2511 bool virt_is_acpi_enabled(VirtMachineState *vms) 2512 { 2513 if (vms->acpi == ON_OFF_AUTO_OFF) { 2514 return false; 2515 } 2516 return true; 2517 } 2518 2519 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 2520 void *opaque, Error **errp) 2521 { 2522 VirtMachineState *vms = VIRT_MACHINE(obj); 2523 OnOffAuto acpi = vms->acpi; 2524 2525 visit_type_OnOffAuto(v, name, &acpi, errp); 2526 } 2527 2528 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 2529 void *opaque, Error **errp) 2530 { 2531 VirtMachineState *vms = VIRT_MACHINE(obj); 2532 2533 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 2534 } 2535 2536 static bool virt_get_ras(Object *obj, Error **errp) 2537 { 2538 VirtMachineState *vms = VIRT_MACHINE(obj); 2539 2540 return vms->ras; 2541 } 2542 2543 static void virt_set_ras(Object *obj, bool value, Error **errp) 2544 { 2545 VirtMachineState *vms = VIRT_MACHINE(obj); 2546 2547 vms->ras = value; 2548 } 2549 2550 static bool virt_get_mte(Object *obj, Error **errp) 2551 { 2552 VirtMachineState *vms = VIRT_MACHINE(obj); 2553 2554 return vms->mte; 2555 } 2556 2557 static void virt_set_mte(Object *obj, bool value, Error **errp) 2558 { 2559 VirtMachineState *vms = VIRT_MACHINE(obj); 2560 2561 vms->mte = value; 2562 } 2563 2564 static char *virt_get_gic_version(Object *obj, Error **errp) 2565 { 2566 VirtMachineState *vms = VIRT_MACHINE(obj); 2567 const char *val; 2568 2569 switch (vms->gic_version) { 2570 case VIRT_GIC_VERSION_4: 2571 val = "4"; 2572 break; 2573 case VIRT_GIC_VERSION_3: 2574 val = "3"; 2575 break; 2576 default: 2577 val = "2"; 2578 break; 2579 } 2580 return g_strdup(val); 2581 } 2582 2583 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2584 { 2585 VirtMachineState *vms = VIRT_MACHINE(obj); 2586 2587 if (!strcmp(value, "4")) { 2588 vms->gic_version = VIRT_GIC_VERSION_4; 2589 } else if (!strcmp(value, "3")) { 2590 vms->gic_version = VIRT_GIC_VERSION_3; 2591 } else if (!strcmp(value, "2")) { 2592 vms->gic_version = VIRT_GIC_VERSION_2; 2593 } else if (!strcmp(value, "host")) { 2594 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2595 } else if (!strcmp(value, "max")) { 2596 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2597 } else { 2598 error_setg(errp, "Invalid gic-version value"); 2599 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2600 } 2601 } 2602 2603 static char *virt_get_iommu(Object *obj, Error **errp) 2604 { 2605 VirtMachineState *vms = VIRT_MACHINE(obj); 2606 2607 switch (vms->iommu) { 2608 case VIRT_IOMMU_NONE: 2609 return g_strdup("none"); 2610 case VIRT_IOMMU_SMMUV3: 2611 return g_strdup("smmuv3"); 2612 default: 2613 g_assert_not_reached(); 2614 } 2615 } 2616 2617 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2618 { 2619 VirtMachineState *vms = VIRT_MACHINE(obj); 2620 2621 if (!strcmp(value, "smmuv3")) { 2622 vms->iommu = VIRT_IOMMU_SMMUV3; 2623 } else if (!strcmp(value, "none")) { 2624 vms->iommu = VIRT_IOMMU_NONE; 2625 } else { 2626 error_setg(errp, "Invalid iommu value"); 2627 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2628 } 2629 } 2630 2631 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp) 2632 { 2633 VirtMachineState *vms = VIRT_MACHINE(obj); 2634 2635 return vms->default_bus_bypass_iommu; 2636 } 2637 2638 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value, 2639 Error **errp) 2640 { 2641 VirtMachineState *vms = VIRT_MACHINE(obj); 2642 2643 vms->default_bus_bypass_iommu = value; 2644 } 2645 2646 static CpuInstanceProperties 2647 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2648 { 2649 MachineClass *mc = MACHINE_GET_CLASS(ms); 2650 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2651 2652 assert(cpu_index < possible_cpus->len); 2653 return possible_cpus->cpus[cpu_index].props; 2654 } 2655 2656 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2657 { 2658 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 2659 2660 return socket_id % ms->numa_state->num_nodes; 2661 } 2662 2663 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2664 { 2665 int n; 2666 unsigned int max_cpus = ms->smp.max_cpus; 2667 VirtMachineState *vms = VIRT_MACHINE(ms); 2668 MachineClass *mc = MACHINE_GET_CLASS(vms); 2669 2670 if (ms->possible_cpus) { 2671 assert(ms->possible_cpus->len == max_cpus); 2672 return ms->possible_cpus; 2673 } 2674 2675 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2676 sizeof(CPUArchId) * max_cpus); 2677 ms->possible_cpus->len = max_cpus; 2678 for (n = 0; n < ms->possible_cpus->len; n++) { 2679 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2680 ms->possible_cpus->cpus[n].arch_id = 2681 virt_cpu_mp_affinity(vms, n); 2682 2683 assert(!mc->smp_props.dies_supported); 2684 ms->possible_cpus->cpus[n].props.has_socket_id = true; 2685 ms->possible_cpus->cpus[n].props.socket_id = 2686 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); 2687 ms->possible_cpus->cpus[n].props.has_cluster_id = true; 2688 ms->possible_cpus->cpus[n].props.cluster_id = 2689 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; 2690 ms->possible_cpus->cpus[n].props.has_core_id = true; 2691 ms->possible_cpus->cpus[n].props.core_id = 2692 (n / ms->smp.threads) % ms->smp.cores; 2693 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2694 ms->possible_cpus->cpus[n].props.thread_id = 2695 n % ms->smp.threads; 2696 } 2697 return ms->possible_cpus; 2698 } 2699 2700 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2701 Error **errp) 2702 { 2703 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2704 const MachineState *ms = MACHINE(hotplug_dev); 2705 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2706 2707 if (!vms->acpi_dev) { 2708 error_setg(errp, 2709 "memory hotplug is not enabled: missing acpi-ged device"); 2710 return; 2711 } 2712 2713 if (vms->mte) { 2714 error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); 2715 return; 2716 } 2717 2718 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2719 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2720 return; 2721 } 2722 2723 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 2724 } 2725 2726 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2727 DeviceState *dev, Error **errp) 2728 { 2729 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2730 MachineState *ms = MACHINE(hotplug_dev); 2731 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2732 2733 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); 2734 2735 if (is_nvdimm) { 2736 nvdimm_plug(ms->nvdimms_state); 2737 } 2738 2739 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2740 dev, &error_abort); 2741 } 2742 2743 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2744 DeviceState *dev, Error **errp) 2745 { 2746 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2747 2748 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2749 virt_memory_pre_plug(hotplug_dev, dev, errp); 2750 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2751 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2752 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2753 hwaddr db_start = 0, db_end = 0; 2754 QList *reserved_regions; 2755 char *resv_prop_str; 2756 2757 if (vms->iommu != VIRT_IOMMU_NONE) { 2758 error_setg(errp, "virt machine does not support multiple IOMMUs"); 2759 return; 2760 } 2761 2762 switch (vms->msi_controller) { 2763 case VIRT_MSI_CTRL_NONE: 2764 return; 2765 case VIRT_MSI_CTRL_ITS: 2766 /* GITS_TRANSLATER page */ 2767 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; 2768 db_end = base_memmap[VIRT_GIC_ITS].base + 2769 base_memmap[VIRT_GIC_ITS].size - 1; 2770 break; 2771 case VIRT_MSI_CTRL_GICV2M: 2772 /* MSI_SETSPI_NS page */ 2773 db_start = base_memmap[VIRT_GIC_V2M].base; 2774 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; 2775 break; 2776 } 2777 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", 2778 db_start, db_end, 2779 VIRTIO_IOMMU_RESV_MEM_T_MSI); 2780 2781 reserved_regions = qlist_new(); 2782 qlist_append_str(reserved_regions, resv_prop_str); 2783 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 2784 g_free(resv_prop_str); 2785 } 2786 } 2787 2788 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2789 DeviceState *dev, Error **errp) 2790 { 2791 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2792 2793 if (vms->platform_bus_dev) { 2794 MachineClass *mc = MACHINE_GET_CLASS(vms); 2795 2796 if (device_is_dynamic_sysbus(mc, dev)) { 2797 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2798 SYS_BUS_DEVICE(dev)); 2799 } 2800 } 2801 2802 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2803 virt_memory_plug(hotplug_dev, dev, errp); 2804 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2805 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2806 } 2807 2808 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2809 PCIDevice *pdev = PCI_DEVICE(dev); 2810 2811 vms->iommu = VIRT_IOMMU_VIRTIO; 2812 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2813 create_virtio_iommu_dt_bindings(vms); 2814 } 2815 } 2816 2817 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, 2818 DeviceState *dev, Error **errp) 2819 { 2820 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2821 2822 if (!vms->acpi_dev) { 2823 error_setg(errp, 2824 "memory hotplug is not enabled: missing acpi-ged device"); 2825 return; 2826 } 2827 2828 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2829 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 2830 return; 2831 } 2832 2833 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, 2834 errp); 2835 } 2836 2837 static void virt_dimm_unplug(HotplugHandler *hotplug_dev, 2838 DeviceState *dev, Error **errp) 2839 { 2840 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2841 Error *local_err = NULL; 2842 2843 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); 2844 if (local_err) { 2845 goto out; 2846 } 2847 2848 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); 2849 qdev_unrealize(dev); 2850 2851 out: 2852 error_propagate(errp, local_err); 2853 } 2854 2855 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2856 DeviceState *dev, Error **errp) 2857 { 2858 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2859 virt_dimm_unplug_request(hotplug_dev, dev, errp); 2860 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2861 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 2862 errp); 2863 } else { 2864 error_setg(errp, "device unplug request for unsupported device" 2865 " type: %s", object_get_typename(OBJECT(dev))); 2866 } 2867 } 2868 2869 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2870 DeviceState *dev, Error **errp) 2871 { 2872 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2873 virt_dimm_unplug(hotplug_dev, dev, errp); 2874 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2875 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2876 } else { 2877 error_setg(errp, "virt: device unplug for unsupported device" 2878 " type: %s", object_get_typename(OBJECT(dev))); 2879 } 2880 } 2881 2882 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2883 DeviceState *dev) 2884 { 2885 MachineClass *mc = MACHINE_GET_CLASS(machine); 2886 2887 if (device_is_dynamic_sysbus(mc, dev) || 2888 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2889 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 2890 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2891 return HOTPLUG_HANDLER(machine); 2892 } 2893 return NULL; 2894 } 2895 2896 /* 2897 * for arm64 kvm_type [7-0] encodes the requested number of bits 2898 * in the IPA address space 2899 */ 2900 static int virt_kvm_type(MachineState *ms, const char *type_str) 2901 { 2902 VirtMachineState *vms = VIRT_MACHINE(ms); 2903 int max_vm_pa_size, requested_pa_size; 2904 bool fixed_ipa; 2905 2906 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 2907 2908 /* we freeze the memory map to compute the highest gpa */ 2909 virt_set_memmap(vms, max_vm_pa_size); 2910 2911 requested_pa_size = 64 - clz64(vms->highest_gpa); 2912 2913 /* 2914 * KVM requires the IPA size to be at least 32 bits. 2915 */ 2916 if (requested_pa_size < 32) { 2917 requested_pa_size = 32; 2918 } 2919 2920 if (requested_pa_size > max_vm_pa_size) { 2921 error_report("-m and ,maxmem option values " 2922 "require an IPA range (%d bits) larger than " 2923 "the one supported by the host (%d bits)", 2924 requested_pa_size, max_vm_pa_size); 2925 return -1; 2926 } 2927 /* 2928 * We return the requested PA log size, unless KVM only supports 2929 * the implicit legacy 40b IPA setting, in which case the kvm_type 2930 * must be 0. 2931 */ 2932 return fixed_ipa ? 0 : requested_pa_size; 2933 } 2934 2935 static void virt_machine_class_init(ObjectClass *oc, void *data) 2936 { 2937 MachineClass *mc = MACHINE_CLASS(oc); 2938 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2939 static const char * const valid_cpu_types[] = { 2940 #ifdef CONFIG_TCG 2941 ARM_CPU_TYPE_NAME("cortex-a7"), 2942 ARM_CPU_TYPE_NAME("cortex-a15"), 2943 #ifdef TARGET_AARCH64 2944 ARM_CPU_TYPE_NAME("cortex-a35"), 2945 ARM_CPU_TYPE_NAME("cortex-a55"), 2946 ARM_CPU_TYPE_NAME("cortex-a72"), 2947 ARM_CPU_TYPE_NAME("cortex-a76"), 2948 ARM_CPU_TYPE_NAME("cortex-a710"), 2949 ARM_CPU_TYPE_NAME("a64fx"), 2950 ARM_CPU_TYPE_NAME("neoverse-n1"), 2951 ARM_CPU_TYPE_NAME("neoverse-v1"), 2952 ARM_CPU_TYPE_NAME("neoverse-n2"), 2953 #endif /* TARGET_AARCH64 */ 2954 #endif /* CONFIG_TCG */ 2955 #ifdef TARGET_AARCH64 2956 ARM_CPU_TYPE_NAME("cortex-a53"), 2957 ARM_CPU_TYPE_NAME("cortex-a57"), 2958 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 2959 ARM_CPU_TYPE_NAME("host"), 2960 #endif /* CONFIG_KVM || CONFIG_HVF */ 2961 #endif /* TARGET_AARCH64 */ 2962 ARM_CPU_TYPE_NAME("max"), 2963 NULL 2964 }; 2965 2966 mc->init = machvirt_init; 2967 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 2968 * The value may be reduced later when we have more information about the 2969 * configuration of the particular instance. 2970 */ 2971 mc->max_cpus = 512; 2972 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 2973 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 2974 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 2975 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 2976 #ifdef CONFIG_TPM 2977 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 2978 #endif 2979 mc->block_default_type = IF_VIRTIO; 2980 mc->no_cdrom = 1; 2981 mc->pci_allow_0_address = true; 2982 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 2983 mc->minimum_page_bits = 12; 2984 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 2985 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 2986 #ifdef CONFIG_TCG 2987 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 2988 #else 2989 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); 2990 #endif 2991 mc->valid_cpu_types = valid_cpu_types; 2992 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 2993 mc->kvm_type = virt_kvm_type; 2994 assert(!mc->get_hotplug_handler); 2995 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 2996 hc->pre_plug = virt_machine_device_pre_plug_cb; 2997 hc->plug = virt_machine_device_plug_cb; 2998 hc->unplug_request = virt_machine_device_unplug_request_cb; 2999 hc->unplug = virt_machine_device_unplug_cb; 3000 mc->nvdimm_supported = true; 3001 mc->smp_props.clusters_supported = true; 3002 mc->auto_enable_numa_with_memhp = true; 3003 mc->auto_enable_numa_with_memdev = true; 3004 /* platform instead of architectural choice */ 3005 mc->cpu_cluster_has_numa_boundary = true; 3006 mc->default_ram_id = "mach-virt.ram"; 3007 mc->default_nic = "virtio-net-pci"; 3008 3009 object_class_property_add(oc, "acpi", "OnOffAuto", 3010 virt_get_acpi, virt_set_acpi, 3011 NULL, NULL); 3012 object_class_property_set_description(oc, "acpi", 3013 "Enable ACPI"); 3014 object_class_property_add_bool(oc, "secure", virt_get_secure, 3015 virt_set_secure); 3016 object_class_property_set_description(oc, "secure", 3017 "Set on/off to enable/disable the ARM " 3018 "Security Extensions (TrustZone)"); 3019 3020 object_class_property_add_bool(oc, "virtualization", virt_get_virt, 3021 virt_set_virt); 3022 object_class_property_set_description(oc, "virtualization", 3023 "Set on/off to enable/disable emulating a " 3024 "guest CPU which implements the ARM " 3025 "Virtualization Extensions"); 3026 3027 object_class_property_add_bool(oc, "highmem", virt_get_highmem, 3028 virt_set_highmem); 3029 object_class_property_set_description(oc, "highmem", 3030 "Set on/off to enable/disable using " 3031 "physical address space above 32 bits"); 3032 3033 object_class_property_add_bool(oc, "compact-highmem", 3034 virt_get_compact_highmem, 3035 virt_set_compact_highmem); 3036 object_class_property_set_description(oc, "compact-highmem", 3037 "Set on/off to enable/disable compact " 3038 "layout for high memory regions"); 3039 3040 object_class_property_add_bool(oc, "highmem-redists", 3041 virt_get_highmem_redists, 3042 virt_set_highmem_redists); 3043 object_class_property_set_description(oc, "highmem-redists", 3044 "Set on/off to enable/disable high " 3045 "memory region for GICv3 or GICv4 " 3046 "redistributor"); 3047 3048 object_class_property_add_bool(oc, "highmem-ecam", 3049 virt_get_highmem_ecam, 3050 virt_set_highmem_ecam); 3051 object_class_property_set_description(oc, "highmem-ecam", 3052 "Set on/off to enable/disable high " 3053 "memory region for PCI ECAM"); 3054 3055 object_class_property_add_bool(oc, "highmem-mmio", 3056 virt_get_highmem_mmio, 3057 virt_set_highmem_mmio); 3058 object_class_property_set_description(oc, "highmem-mmio", 3059 "Set on/off to enable/disable high " 3060 "memory region for PCI MMIO"); 3061 3062 object_class_property_add_str(oc, "gic-version", virt_get_gic_version, 3063 virt_set_gic_version); 3064 object_class_property_set_description(oc, "gic-version", 3065 "Set GIC version. " 3066 "Valid values are 2, 3, 4, host and max"); 3067 3068 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); 3069 object_class_property_set_description(oc, "iommu", 3070 "Set the IOMMU type. " 3071 "Valid values are none and smmuv3"); 3072 3073 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 3074 virt_get_default_bus_bypass_iommu, 3075 virt_set_default_bus_bypass_iommu); 3076 object_class_property_set_description(oc, "default-bus-bypass-iommu", 3077 "Set on/off to enable/disable " 3078 "bypass_iommu for default root bus"); 3079 3080 object_class_property_add_bool(oc, "ras", virt_get_ras, 3081 virt_set_ras); 3082 object_class_property_set_description(oc, "ras", 3083 "Set on/off to enable/disable reporting host memory errors " 3084 "to a KVM guest using ACPI and guest external abort exceptions"); 3085 3086 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); 3087 object_class_property_set_description(oc, "mte", 3088 "Set on/off to enable/disable emulating a " 3089 "guest CPU which implements the ARM " 3090 "Memory Tagging Extension"); 3091 3092 object_class_property_add_bool(oc, "its", virt_get_its, 3093 virt_set_its); 3094 object_class_property_set_description(oc, "its", 3095 "Set on/off to enable/disable " 3096 "ITS instantiation"); 3097 3098 object_class_property_add_bool(oc, "dtb-randomness", 3099 virt_get_dtb_randomness, 3100 virt_set_dtb_randomness); 3101 object_class_property_set_description(oc, "dtb-randomness", 3102 "Set off to disable passing random or " 3103 "non-deterministic dtb nodes to guest"); 3104 3105 object_class_property_add_bool(oc, "dtb-kaslr-seed", 3106 virt_get_dtb_randomness, 3107 virt_set_dtb_randomness); 3108 object_class_property_set_description(oc, "dtb-kaslr-seed", 3109 "Deprecated synonym of dtb-randomness"); 3110 3111 object_class_property_add_str(oc, "x-oem-id", 3112 virt_get_oem_id, 3113 virt_set_oem_id); 3114 object_class_property_set_description(oc, "x-oem-id", 3115 "Override the default value of field OEMID " 3116 "in ACPI table header." 3117 "The string may be up to 6 bytes in size"); 3118 3119 3120 object_class_property_add_str(oc, "x-oem-table-id", 3121 virt_get_oem_table_id, 3122 virt_set_oem_table_id); 3123 object_class_property_set_description(oc, "x-oem-table-id", 3124 "Override the default value of field OEM Table ID " 3125 "in ACPI table header." 3126 "The string may be up to 8 bytes in size"); 3127 3128 } 3129 3130 static void virt_instance_init(Object *obj) 3131 { 3132 VirtMachineState *vms = VIRT_MACHINE(obj); 3133 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 3134 3135 /* EL3 is disabled by default on virt: this makes us consistent 3136 * between KVM and TCG for this board, and it also allows us to 3137 * boot UEFI blobs which assume no TrustZone support. 3138 */ 3139 vms->secure = false; 3140 3141 /* EL2 is also disabled by default, for similar reasons */ 3142 vms->virt = false; 3143 3144 /* High memory is enabled by default */ 3145 vms->highmem = true; 3146 vms->highmem_compact = !vmc->no_highmem_compact; 3147 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 3148 3149 vms->highmem_ecam = !vmc->no_highmem_ecam; 3150 vms->highmem_mmio = true; 3151 vms->highmem_redists = true; 3152 3153 if (vmc->no_its) { 3154 vms->its = false; 3155 } else { 3156 /* Default allows ITS instantiation */ 3157 vms->its = true; 3158 3159 if (vmc->no_tcg_its) { 3160 vms->tcg_its = false; 3161 } else { 3162 vms->tcg_its = true; 3163 } 3164 } 3165 3166 /* Default disallows iommu instantiation */ 3167 vms->iommu = VIRT_IOMMU_NONE; 3168 3169 /* The default root bus is attached to iommu by default */ 3170 vms->default_bus_bypass_iommu = false; 3171 3172 /* Default disallows RAS instantiation */ 3173 vms->ras = false; 3174 3175 /* MTE is disabled by default. */ 3176 vms->mte = false; 3177 3178 /* Supply kaslr-seed and rng-seed by default */ 3179 vms->dtb_randomness = true; 3180 3181 vms->irqmap = a15irqmap; 3182 3183 virt_flash_create(vms); 3184 3185 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 3186 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 3187 } 3188 3189 static const TypeInfo virt_machine_info = { 3190 .name = TYPE_VIRT_MACHINE, 3191 .parent = TYPE_MACHINE, 3192 .abstract = true, 3193 .instance_size = sizeof(VirtMachineState), 3194 .class_size = sizeof(VirtMachineClass), 3195 .class_init = virt_machine_class_init, 3196 .instance_init = virt_instance_init, 3197 .interfaces = (InterfaceInfo[]) { 3198 { TYPE_HOTPLUG_HANDLER }, 3199 { } 3200 }, 3201 }; 3202 3203 static void machvirt_machine_init(void) 3204 { 3205 type_register_static(&virt_machine_info); 3206 } 3207 type_init(machvirt_machine_init); 3208 3209 static void virt_machine_9_0_options(MachineClass *mc) 3210 { 3211 } 3212 DEFINE_VIRT_MACHINE_AS_LATEST(9, 0) 3213 3214 static void virt_machine_8_2_options(MachineClass *mc) 3215 { 3216 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3217 3218 virt_machine_9_0_options(mc); 3219 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len); 3220 /* 3221 * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and 3222 * earlier machines. (Exposing it tickles a bug in older EDK2 3223 * guest BIOS binaries.) 3224 */ 3225 vmc->no_ns_el2_virt_timer_irq = true; 3226 } 3227 DEFINE_VIRT_MACHINE(8, 2) 3228 3229 static void virt_machine_8_1_options(MachineClass *mc) 3230 { 3231 virt_machine_8_2_options(mc); 3232 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len); 3233 } 3234 DEFINE_VIRT_MACHINE(8, 1) 3235 3236 static void virt_machine_8_0_options(MachineClass *mc) 3237 { 3238 virt_machine_8_1_options(mc); 3239 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 3240 } 3241 DEFINE_VIRT_MACHINE(8, 0) 3242 3243 static void virt_machine_7_2_options(MachineClass *mc) 3244 { 3245 virt_machine_8_0_options(mc); 3246 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 3247 } 3248 DEFINE_VIRT_MACHINE(7, 2) 3249 3250 static void virt_machine_7_1_options(MachineClass *mc) 3251 { 3252 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3253 3254 virt_machine_7_2_options(mc); 3255 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 3256 /* Compact layout for high memory regions was introduced with 7.2 */ 3257 vmc->no_highmem_compact = true; 3258 } 3259 DEFINE_VIRT_MACHINE(7, 1) 3260 3261 static void virt_machine_7_0_options(MachineClass *mc) 3262 { 3263 virt_machine_7_1_options(mc); 3264 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 3265 } 3266 DEFINE_VIRT_MACHINE(7, 0) 3267 3268 static void virt_machine_6_2_options(MachineClass *mc) 3269 { 3270 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3271 3272 virt_machine_7_0_options(mc); 3273 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 3274 vmc->no_tcg_lpa2 = true; 3275 } 3276 DEFINE_VIRT_MACHINE(6, 2) 3277 3278 static void virt_machine_6_1_options(MachineClass *mc) 3279 { 3280 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3281 3282 virt_machine_6_2_options(mc); 3283 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 3284 mc->smp_props.prefer_sockets = true; 3285 vmc->no_cpu_topology = true; 3286 3287 /* qemu ITS was introduced with 6.2 */ 3288 vmc->no_tcg_its = true; 3289 } 3290 DEFINE_VIRT_MACHINE(6, 1) 3291 3292 static void virt_machine_6_0_options(MachineClass *mc) 3293 { 3294 virt_machine_6_1_options(mc); 3295 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 3296 } 3297 DEFINE_VIRT_MACHINE(6, 0) 3298 3299 static void virt_machine_5_2_options(MachineClass *mc) 3300 { 3301 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3302 3303 virt_machine_6_0_options(mc); 3304 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 3305 vmc->no_secure_gpio = true; 3306 } 3307 DEFINE_VIRT_MACHINE(5, 2) 3308 3309 static void virt_machine_5_1_options(MachineClass *mc) 3310 { 3311 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3312 3313 virt_machine_5_2_options(mc); 3314 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 3315 vmc->no_kvm_steal_time = true; 3316 } 3317 DEFINE_VIRT_MACHINE(5, 1) 3318 3319 static void virt_machine_5_0_options(MachineClass *mc) 3320 { 3321 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3322 3323 virt_machine_5_1_options(mc); 3324 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 3325 mc->numa_mem_supported = true; 3326 vmc->acpi_expose_flash = true; 3327 mc->auto_enable_numa_with_memdev = false; 3328 } 3329 DEFINE_VIRT_MACHINE(5, 0) 3330 3331 static void virt_machine_4_2_options(MachineClass *mc) 3332 { 3333 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3334 3335 virt_machine_5_0_options(mc); 3336 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 3337 vmc->kvm_no_adjvtime = true; 3338 } 3339 DEFINE_VIRT_MACHINE(4, 2) 3340 3341 static void virt_machine_4_1_options(MachineClass *mc) 3342 { 3343 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3344 3345 virt_machine_4_2_options(mc); 3346 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 3347 vmc->no_ged = true; 3348 mc->auto_enable_numa_with_memhp = false; 3349 } 3350 DEFINE_VIRT_MACHINE(4, 1) 3351 3352 static void virt_machine_4_0_options(MachineClass *mc) 3353 { 3354 virt_machine_4_1_options(mc); 3355 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 3356 } 3357 DEFINE_VIRT_MACHINE(4, 0) 3358 3359 static void virt_machine_3_1_options(MachineClass *mc) 3360 { 3361 virt_machine_4_0_options(mc); 3362 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 3363 } 3364 DEFINE_VIRT_MACHINE(3, 1) 3365 3366 static void virt_machine_3_0_options(MachineClass *mc) 3367 { 3368 virt_machine_3_1_options(mc); 3369 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 3370 } 3371 DEFINE_VIRT_MACHINE(3, 0) 3372 3373 static void virt_machine_2_12_options(MachineClass *mc) 3374 { 3375 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3376 3377 virt_machine_3_0_options(mc); 3378 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 3379 vmc->no_highmem_ecam = true; 3380 mc->max_cpus = 255; 3381 } 3382 DEFINE_VIRT_MACHINE(2, 12) 3383 3384 static void virt_machine_2_11_options(MachineClass *mc) 3385 { 3386 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3387 3388 virt_machine_2_12_options(mc); 3389 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 3390 vmc->smbios_old_sys_ver = true; 3391 } 3392 DEFINE_VIRT_MACHINE(2, 11) 3393 3394 static void virt_machine_2_10_options(MachineClass *mc) 3395 { 3396 virt_machine_2_11_options(mc); 3397 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 3398 /* before 2.11 we never faulted accesses to bad addresses */ 3399 mc->ignore_memory_transaction_failures = true; 3400 } 3401 DEFINE_VIRT_MACHINE(2, 10) 3402 3403 static void virt_machine_2_9_options(MachineClass *mc) 3404 { 3405 virt_machine_2_10_options(mc); 3406 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 3407 } 3408 DEFINE_VIRT_MACHINE(2, 9) 3409 3410 static void virt_machine_2_8_options(MachineClass *mc) 3411 { 3412 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3413 3414 virt_machine_2_9_options(mc); 3415 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 3416 /* For 2.8 and earlier we falsely claimed in the DT that 3417 * our timers were edge-triggered, not level-triggered. 3418 */ 3419 vmc->claim_edge_triggered_timers = true; 3420 } 3421 DEFINE_VIRT_MACHINE(2, 8) 3422 3423 static void virt_machine_2_7_options(MachineClass *mc) 3424 { 3425 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3426 3427 virt_machine_2_8_options(mc); 3428 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 3429 /* ITS was introduced with 2.8 */ 3430 vmc->no_its = true; 3431 /* Stick with 1K pages for migration compatibility */ 3432 mc->minimum_page_bits = 0; 3433 } 3434 DEFINE_VIRT_MACHINE(2, 7) 3435 3436 static void virt_machine_2_6_options(MachineClass *mc) 3437 { 3438 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3439 3440 virt_machine_2_7_options(mc); 3441 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 3442 vmc->disallow_affinity_adjustment = true; 3443 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 3444 vmc->no_pmu = true; 3445 } 3446 DEFINE_VIRT_MACHINE(2, 6) 3447