1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qapi/error.h" 33 #include "hw/sysbus.h" 34 #include "hw/arm/arm.h" 35 #include "hw/arm/primecell.h" 36 #include "hw/arm/virt.h" 37 #include "hw/vfio/vfio-calxeda-xgmac.h" 38 #include "hw/vfio/vfio-amd-xgbe.h" 39 #include "hw/devices.h" 40 #include "net/net.h" 41 #include "sysemu/block-backend.h" 42 #include "sysemu/device_tree.h" 43 #include "sysemu/numa.h" 44 #include "sysemu/sysemu.h" 45 #include "sysemu/kvm.h" 46 #include "hw/compat.h" 47 #include "hw/loader.h" 48 #include "exec/address-spaces.h" 49 #include "qemu/bitops.h" 50 #include "qemu/error-report.h" 51 #include "hw/pci-host/gpex.h" 52 #include "hw/arm/sysbus-fdt.h" 53 #include "hw/platform-bus.h" 54 #include "hw/arm/fdt.h" 55 #include "hw/intc/arm_gic.h" 56 #include "hw/intc/arm_gicv3_common.h" 57 #include "kvm_arm.h" 58 #include "hw/smbios/smbios.h" 59 #include "qapi/visitor.h" 60 #include "standard-headers/linux/input.h" 61 62 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 63 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 64 void *data) \ 65 { \ 66 MachineClass *mc = MACHINE_CLASS(oc); \ 67 virt_machine_##major##_##minor##_options(mc); \ 68 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 69 if (latest) { \ 70 mc->alias = "virt"; \ 71 } \ 72 } \ 73 static const TypeInfo machvirt_##major##_##minor##_info = { \ 74 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 75 .parent = TYPE_VIRT_MACHINE, \ 76 .instance_init = virt_##major##_##minor##_instance_init, \ 77 .class_init = virt_##major##_##minor##_class_init, \ 78 }; \ 79 static void machvirt_machine_##major##_##minor##_init(void) \ 80 { \ 81 type_register_static(&machvirt_##major##_##minor##_info); \ 82 } \ 83 type_init(machvirt_machine_##major##_##minor##_init); 84 85 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 86 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 87 #define DEFINE_VIRT_MACHINE(major, minor) \ 88 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 89 90 91 /* Number of external interrupt lines to configure the GIC with */ 92 #define NUM_IRQS 256 93 94 #define PLATFORM_BUS_NUM_IRQS 64 95 96 static ARMPlatformBusSystemParams platform_bus_params; 97 98 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means 99 * RAM can go up to the 256GB mark, leaving 256GB of the physical 100 * address space unallocated and free for future use between 256G and 512G. 101 * If we need to provide more RAM to VMs in the future then we need to: 102 * * allocate a second bank of RAM starting at 2TB and working up 103 * * fix the DT and ACPI table generation code in QEMU to correctly 104 * report two split lumps of RAM to the guest 105 * * fix KVM in the host kernel to allow guests with >40 bit address spaces 106 * (We don't want to fill all the way up to 512GB with RAM because 107 * we might want it for non-RAM purposes later. Conversely it seems 108 * reasonable to assume that anybody configuring a VM with a quarter 109 * of a terabyte of RAM will be doing it on a host with more than a 110 * terabyte of physical address space.) 111 */ 112 #define RAMLIMIT_GB 255 113 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) 114 115 /* Addresses and sizes of our components. 116 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 117 * 128MB..256MB is used for miscellaneous device I/O. 118 * 256MB..1GB is reserved for possible future PCI support (ie where the 119 * PCI memory window will go if we add a PCI host controller). 120 * 1GB and up is RAM (which may happily spill over into the 121 * high memory region beyond 4GB). 122 * This represents a compromise between how much RAM can be given to 123 * a 32 bit VM and leaving space for expansion and in particular for PCI. 124 * Note that devices should generally be placed at multiples of 0x10000, 125 * to accommodate guests using 64K pages. 126 */ 127 static const MemMapEntry a15memmap[] = { 128 /* Space up to 0x8000000 is reserved for a boot ROM */ 129 [VIRT_FLASH] = { 0, 0x08000000 }, 130 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 131 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 132 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 133 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 134 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 135 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 136 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 137 /* This redistributor space allows up to 2*64kB*123 CPUs */ 138 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 139 [VIRT_UART] = { 0x09000000, 0x00001000 }, 140 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 141 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 142 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 143 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 144 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 145 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 146 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 147 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 148 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 149 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 150 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 151 [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES }, 152 /* Second PCIe window, 512GB wide at the 512GB boundary */ 153 [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL }, 154 }; 155 156 static const int a15irqmap[] = { 157 [VIRT_UART] = 1, 158 [VIRT_RTC] = 2, 159 [VIRT_PCIE] = 3, /* ... to 6 */ 160 [VIRT_GPIO] = 7, 161 [VIRT_SECURE_UART] = 8, 162 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 163 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 164 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 165 }; 166 167 static const char *valid_cpus[] = { 168 ARM_CPU_TYPE_NAME("cortex-a15"), 169 ARM_CPU_TYPE_NAME("cortex-a53"), 170 ARM_CPU_TYPE_NAME("cortex-a57"), 171 ARM_CPU_TYPE_NAME("host"), 172 }; 173 174 static bool cpu_type_valid(const char *cpu) 175 { 176 int i; 177 178 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 179 if (strcmp(cpu, valid_cpus[i]) == 0) { 180 return true; 181 } 182 } 183 return false; 184 } 185 186 static void create_fdt(VirtMachineState *vms) 187 { 188 void *fdt = create_device_tree(&vms->fdt_size); 189 190 if (!fdt) { 191 error_report("create_device_tree() failed"); 192 exit(1); 193 } 194 195 vms->fdt = fdt; 196 197 /* Header */ 198 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 199 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 200 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 201 202 /* 203 * /chosen and /memory nodes must exist for load_dtb 204 * to fill in necessary properties later 205 */ 206 qemu_fdt_add_subnode(fdt, "/chosen"); 207 qemu_fdt_add_subnode(fdt, "/memory"); 208 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 209 210 /* Clock node, for the benefit of the UART. The kernel device tree 211 * binding documentation claims the PL011 node clock properties are 212 * optional but in practice if you omit them the kernel refuses to 213 * probe for the device. 214 */ 215 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 216 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 217 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 218 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 219 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 220 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 221 "clk24mhz"); 222 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 223 224 if (have_numa_distance) { 225 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 226 uint32_t *matrix = g_malloc0(size); 227 int idx, i, j; 228 229 for (i = 0; i < nb_numa_nodes; i++) { 230 for (j = 0; j < nb_numa_nodes; j++) { 231 idx = (i * nb_numa_nodes + j) * 3; 232 matrix[idx + 0] = cpu_to_be32(i); 233 matrix[idx + 1] = cpu_to_be32(j); 234 matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]); 235 } 236 } 237 238 qemu_fdt_add_subnode(fdt, "/distance-map"); 239 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 240 "numa-distance-map-v1"); 241 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 242 matrix, size); 243 g_free(matrix); 244 } 245 } 246 247 static void fdt_add_timer_nodes(const VirtMachineState *vms) 248 { 249 /* On real hardware these interrupts are level-triggered. 250 * On KVM they were edge-triggered before host kernel version 4.4, 251 * and level-triggered afterwards. 252 * On emulated QEMU they are level-triggered. 253 * 254 * Getting the DTB info about them wrong is awkward for some 255 * guest kernels: 256 * pre-4.8 ignore the DT and leave the interrupt configured 257 * with whatever the GIC reset value (or the bootloader) left it at 258 * 4.8 before rc6 honour the incorrect data by programming it back 259 * into the GIC, causing problems 260 * 4.8rc6 and later ignore the DT and always write "level triggered" 261 * into the GIC 262 * 263 * For backwards-compatibility, virt-2.8 and earlier will continue 264 * to say these are edge-triggered, but later machines will report 265 * the correct information. 266 */ 267 ARMCPU *armcpu; 268 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 269 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 270 271 if (vmc->claim_edge_triggered_timers) { 272 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 273 } 274 275 if (vms->gic_version == 2) { 276 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 277 GIC_FDT_IRQ_PPI_CPU_WIDTH, 278 (1 << vms->smp_cpus) - 1); 279 } 280 281 qemu_fdt_add_subnode(vms->fdt, "/timer"); 282 283 armcpu = ARM_CPU(qemu_get_cpu(0)); 284 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 285 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 286 qemu_fdt_setprop(vms->fdt, "/timer", "compatible", 287 compat, sizeof(compat)); 288 } else { 289 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible", 290 "arm,armv7-timer"); 291 } 292 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0); 293 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts", 294 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 295 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 296 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 297 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 298 } 299 300 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 301 { 302 int cpu; 303 int addr_cells = 1; 304 const MachineState *ms = MACHINE(vms); 305 306 /* 307 * From Documentation/devicetree/bindings/arm/cpus.txt 308 * On ARM v8 64-bit systems value should be set to 2, 309 * that corresponds to the MPIDR_EL1 register size. 310 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 311 * in the system, #address-cells can be set to 1, since 312 * MPIDR_EL1[63:32] bits are not used for CPUs 313 * identification. 314 * 315 * Here we actually don't know whether our system is 32- or 64-bit one. 316 * The simplest way to go is to examine affinity IDs of all our CPUs. If 317 * at least one of them has Aff3 populated, we set #address-cells to 2. 318 */ 319 for (cpu = 0; cpu < vms->smp_cpus; cpu++) { 320 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 321 322 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 323 addr_cells = 2; 324 break; 325 } 326 } 327 328 qemu_fdt_add_subnode(vms->fdt, "/cpus"); 329 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); 330 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); 331 332 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { 333 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 334 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 335 CPUState *cs = CPU(armcpu); 336 337 qemu_fdt_add_subnode(vms->fdt, nodename); 338 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); 339 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 340 armcpu->dtb_compatible); 341 342 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED 343 && vms->smp_cpus > 1) { 344 qemu_fdt_setprop_string(vms->fdt, nodename, 345 "enable-method", "psci"); 346 } 347 348 if (addr_cells == 2) { 349 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", 350 armcpu->mp_affinity); 351 } else { 352 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", 353 armcpu->mp_affinity); 354 } 355 356 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 357 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", 358 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 359 } 360 361 g_free(nodename); 362 } 363 } 364 365 static void fdt_add_its_gic_node(VirtMachineState *vms) 366 { 367 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 368 qemu_fdt_add_subnode(vms->fdt, "/intc/its"); 369 qemu_fdt_setprop_string(vms->fdt, "/intc/its", "compatible", 370 "arm,gic-v3-its"); 371 qemu_fdt_setprop(vms->fdt, "/intc/its", "msi-controller", NULL, 0); 372 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/its", "reg", 373 2, vms->memmap[VIRT_GIC_ITS].base, 374 2, vms->memmap[VIRT_GIC_ITS].size); 375 qemu_fdt_setprop_cell(vms->fdt, "/intc/its", "phandle", vms->msi_phandle); 376 } 377 378 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 379 { 380 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 381 qemu_fdt_add_subnode(vms->fdt, "/intc/v2m"); 382 qemu_fdt_setprop_string(vms->fdt, "/intc/v2m", "compatible", 383 "arm,gic-v2m-frame"); 384 qemu_fdt_setprop(vms->fdt, "/intc/v2m", "msi-controller", NULL, 0); 385 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/v2m", "reg", 386 2, vms->memmap[VIRT_GIC_V2M].base, 387 2, vms->memmap[VIRT_GIC_V2M].size); 388 qemu_fdt_setprop_cell(vms->fdt, "/intc/v2m", "phandle", vms->msi_phandle); 389 } 390 391 static void fdt_add_gic_node(VirtMachineState *vms) 392 { 393 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt); 394 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle); 395 396 qemu_fdt_add_subnode(vms->fdt, "/intc"); 397 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#interrupt-cells", 3); 398 qemu_fdt_setprop(vms->fdt, "/intc", "interrupt-controller", NULL, 0); 399 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#address-cells", 0x2); 400 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#size-cells", 0x2); 401 qemu_fdt_setprop(vms->fdt, "/intc", "ranges", NULL, 0); 402 if (vms->gic_version == 3) { 403 qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", 404 "arm,gic-v3"); 405 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", 406 2, vms->memmap[VIRT_GIC_DIST].base, 407 2, vms->memmap[VIRT_GIC_DIST].size, 408 2, vms->memmap[VIRT_GIC_REDIST].base, 409 2, vms->memmap[VIRT_GIC_REDIST].size); 410 if (vms->virt) { 411 qemu_fdt_setprop_cells(vms->fdt, "/intc", "interrupts", 412 GIC_FDT_IRQ_TYPE_PPI, ARCH_GICV3_MAINT_IRQ, 413 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 414 } 415 } else { 416 /* 'cortex-a15-gic' means 'GIC v2' */ 417 qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", 418 "arm,cortex-a15-gic"); 419 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", 420 2, vms->memmap[VIRT_GIC_DIST].base, 421 2, vms->memmap[VIRT_GIC_DIST].size, 422 2, vms->memmap[VIRT_GIC_CPU].base, 423 2, vms->memmap[VIRT_GIC_CPU].size); 424 } 425 426 qemu_fdt_setprop_cell(vms->fdt, "/intc", "phandle", vms->gic_phandle); 427 } 428 429 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 430 { 431 CPUState *cpu; 432 ARMCPU *armcpu; 433 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 434 435 CPU_FOREACH(cpu) { 436 armcpu = ARM_CPU(cpu); 437 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 438 return; 439 } 440 if (kvm_enabled()) { 441 if (kvm_irqchip_in_kernel()) { 442 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 443 } 444 kvm_arm_pmu_init(cpu); 445 } 446 } 447 448 if (vms->gic_version == 2) { 449 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 450 GIC_FDT_IRQ_PPI_CPU_WIDTH, 451 (1 << vms->smp_cpus) - 1); 452 } 453 454 armcpu = ARM_CPU(qemu_get_cpu(0)); 455 qemu_fdt_add_subnode(vms->fdt, "/pmu"); 456 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 457 const char compat[] = "arm,armv8-pmuv3"; 458 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible", 459 compat, sizeof(compat)); 460 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts", 461 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 462 } 463 } 464 465 static void create_its(VirtMachineState *vms, DeviceState *gicdev) 466 { 467 const char *itsclass = its_class_name(); 468 DeviceState *dev; 469 470 if (!itsclass) { 471 /* Do nothing if not supported */ 472 return; 473 } 474 475 dev = qdev_create(NULL, itsclass); 476 477 object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3", 478 &error_abort); 479 qdev_init_nofail(dev); 480 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 481 482 fdt_add_its_gic_node(vms); 483 } 484 485 static void create_v2m(VirtMachineState *vms, qemu_irq *pic) 486 { 487 int i; 488 int irq = vms->irqmap[VIRT_GIC_V2M]; 489 DeviceState *dev; 490 491 dev = qdev_create(NULL, "arm-gicv2m"); 492 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 493 qdev_prop_set_uint32(dev, "base-spi", irq); 494 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 495 qdev_init_nofail(dev); 496 497 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 498 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 499 } 500 501 fdt_add_v2m_gic_node(vms); 502 } 503 504 static void create_gic(VirtMachineState *vms, qemu_irq *pic) 505 { 506 /* We create a standalone GIC */ 507 DeviceState *gicdev; 508 SysBusDevice *gicbusdev; 509 const char *gictype; 510 int type = vms->gic_version, i; 511 512 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 513 514 gicdev = qdev_create(NULL, gictype); 515 qdev_prop_set_uint32(gicdev, "revision", type); 516 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 517 /* Note that the num-irq property counts both internal and external 518 * interrupts; there are always 32 of the former (mandated by GIC spec). 519 */ 520 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 521 if (!kvm_irqchip_in_kernel()) { 522 qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure); 523 } 524 qdev_init_nofail(gicdev); 525 gicbusdev = SYS_BUS_DEVICE(gicdev); 526 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 527 if (type == 3) { 528 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 529 } else { 530 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 531 } 532 533 /* Wire the outputs from each CPU's generic timer and the GICv3 534 * maintenance interrupt signal to the appropriate GIC PPI inputs, 535 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 536 */ 537 for (i = 0; i < smp_cpus; i++) { 538 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 539 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 540 int irq; 541 /* Mapping from the output timer irq lines from the CPU to the 542 * GIC PPI inputs we use for the virt board. 543 */ 544 const int timer_irq[] = { 545 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 546 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 547 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 548 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 549 }; 550 551 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 552 qdev_connect_gpio_out(cpudev, irq, 553 qdev_get_gpio_in(gicdev, 554 ppibase + timer_irq[irq])); 555 } 556 557 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 558 qdev_get_gpio_in(gicdev, ppibase 559 + ARCH_GICV3_MAINT_IRQ)); 560 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 561 qdev_get_gpio_in(gicdev, ppibase 562 + VIRTUAL_PMU_IRQ)); 563 564 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 565 sysbus_connect_irq(gicbusdev, i + smp_cpus, 566 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 567 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 568 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 569 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 570 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 571 } 572 573 for (i = 0; i < NUM_IRQS; i++) { 574 pic[i] = qdev_get_gpio_in(gicdev, i); 575 } 576 577 fdt_add_gic_node(vms); 578 579 if (type == 3 && vms->its) { 580 create_its(vms, gicdev); 581 } else if (type == 2) { 582 create_v2m(vms, pic); 583 } 584 } 585 586 static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart, 587 MemoryRegion *mem, Chardev *chr) 588 { 589 char *nodename; 590 hwaddr base = vms->memmap[uart].base; 591 hwaddr size = vms->memmap[uart].size; 592 int irq = vms->irqmap[uart]; 593 const char compat[] = "arm,pl011\0arm,primecell"; 594 const char clocknames[] = "uartclk\0apb_pclk"; 595 DeviceState *dev = qdev_create(NULL, "pl011"); 596 SysBusDevice *s = SYS_BUS_DEVICE(dev); 597 598 qdev_prop_set_chr(dev, "chardev", chr); 599 qdev_init_nofail(dev); 600 memory_region_add_subregion(mem, base, 601 sysbus_mmio_get_region(s, 0)); 602 sysbus_connect_irq(s, 0, pic[irq]); 603 604 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 605 qemu_fdt_add_subnode(vms->fdt, nodename); 606 /* Note that we can't use setprop_string because of the embedded NUL */ 607 qemu_fdt_setprop(vms->fdt, nodename, "compatible", 608 compat, sizeof(compat)); 609 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 610 2, base, 2, size); 611 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 612 GIC_FDT_IRQ_TYPE_SPI, irq, 613 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 614 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks", 615 vms->clock_phandle, vms->clock_phandle); 616 qemu_fdt_setprop(vms->fdt, nodename, "clock-names", 617 clocknames, sizeof(clocknames)); 618 619 if (uart == VIRT_UART) { 620 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); 621 } else { 622 /* Mark as not usable by the normal world */ 623 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 624 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 625 } 626 627 g_free(nodename); 628 } 629 630 static void create_rtc(const VirtMachineState *vms, qemu_irq *pic) 631 { 632 char *nodename; 633 hwaddr base = vms->memmap[VIRT_RTC].base; 634 hwaddr size = vms->memmap[VIRT_RTC].size; 635 int irq = vms->irqmap[VIRT_RTC]; 636 const char compat[] = "arm,pl031\0arm,primecell"; 637 638 sysbus_create_simple("pl031", base, pic[irq]); 639 640 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 641 qemu_fdt_add_subnode(vms->fdt, nodename); 642 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 643 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 644 2, base, 2, size); 645 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 646 GIC_FDT_IRQ_TYPE_SPI, irq, 647 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 648 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 649 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 650 g_free(nodename); 651 } 652 653 static DeviceState *gpio_key_dev; 654 static void virt_powerdown_req(Notifier *n, void *opaque) 655 { 656 /* use gpio Pin 3 for power button event */ 657 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 658 } 659 660 static Notifier virt_system_powerdown_notifier = { 661 .notify = virt_powerdown_req 662 }; 663 664 static void create_gpio(const VirtMachineState *vms, qemu_irq *pic) 665 { 666 char *nodename; 667 DeviceState *pl061_dev; 668 hwaddr base = vms->memmap[VIRT_GPIO].base; 669 hwaddr size = vms->memmap[VIRT_GPIO].size; 670 int irq = vms->irqmap[VIRT_GPIO]; 671 const char compat[] = "arm,pl061\0arm,primecell"; 672 673 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); 674 675 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); 676 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 677 qemu_fdt_add_subnode(vms->fdt, nodename); 678 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 679 2, base, 2, size); 680 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 681 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); 682 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); 683 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 684 GIC_FDT_IRQ_TYPE_SPI, irq, 685 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 686 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 687 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 688 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); 689 690 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 691 qdev_get_gpio_in(pl061_dev, 3)); 692 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); 693 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); 694 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); 695 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); 696 697 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); 698 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", 699 "label", "GPIO Key Poweroff"); 700 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", 701 KEY_POWER); 702 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", 703 "gpios", phandle, 3, 0); 704 705 /* connect powerdown request */ 706 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier); 707 708 g_free(nodename); 709 } 710 711 static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic) 712 { 713 int i; 714 hwaddr size = vms->memmap[VIRT_MMIO].size; 715 716 /* We create the transports in forwards order. Since qbus_realize() 717 * prepends (not appends) new child buses, the incrementing loop below will 718 * create a list of virtio-mmio buses with decreasing base addresses. 719 * 720 * When a -device option is processed from the command line, 721 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 722 * order. The upshot is that -device options in increasing command line 723 * order are mapped to virtio-mmio buses with decreasing base addresses. 724 * 725 * When this code was originally written, that arrangement ensured that the 726 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 727 * the first -device on the command line. (The end-to-end order is a 728 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 729 * guest kernel's name-to-address assignment strategy.) 730 * 731 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 732 * the message, if not necessarily the code, of commit 70161ff336. 733 * Therefore the loop now establishes the inverse of the original intent. 734 * 735 * Unfortunately, we can't counteract the kernel change by reversing the 736 * loop; it would break existing command lines. 737 * 738 * In any case, the kernel makes no guarantee about the stability of 739 * enumeration order of virtio devices (as demonstrated by it changing 740 * between kernel versions). For reliable and stable identification 741 * of disks users must use UUIDs or similar mechanisms. 742 */ 743 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 744 int irq = vms->irqmap[VIRT_MMIO] + i; 745 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 746 747 sysbus_create_simple("virtio-mmio", base, pic[irq]); 748 } 749 750 /* We add dtb nodes in reverse order so that they appear in the finished 751 * device tree lowest address first. 752 * 753 * Note that this mapping is independent of the loop above. The previous 754 * loop influences virtio device to virtio transport assignment, whereas 755 * this loop controls how virtio transports are laid out in the dtb. 756 */ 757 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 758 char *nodename; 759 int irq = vms->irqmap[VIRT_MMIO] + i; 760 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 761 762 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 763 qemu_fdt_add_subnode(vms->fdt, nodename); 764 qemu_fdt_setprop_string(vms->fdt, nodename, 765 "compatible", "virtio,mmio"); 766 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 767 2, base, 2, size); 768 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 769 GIC_FDT_IRQ_TYPE_SPI, irq, 770 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 771 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 772 g_free(nodename); 773 } 774 } 775 776 static void create_one_flash(const char *name, hwaddr flashbase, 777 hwaddr flashsize, const char *file, 778 MemoryRegion *sysmem) 779 { 780 /* Create and map a single flash device. We use the same 781 * parameters as the flash devices on the Versatile Express board. 782 */ 783 DriveInfo *dinfo = drive_get_next(IF_PFLASH); 784 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 785 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 786 const uint64_t sectorlength = 256 * 1024; 787 788 if (dinfo) { 789 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 790 &error_abort); 791 } 792 793 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); 794 qdev_prop_set_uint64(dev, "sector-length", sectorlength); 795 qdev_prop_set_uint8(dev, "width", 4); 796 qdev_prop_set_uint8(dev, "device-width", 2); 797 qdev_prop_set_bit(dev, "big-endian", false); 798 qdev_prop_set_uint16(dev, "id0", 0x89); 799 qdev_prop_set_uint16(dev, "id1", 0x18); 800 qdev_prop_set_uint16(dev, "id2", 0x00); 801 qdev_prop_set_uint16(dev, "id3", 0x00); 802 qdev_prop_set_string(dev, "name", name); 803 qdev_init_nofail(dev); 804 805 memory_region_add_subregion(sysmem, flashbase, 806 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 807 808 if (file) { 809 char *fn; 810 int image_size; 811 812 if (drive_get(IF_PFLASH, 0, 0)) { 813 error_report("The contents of the first flash device may be " 814 "specified with -bios or with -drive if=pflash... " 815 "but you cannot use both options at once"); 816 exit(1); 817 } 818 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file); 819 if (!fn) { 820 error_report("Could not find ROM image '%s'", file); 821 exit(1); 822 } 823 image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0)); 824 g_free(fn); 825 if (image_size < 0) { 826 error_report("Could not load ROM image '%s'", file); 827 exit(1); 828 } 829 } 830 } 831 832 static void create_flash(const VirtMachineState *vms, 833 MemoryRegion *sysmem, 834 MemoryRegion *secure_sysmem) 835 { 836 /* Create two flash devices to fill the VIRT_FLASH space in the memmap. 837 * Any file passed via -bios goes in the first of these. 838 * sysmem is the system memory space. secure_sysmem is the secure view 839 * of the system, and the first flash device should be made visible only 840 * there. The second flash device is visible to both secure and nonsecure. 841 * If sysmem == secure_sysmem this means there is no separate Secure 842 * address space and both flash devices are generally visible. 843 */ 844 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 845 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 846 char *nodename; 847 848 create_one_flash("virt.flash0", flashbase, flashsize, 849 bios_name, secure_sysmem); 850 create_one_flash("virt.flash1", flashbase + flashsize, flashsize, 851 NULL, sysmem); 852 853 if (sysmem == secure_sysmem) { 854 /* Report both flash devices as a single node in the DT */ 855 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 856 qemu_fdt_add_subnode(vms->fdt, nodename); 857 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 858 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 859 2, flashbase, 2, flashsize, 860 2, flashbase + flashsize, 2, flashsize); 861 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 862 g_free(nodename); 863 } else { 864 /* Report the devices as separate nodes so we can mark one as 865 * only visible to the secure world. 866 */ 867 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 868 qemu_fdt_add_subnode(vms->fdt, nodename); 869 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 870 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 871 2, flashbase, 2, flashsize); 872 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 873 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 874 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 875 g_free(nodename); 876 877 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 878 qemu_fdt_add_subnode(vms->fdt, nodename); 879 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 880 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 881 2, flashbase + flashsize, 2, flashsize); 882 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 883 g_free(nodename); 884 } 885 } 886 887 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 888 { 889 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 890 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 891 FWCfgState *fw_cfg; 892 char *nodename; 893 894 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 895 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 896 897 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 898 qemu_fdt_add_subnode(vms->fdt, nodename); 899 qemu_fdt_setprop_string(vms->fdt, nodename, 900 "compatible", "qemu,fw-cfg-mmio"); 901 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 902 2, base, 2, size); 903 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 904 g_free(nodename); 905 return fw_cfg; 906 } 907 908 static void create_pcie_irq_map(const VirtMachineState *vms, 909 uint32_t gic_phandle, 910 int first_irq, const char *nodename) 911 { 912 int devfn, pin; 913 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 914 uint32_t *irq_map = full_irq_map; 915 916 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 917 for (pin = 0; pin < 4; pin++) { 918 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 919 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 920 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 921 int i; 922 923 uint32_t map[] = { 924 devfn << 8, 0, 0, /* devfn */ 925 pin + 1, /* PCI pin */ 926 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 927 928 /* Convert map to big endian */ 929 for (i = 0; i < 10; i++) { 930 irq_map[i] = cpu_to_be32(map[i]); 931 } 932 irq_map += 10; 933 } 934 } 935 936 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map", 937 full_irq_map, sizeof(full_irq_map)); 938 939 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask", 940 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 941 0x7 /* PCI irq */); 942 } 943 944 static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) 945 { 946 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 947 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 948 hwaddr base_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].base; 949 hwaddr size_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].size; 950 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 951 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 952 hwaddr base_ecam = vms->memmap[VIRT_PCIE_ECAM].base; 953 hwaddr size_ecam = vms->memmap[VIRT_PCIE_ECAM].size; 954 hwaddr base = base_mmio; 955 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 956 int irq = vms->irqmap[VIRT_PCIE]; 957 MemoryRegion *mmio_alias; 958 MemoryRegion *mmio_reg; 959 MemoryRegion *ecam_alias; 960 MemoryRegion *ecam_reg; 961 DeviceState *dev; 962 char *nodename; 963 int i; 964 PCIHostState *pci; 965 966 dev = qdev_create(NULL, TYPE_GPEX_HOST); 967 qdev_init_nofail(dev); 968 969 /* Map only the first size_ecam bytes of ECAM space */ 970 ecam_alias = g_new0(MemoryRegion, 1); 971 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 972 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 973 ecam_reg, 0, size_ecam); 974 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 975 976 /* Map the MMIO window into system address space so as to expose 977 * the section of PCI MMIO space which starts at the same base address 978 * (ie 1:1 mapping for that part of PCI MMIO space visible through 979 * the window). 980 */ 981 mmio_alias = g_new0(MemoryRegion, 1); 982 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 983 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 984 mmio_reg, base_mmio, size_mmio); 985 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 986 987 if (vms->highmem) { 988 /* Map high MMIO space */ 989 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 990 991 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 992 mmio_reg, base_mmio_high, size_mmio_high); 993 memory_region_add_subregion(get_system_memory(), base_mmio_high, 994 high_mmio_alias); 995 } 996 997 /* Map IO port space */ 998 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 999 1000 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1001 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 1002 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1003 } 1004 1005 pci = PCI_HOST_BRIDGE(dev); 1006 if (pci->bus) { 1007 for (i = 0; i < nb_nics; i++) { 1008 NICInfo *nd = &nd_table[i]; 1009 1010 if (!nd->model) { 1011 nd->model = g_strdup("virtio"); 1012 } 1013 1014 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1015 } 1016 } 1017 1018 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1019 qemu_fdt_add_subnode(vms->fdt, nodename); 1020 qemu_fdt_setprop_string(vms->fdt, nodename, 1021 "compatible", "pci-host-ecam-generic"); 1022 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci"); 1023 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3); 1024 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2); 1025 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0, 1026 nr_pcie_buses - 1); 1027 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1028 1029 if (vms->msi_phandle) { 1030 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", 1031 vms->msi_phandle); 1032 } 1033 1034 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1035 2, base_ecam, 2, size_ecam); 1036 1037 if (vms->highmem) { 1038 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1039 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1040 2, base_pio, 2, size_pio, 1041 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1042 2, base_mmio, 2, size_mmio, 1043 1, FDT_PCI_RANGE_MMIO_64BIT, 1044 2, base_mmio_high, 1045 2, base_mmio_high, 2, size_mmio_high); 1046 } else { 1047 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1048 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1049 2, base_pio, 2, size_pio, 1050 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1051 2, base_mmio, 2, size_mmio); 1052 } 1053 1054 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); 1055 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); 1056 1057 g_free(nodename); 1058 } 1059 1060 static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic) 1061 { 1062 DeviceState *dev; 1063 SysBusDevice *s; 1064 int i; 1065 ARMPlatformBusFDTParams *fdt_params = g_new(ARMPlatformBusFDTParams, 1); 1066 MemoryRegion *sysmem = get_system_memory(); 1067 1068 platform_bus_params.platform_bus_base = vms->memmap[VIRT_PLATFORM_BUS].base; 1069 platform_bus_params.platform_bus_size = vms->memmap[VIRT_PLATFORM_BUS].size; 1070 platform_bus_params.platform_bus_first_irq = vms->irqmap[VIRT_PLATFORM_BUS]; 1071 platform_bus_params.platform_bus_num_irqs = PLATFORM_BUS_NUM_IRQS; 1072 1073 fdt_params->system_params = &platform_bus_params; 1074 fdt_params->binfo = &vms->bootinfo; 1075 fdt_params->intc = "/intc"; 1076 /* 1077 * register a machine init done notifier that creates the device tree 1078 * nodes of the platform bus and its children dynamic sysbus devices 1079 */ 1080 arm_register_platform_bus_fdt_creator(fdt_params); 1081 1082 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1083 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1084 qdev_prop_set_uint32(dev, "num_irqs", 1085 platform_bus_params.platform_bus_num_irqs); 1086 qdev_prop_set_uint32(dev, "mmio_size", 1087 platform_bus_params.platform_bus_size); 1088 qdev_init_nofail(dev); 1089 s = SYS_BUS_DEVICE(dev); 1090 1091 for (i = 0; i < platform_bus_params.platform_bus_num_irqs; i++) { 1092 int irqn = platform_bus_params.platform_bus_first_irq + i; 1093 sysbus_connect_irq(s, i, pic[irqn]); 1094 } 1095 1096 memory_region_add_subregion(sysmem, 1097 platform_bus_params.platform_bus_base, 1098 sysbus_mmio_get_region(s, 0)); 1099 } 1100 1101 static void create_secure_ram(VirtMachineState *vms, 1102 MemoryRegion *secure_sysmem) 1103 { 1104 MemoryRegion *secram = g_new(MemoryRegion, 1); 1105 char *nodename; 1106 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1107 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1108 1109 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1110 &error_fatal); 1111 memory_region_add_subregion(secure_sysmem, base, secram); 1112 1113 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1114 qemu_fdt_add_subnode(vms->fdt, nodename); 1115 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory"); 1116 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size); 1117 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1118 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1119 1120 g_free(nodename); 1121 } 1122 1123 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1124 { 1125 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1126 bootinfo); 1127 1128 *fdt_size = board->fdt_size; 1129 return board->fdt; 1130 } 1131 1132 static void virt_build_smbios(VirtMachineState *vms) 1133 { 1134 uint8_t *smbios_tables, *smbios_anchor; 1135 size_t smbios_tables_len, smbios_anchor_len; 1136 const char *product = "QEMU Virtual Machine"; 1137 1138 if (!vms->fw_cfg) { 1139 return; 1140 } 1141 1142 if (kvm_enabled()) { 1143 product = "KVM Virtual Machine"; 1144 } 1145 1146 smbios_set_defaults("QEMU", product, 1147 "1.0", false, true, SMBIOS_ENTRY_POINT_30); 1148 1149 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, 1150 &smbios_anchor, &smbios_anchor_len); 1151 1152 if (smbios_anchor) { 1153 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1154 smbios_tables, smbios_tables_len); 1155 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1156 smbios_anchor, smbios_anchor_len); 1157 } 1158 } 1159 1160 static 1161 void virt_machine_done(Notifier *notifier, void *data) 1162 { 1163 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1164 machine_done); 1165 1166 virt_acpi_setup(vms); 1167 virt_build_smbios(vms); 1168 } 1169 1170 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1171 { 1172 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1173 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1174 1175 if (!vmc->disallow_affinity_adjustment) { 1176 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1177 * GIC's target-list limitations. 32-bit KVM hosts currently 1178 * always create clusters of 4 CPUs, but that is expected to 1179 * change when they gain support for gicv3. When KVM is enabled 1180 * it will override the changes we make here, therefore our 1181 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1182 * and to improve SGI efficiency. 1183 */ 1184 if (vms->gic_version == 3) { 1185 clustersz = GICV3_TARGETLIST_BITS; 1186 } else { 1187 clustersz = GIC_TARGETLIST_BITS; 1188 } 1189 } 1190 return arm_cpu_mp_affinity(idx, clustersz); 1191 } 1192 1193 static void machvirt_init(MachineState *machine) 1194 { 1195 VirtMachineState *vms = VIRT_MACHINE(machine); 1196 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1197 MachineClass *mc = MACHINE_GET_CLASS(machine); 1198 const CPUArchIdList *possible_cpus; 1199 qemu_irq pic[NUM_IRQS]; 1200 MemoryRegion *sysmem = get_system_memory(); 1201 MemoryRegion *secure_sysmem = NULL; 1202 int n, virt_max_cpus; 1203 MemoryRegion *ram = g_new(MemoryRegion, 1); 1204 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); 1205 1206 /* We can probe only here because during property set 1207 * KVM is not available yet 1208 */ 1209 if (!vms->gic_version) { 1210 if (!kvm_enabled()) { 1211 error_report("gic-version=host requires KVM"); 1212 exit(1); 1213 } 1214 1215 vms->gic_version = kvm_arm_vgic_probe(); 1216 if (!vms->gic_version) { 1217 error_report("Unable to determine GIC version supported by host"); 1218 exit(1); 1219 } 1220 } 1221 1222 if (!cpu_type_valid(machine->cpu_type)) { 1223 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 1224 exit(1); 1225 } 1226 1227 /* If we have an EL3 boot ROM then the assumption is that it will 1228 * implement PSCI itself, so disable QEMU's internal implementation 1229 * so it doesn't get in the way. Instead of starting secondary 1230 * CPUs in PSCI powerdown state we will start them all running and 1231 * let the boot ROM sort them out. 1232 * The usual case is that we do use QEMU's PSCI implementation; 1233 * if the guest has EL2 then we will use SMC as the conduit, 1234 * and otherwise we will use HVC (for backwards compatibility and 1235 * because if we're using KVM then we must use HVC). 1236 */ 1237 if (vms->secure && firmware_loaded) { 1238 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1239 } else if (vms->virt) { 1240 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 1241 } else { 1242 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 1243 } 1244 1245 /* The maximum number of CPUs depends on the GIC version, or on how 1246 * many redistributors we can fit into the memory map. 1247 */ 1248 if (vms->gic_version == 3) { 1249 virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / 0x20000; 1250 } else { 1251 virt_max_cpus = GIC_NCPU; 1252 } 1253 1254 if (max_cpus > virt_max_cpus) { 1255 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1256 "supported by machine 'mach-virt' (%d)", 1257 max_cpus, virt_max_cpus); 1258 exit(1); 1259 } 1260 1261 vms->smp_cpus = smp_cpus; 1262 1263 if (machine->ram_size > vms->memmap[VIRT_MEM].size) { 1264 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB); 1265 exit(1); 1266 } 1267 1268 if (vms->virt && kvm_enabled()) { 1269 error_report("mach-virt: KVM does not support providing " 1270 "Virtualization extensions to the guest CPU"); 1271 exit(1); 1272 } 1273 1274 if (vms->secure) { 1275 if (kvm_enabled()) { 1276 error_report("mach-virt: KVM does not support Security extensions"); 1277 exit(1); 1278 } 1279 1280 /* The Secure view of the world is the same as the NonSecure, 1281 * but with a few extra devices. Create it as a container region 1282 * containing the system memory at low priority; any secure-only 1283 * devices go in at higher priority and take precedence. 1284 */ 1285 secure_sysmem = g_new(MemoryRegion, 1); 1286 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1287 UINT64_MAX); 1288 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1289 } 1290 1291 create_fdt(vms); 1292 1293 possible_cpus = mc->possible_cpu_arch_ids(machine); 1294 for (n = 0; n < possible_cpus->len; n++) { 1295 Object *cpuobj; 1296 CPUState *cs; 1297 1298 if (n >= smp_cpus) { 1299 break; 1300 } 1301 1302 cpuobj = object_new(possible_cpus->cpus[n].type); 1303 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 1304 "mp-affinity", NULL); 1305 1306 cs = CPU(cpuobj); 1307 cs->cpu_index = n; 1308 1309 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 1310 &error_fatal); 1311 1312 if (!vms->secure) { 1313 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1314 } 1315 1316 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { 1317 object_property_set_bool(cpuobj, false, "has_el2", NULL); 1318 } 1319 1320 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1321 object_property_set_int(cpuobj, vms->psci_conduit, 1322 "psci-conduit", NULL); 1323 1324 /* Secondary CPUs start in PSCI powered-down state */ 1325 if (n > 0) { 1326 object_property_set_bool(cpuobj, true, 1327 "start-powered-off", NULL); 1328 } 1329 } 1330 1331 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { 1332 object_property_set_bool(cpuobj, false, "pmu", NULL); 1333 } 1334 1335 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1336 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, 1337 "reset-cbar", &error_abort); 1338 } 1339 1340 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1341 &error_abort); 1342 if (vms->secure) { 1343 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1344 "secure-memory", &error_abort); 1345 } 1346 1347 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 1348 object_unref(cpuobj); 1349 } 1350 fdt_add_timer_nodes(vms); 1351 fdt_add_cpu_nodes(vms); 1352 1353 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", 1354 machine->ram_size); 1355 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); 1356 1357 create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem); 1358 1359 create_gic(vms, pic); 1360 1361 fdt_add_pmu_nodes(vms); 1362 1363 create_uart(vms, pic, VIRT_UART, sysmem, serial_hds[0]); 1364 1365 if (vms->secure) { 1366 create_secure_ram(vms, secure_sysmem); 1367 create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hds[1]); 1368 } 1369 1370 create_rtc(vms, pic); 1371 1372 create_pcie(vms, pic); 1373 1374 create_gpio(vms, pic); 1375 1376 /* Create mmio transports, so the user can create virtio backends 1377 * (which will be automatically plugged in to the transports). If 1378 * no backend is created the transport will just sit harmlessly idle. 1379 */ 1380 create_virtio_devices(vms, pic); 1381 1382 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 1383 rom_set_fw(vms->fw_cfg); 1384 1385 vms->machine_done.notify = virt_machine_done; 1386 qemu_add_machine_init_done_notifier(&vms->machine_done); 1387 1388 vms->bootinfo.ram_size = machine->ram_size; 1389 vms->bootinfo.kernel_filename = machine->kernel_filename; 1390 vms->bootinfo.kernel_cmdline = machine->kernel_cmdline; 1391 vms->bootinfo.initrd_filename = machine->initrd_filename; 1392 vms->bootinfo.nb_cpus = smp_cpus; 1393 vms->bootinfo.board_id = -1; 1394 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 1395 vms->bootinfo.get_dtb = machvirt_dtb; 1396 vms->bootinfo.firmware_loaded = firmware_loaded; 1397 arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo); 1398 1399 /* 1400 * arm_load_kernel machine init done notifier registration must 1401 * happen before the platform_bus_create call. In this latter, 1402 * another notifier is registered which adds platform bus nodes. 1403 * Notifiers are executed in registration reverse order. 1404 */ 1405 create_platform_bus(vms, pic); 1406 } 1407 1408 static bool virt_get_secure(Object *obj, Error **errp) 1409 { 1410 VirtMachineState *vms = VIRT_MACHINE(obj); 1411 1412 return vms->secure; 1413 } 1414 1415 static void virt_set_secure(Object *obj, bool value, Error **errp) 1416 { 1417 VirtMachineState *vms = VIRT_MACHINE(obj); 1418 1419 vms->secure = value; 1420 } 1421 1422 static bool virt_get_virt(Object *obj, Error **errp) 1423 { 1424 VirtMachineState *vms = VIRT_MACHINE(obj); 1425 1426 return vms->virt; 1427 } 1428 1429 static void virt_set_virt(Object *obj, bool value, Error **errp) 1430 { 1431 VirtMachineState *vms = VIRT_MACHINE(obj); 1432 1433 vms->virt = value; 1434 } 1435 1436 static bool virt_get_highmem(Object *obj, Error **errp) 1437 { 1438 VirtMachineState *vms = VIRT_MACHINE(obj); 1439 1440 return vms->highmem; 1441 } 1442 1443 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1444 { 1445 VirtMachineState *vms = VIRT_MACHINE(obj); 1446 1447 vms->highmem = value; 1448 } 1449 1450 static bool virt_get_its(Object *obj, Error **errp) 1451 { 1452 VirtMachineState *vms = VIRT_MACHINE(obj); 1453 1454 return vms->its; 1455 } 1456 1457 static void virt_set_its(Object *obj, bool value, Error **errp) 1458 { 1459 VirtMachineState *vms = VIRT_MACHINE(obj); 1460 1461 vms->its = value; 1462 } 1463 1464 static char *virt_get_gic_version(Object *obj, Error **errp) 1465 { 1466 VirtMachineState *vms = VIRT_MACHINE(obj); 1467 const char *val = vms->gic_version == 3 ? "3" : "2"; 1468 1469 return g_strdup(val); 1470 } 1471 1472 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 1473 { 1474 VirtMachineState *vms = VIRT_MACHINE(obj); 1475 1476 if (!strcmp(value, "3")) { 1477 vms->gic_version = 3; 1478 } else if (!strcmp(value, "2")) { 1479 vms->gic_version = 2; 1480 } else if (!strcmp(value, "host")) { 1481 vms->gic_version = 0; /* Will probe later */ 1482 } else { 1483 error_setg(errp, "Invalid gic-version value"); 1484 error_append_hint(errp, "Valid values are 3, 2, host.\n"); 1485 } 1486 } 1487 1488 static CpuInstanceProperties 1489 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1490 { 1491 MachineClass *mc = MACHINE_GET_CLASS(ms); 1492 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1493 1494 assert(cpu_index < possible_cpus->len); 1495 return possible_cpus->cpus[cpu_index].props; 1496 } 1497 1498 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1499 { 1500 return idx % nb_numa_nodes; 1501 } 1502 1503 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1504 { 1505 int n; 1506 VirtMachineState *vms = VIRT_MACHINE(ms); 1507 1508 if (ms->possible_cpus) { 1509 assert(ms->possible_cpus->len == max_cpus); 1510 return ms->possible_cpus; 1511 } 1512 1513 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1514 sizeof(CPUArchId) * max_cpus); 1515 ms->possible_cpus->len = max_cpus; 1516 for (n = 0; n < ms->possible_cpus->len; n++) { 1517 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1518 ms->possible_cpus->cpus[n].arch_id = 1519 virt_cpu_mp_affinity(vms, n); 1520 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1521 ms->possible_cpus->cpus[n].props.thread_id = n; 1522 } 1523 return ms->possible_cpus; 1524 } 1525 1526 static void virt_machine_class_init(ObjectClass *oc, void *data) 1527 { 1528 MachineClass *mc = MACHINE_CLASS(oc); 1529 1530 mc->init = machvirt_init; 1531 /* Start max_cpus at the maximum QEMU supports. We'll further restrict 1532 * it later in machvirt_init, where we have more information about the 1533 * configuration of the particular instance. 1534 */ 1535 mc->max_cpus = 255; 1536 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 1537 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 1538 mc->block_default_type = IF_VIRTIO; 1539 mc->no_cdrom = 1; 1540 mc->pci_allow_0_address = true; 1541 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 1542 mc->minimum_page_bits = 12; 1543 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1544 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1545 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 1546 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1547 } 1548 1549 static const TypeInfo virt_machine_info = { 1550 .name = TYPE_VIRT_MACHINE, 1551 .parent = TYPE_MACHINE, 1552 .abstract = true, 1553 .instance_size = sizeof(VirtMachineState), 1554 .class_size = sizeof(VirtMachineClass), 1555 .class_init = virt_machine_class_init, 1556 }; 1557 1558 static void machvirt_machine_init(void) 1559 { 1560 type_register_static(&virt_machine_info); 1561 } 1562 type_init(machvirt_machine_init); 1563 1564 static void virt_2_12_instance_init(Object *obj) 1565 { 1566 VirtMachineState *vms = VIRT_MACHINE(obj); 1567 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1568 1569 /* EL3 is disabled by default on virt: this makes us consistent 1570 * between KVM and TCG for this board, and it also allows us to 1571 * boot UEFI blobs which assume no TrustZone support. 1572 */ 1573 vms->secure = false; 1574 object_property_add_bool(obj, "secure", virt_get_secure, 1575 virt_set_secure, NULL); 1576 object_property_set_description(obj, "secure", 1577 "Set on/off to enable/disable the ARM " 1578 "Security Extensions (TrustZone)", 1579 NULL); 1580 1581 /* EL2 is also disabled by default, for similar reasons */ 1582 vms->virt = false; 1583 object_property_add_bool(obj, "virtualization", virt_get_virt, 1584 virt_set_virt, NULL); 1585 object_property_set_description(obj, "virtualization", 1586 "Set on/off to enable/disable emulating a " 1587 "guest CPU which implements the ARM " 1588 "Virtualization Extensions", 1589 NULL); 1590 1591 /* High memory is enabled by default */ 1592 vms->highmem = true; 1593 object_property_add_bool(obj, "highmem", virt_get_highmem, 1594 virt_set_highmem, NULL); 1595 object_property_set_description(obj, "highmem", 1596 "Set on/off to enable/disable using " 1597 "physical address space above 32 bits", 1598 NULL); 1599 /* Default GIC type is v2 */ 1600 vms->gic_version = 2; 1601 object_property_add_str(obj, "gic-version", virt_get_gic_version, 1602 virt_set_gic_version, NULL); 1603 object_property_set_description(obj, "gic-version", 1604 "Set GIC version. " 1605 "Valid values are 2, 3 and host", NULL); 1606 1607 if (vmc->no_its) { 1608 vms->its = false; 1609 } else { 1610 /* Default allows ITS instantiation */ 1611 vms->its = true; 1612 object_property_add_bool(obj, "its", virt_get_its, 1613 virt_set_its, NULL); 1614 object_property_set_description(obj, "its", 1615 "Set on/off to enable/disable " 1616 "ITS instantiation", 1617 NULL); 1618 } 1619 1620 vms->memmap = a15memmap; 1621 vms->irqmap = a15irqmap; 1622 } 1623 1624 static void virt_machine_2_12_options(MachineClass *mc) 1625 { 1626 } 1627 DEFINE_VIRT_MACHINE_AS_LATEST(2, 12) 1628 1629 #define VIRT_COMPAT_2_11 \ 1630 HW_COMPAT_2_11 1631 1632 static void virt_2_11_instance_init(Object *obj) 1633 { 1634 virt_2_12_instance_init(obj); 1635 } 1636 1637 static void virt_machine_2_11_options(MachineClass *mc) 1638 { 1639 virt_machine_2_12_options(mc); 1640 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_11); 1641 } 1642 DEFINE_VIRT_MACHINE(2, 11) 1643 1644 #define VIRT_COMPAT_2_10 \ 1645 HW_COMPAT_2_10 1646 1647 static void virt_2_10_instance_init(Object *obj) 1648 { 1649 virt_2_11_instance_init(obj); 1650 } 1651 1652 static void virt_machine_2_10_options(MachineClass *mc) 1653 { 1654 virt_machine_2_11_options(mc); 1655 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_10); 1656 } 1657 DEFINE_VIRT_MACHINE(2, 10) 1658 1659 #define VIRT_COMPAT_2_9 \ 1660 HW_COMPAT_2_9 1661 1662 static void virt_2_9_instance_init(Object *obj) 1663 { 1664 virt_2_10_instance_init(obj); 1665 } 1666 1667 static void virt_machine_2_9_options(MachineClass *mc) 1668 { 1669 virt_machine_2_10_options(mc); 1670 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_9); 1671 } 1672 DEFINE_VIRT_MACHINE(2, 9) 1673 1674 #define VIRT_COMPAT_2_8 \ 1675 HW_COMPAT_2_8 1676 1677 static void virt_2_8_instance_init(Object *obj) 1678 { 1679 virt_2_9_instance_init(obj); 1680 } 1681 1682 static void virt_machine_2_8_options(MachineClass *mc) 1683 { 1684 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1685 1686 virt_machine_2_9_options(mc); 1687 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_8); 1688 /* For 2.8 and earlier we falsely claimed in the DT that 1689 * our timers were edge-triggered, not level-triggered. 1690 */ 1691 vmc->claim_edge_triggered_timers = true; 1692 } 1693 DEFINE_VIRT_MACHINE(2, 8) 1694 1695 #define VIRT_COMPAT_2_7 \ 1696 HW_COMPAT_2_7 1697 1698 static void virt_2_7_instance_init(Object *obj) 1699 { 1700 virt_2_8_instance_init(obj); 1701 } 1702 1703 static void virt_machine_2_7_options(MachineClass *mc) 1704 { 1705 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1706 1707 virt_machine_2_8_options(mc); 1708 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_7); 1709 /* ITS was introduced with 2.8 */ 1710 vmc->no_its = true; 1711 /* Stick with 1K pages for migration compatibility */ 1712 mc->minimum_page_bits = 0; 1713 } 1714 DEFINE_VIRT_MACHINE(2, 7) 1715 1716 #define VIRT_COMPAT_2_6 \ 1717 HW_COMPAT_2_6 1718 1719 static void virt_2_6_instance_init(Object *obj) 1720 { 1721 virt_2_7_instance_init(obj); 1722 } 1723 1724 static void virt_machine_2_6_options(MachineClass *mc) 1725 { 1726 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1727 1728 virt_machine_2_7_options(mc); 1729 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6); 1730 vmc->disallow_affinity_adjustment = true; 1731 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 1732 vmc->no_pmu = true; 1733 } 1734 DEFINE_VIRT_MACHINE(2, 6) 1735