1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu-common.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "qapi/error.h" 36 #include "hw/sysbus.h" 37 #include "hw/arm/boot.h" 38 #include "hw/arm/primecell.h" 39 #include "hw/arm/virt.h" 40 #include "hw/block/flash.h" 41 #include "hw/vfio/vfio-calxeda-xgmac.h" 42 #include "hw/vfio/vfio-amd-xgbe.h" 43 #include "hw/display/ramfb.h" 44 #include "net/net.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/numa.h" 47 #include "sysemu/sysemu.h" 48 #include "sysemu/kvm.h" 49 #include "hw/loader.h" 50 #include "exec/address-spaces.h" 51 #include "qemu/bitops.h" 52 #include "qemu/error-report.h" 53 #include "qemu/module.h" 54 #include "hw/pci-host/gpex.h" 55 #include "hw/arm/sysbus-fdt.h" 56 #include "hw/platform-bus.h" 57 #include "hw/arm/fdt.h" 58 #include "hw/intc/arm_gic.h" 59 #include "hw/intc/arm_gicv3_common.h" 60 #include "kvm_arm.h" 61 #include "hw/firmware/smbios.h" 62 #include "qapi/visitor.h" 63 #include "standard-headers/linux/input.h" 64 #include "hw/arm/smmuv3.h" 65 #include "hw/acpi/acpi.h" 66 #include "target/arm/internals.h" 67 68 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 69 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 70 void *data) \ 71 { \ 72 MachineClass *mc = MACHINE_CLASS(oc); \ 73 virt_machine_##major##_##minor##_options(mc); \ 74 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 75 if (latest) { \ 76 mc->alias = "virt"; \ 77 } \ 78 } \ 79 static const TypeInfo machvirt_##major##_##minor##_info = { \ 80 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 81 .parent = TYPE_VIRT_MACHINE, \ 82 .class_init = virt_##major##_##minor##_class_init, \ 83 }; \ 84 static void machvirt_machine_##major##_##minor##_init(void) \ 85 { \ 86 type_register_static(&machvirt_##major##_##minor##_info); \ 87 } \ 88 type_init(machvirt_machine_##major##_##minor##_init); 89 90 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 91 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 92 #define DEFINE_VIRT_MACHINE(major, minor) \ 93 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 94 95 96 /* Number of external interrupt lines to configure the GIC with */ 97 #define NUM_IRQS 256 98 99 #define PLATFORM_BUS_NUM_IRQS 64 100 101 /* Legacy RAM limit in GB (< version 4.0) */ 102 #define LEGACY_RAMLIMIT_GB 255 103 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 104 105 /* Addresses and sizes of our components. 106 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 107 * 128MB..256MB is used for miscellaneous device I/O. 108 * 256MB..1GB is reserved for possible future PCI support (ie where the 109 * PCI memory window will go if we add a PCI host controller). 110 * 1GB and up is RAM (which may happily spill over into the 111 * high memory region beyond 4GB). 112 * This represents a compromise between how much RAM can be given to 113 * a 32 bit VM and leaving space for expansion and in particular for PCI. 114 * Note that devices should generally be placed at multiples of 0x10000, 115 * to accommodate guests using 64K pages. 116 */ 117 static const MemMapEntry base_memmap[] = { 118 /* Space up to 0x8000000 is reserved for a boot ROM */ 119 [VIRT_FLASH] = { 0, 0x08000000 }, 120 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 121 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 122 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 123 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 124 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 125 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 126 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 127 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 128 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 129 /* This redistributor space allows up to 2*64kB*123 CPUs */ 130 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 131 [VIRT_UART] = { 0x09000000, 0x00001000 }, 132 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 133 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 134 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 135 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 136 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 137 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 138 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 139 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 140 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 141 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 142 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 143 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 144 /* Actual RAM size depends on initial RAM and device memory settings */ 145 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 146 }; 147 148 /* 149 * Highmem IO Regions: This memory map is floating, located after the RAM. 150 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 151 * top of the RAM, so that its base get the same alignment as the size, 152 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 153 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 154 * Note the extended_memmap is sized so that it eventually also includes the 155 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 156 * index of base_memmap). 157 */ 158 static MemMapEntry extended_memmap[] = { 159 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 160 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 161 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 162 /* Second PCIe window */ 163 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 164 }; 165 166 static const int a15irqmap[] = { 167 [VIRT_UART] = 1, 168 [VIRT_RTC] = 2, 169 [VIRT_PCIE] = 3, /* ... to 6 */ 170 [VIRT_GPIO] = 7, 171 [VIRT_SECURE_UART] = 8, 172 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 173 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 174 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 175 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 176 }; 177 178 static const char *valid_cpus[] = { 179 ARM_CPU_TYPE_NAME("cortex-a15"), 180 ARM_CPU_TYPE_NAME("cortex-a53"), 181 ARM_CPU_TYPE_NAME("cortex-a57"), 182 ARM_CPU_TYPE_NAME("cortex-a72"), 183 ARM_CPU_TYPE_NAME("host"), 184 ARM_CPU_TYPE_NAME("max"), 185 }; 186 187 static bool cpu_type_valid(const char *cpu) 188 { 189 int i; 190 191 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 192 if (strcmp(cpu, valid_cpus[i]) == 0) { 193 return true; 194 } 195 } 196 return false; 197 } 198 199 static void create_fdt(VirtMachineState *vms) 200 { 201 void *fdt = create_device_tree(&vms->fdt_size); 202 203 if (!fdt) { 204 error_report("create_device_tree() failed"); 205 exit(1); 206 } 207 208 vms->fdt = fdt; 209 210 /* Header */ 211 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 212 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 213 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 214 215 /* /chosen must exist for load_dtb to fill in necessary properties later */ 216 qemu_fdt_add_subnode(fdt, "/chosen"); 217 218 /* Clock node, for the benefit of the UART. The kernel device tree 219 * binding documentation claims the PL011 node clock properties are 220 * optional but in practice if you omit them the kernel refuses to 221 * probe for the device. 222 */ 223 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 224 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 225 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 226 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 227 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 228 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 229 "clk24mhz"); 230 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 231 232 if (have_numa_distance) { 233 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 234 uint32_t *matrix = g_malloc0(size); 235 int idx, i, j; 236 237 for (i = 0; i < nb_numa_nodes; i++) { 238 for (j = 0; j < nb_numa_nodes; j++) { 239 idx = (i * nb_numa_nodes + j) * 3; 240 matrix[idx + 0] = cpu_to_be32(i); 241 matrix[idx + 1] = cpu_to_be32(j); 242 matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]); 243 } 244 } 245 246 qemu_fdt_add_subnode(fdt, "/distance-map"); 247 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 248 "numa-distance-map-v1"); 249 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 250 matrix, size); 251 g_free(matrix); 252 } 253 } 254 255 static void fdt_add_timer_nodes(const VirtMachineState *vms) 256 { 257 /* On real hardware these interrupts are level-triggered. 258 * On KVM they were edge-triggered before host kernel version 4.4, 259 * and level-triggered afterwards. 260 * On emulated QEMU they are level-triggered. 261 * 262 * Getting the DTB info about them wrong is awkward for some 263 * guest kernels: 264 * pre-4.8 ignore the DT and leave the interrupt configured 265 * with whatever the GIC reset value (or the bootloader) left it at 266 * 4.8 before rc6 honour the incorrect data by programming it back 267 * into the GIC, causing problems 268 * 4.8rc6 and later ignore the DT and always write "level triggered" 269 * into the GIC 270 * 271 * For backwards-compatibility, virt-2.8 and earlier will continue 272 * to say these are edge-triggered, but later machines will report 273 * the correct information. 274 */ 275 ARMCPU *armcpu; 276 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 277 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 278 279 if (vmc->claim_edge_triggered_timers) { 280 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 281 } 282 283 if (vms->gic_version == 2) { 284 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 285 GIC_FDT_IRQ_PPI_CPU_WIDTH, 286 (1 << vms->smp_cpus) - 1); 287 } 288 289 qemu_fdt_add_subnode(vms->fdt, "/timer"); 290 291 armcpu = ARM_CPU(qemu_get_cpu(0)); 292 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 293 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 294 qemu_fdt_setprop(vms->fdt, "/timer", "compatible", 295 compat, sizeof(compat)); 296 } else { 297 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible", 298 "arm,armv7-timer"); 299 } 300 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0); 301 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts", 302 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 303 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 304 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 305 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 306 } 307 308 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 309 { 310 int cpu; 311 int addr_cells = 1; 312 const MachineState *ms = MACHINE(vms); 313 314 /* 315 * From Documentation/devicetree/bindings/arm/cpus.txt 316 * On ARM v8 64-bit systems value should be set to 2, 317 * that corresponds to the MPIDR_EL1 register size. 318 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 319 * in the system, #address-cells can be set to 1, since 320 * MPIDR_EL1[63:32] bits are not used for CPUs 321 * identification. 322 * 323 * Here we actually don't know whether our system is 32- or 64-bit one. 324 * The simplest way to go is to examine affinity IDs of all our CPUs. If 325 * at least one of them has Aff3 populated, we set #address-cells to 2. 326 */ 327 for (cpu = 0; cpu < vms->smp_cpus; cpu++) { 328 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 329 330 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 331 addr_cells = 2; 332 break; 333 } 334 } 335 336 qemu_fdt_add_subnode(vms->fdt, "/cpus"); 337 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); 338 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); 339 340 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { 341 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 342 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 343 CPUState *cs = CPU(armcpu); 344 345 qemu_fdt_add_subnode(vms->fdt, nodename); 346 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); 347 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 348 armcpu->dtb_compatible); 349 350 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED 351 && vms->smp_cpus > 1) { 352 qemu_fdt_setprop_string(vms->fdt, nodename, 353 "enable-method", "psci"); 354 } 355 356 if (addr_cells == 2) { 357 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", 358 armcpu->mp_affinity); 359 } else { 360 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", 361 armcpu->mp_affinity); 362 } 363 364 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 365 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", 366 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 367 } 368 369 g_free(nodename); 370 } 371 } 372 373 static void fdt_add_its_gic_node(VirtMachineState *vms) 374 { 375 char *nodename; 376 377 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 378 nodename = g_strdup_printf("/intc/its@%" PRIx64, 379 vms->memmap[VIRT_GIC_ITS].base); 380 qemu_fdt_add_subnode(vms->fdt, nodename); 381 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 382 "arm,gic-v3-its"); 383 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); 384 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 385 2, vms->memmap[VIRT_GIC_ITS].base, 386 2, vms->memmap[VIRT_GIC_ITS].size); 387 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); 388 g_free(nodename); 389 } 390 391 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 392 { 393 char *nodename; 394 395 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 396 vms->memmap[VIRT_GIC_V2M].base); 397 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 398 qemu_fdt_add_subnode(vms->fdt, nodename); 399 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 400 "arm,gic-v2m-frame"); 401 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); 402 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 403 2, vms->memmap[VIRT_GIC_V2M].base, 404 2, vms->memmap[VIRT_GIC_V2M].size); 405 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); 406 g_free(nodename); 407 } 408 409 static void fdt_add_gic_node(VirtMachineState *vms) 410 { 411 char *nodename; 412 413 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt); 414 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle); 415 416 nodename = g_strdup_printf("/intc@%" PRIx64, 417 vms->memmap[VIRT_GIC_DIST].base); 418 qemu_fdt_add_subnode(vms->fdt, nodename); 419 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 3); 420 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-controller", NULL, 0); 421 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2); 422 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2); 423 qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0); 424 if (vms->gic_version == 3) { 425 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 426 427 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 428 "arm,gic-v3"); 429 430 qemu_fdt_setprop_cell(vms->fdt, nodename, 431 "#redistributor-regions", nb_redist_regions); 432 433 if (nb_redist_regions == 1) { 434 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 435 2, vms->memmap[VIRT_GIC_DIST].base, 436 2, vms->memmap[VIRT_GIC_DIST].size, 437 2, vms->memmap[VIRT_GIC_REDIST].base, 438 2, vms->memmap[VIRT_GIC_REDIST].size); 439 } else { 440 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 441 2, vms->memmap[VIRT_GIC_DIST].base, 442 2, vms->memmap[VIRT_GIC_DIST].size, 443 2, vms->memmap[VIRT_GIC_REDIST].base, 444 2, vms->memmap[VIRT_GIC_REDIST].size, 445 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 446 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 447 } 448 449 if (vms->virt) { 450 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 451 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 452 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 453 } 454 } else { 455 /* 'cortex-a15-gic' means 'GIC v2' */ 456 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 457 "arm,cortex-a15-gic"); 458 if (!vms->virt) { 459 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 460 2, vms->memmap[VIRT_GIC_DIST].base, 461 2, vms->memmap[VIRT_GIC_DIST].size, 462 2, vms->memmap[VIRT_GIC_CPU].base, 463 2, vms->memmap[VIRT_GIC_CPU].size); 464 } else { 465 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 466 2, vms->memmap[VIRT_GIC_DIST].base, 467 2, vms->memmap[VIRT_GIC_DIST].size, 468 2, vms->memmap[VIRT_GIC_CPU].base, 469 2, vms->memmap[VIRT_GIC_CPU].size, 470 2, vms->memmap[VIRT_GIC_HYP].base, 471 2, vms->memmap[VIRT_GIC_HYP].size, 472 2, vms->memmap[VIRT_GIC_VCPU].base, 473 2, vms->memmap[VIRT_GIC_VCPU].size); 474 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 475 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 476 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 477 } 478 } 479 480 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle); 481 g_free(nodename); 482 } 483 484 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 485 { 486 CPUState *cpu; 487 ARMCPU *armcpu; 488 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 489 490 CPU_FOREACH(cpu) { 491 armcpu = ARM_CPU(cpu); 492 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 493 return; 494 } 495 if (kvm_enabled()) { 496 if (kvm_irqchip_in_kernel()) { 497 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 498 } 499 kvm_arm_pmu_init(cpu); 500 } 501 } 502 503 if (vms->gic_version == 2) { 504 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 505 GIC_FDT_IRQ_PPI_CPU_WIDTH, 506 (1 << vms->smp_cpus) - 1); 507 } 508 509 armcpu = ARM_CPU(qemu_get_cpu(0)); 510 qemu_fdt_add_subnode(vms->fdt, "/pmu"); 511 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 512 const char compat[] = "arm,armv8-pmuv3"; 513 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible", 514 compat, sizeof(compat)); 515 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts", 516 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 517 } 518 } 519 520 static void create_its(VirtMachineState *vms, DeviceState *gicdev) 521 { 522 const char *itsclass = its_class_name(); 523 DeviceState *dev; 524 525 if (!itsclass) { 526 /* Do nothing if not supported */ 527 return; 528 } 529 530 dev = qdev_create(NULL, itsclass); 531 532 object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3", 533 &error_abort); 534 qdev_init_nofail(dev); 535 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 536 537 fdt_add_its_gic_node(vms); 538 } 539 540 static void create_v2m(VirtMachineState *vms, qemu_irq *pic) 541 { 542 int i; 543 int irq = vms->irqmap[VIRT_GIC_V2M]; 544 DeviceState *dev; 545 546 dev = qdev_create(NULL, "arm-gicv2m"); 547 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 548 qdev_prop_set_uint32(dev, "base-spi", irq); 549 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 550 qdev_init_nofail(dev); 551 552 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 553 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 554 } 555 556 fdt_add_v2m_gic_node(vms); 557 } 558 559 static void create_gic(VirtMachineState *vms, qemu_irq *pic) 560 { 561 /* We create a standalone GIC */ 562 DeviceState *gicdev; 563 SysBusDevice *gicbusdev; 564 const char *gictype; 565 int type = vms->gic_version, i; 566 uint32_t nb_redist_regions = 0; 567 568 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 569 570 gicdev = qdev_create(NULL, gictype); 571 qdev_prop_set_uint32(gicdev, "revision", type); 572 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 573 /* Note that the num-irq property counts both internal and external 574 * interrupts; there are always 32 of the former (mandated by GIC spec). 575 */ 576 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 577 if (!kvm_irqchip_in_kernel()) { 578 qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure); 579 } 580 581 if (type == 3) { 582 uint32_t redist0_capacity = 583 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 584 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 585 586 nb_redist_regions = virt_gicv3_redist_region_count(vms); 587 588 qdev_prop_set_uint32(gicdev, "len-redist-region-count", 589 nb_redist_regions); 590 qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count); 591 592 if (nb_redist_regions == 2) { 593 uint32_t redist1_capacity = 594 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; 595 596 qdev_prop_set_uint32(gicdev, "redist-region-count[1]", 597 MIN(smp_cpus - redist0_count, redist1_capacity)); 598 } 599 } else { 600 if (!kvm_irqchip_in_kernel()) { 601 qdev_prop_set_bit(gicdev, "has-virtualization-extensions", 602 vms->virt); 603 } 604 } 605 qdev_init_nofail(gicdev); 606 gicbusdev = SYS_BUS_DEVICE(gicdev); 607 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 608 if (type == 3) { 609 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 610 if (nb_redist_regions == 2) { 611 sysbus_mmio_map(gicbusdev, 2, 612 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 613 } 614 } else { 615 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 616 if (vms->virt) { 617 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 618 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 619 } 620 } 621 622 /* Wire the outputs from each CPU's generic timer and the GICv3 623 * maintenance interrupt signal to the appropriate GIC PPI inputs, 624 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 625 */ 626 for (i = 0; i < smp_cpus; i++) { 627 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 628 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 629 int irq; 630 /* Mapping from the output timer irq lines from the CPU to the 631 * GIC PPI inputs we use for the virt board. 632 */ 633 const int timer_irq[] = { 634 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 635 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 636 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 637 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 638 }; 639 640 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 641 qdev_connect_gpio_out(cpudev, irq, 642 qdev_get_gpio_in(gicdev, 643 ppibase + timer_irq[irq])); 644 } 645 646 if (type == 3) { 647 qemu_irq irq = qdev_get_gpio_in(gicdev, 648 ppibase + ARCH_GIC_MAINT_IRQ); 649 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 650 0, irq); 651 } else if (vms->virt) { 652 qemu_irq irq = qdev_get_gpio_in(gicdev, 653 ppibase + ARCH_GIC_MAINT_IRQ); 654 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 655 } 656 657 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 658 qdev_get_gpio_in(gicdev, ppibase 659 + VIRTUAL_PMU_IRQ)); 660 661 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 662 sysbus_connect_irq(gicbusdev, i + smp_cpus, 663 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 664 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 665 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 666 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 667 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 668 } 669 670 for (i = 0; i < NUM_IRQS; i++) { 671 pic[i] = qdev_get_gpio_in(gicdev, i); 672 } 673 674 fdt_add_gic_node(vms); 675 676 if (type == 3 && vms->its) { 677 create_its(vms, gicdev); 678 } else if (type == 2) { 679 create_v2m(vms, pic); 680 } 681 } 682 683 static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart, 684 MemoryRegion *mem, Chardev *chr) 685 { 686 char *nodename; 687 hwaddr base = vms->memmap[uart].base; 688 hwaddr size = vms->memmap[uart].size; 689 int irq = vms->irqmap[uart]; 690 const char compat[] = "arm,pl011\0arm,primecell"; 691 const char clocknames[] = "uartclk\0apb_pclk"; 692 DeviceState *dev = qdev_create(NULL, "pl011"); 693 SysBusDevice *s = SYS_BUS_DEVICE(dev); 694 695 qdev_prop_set_chr(dev, "chardev", chr); 696 qdev_init_nofail(dev); 697 memory_region_add_subregion(mem, base, 698 sysbus_mmio_get_region(s, 0)); 699 sysbus_connect_irq(s, 0, pic[irq]); 700 701 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 702 qemu_fdt_add_subnode(vms->fdt, nodename); 703 /* Note that we can't use setprop_string because of the embedded NUL */ 704 qemu_fdt_setprop(vms->fdt, nodename, "compatible", 705 compat, sizeof(compat)); 706 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 707 2, base, 2, size); 708 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 709 GIC_FDT_IRQ_TYPE_SPI, irq, 710 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 711 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks", 712 vms->clock_phandle, vms->clock_phandle); 713 qemu_fdt_setprop(vms->fdt, nodename, "clock-names", 714 clocknames, sizeof(clocknames)); 715 716 if (uart == VIRT_UART) { 717 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); 718 } else { 719 /* Mark as not usable by the normal world */ 720 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 721 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 722 723 qemu_fdt_add_subnode(vms->fdt, "/secure-chosen"); 724 qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path", 725 nodename); 726 } 727 728 g_free(nodename); 729 } 730 731 static void create_rtc(const VirtMachineState *vms, qemu_irq *pic) 732 { 733 char *nodename; 734 hwaddr base = vms->memmap[VIRT_RTC].base; 735 hwaddr size = vms->memmap[VIRT_RTC].size; 736 int irq = vms->irqmap[VIRT_RTC]; 737 const char compat[] = "arm,pl031\0arm,primecell"; 738 739 sysbus_create_simple("pl031", base, pic[irq]); 740 741 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 742 qemu_fdt_add_subnode(vms->fdt, nodename); 743 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 744 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 745 2, base, 2, size); 746 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 747 GIC_FDT_IRQ_TYPE_SPI, irq, 748 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 749 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 750 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 751 g_free(nodename); 752 } 753 754 static DeviceState *gpio_key_dev; 755 static void virt_powerdown_req(Notifier *n, void *opaque) 756 { 757 /* use gpio Pin 3 for power button event */ 758 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 759 } 760 761 static Notifier virt_system_powerdown_notifier = { 762 .notify = virt_powerdown_req 763 }; 764 765 static void create_gpio(const VirtMachineState *vms, qemu_irq *pic) 766 { 767 char *nodename; 768 DeviceState *pl061_dev; 769 hwaddr base = vms->memmap[VIRT_GPIO].base; 770 hwaddr size = vms->memmap[VIRT_GPIO].size; 771 int irq = vms->irqmap[VIRT_GPIO]; 772 const char compat[] = "arm,pl061\0arm,primecell"; 773 774 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); 775 776 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); 777 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 778 qemu_fdt_add_subnode(vms->fdt, nodename); 779 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 780 2, base, 2, size); 781 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 782 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); 783 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); 784 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 785 GIC_FDT_IRQ_TYPE_SPI, irq, 786 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 787 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 788 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 789 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); 790 791 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 792 qdev_get_gpio_in(pl061_dev, 3)); 793 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); 794 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); 795 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); 796 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); 797 798 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); 799 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", 800 "label", "GPIO Key Poweroff"); 801 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", 802 KEY_POWER); 803 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", 804 "gpios", phandle, 3, 0); 805 806 /* connect powerdown request */ 807 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier); 808 809 g_free(nodename); 810 } 811 812 static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic) 813 { 814 int i; 815 hwaddr size = vms->memmap[VIRT_MMIO].size; 816 817 /* We create the transports in forwards order. Since qbus_realize() 818 * prepends (not appends) new child buses, the incrementing loop below will 819 * create a list of virtio-mmio buses with decreasing base addresses. 820 * 821 * When a -device option is processed from the command line, 822 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 823 * order. The upshot is that -device options in increasing command line 824 * order are mapped to virtio-mmio buses with decreasing base addresses. 825 * 826 * When this code was originally written, that arrangement ensured that the 827 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 828 * the first -device on the command line. (The end-to-end order is a 829 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 830 * guest kernel's name-to-address assignment strategy.) 831 * 832 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 833 * the message, if not necessarily the code, of commit 70161ff336. 834 * Therefore the loop now establishes the inverse of the original intent. 835 * 836 * Unfortunately, we can't counteract the kernel change by reversing the 837 * loop; it would break existing command lines. 838 * 839 * In any case, the kernel makes no guarantee about the stability of 840 * enumeration order of virtio devices (as demonstrated by it changing 841 * between kernel versions). For reliable and stable identification 842 * of disks users must use UUIDs or similar mechanisms. 843 */ 844 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 845 int irq = vms->irqmap[VIRT_MMIO] + i; 846 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 847 848 sysbus_create_simple("virtio-mmio", base, pic[irq]); 849 } 850 851 /* We add dtb nodes in reverse order so that they appear in the finished 852 * device tree lowest address first. 853 * 854 * Note that this mapping is independent of the loop above. The previous 855 * loop influences virtio device to virtio transport assignment, whereas 856 * this loop controls how virtio transports are laid out in the dtb. 857 */ 858 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 859 char *nodename; 860 int irq = vms->irqmap[VIRT_MMIO] + i; 861 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 862 863 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 864 qemu_fdt_add_subnode(vms->fdt, nodename); 865 qemu_fdt_setprop_string(vms->fdt, nodename, 866 "compatible", "virtio,mmio"); 867 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 868 2, base, 2, size); 869 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 870 GIC_FDT_IRQ_TYPE_SPI, irq, 871 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 872 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 873 g_free(nodename); 874 } 875 } 876 877 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 878 879 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 880 const char *name, 881 const char *alias_prop_name) 882 { 883 /* 884 * Create a single flash device. We use the same parameters as 885 * the flash devices on the Versatile Express board. 886 */ 887 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01); 888 889 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 890 qdev_prop_set_uint8(dev, "width", 4); 891 qdev_prop_set_uint8(dev, "device-width", 2); 892 qdev_prop_set_bit(dev, "big-endian", false); 893 qdev_prop_set_uint16(dev, "id0", 0x89); 894 qdev_prop_set_uint16(dev, "id1", 0x18); 895 qdev_prop_set_uint16(dev, "id2", 0x00); 896 qdev_prop_set_uint16(dev, "id3", 0x00); 897 qdev_prop_set_string(dev, "name", name); 898 object_property_add_child(OBJECT(vms), name, OBJECT(dev), 899 &error_abort); 900 object_property_add_alias(OBJECT(vms), alias_prop_name, 901 OBJECT(dev), "drive", &error_abort); 902 return PFLASH_CFI01(dev); 903 } 904 905 static void virt_flash_create(VirtMachineState *vms) 906 { 907 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 908 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 909 } 910 911 static void virt_flash_map1(PFlashCFI01 *flash, 912 hwaddr base, hwaddr size, 913 MemoryRegion *sysmem) 914 { 915 DeviceState *dev = DEVICE(flash); 916 917 assert(size % VIRT_FLASH_SECTOR_SIZE == 0); 918 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 919 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 920 qdev_init_nofail(dev); 921 922 memory_region_add_subregion(sysmem, base, 923 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 924 0)); 925 } 926 927 static void virt_flash_map(VirtMachineState *vms, 928 MemoryRegion *sysmem, 929 MemoryRegion *secure_sysmem) 930 { 931 /* 932 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 933 * sysmem is the system memory space. secure_sysmem is the secure view 934 * of the system, and the first flash device should be made visible only 935 * there. The second flash device is visible to both secure and nonsecure. 936 * If sysmem == secure_sysmem this means there is no separate Secure 937 * address space and both flash devices are generally visible. 938 */ 939 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 940 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 941 942 virt_flash_map1(vms->flash[0], flashbase, flashsize, 943 secure_sysmem); 944 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 945 sysmem); 946 } 947 948 static void virt_flash_fdt(VirtMachineState *vms, 949 MemoryRegion *sysmem, 950 MemoryRegion *secure_sysmem) 951 { 952 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 953 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 954 char *nodename; 955 956 if (sysmem == secure_sysmem) { 957 /* Report both flash devices as a single node in the DT */ 958 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 959 qemu_fdt_add_subnode(vms->fdt, nodename); 960 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 961 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 962 2, flashbase, 2, flashsize, 963 2, flashbase + flashsize, 2, flashsize); 964 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 965 g_free(nodename); 966 } else { 967 /* 968 * Report the devices as separate nodes so we can mark one as 969 * only visible to the secure world. 970 */ 971 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 972 qemu_fdt_add_subnode(vms->fdt, nodename); 973 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 974 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 975 2, flashbase, 2, flashsize); 976 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 977 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 978 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 979 g_free(nodename); 980 981 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 982 qemu_fdt_add_subnode(vms->fdt, nodename); 983 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 984 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 985 2, flashbase + flashsize, 2, flashsize); 986 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 987 g_free(nodename); 988 } 989 } 990 991 static bool virt_firmware_init(VirtMachineState *vms, 992 MemoryRegion *sysmem, 993 MemoryRegion *secure_sysmem) 994 { 995 int i; 996 BlockBackend *pflash_blk0; 997 998 /* Map legacy -drive if=pflash to machine properties */ 999 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1000 pflash_cfi01_legacy_drive(vms->flash[i], 1001 drive_get(IF_PFLASH, 0, i)); 1002 } 1003 1004 virt_flash_map(vms, sysmem, secure_sysmem); 1005 1006 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1007 1008 if (bios_name) { 1009 char *fname; 1010 MemoryRegion *mr; 1011 int image_size; 1012 1013 if (pflash_blk0) { 1014 error_report("The contents of the first flash device may be " 1015 "specified with -bios or with -drive if=pflash... " 1016 "but you cannot use both options at once"); 1017 exit(1); 1018 } 1019 1020 /* Fall back to -bios */ 1021 1022 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1023 if (!fname) { 1024 error_report("Could not find ROM image '%s'", bios_name); 1025 exit(1); 1026 } 1027 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1028 image_size = load_image_mr(fname, mr); 1029 g_free(fname); 1030 if (image_size < 0) { 1031 error_report("Could not load ROM image '%s'", bios_name); 1032 exit(1); 1033 } 1034 } 1035 1036 return pflash_blk0 || bios_name; 1037 } 1038 1039 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1040 { 1041 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1042 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1043 FWCfgState *fw_cfg; 1044 char *nodename; 1045 1046 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1047 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 1048 1049 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1050 qemu_fdt_add_subnode(vms->fdt, nodename); 1051 qemu_fdt_setprop_string(vms->fdt, nodename, 1052 "compatible", "qemu,fw-cfg-mmio"); 1053 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1054 2, base, 2, size); 1055 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1056 g_free(nodename); 1057 return fw_cfg; 1058 } 1059 1060 static void create_pcie_irq_map(const VirtMachineState *vms, 1061 uint32_t gic_phandle, 1062 int first_irq, const char *nodename) 1063 { 1064 int devfn, pin; 1065 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1066 uint32_t *irq_map = full_irq_map; 1067 1068 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1069 for (pin = 0; pin < 4; pin++) { 1070 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1071 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1072 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1073 int i; 1074 1075 uint32_t map[] = { 1076 devfn << 8, 0, 0, /* devfn */ 1077 pin + 1, /* PCI pin */ 1078 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1079 1080 /* Convert map to big endian */ 1081 for (i = 0; i < 10; i++) { 1082 irq_map[i] = cpu_to_be32(map[i]); 1083 } 1084 irq_map += 10; 1085 } 1086 } 1087 1088 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map", 1089 full_irq_map, sizeof(full_irq_map)); 1090 1091 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask", 1092 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 1093 0x7 /* PCI irq */); 1094 } 1095 1096 static void create_smmu(const VirtMachineState *vms, qemu_irq *pic, 1097 PCIBus *bus) 1098 { 1099 char *node; 1100 const char compat[] = "arm,smmu-v3"; 1101 int irq = vms->irqmap[VIRT_SMMU]; 1102 int i; 1103 hwaddr base = vms->memmap[VIRT_SMMU].base; 1104 hwaddr size = vms->memmap[VIRT_SMMU].size; 1105 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1106 DeviceState *dev; 1107 1108 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1109 return; 1110 } 1111 1112 dev = qdev_create(NULL, "arm-smmuv3"); 1113 1114 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", 1115 &error_abort); 1116 qdev_init_nofail(dev); 1117 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1118 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1119 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 1120 } 1121 1122 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1123 qemu_fdt_add_subnode(vms->fdt, node); 1124 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat)); 1125 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size); 1126 1127 qemu_fdt_setprop_cells(vms->fdt, node, "interrupts", 1128 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1129 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1130 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1131 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1132 1133 qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names, 1134 sizeof(irq_names)); 1135 1136 qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle); 1137 qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk"); 1138 qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0); 1139 1140 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1); 1141 1142 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle); 1143 g_free(node); 1144 } 1145 1146 static void create_pcie(VirtMachineState *vms, qemu_irq *pic) 1147 { 1148 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1149 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1150 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1151 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1152 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1153 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1154 hwaddr base_ecam, size_ecam; 1155 hwaddr base = base_mmio; 1156 int nr_pcie_buses; 1157 int irq = vms->irqmap[VIRT_PCIE]; 1158 MemoryRegion *mmio_alias; 1159 MemoryRegion *mmio_reg; 1160 MemoryRegion *ecam_alias; 1161 MemoryRegion *ecam_reg; 1162 DeviceState *dev; 1163 char *nodename; 1164 int i, ecam_id; 1165 PCIHostState *pci; 1166 1167 dev = qdev_create(NULL, TYPE_GPEX_HOST); 1168 qdev_init_nofail(dev); 1169 1170 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1171 base_ecam = vms->memmap[ecam_id].base; 1172 size_ecam = vms->memmap[ecam_id].size; 1173 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1174 /* Map only the first size_ecam bytes of ECAM space */ 1175 ecam_alias = g_new0(MemoryRegion, 1); 1176 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1177 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1178 ecam_reg, 0, size_ecam); 1179 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1180 1181 /* Map the MMIO window into system address space so as to expose 1182 * the section of PCI MMIO space which starts at the same base address 1183 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1184 * the window). 1185 */ 1186 mmio_alias = g_new0(MemoryRegion, 1); 1187 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1188 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1189 mmio_reg, base_mmio, size_mmio); 1190 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1191 1192 if (vms->highmem) { 1193 /* Map high MMIO space */ 1194 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1195 1196 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1197 mmio_reg, base_mmio_high, size_mmio_high); 1198 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1199 high_mmio_alias); 1200 } 1201 1202 /* Map IO port space */ 1203 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1204 1205 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1206 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 1207 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1208 } 1209 1210 pci = PCI_HOST_BRIDGE(dev); 1211 if (pci->bus) { 1212 for (i = 0; i < nb_nics; i++) { 1213 NICInfo *nd = &nd_table[i]; 1214 1215 if (!nd->model) { 1216 nd->model = g_strdup("virtio"); 1217 } 1218 1219 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1220 } 1221 } 1222 1223 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1224 qemu_fdt_add_subnode(vms->fdt, nodename); 1225 qemu_fdt_setprop_string(vms->fdt, nodename, 1226 "compatible", "pci-host-ecam-generic"); 1227 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci"); 1228 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3); 1229 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2); 1230 qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0); 1231 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0, 1232 nr_pcie_buses - 1); 1233 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1234 1235 if (vms->msi_phandle) { 1236 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", 1237 vms->msi_phandle); 1238 } 1239 1240 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1241 2, base_ecam, 2, size_ecam); 1242 1243 if (vms->highmem) { 1244 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1245 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1246 2, base_pio, 2, size_pio, 1247 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1248 2, base_mmio, 2, size_mmio, 1249 1, FDT_PCI_RANGE_MMIO_64BIT, 1250 2, base_mmio_high, 1251 2, base_mmio_high, 2, size_mmio_high); 1252 } else { 1253 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1254 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1255 2, base_pio, 2, size_pio, 1256 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1257 2, base_mmio, 2, size_mmio); 1258 } 1259 1260 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); 1261 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); 1262 1263 if (vms->iommu) { 1264 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt); 1265 1266 create_smmu(vms, pic, pci->bus); 1267 1268 qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map", 1269 0x0, vms->iommu_phandle, 0x0, 0x10000); 1270 } 1271 1272 g_free(nodename); 1273 } 1274 1275 static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic) 1276 { 1277 DeviceState *dev; 1278 SysBusDevice *s; 1279 int i; 1280 MemoryRegion *sysmem = get_system_memory(); 1281 1282 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1283 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1284 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1285 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1286 qdev_init_nofail(dev); 1287 vms->platform_bus_dev = dev; 1288 1289 s = SYS_BUS_DEVICE(dev); 1290 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1291 int irqn = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1292 sysbus_connect_irq(s, i, pic[irqn]); 1293 } 1294 1295 memory_region_add_subregion(sysmem, 1296 vms->memmap[VIRT_PLATFORM_BUS].base, 1297 sysbus_mmio_get_region(s, 0)); 1298 } 1299 1300 static void create_secure_ram(VirtMachineState *vms, 1301 MemoryRegion *secure_sysmem) 1302 { 1303 MemoryRegion *secram = g_new(MemoryRegion, 1); 1304 char *nodename; 1305 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1306 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1307 1308 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1309 &error_fatal); 1310 memory_region_add_subregion(secure_sysmem, base, secram); 1311 1312 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1313 qemu_fdt_add_subnode(vms->fdt, nodename); 1314 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory"); 1315 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size); 1316 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1317 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1318 1319 g_free(nodename); 1320 } 1321 1322 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1323 { 1324 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1325 bootinfo); 1326 1327 *fdt_size = board->fdt_size; 1328 return board->fdt; 1329 } 1330 1331 static void virt_build_smbios(VirtMachineState *vms) 1332 { 1333 MachineClass *mc = MACHINE_GET_CLASS(vms); 1334 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1335 uint8_t *smbios_tables, *smbios_anchor; 1336 size_t smbios_tables_len, smbios_anchor_len; 1337 const char *product = "QEMU Virtual Machine"; 1338 1339 if (kvm_enabled()) { 1340 product = "KVM Virtual Machine"; 1341 } 1342 1343 smbios_set_defaults("QEMU", product, 1344 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1345 true, SMBIOS_ENTRY_POINT_30); 1346 1347 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, 1348 &smbios_anchor, &smbios_anchor_len); 1349 1350 if (smbios_anchor) { 1351 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1352 smbios_tables, smbios_tables_len); 1353 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1354 smbios_anchor, smbios_anchor_len); 1355 } 1356 } 1357 1358 static 1359 void virt_machine_done(Notifier *notifier, void *data) 1360 { 1361 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1362 machine_done); 1363 ARMCPU *cpu = ARM_CPU(first_cpu); 1364 struct arm_boot_info *info = &vms->bootinfo; 1365 AddressSpace *as = arm_boot_address_space(cpu, info); 1366 1367 /* 1368 * If the user provided a dtb, we assume the dynamic sysbus nodes 1369 * already are integrated there. This corresponds to a use case where 1370 * the dynamic sysbus nodes are complex and their generation is not yet 1371 * supported. In that case the user can take charge of the guest dt 1372 * while qemu takes charge of the qom stuff. 1373 */ 1374 if (info->dtb_filename == NULL) { 1375 platform_bus_add_all_fdt_nodes(vms->fdt, "/intc", 1376 vms->memmap[VIRT_PLATFORM_BUS].base, 1377 vms->memmap[VIRT_PLATFORM_BUS].size, 1378 vms->irqmap[VIRT_PLATFORM_BUS]); 1379 } 1380 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) { 1381 exit(1); 1382 } 1383 1384 virt_acpi_setup(vms); 1385 virt_build_smbios(vms); 1386 } 1387 1388 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1389 { 1390 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1391 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1392 1393 if (!vmc->disallow_affinity_adjustment) { 1394 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1395 * GIC's target-list limitations. 32-bit KVM hosts currently 1396 * always create clusters of 4 CPUs, but that is expected to 1397 * change when they gain support for gicv3. When KVM is enabled 1398 * it will override the changes we make here, therefore our 1399 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1400 * and to improve SGI efficiency. 1401 */ 1402 if (vms->gic_version == 3) { 1403 clustersz = GICV3_TARGETLIST_BITS; 1404 } else { 1405 clustersz = GIC_TARGETLIST_BITS; 1406 } 1407 } 1408 return arm_cpu_mp_affinity(idx, clustersz); 1409 } 1410 1411 static void virt_set_memmap(VirtMachineState *vms) 1412 { 1413 MachineState *ms = MACHINE(vms); 1414 hwaddr base, device_memory_base, device_memory_size; 1415 int i; 1416 1417 vms->memmap = extended_memmap; 1418 1419 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1420 vms->memmap[i] = base_memmap[i]; 1421 } 1422 1423 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1424 error_report("unsupported number of memory slots: %"PRIu64, 1425 ms->ram_slots); 1426 exit(EXIT_FAILURE); 1427 } 1428 1429 /* 1430 * We compute the base of the high IO region depending on the 1431 * amount of initial and device memory. The device memory start/size 1432 * is aligned on 1GiB. We never put the high IO region below 256GiB 1433 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1434 * The device region size assumes 1GiB page max alignment per slot. 1435 */ 1436 device_memory_base = 1437 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1438 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1439 1440 /* Base address of the high IO region */ 1441 base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1442 if (base < device_memory_base) { 1443 error_report("maxmem/slots too huge"); 1444 exit(EXIT_FAILURE); 1445 } 1446 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1447 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1448 } 1449 1450 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1451 hwaddr size = extended_memmap[i].size; 1452 1453 base = ROUND_UP(base, size); 1454 vms->memmap[i].base = base; 1455 vms->memmap[i].size = size; 1456 base += size; 1457 } 1458 vms->highest_gpa = base - 1; 1459 if (device_memory_size > 0) { 1460 ms->device_memory = g_malloc0(sizeof(*ms->device_memory)); 1461 ms->device_memory->base = device_memory_base; 1462 memory_region_init(&ms->device_memory->mr, OBJECT(vms), 1463 "device-memory", device_memory_size); 1464 } 1465 } 1466 1467 static void machvirt_init(MachineState *machine) 1468 { 1469 VirtMachineState *vms = VIRT_MACHINE(machine); 1470 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1471 MachineClass *mc = MACHINE_GET_CLASS(machine); 1472 const CPUArchIdList *possible_cpus; 1473 qemu_irq pic[NUM_IRQS]; 1474 MemoryRegion *sysmem = get_system_memory(); 1475 MemoryRegion *secure_sysmem = NULL; 1476 int n, virt_max_cpus; 1477 MemoryRegion *ram = g_new(MemoryRegion, 1); 1478 bool firmware_loaded; 1479 bool aarch64 = true; 1480 1481 /* 1482 * In accelerated mode, the memory map is computed earlier in kvm_type() 1483 * to create a VM with the right number of IPA bits. 1484 */ 1485 if (!vms->memmap) { 1486 virt_set_memmap(vms); 1487 } 1488 1489 /* We can probe only here because during property set 1490 * KVM is not available yet 1491 */ 1492 if (vms->gic_version <= 0) { 1493 /* "host" or "max" */ 1494 if (!kvm_enabled()) { 1495 if (vms->gic_version == 0) { 1496 error_report("gic-version=host requires KVM"); 1497 exit(1); 1498 } else { 1499 /* "max": currently means 3 for TCG */ 1500 vms->gic_version = 3; 1501 } 1502 } else { 1503 vms->gic_version = kvm_arm_vgic_probe(); 1504 if (!vms->gic_version) { 1505 error_report( 1506 "Unable to determine GIC version supported by host"); 1507 exit(1); 1508 } 1509 } 1510 } 1511 1512 if (!cpu_type_valid(machine->cpu_type)) { 1513 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 1514 exit(1); 1515 } 1516 1517 if (vms->secure) { 1518 if (kvm_enabled()) { 1519 error_report("mach-virt: KVM does not support Security extensions"); 1520 exit(1); 1521 } 1522 1523 /* 1524 * The Secure view of the world is the same as the NonSecure, 1525 * but with a few extra devices. Create it as a container region 1526 * containing the system memory at low priority; any secure-only 1527 * devices go in at higher priority and take precedence. 1528 */ 1529 secure_sysmem = g_new(MemoryRegion, 1); 1530 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1531 UINT64_MAX); 1532 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1533 } 1534 1535 firmware_loaded = virt_firmware_init(vms, sysmem, 1536 secure_sysmem ?: sysmem); 1537 1538 /* If we have an EL3 boot ROM then the assumption is that it will 1539 * implement PSCI itself, so disable QEMU's internal implementation 1540 * so it doesn't get in the way. Instead of starting secondary 1541 * CPUs in PSCI powerdown state we will start them all running and 1542 * let the boot ROM sort them out. 1543 * The usual case is that we do use QEMU's PSCI implementation; 1544 * if the guest has EL2 then we will use SMC as the conduit, 1545 * and otherwise we will use HVC (for backwards compatibility and 1546 * because if we're using KVM then we must use HVC). 1547 */ 1548 if (vms->secure && firmware_loaded) { 1549 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1550 } else if (vms->virt) { 1551 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 1552 } else { 1553 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 1554 } 1555 1556 /* The maximum number of CPUs depends on the GIC version, or on how 1557 * many redistributors we can fit into the memory map. 1558 */ 1559 if (vms->gic_version == 3) { 1560 virt_max_cpus = 1561 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 1562 virt_max_cpus += 1563 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; 1564 } else { 1565 virt_max_cpus = GIC_NCPU; 1566 } 1567 1568 if (max_cpus > virt_max_cpus) { 1569 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1570 "supported by machine 'mach-virt' (%d)", 1571 max_cpus, virt_max_cpus); 1572 exit(1); 1573 } 1574 1575 vms->smp_cpus = smp_cpus; 1576 1577 if (vms->virt && kvm_enabled()) { 1578 error_report("mach-virt: KVM does not support providing " 1579 "Virtualization extensions to the guest CPU"); 1580 exit(1); 1581 } 1582 1583 create_fdt(vms); 1584 1585 possible_cpus = mc->possible_cpu_arch_ids(machine); 1586 for (n = 0; n < possible_cpus->len; n++) { 1587 Object *cpuobj; 1588 CPUState *cs; 1589 1590 if (n >= smp_cpus) { 1591 break; 1592 } 1593 1594 cpuobj = object_new(possible_cpus->cpus[n].type); 1595 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 1596 "mp-affinity", NULL); 1597 1598 cs = CPU(cpuobj); 1599 cs->cpu_index = n; 1600 1601 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 1602 &error_fatal); 1603 1604 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 1605 1606 if (!vms->secure) { 1607 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1608 } 1609 1610 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { 1611 object_property_set_bool(cpuobj, false, "has_el2", NULL); 1612 } 1613 1614 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1615 object_property_set_int(cpuobj, vms->psci_conduit, 1616 "psci-conduit", NULL); 1617 1618 /* Secondary CPUs start in PSCI powered-down state */ 1619 if (n > 0) { 1620 object_property_set_bool(cpuobj, true, 1621 "start-powered-off", NULL); 1622 } 1623 } 1624 1625 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { 1626 object_property_set_bool(cpuobj, false, "pmu", NULL); 1627 } 1628 1629 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1630 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, 1631 "reset-cbar", &error_abort); 1632 } 1633 1634 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1635 &error_abort); 1636 if (vms->secure) { 1637 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1638 "secure-memory", &error_abort); 1639 } 1640 1641 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 1642 object_unref(cpuobj); 1643 } 1644 fdt_add_timer_nodes(vms); 1645 fdt_add_cpu_nodes(vms); 1646 1647 if (!kvm_enabled()) { 1648 ARMCPU *cpu = ARM_CPU(first_cpu); 1649 bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL); 1650 1651 if (aarch64 && vms->highmem) { 1652 int requested_pa_size, pamax = arm_pamax(cpu); 1653 1654 requested_pa_size = 64 - clz64(vms->highest_gpa); 1655 if (pamax < requested_pa_size) { 1656 error_report("VCPU supports less PA bits (%d) than requested " 1657 "by the memory map (%d)", pamax, requested_pa_size); 1658 exit(1); 1659 } 1660 } 1661 } 1662 1663 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", 1664 machine->ram_size); 1665 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); 1666 if (machine->device_memory) { 1667 memory_region_add_subregion(sysmem, machine->device_memory->base, 1668 &machine->device_memory->mr); 1669 } 1670 1671 virt_flash_fdt(vms, sysmem, secure_sysmem); 1672 1673 create_gic(vms, pic); 1674 1675 fdt_add_pmu_nodes(vms); 1676 1677 create_uart(vms, pic, VIRT_UART, sysmem, serial_hd(0)); 1678 1679 if (vms->secure) { 1680 create_secure_ram(vms, secure_sysmem); 1681 create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 1682 } 1683 1684 vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64); 1685 1686 create_rtc(vms, pic); 1687 1688 create_pcie(vms, pic); 1689 1690 create_gpio(vms, pic); 1691 1692 /* Create mmio transports, so the user can create virtio backends 1693 * (which will be automatically plugged in to the transports). If 1694 * no backend is created the transport will just sit harmlessly idle. 1695 */ 1696 create_virtio_devices(vms, pic); 1697 1698 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 1699 rom_set_fw(vms->fw_cfg); 1700 1701 create_platform_bus(vms, pic); 1702 1703 vms->bootinfo.ram_size = machine->ram_size; 1704 vms->bootinfo.kernel_filename = machine->kernel_filename; 1705 vms->bootinfo.kernel_cmdline = machine->kernel_cmdline; 1706 vms->bootinfo.initrd_filename = machine->initrd_filename; 1707 vms->bootinfo.nb_cpus = smp_cpus; 1708 vms->bootinfo.board_id = -1; 1709 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 1710 vms->bootinfo.get_dtb = machvirt_dtb; 1711 vms->bootinfo.skip_dtb_autoload = true; 1712 vms->bootinfo.firmware_loaded = firmware_loaded; 1713 arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo); 1714 1715 vms->machine_done.notify = virt_machine_done; 1716 qemu_add_machine_init_done_notifier(&vms->machine_done); 1717 } 1718 1719 static bool virt_get_secure(Object *obj, Error **errp) 1720 { 1721 VirtMachineState *vms = VIRT_MACHINE(obj); 1722 1723 return vms->secure; 1724 } 1725 1726 static void virt_set_secure(Object *obj, bool value, Error **errp) 1727 { 1728 VirtMachineState *vms = VIRT_MACHINE(obj); 1729 1730 vms->secure = value; 1731 } 1732 1733 static bool virt_get_virt(Object *obj, Error **errp) 1734 { 1735 VirtMachineState *vms = VIRT_MACHINE(obj); 1736 1737 return vms->virt; 1738 } 1739 1740 static void virt_set_virt(Object *obj, bool value, Error **errp) 1741 { 1742 VirtMachineState *vms = VIRT_MACHINE(obj); 1743 1744 vms->virt = value; 1745 } 1746 1747 static bool virt_get_highmem(Object *obj, Error **errp) 1748 { 1749 VirtMachineState *vms = VIRT_MACHINE(obj); 1750 1751 return vms->highmem; 1752 } 1753 1754 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1755 { 1756 VirtMachineState *vms = VIRT_MACHINE(obj); 1757 1758 vms->highmem = value; 1759 } 1760 1761 static bool virt_get_its(Object *obj, Error **errp) 1762 { 1763 VirtMachineState *vms = VIRT_MACHINE(obj); 1764 1765 return vms->its; 1766 } 1767 1768 static void virt_set_its(Object *obj, bool value, Error **errp) 1769 { 1770 VirtMachineState *vms = VIRT_MACHINE(obj); 1771 1772 vms->its = value; 1773 } 1774 1775 static char *virt_get_gic_version(Object *obj, Error **errp) 1776 { 1777 VirtMachineState *vms = VIRT_MACHINE(obj); 1778 const char *val = vms->gic_version == 3 ? "3" : "2"; 1779 1780 return g_strdup(val); 1781 } 1782 1783 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 1784 { 1785 VirtMachineState *vms = VIRT_MACHINE(obj); 1786 1787 if (!strcmp(value, "3")) { 1788 vms->gic_version = 3; 1789 } else if (!strcmp(value, "2")) { 1790 vms->gic_version = 2; 1791 } else if (!strcmp(value, "host")) { 1792 vms->gic_version = 0; /* Will probe later */ 1793 } else if (!strcmp(value, "max")) { 1794 vms->gic_version = -1; /* Will probe later */ 1795 } else { 1796 error_setg(errp, "Invalid gic-version value"); 1797 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 1798 } 1799 } 1800 1801 static char *virt_get_iommu(Object *obj, Error **errp) 1802 { 1803 VirtMachineState *vms = VIRT_MACHINE(obj); 1804 1805 switch (vms->iommu) { 1806 case VIRT_IOMMU_NONE: 1807 return g_strdup("none"); 1808 case VIRT_IOMMU_SMMUV3: 1809 return g_strdup("smmuv3"); 1810 default: 1811 g_assert_not_reached(); 1812 } 1813 } 1814 1815 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 1816 { 1817 VirtMachineState *vms = VIRT_MACHINE(obj); 1818 1819 if (!strcmp(value, "smmuv3")) { 1820 vms->iommu = VIRT_IOMMU_SMMUV3; 1821 } else if (!strcmp(value, "none")) { 1822 vms->iommu = VIRT_IOMMU_NONE; 1823 } else { 1824 error_setg(errp, "Invalid iommu value"); 1825 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 1826 } 1827 } 1828 1829 static CpuInstanceProperties 1830 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1831 { 1832 MachineClass *mc = MACHINE_GET_CLASS(ms); 1833 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1834 1835 assert(cpu_index < possible_cpus->len); 1836 return possible_cpus->cpus[cpu_index].props; 1837 } 1838 1839 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1840 { 1841 return idx % nb_numa_nodes; 1842 } 1843 1844 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1845 { 1846 int n; 1847 VirtMachineState *vms = VIRT_MACHINE(ms); 1848 1849 if (ms->possible_cpus) { 1850 assert(ms->possible_cpus->len == max_cpus); 1851 return ms->possible_cpus; 1852 } 1853 1854 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1855 sizeof(CPUArchId) * max_cpus); 1856 ms->possible_cpus->len = max_cpus; 1857 for (n = 0; n < ms->possible_cpus->len; n++) { 1858 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1859 ms->possible_cpus->cpus[n].arch_id = 1860 virt_cpu_mp_affinity(vms, n); 1861 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1862 ms->possible_cpus->cpus[n].props.thread_id = n; 1863 } 1864 return ms->possible_cpus; 1865 } 1866 1867 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1868 DeviceState *dev, Error **errp) 1869 { 1870 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 1871 1872 if (vms->platform_bus_dev) { 1873 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) { 1874 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 1875 SYS_BUS_DEVICE(dev)); 1876 } 1877 } 1878 } 1879 1880 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1881 DeviceState *dev) 1882 { 1883 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) { 1884 return HOTPLUG_HANDLER(machine); 1885 } 1886 1887 return NULL; 1888 } 1889 1890 /* 1891 * for arm64 kvm_type [7-0] encodes the requested number of bits 1892 * in the IPA address space 1893 */ 1894 static int virt_kvm_type(MachineState *ms, const char *type_str) 1895 { 1896 VirtMachineState *vms = VIRT_MACHINE(ms); 1897 int max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms); 1898 int requested_pa_size; 1899 1900 /* we freeze the memory map to compute the highest gpa */ 1901 virt_set_memmap(vms); 1902 1903 requested_pa_size = 64 - clz64(vms->highest_gpa); 1904 1905 if (requested_pa_size > max_vm_pa_size) { 1906 error_report("-m and ,maxmem option values " 1907 "require an IPA range (%d bits) larger than " 1908 "the one supported by the host (%d bits)", 1909 requested_pa_size, max_vm_pa_size); 1910 exit(1); 1911 } 1912 /* 1913 * By default we return 0 which corresponds to an implicit legacy 1914 * 40b IPA setting. Otherwise we return the actual requested PA 1915 * logsize 1916 */ 1917 return requested_pa_size > 40 ? requested_pa_size : 0; 1918 } 1919 1920 static void virt_machine_class_init(ObjectClass *oc, void *data) 1921 { 1922 MachineClass *mc = MACHINE_CLASS(oc); 1923 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1924 1925 mc->init = machvirt_init; 1926 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 1927 * The value may be reduced later when we have more information about the 1928 * configuration of the particular instance. 1929 */ 1930 mc->max_cpus = 512; 1931 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 1932 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 1933 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1934 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 1935 mc->block_default_type = IF_VIRTIO; 1936 mc->no_cdrom = 1; 1937 mc->pci_allow_0_address = true; 1938 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 1939 mc->minimum_page_bits = 12; 1940 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1941 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1942 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 1943 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1944 mc->kvm_type = virt_kvm_type; 1945 assert(!mc->get_hotplug_handler); 1946 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1947 hc->plug = virt_machine_device_plug_cb; 1948 } 1949 1950 static void virt_instance_init(Object *obj) 1951 { 1952 VirtMachineState *vms = VIRT_MACHINE(obj); 1953 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1954 1955 /* EL3 is disabled by default on virt: this makes us consistent 1956 * between KVM and TCG for this board, and it also allows us to 1957 * boot UEFI blobs which assume no TrustZone support. 1958 */ 1959 vms->secure = false; 1960 object_property_add_bool(obj, "secure", virt_get_secure, 1961 virt_set_secure, NULL); 1962 object_property_set_description(obj, "secure", 1963 "Set on/off to enable/disable the ARM " 1964 "Security Extensions (TrustZone)", 1965 NULL); 1966 1967 /* EL2 is also disabled by default, for similar reasons */ 1968 vms->virt = false; 1969 object_property_add_bool(obj, "virtualization", virt_get_virt, 1970 virt_set_virt, NULL); 1971 object_property_set_description(obj, "virtualization", 1972 "Set on/off to enable/disable emulating a " 1973 "guest CPU which implements the ARM " 1974 "Virtualization Extensions", 1975 NULL); 1976 1977 /* High memory is enabled by default */ 1978 vms->highmem = true; 1979 object_property_add_bool(obj, "highmem", virt_get_highmem, 1980 virt_set_highmem, NULL); 1981 object_property_set_description(obj, "highmem", 1982 "Set on/off to enable/disable using " 1983 "physical address space above 32 bits", 1984 NULL); 1985 /* Default GIC type is v2 */ 1986 vms->gic_version = 2; 1987 object_property_add_str(obj, "gic-version", virt_get_gic_version, 1988 virt_set_gic_version, NULL); 1989 object_property_set_description(obj, "gic-version", 1990 "Set GIC version. " 1991 "Valid values are 2, 3 and host", NULL); 1992 1993 vms->highmem_ecam = !vmc->no_highmem_ecam; 1994 1995 if (vmc->no_its) { 1996 vms->its = false; 1997 } else { 1998 /* Default allows ITS instantiation */ 1999 vms->its = true; 2000 object_property_add_bool(obj, "its", virt_get_its, 2001 virt_set_its, NULL); 2002 object_property_set_description(obj, "its", 2003 "Set on/off to enable/disable " 2004 "ITS instantiation", 2005 NULL); 2006 } 2007 2008 /* Default disallows iommu instantiation */ 2009 vms->iommu = VIRT_IOMMU_NONE; 2010 object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu, NULL); 2011 object_property_set_description(obj, "iommu", 2012 "Set the IOMMU type. " 2013 "Valid values are none and smmuv3", 2014 NULL); 2015 2016 vms->irqmap = a15irqmap; 2017 2018 virt_flash_create(vms); 2019 } 2020 2021 static const TypeInfo virt_machine_info = { 2022 .name = TYPE_VIRT_MACHINE, 2023 .parent = TYPE_MACHINE, 2024 .abstract = true, 2025 .instance_size = sizeof(VirtMachineState), 2026 .class_size = sizeof(VirtMachineClass), 2027 .class_init = virt_machine_class_init, 2028 .instance_init = virt_instance_init, 2029 .interfaces = (InterfaceInfo[]) { 2030 { TYPE_HOTPLUG_HANDLER }, 2031 { } 2032 }, 2033 }; 2034 2035 static void machvirt_machine_init(void) 2036 { 2037 type_register_static(&virt_machine_info); 2038 } 2039 type_init(machvirt_machine_init); 2040 2041 static void virt_machine_4_1_options(MachineClass *mc) 2042 { 2043 } 2044 DEFINE_VIRT_MACHINE_AS_LATEST(4, 1) 2045 2046 static void virt_machine_4_0_options(MachineClass *mc) 2047 { 2048 virt_machine_4_1_options(mc); 2049 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 2050 } 2051 DEFINE_VIRT_MACHINE(4, 0) 2052 2053 static void virt_machine_3_1_options(MachineClass *mc) 2054 { 2055 virt_machine_4_0_options(mc); 2056 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 2057 } 2058 DEFINE_VIRT_MACHINE(3, 1) 2059 2060 static void virt_machine_3_0_options(MachineClass *mc) 2061 { 2062 virt_machine_3_1_options(mc); 2063 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 2064 } 2065 DEFINE_VIRT_MACHINE(3, 0) 2066 2067 static void virt_machine_2_12_options(MachineClass *mc) 2068 { 2069 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2070 2071 virt_machine_3_0_options(mc); 2072 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 2073 vmc->no_highmem_ecam = true; 2074 mc->max_cpus = 255; 2075 } 2076 DEFINE_VIRT_MACHINE(2, 12) 2077 2078 static void virt_machine_2_11_options(MachineClass *mc) 2079 { 2080 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2081 2082 virt_machine_2_12_options(mc); 2083 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 2084 vmc->smbios_old_sys_ver = true; 2085 } 2086 DEFINE_VIRT_MACHINE(2, 11) 2087 2088 static void virt_machine_2_10_options(MachineClass *mc) 2089 { 2090 virt_machine_2_11_options(mc); 2091 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 2092 /* before 2.11 we never faulted accesses to bad addresses */ 2093 mc->ignore_memory_transaction_failures = true; 2094 } 2095 DEFINE_VIRT_MACHINE(2, 10) 2096 2097 static void virt_machine_2_9_options(MachineClass *mc) 2098 { 2099 virt_machine_2_10_options(mc); 2100 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 2101 } 2102 DEFINE_VIRT_MACHINE(2, 9) 2103 2104 static void virt_machine_2_8_options(MachineClass *mc) 2105 { 2106 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2107 2108 virt_machine_2_9_options(mc); 2109 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 2110 /* For 2.8 and earlier we falsely claimed in the DT that 2111 * our timers were edge-triggered, not level-triggered. 2112 */ 2113 vmc->claim_edge_triggered_timers = true; 2114 } 2115 DEFINE_VIRT_MACHINE(2, 8) 2116 2117 static void virt_machine_2_7_options(MachineClass *mc) 2118 { 2119 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2120 2121 virt_machine_2_8_options(mc); 2122 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 2123 /* ITS was introduced with 2.8 */ 2124 vmc->no_its = true; 2125 /* Stick with 1K pages for migration compatibility */ 2126 mc->minimum_page_bits = 0; 2127 } 2128 DEFINE_VIRT_MACHINE(2, 7) 2129 2130 static void virt_machine_2_6_options(MachineClass *mc) 2131 { 2132 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2133 2134 virt_machine_2_7_options(mc); 2135 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 2136 vmc->disallow_affinity_adjustment = true; 2137 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 2138 vmc->no_pmu = true; 2139 } 2140 DEFINE_VIRT_MACHINE(2, 6) 2141