1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qapi/error.h" 33 #include "hw/sysbus.h" 34 #include "hw/arm/arm.h" 35 #include "hw/arm/primecell.h" 36 #include "hw/arm/virt.h" 37 #include "hw/devices.h" 38 #include "net/net.h" 39 #include "sysemu/block-backend.h" 40 #include "sysemu/device_tree.h" 41 #include "sysemu/numa.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/kvm.h" 44 #include "hw/compat.h" 45 #include "hw/loader.h" 46 #include "exec/address-spaces.h" 47 #include "qemu/bitops.h" 48 #include "qemu/error-report.h" 49 #include "hw/pci-host/gpex.h" 50 #include "hw/arm/sysbus-fdt.h" 51 #include "hw/platform-bus.h" 52 #include "hw/arm/fdt.h" 53 #include "hw/intc/arm_gic.h" 54 #include "hw/intc/arm_gicv3_common.h" 55 #include "kvm_arm.h" 56 #include "hw/smbios/smbios.h" 57 #include "qapi/visitor.h" 58 #include "standard-headers/linux/input.h" 59 60 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 61 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 62 void *data) \ 63 { \ 64 MachineClass *mc = MACHINE_CLASS(oc); \ 65 virt_machine_##major##_##minor##_options(mc); \ 66 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 67 if (latest) { \ 68 mc->alias = "virt"; \ 69 } \ 70 } \ 71 static const TypeInfo machvirt_##major##_##minor##_info = { \ 72 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 73 .parent = TYPE_VIRT_MACHINE, \ 74 .instance_init = virt_##major##_##minor##_instance_init, \ 75 .class_init = virt_##major##_##minor##_class_init, \ 76 }; \ 77 static void machvirt_machine_##major##_##minor##_init(void) \ 78 { \ 79 type_register_static(&machvirt_##major##_##minor##_info); \ 80 } \ 81 type_init(machvirt_machine_##major##_##minor##_init); 82 83 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 84 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 85 #define DEFINE_VIRT_MACHINE(major, minor) \ 86 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 87 88 89 /* Number of external interrupt lines to configure the GIC with */ 90 #define NUM_IRQS 256 91 92 #define PLATFORM_BUS_NUM_IRQS 64 93 94 static ARMPlatformBusSystemParams platform_bus_params; 95 96 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means 97 * RAM can go up to the 256GB mark, leaving 256GB of the physical 98 * address space unallocated and free for future use between 256G and 512G. 99 * If we need to provide more RAM to VMs in the future then we need to: 100 * * allocate a second bank of RAM starting at 2TB and working up 101 * * fix the DT and ACPI table generation code in QEMU to correctly 102 * report two split lumps of RAM to the guest 103 * * fix KVM in the host kernel to allow guests with >40 bit address spaces 104 * (We don't want to fill all the way up to 512GB with RAM because 105 * we might want it for non-RAM purposes later. Conversely it seems 106 * reasonable to assume that anybody configuring a VM with a quarter 107 * of a terabyte of RAM will be doing it on a host with more than a 108 * terabyte of physical address space.) 109 */ 110 #define RAMLIMIT_GB 255 111 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) 112 113 /* Addresses and sizes of our components. 114 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 115 * 128MB..256MB is used for miscellaneous device I/O. 116 * 256MB..1GB is reserved for possible future PCI support (ie where the 117 * PCI memory window will go if we add a PCI host controller). 118 * 1GB and up is RAM (which may happily spill over into the 119 * high memory region beyond 4GB). 120 * This represents a compromise between how much RAM can be given to 121 * a 32 bit VM and leaving space for expansion and in particular for PCI. 122 * Note that devices should generally be placed at multiples of 0x10000, 123 * to accommodate guests using 64K pages. 124 */ 125 static const MemMapEntry a15memmap[] = { 126 /* Space up to 0x8000000 is reserved for a boot ROM */ 127 [VIRT_FLASH] = { 0, 0x08000000 }, 128 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 129 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 130 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 131 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 132 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 133 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 134 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 135 /* This redistributor space allows up to 2*64kB*123 CPUs */ 136 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 137 [VIRT_UART] = { 0x09000000, 0x00001000 }, 138 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 139 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 140 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 141 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 142 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 143 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 144 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 145 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 146 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 147 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 148 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 149 [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES }, 150 /* Second PCIe window, 512GB wide at the 512GB boundary */ 151 [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL }, 152 }; 153 154 static const int a15irqmap[] = { 155 [VIRT_UART] = 1, 156 [VIRT_RTC] = 2, 157 [VIRT_PCIE] = 3, /* ... to 6 */ 158 [VIRT_GPIO] = 7, 159 [VIRT_SECURE_UART] = 8, 160 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 161 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 162 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 163 }; 164 165 static const char *valid_cpus[] = { 166 "cortex-a15", 167 "cortex-a53", 168 "cortex-a57", 169 "host", 170 }; 171 172 static bool cpuname_valid(const char *cpu) 173 { 174 int i; 175 176 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 177 if (strcmp(cpu, valid_cpus[i]) == 0) { 178 return true; 179 } 180 } 181 return false; 182 } 183 184 static void create_fdt(VirtMachineState *vms) 185 { 186 void *fdt = create_device_tree(&vms->fdt_size); 187 188 if (!fdt) { 189 error_report("create_device_tree() failed"); 190 exit(1); 191 } 192 193 vms->fdt = fdt; 194 195 /* Header */ 196 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 197 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 198 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 199 200 /* 201 * /chosen and /memory nodes must exist for load_dtb 202 * to fill in necessary properties later 203 */ 204 qemu_fdt_add_subnode(fdt, "/chosen"); 205 qemu_fdt_add_subnode(fdt, "/memory"); 206 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 207 208 /* Clock node, for the benefit of the UART. The kernel device tree 209 * binding documentation claims the PL011 node clock properties are 210 * optional but in practice if you omit them the kernel refuses to 211 * probe for the device. 212 */ 213 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 214 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 215 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 216 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 217 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 218 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 219 "clk24mhz"); 220 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 221 222 } 223 224 static void fdt_add_psci_node(const VirtMachineState *vms) 225 { 226 uint32_t cpu_suspend_fn; 227 uint32_t cpu_off_fn; 228 uint32_t cpu_on_fn; 229 uint32_t migrate_fn; 230 void *fdt = vms->fdt; 231 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 232 const char *psci_method; 233 234 switch (vms->psci_conduit) { 235 case QEMU_PSCI_CONDUIT_DISABLED: 236 return; 237 case QEMU_PSCI_CONDUIT_HVC: 238 psci_method = "hvc"; 239 break; 240 case QEMU_PSCI_CONDUIT_SMC: 241 psci_method = "smc"; 242 break; 243 default: 244 g_assert_not_reached(); 245 } 246 247 qemu_fdt_add_subnode(fdt, "/psci"); 248 if (armcpu->psci_version == 2) { 249 const char comp[] = "arm,psci-0.2\0arm,psci"; 250 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 251 252 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 253 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 254 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 255 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 256 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 257 } else { 258 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 259 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 260 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 261 } 262 } else { 263 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 264 265 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 266 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 267 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 268 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 269 } 270 271 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 272 * to the instruction that should be used to invoke PSCI functions. 273 * However, the device tree binding uses 'method' instead, so that is 274 * what we should use here. 275 */ 276 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 277 278 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 279 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 280 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 281 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 282 } 283 284 static void fdt_add_timer_nodes(const VirtMachineState *vms) 285 { 286 /* On real hardware these interrupts are level-triggered. 287 * On KVM they were edge-triggered before host kernel version 4.4, 288 * and level-triggered afterwards. 289 * On emulated QEMU they are level-triggered. 290 * 291 * Getting the DTB info about them wrong is awkward for some 292 * guest kernels: 293 * pre-4.8 ignore the DT and leave the interrupt configured 294 * with whatever the GIC reset value (or the bootloader) left it at 295 * 4.8 before rc6 honour the incorrect data by programming it back 296 * into the GIC, causing problems 297 * 4.8rc6 and later ignore the DT and always write "level triggered" 298 * into the GIC 299 * 300 * For backwards-compatibility, virt-2.8 and earlier will continue 301 * to say these are edge-triggered, but later machines will report 302 * the correct information. 303 */ 304 ARMCPU *armcpu; 305 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 306 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 307 308 if (vmc->claim_edge_triggered_timers) { 309 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 310 } 311 312 if (vms->gic_version == 2) { 313 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 314 GIC_FDT_IRQ_PPI_CPU_WIDTH, 315 (1 << vms->smp_cpus) - 1); 316 } 317 318 qemu_fdt_add_subnode(vms->fdt, "/timer"); 319 320 armcpu = ARM_CPU(qemu_get_cpu(0)); 321 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 322 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 323 qemu_fdt_setprop(vms->fdt, "/timer", "compatible", 324 compat, sizeof(compat)); 325 } else { 326 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible", 327 "arm,armv7-timer"); 328 } 329 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0); 330 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts", 331 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 332 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 333 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 334 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 335 } 336 337 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 338 { 339 int cpu; 340 int addr_cells = 1; 341 unsigned int i; 342 343 /* 344 * From Documentation/devicetree/bindings/arm/cpus.txt 345 * On ARM v8 64-bit systems value should be set to 2, 346 * that corresponds to the MPIDR_EL1 register size. 347 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 348 * in the system, #address-cells can be set to 1, since 349 * MPIDR_EL1[63:32] bits are not used for CPUs 350 * identification. 351 * 352 * Here we actually don't know whether our system is 32- or 64-bit one. 353 * The simplest way to go is to examine affinity IDs of all our CPUs. If 354 * at least one of them has Aff3 populated, we set #address-cells to 2. 355 */ 356 for (cpu = 0; cpu < vms->smp_cpus; cpu++) { 357 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 358 359 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 360 addr_cells = 2; 361 break; 362 } 363 } 364 365 qemu_fdt_add_subnode(vms->fdt, "/cpus"); 366 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); 367 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); 368 369 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { 370 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 371 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 372 373 qemu_fdt_add_subnode(vms->fdt, nodename); 374 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); 375 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 376 armcpu->dtb_compatible); 377 378 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED 379 && vms->smp_cpus > 1) { 380 qemu_fdt_setprop_string(vms->fdt, nodename, 381 "enable-method", "psci"); 382 } 383 384 if (addr_cells == 2) { 385 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", 386 armcpu->mp_affinity); 387 } else { 388 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", 389 armcpu->mp_affinity); 390 } 391 392 i = numa_get_node_for_cpu(cpu); 393 if (i < nb_numa_nodes) { 394 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", i); 395 } 396 397 g_free(nodename); 398 } 399 } 400 401 static void fdt_add_its_gic_node(VirtMachineState *vms) 402 { 403 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 404 qemu_fdt_add_subnode(vms->fdt, "/intc/its"); 405 qemu_fdt_setprop_string(vms->fdt, "/intc/its", "compatible", 406 "arm,gic-v3-its"); 407 qemu_fdt_setprop(vms->fdt, "/intc/its", "msi-controller", NULL, 0); 408 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/its", "reg", 409 2, vms->memmap[VIRT_GIC_ITS].base, 410 2, vms->memmap[VIRT_GIC_ITS].size); 411 qemu_fdt_setprop_cell(vms->fdt, "/intc/its", "phandle", vms->msi_phandle); 412 } 413 414 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 415 { 416 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 417 qemu_fdt_add_subnode(vms->fdt, "/intc/v2m"); 418 qemu_fdt_setprop_string(vms->fdt, "/intc/v2m", "compatible", 419 "arm,gic-v2m-frame"); 420 qemu_fdt_setprop(vms->fdt, "/intc/v2m", "msi-controller", NULL, 0); 421 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/v2m", "reg", 422 2, vms->memmap[VIRT_GIC_V2M].base, 423 2, vms->memmap[VIRT_GIC_V2M].size); 424 qemu_fdt_setprop_cell(vms->fdt, "/intc/v2m", "phandle", vms->msi_phandle); 425 } 426 427 static void fdt_add_gic_node(VirtMachineState *vms) 428 { 429 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt); 430 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle); 431 432 qemu_fdt_add_subnode(vms->fdt, "/intc"); 433 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#interrupt-cells", 3); 434 qemu_fdt_setprop(vms->fdt, "/intc", "interrupt-controller", NULL, 0); 435 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#address-cells", 0x2); 436 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#size-cells", 0x2); 437 qemu_fdt_setprop(vms->fdt, "/intc", "ranges", NULL, 0); 438 if (vms->gic_version == 3) { 439 qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", 440 "arm,gic-v3"); 441 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", 442 2, vms->memmap[VIRT_GIC_DIST].base, 443 2, vms->memmap[VIRT_GIC_DIST].size, 444 2, vms->memmap[VIRT_GIC_REDIST].base, 445 2, vms->memmap[VIRT_GIC_REDIST].size); 446 if (vms->virt) { 447 qemu_fdt_setprop_cells(vms->fdt, "/intc", "interrupts", 448 GIC_FDT_IRQ_TYPE_PPI, ARCH_GICV3_MAINT_IRQ, 449 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 450 } 451 } else { 452 /* 'cortex-a15-gic' means 'GIC v2' */ 453 qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", 454 "arm,cortex-a15-gic"); 455 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", 456 2, vms->memmap[VIRT_GIC_DIST].base, 457 2, vms->memmap[VIRT_GIC_DIST].size, 458 2, vms->memmap[VIRT_GIC_CPU].base, 459 2, vms->memmap[VIRT_GIC_CPU].size); 460 } 461 462 qemu_fdt_setprop_cell(vms->fdt, "/intc", "phandle", vms->gic_phandle); 463 } 464 465 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 466 { 467 CPUState *cpu; 468 ARMCPU *armcpu; 469 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 470 471 CPU_FOREACH(cpu) { 472 armcpu = ARM_CPU(cpu); 473 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU) || 474 !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ))) { 475 return; 476 } 477 } 478 479 if (vms->gic_version == 2) { 480 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 481 GIC_FDT_IRQ_PPI_CPU_WIDTH, 482 (1 << vms->smp_cpus) - 1); 483 } 484 485 armcpu = ARM_CPU(qemu_get_cpu(0)); 486 qemu_fdt_add_subnode(vms->fdt, "/pmu"); 487 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 488 const char compat[] = "arm,armv8-pmuv3"; 489 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible", 490 compat, sizeof(compat)); 491 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts", 492 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 493 } 494 } 495 496 static void create_its(VirtMachineState *vms, DeviceState *gicdev) 497 { 498 const char *itsclass = its_class_name(); 499 DeviceState *dev; 500 501 if (!itsclass) { 502 /* Do nothing if not supported */ 503 return; 504 } 505 506 dev = qdev_create(NULL, itsclass); 507 508 object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3", 509 &error_abort); 510 qdev_init_nofail(dev); 511 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 512 513 fdt_add_its_gic_node(vms); 514 } 515 516 static void create_v2m(VirtMachineState *vms, qemu_irq *pic) 517 { 518 int i; 519 int irq = vms->irqmap[VIRT_GIC_V2M]; 520 DeviceState *dev; 521 522 dev = qdev_create(NULL, "arm-gicv2m"); 523 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 524 qdev_prop_set_uint32(dev, "base-spi", irq); 525 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 526 qdev_init_nofail(dev); 527 528 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 529 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 530 } 531 532 fdt_add_v2m_gic_node(vms); 533 } 534 535 static void create_gic(VirtMachineState *vms, qemu_irq *pic) 536 { 537 /* We create a standalone GIC */ 538 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 539 DeviceState *gicdev; 540 SysBusDevice *gicbusdev; 541 const char *gictype; 542 int type = vms->gic_version, i; 543 544 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 545 546 gicdev = qdev_create(NULL, gictype); 547 qdev_prop_set_uint32(gicdev, "revision", type); 548 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 549 /* Note that the num-irq property counts both internal and external 550 * interrupts; there are always 32 of the former (mandated by GIC spec). 551 */ 552 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 553 if (!kvm_irqchip_in_kernel()) { 554 qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure); 555 } 556 qdev_init_nofail(gicdev); 557 gicbusdev = SYS_BUS_DEVICE(gicdev); 558 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 559 if (type == 3) { 560 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 561 } else { 562 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 563 } 564 565 /* Wire the outputs from each CPU's generic timer and the GICv3 566 * maintenance interrupt signal to the appropriate GIC PPI inputs, 567 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 568 */ 569 for (i = 0; i < smp_cpus; i++) { 570 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 571 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 572 int irq; 573 /* Mapping from the output timer irq lines from the CPU to the 574 * GIC PPI inputs we use for the virt board. 575 */ 576 const int timer_irq[] = { 577 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 578 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 579 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 580 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 581 }; 582 583 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 584 qdev_connect_gpio_out(cpudev, irq, 585 qdev_get_gpio_in(gicdev, 586 ppibase + timer_irq[irq])); 587 } 588 589 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 590 qdev_get_gpio_in(gicdev, ppibase 591 + ARCH_GICV3_MAINT_IRQ)); 592 593 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 594 sysbus_connect_irq(gicbusdev, i + smp_cpus, 595 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 596 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 597 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 598 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 599 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 600 } 601 602 for (i = 0; i < NUM_IRQS; i++) { 603 pic[i] = qdev_get_gpio_in(gicdev, i); 604 } 605 606 fdt_add_gic_node(vms); 607 608 if (type == 3 && !vmc->no_its) { 609 create_its(vms, gicdev); 610 } else if (type == 2) { 611 create_v2m(vms, pic); 612 } 613 } 614 615 static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart, 616 MemoryRegion *mem, CharDriverState *chr) 617 { 618 char *nodename; 619 hwaddr base = vms->memmap[uart].base; 620 hwaddr size = vms->memmap[uart].size; 621 int irq = vms->irqmap[uart]; 622 const char compat[] = "arm,pl011\0arm,primecell"; 623 const char clocknames[] = "uartclk\0apb_pclk"; 624 DeviceState *dev = qdev_create(NULL, "pl011"); 625 SysBusDevice *s = SYS_BUS_DEVICE(dev); 626 627 qdev_prop_set_chr(dev, "chardev", chr); 628 qdev_init_nofail(dev); 629 memory_region_add_subregion(mem, base, 630 sysbus_mmio_get_region(s, 0)); 631 sysbus_connect_irq(s, 0, pic[irq]); 632 633 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 634 qemu_fdt_add_subnode(vms->fdt, nodename); 635 /* Note that we can't use setprop_string because of the embedded NUL */ 636 qemu_fdt_setprop(vms->fdt, nodename, "compatible", 637 compat, sizeof(compat)); 638 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 639 2, base, 2, size); 640 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 641 GIC_FDT_IRQ_TYPE_SPI, irq, 642 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 643 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks", 644 vms->clock_phandle, vms->clock_phandle); 645 qemu_fdt_setprop(vms->fdt, nodename, "clock-names", 646 clocknames, sizeof(clocknames)); 647 648 if (uart == VIRT_UART) { 649 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); 650 } else { 651 /* Mark as not usable by the normal world */ 652 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 653 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 654 } 655 656 g_free(nodename); 657 } 658 659 static void create_rtc(const VirtMachineState *vms, qemu_irq *pic) 660 { 661 char *nodename; 662 hwaddr base = vms->memmap[VIRT_RTC].base; 663 hwaddr size = vms->memmap[VIRT_RTC].size; 664 int irq = vms->irqmap[VIRT_RTC]; 665 const char compat[] = "arm,pl031\0arm,primecell"; 666 667 sysbus_create_simple("pl031", base, pic[irq]); 668 669 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 670 qemu_fdt_add_subnode(vms->fdt, nodename); 671 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 672 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 673 2, base, 2, size); 674 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 675 GIC_FDT_IRQ_TYPE_SPI, irq, 676 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 677 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 678 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 679 g_free(nodename); 680 } 681 682 static DeviceState *gpio_key_dev; 683 static void virt_powerdown_req(Notifier *n, void *opaque) 684 { 685 /* use gpio Pin 3 for power button event */ 686 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 687 } 688 689 static Notifier virt_system_powerdown_notifier = { 690 .notify = virt_powerdown_req 691 }; 692 693 static void create_gpio(const VirtMachineState *vms, qemu_irq *pic) 694 { 695 char *nodename; 696 DeviceState *pl061_dev; 697 hwaddr base = vms->memmap[VIRT_GPIO].base; 698 hwaddr size = vms->memmap[VIRT_GPIO].size; 699 int irq = vms->irqmap[VIRT_GPIO]; 700 const char compat[] = "arm,pl061\0arm,primecell"; 701 702 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); 703 704 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); 705 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 706 qemu_fdt_add_subnode(vms->fdt, nodename); 707 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 708 2, base, 2, size); 709 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 710 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); 711 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); 712 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 713 GIC_FDT_IRQ_TYPE_SPI, irq, 714 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 715 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 716 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 717 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); 718 719 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 720 qdev_get_gpio_in(pl061_dev, 3)); 721 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); 722 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); 723 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); 724 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); 725 726 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); 727 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", 728 "label", "GPIO Key Poweroff"); 729 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", 730 KEY_POWER); 731 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", 732 "gpios", phandle, 3, 0); 733 734 /* connect powerdown request */ 735 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier); 736 737 g_free(nodename); 738 } 739 740 static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic) 741 { 742 int i; 743 hwaddr size = vms->memmap[VIRT_MMIO].size; 744 745 /* We create the transports in forwards order. Since qbus_realize() 746 * prepends (not appends) new child buses, the incrementing loop below will 747 * create a list of virtio-mmio buses with decreasing base addresses. 748 * 749 * When a -device option is processed from the command line, 750 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 751 * order. The upshot is that -device options in increasing command line 752 * order are mapped to virtio-mmio buses with decreasing base addresses. 753 * 754 * When this code was originally written, that arrangement ensured that the 755 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 756 * the first -device on the command line. (The end-to-end order is a 757 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 758 * guest kernel's name-to-address assignment strategy.) 759 * 760 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 761 * the message, if not necessarily the code, of commit 70161ff336. 762 * Therefore the loop now establishes the inverse of the original intent. 763 * 764 * Unfortunately, we can't counteract the kernel change by reversing the 765 * loop; it would break existing command lines. 766 * 767 * In any case, the kernel makes no guarantee about the stability of 768 * enumeration order of virtio devices (as demonstrated by it changing 769 * between kernel versions). For reliable and stable identification 770 * of disks users must use UUIDs or similar mechanisms. 771 */ 772 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 773 int irq = vms->irqmap[VIRT_MMIO] + i; 774 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 775 776 sysbus_create_simple("virtio-mmio", base, pic[irq]); 777 } 778 779 /* We add dtb nodes in reverse order so that they appear in the finished 780 * device tree lowest address first. 781 * 782 * Note that this mapping is independent of the loop above. The previous 783 * loop influences virtio device to virtio transport assignment, whereas 784 * this loop controls how virtio transports are laid out in the dtb. 785 */ 786 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 787 char *nodename; 788 int irq = vms->irqmap[VIRT_MMIO] + i; 789 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 790 791 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 792 qemu_fdt_add_subnode(vms->fdt, nodename); 793 qemu_fdt_setprop_string(vms->fdt, nodename, 794 "compatible", "virtio,mmio"); 795 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 796 2, base, 2, size); 797 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 798 GIC_FDT_IRQ_TYPE_SPI, irq, 799 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 800 g_free(nodename); 801 } 802 } 803 804 static void create_one_flash(const char *name, hwaddr flashbase, 805 hwaddr flashsize, const char *file, 806 MemoryRegion *sysmem) 807 { 808 /* Create and map a single flash device. We use the same 809 * parameters as the flash devices on the Versatile Express board. 810 */ 811 DriveInfo *dinfo = drive_get_next(IF_PFLASH); 812 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 813 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 814 const uint64_t sectorlength = 256 * 1024; 815 816 if (dinfo) { 817 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 818 &error_abort); 819 } 820 821 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); 822 qdev_prop_set_uint64(dev, "sector-length", sectorlength); 823 qdev_prop_set_uint8(dev, "width", 4); 824 qdev_prop_set_uint8(dev, "device-width", 2); 825 qdev_prop_set_bit(dev, "big-endian", false); 826 qdev_prop_set_uint16(dev, "id0", 0x89); 827 qdev_prop_set_uint16(dev, "id1", 0x18); 828 qdev_prop_set_uint16(dev, "id2", 0x00); 829 qdev_prop_set_uint16(dev, "id3", 0x00); 830 qdev_prop_set_string(dev, "name", name); 831 qdev_init_nofail(dev); 832 833 memory_region_add_subregion(sysmem, flashbase, 834 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 835 836 if (file) { 837 char *fn; 838 int image_size; 839 840 if (drive_get(IF_PFLASH, 0, 0)) { 841 error_report("The contents of the first flash device may be " 842 "specified with -bios or with -drive if=pflash... " 843 "but you cannot use both options at once"); 844 exit(1); 845 } 846 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file); 847 if (!fn) { 848 error_report("Could not find ROM image '%s'", file); 849 exit(1); 850 } 851 image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0)); 852 g_free(fn); 853 if (image_size < 0) { 854 error_report("Could not load ROM image '%s'", file); 855 exit(1); 856 } 857 } 858 } 859 860 static void create_flash(const VirtMachineState *vms, 861 MemoryRegion *sysmem, 862 MemoryRegion *secure_sysmem) 863 { 864 /* Create two flash devices to fill the VIRT_FLASH space in the memmap. 865 * Any file passed via -bios goes in the first of these. 866 * sysmem is the system memory space. secure_sysmem is the secure view 867 * of the system, and the first flash device should be made visible only 868 * there. The second flash device is visible to both secure and nonsecure. 869 * If sysmem == secure_sysmem this means there is no separate Secure 870 * address space and both flash devices are generally visible. 871 */ 872 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 873 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 874 char *nodename; 875 876 create_one_flash("virt.flash0", flashbase, flashsize, 877 bios_name, secure_sysmem); 878 create_one_flash("virt.flash1", flashbase + flashsize, flashsize, 879 NULL, sysmem); 880 881 if (sysmem == secure_sysmem) { 882 /* Report both flash devices as a single node in the DT */ 883 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 884 qemu_fdt_add_subnode(vms->fdt, nodename); 885 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 886 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 887 2, flashbase, 2, flashsize, 888 2, flashbase + flashsize, 2, flashsize); 889 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 890 g_free(nodename); 891 } else { 892 /* Report the devices as separate nodes so we can mark one as 893 * only visible to the secure world. 894 */ 895 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 896 qemu_fdt_add_subnode(vms->fdt, nodename); 897 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 898 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 899 2, flashbase, 2, flashsize); 900 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 901 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 902 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 903 g_free(nodename); 904 905 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 906 qemu_fdt_add_subnode(vms->fdt, nodename); 907 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 908 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 909 2, flashbase + flashsize, 2, flashsize); 910 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 911 g_free(nodename); 912 } 913 } 914 915 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 916 { 917 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 918 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 919 FWCfgState *fw_cfg; 920 char *nodename; 921 922 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 923 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 924 925 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 926 qemu_fdt_add_subnode(vms->fdt, nodename); 927 qemu_fdt_setprop_string(vms->fdt, nodename, 928 "compatible", "qemu,fw-cfg-mmio"); 929 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 930 2, base, 2, size); 931 g_free(nodename); 932 return fw_cfg; 933 } 934 935 static void create_pcie_irq_map(const VirtMachineState *vms, 936 uint32_t gic_phandle, 937 int first_irq, const char *nodename) 938 { 939 int devfn, pin; 940 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 941 uint32_t *irq_map = full_irq_map; 942 943 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 944 for (pin = 0; pin < 4; pin++) { 945 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 946 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 947 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 948 int i; 949 950 uint32_t map[] = { 951 devfn << 8, 0, 0, /* devfn */ 952 pin + 1, /* PCI pin */ 953 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 954 955 /* Convert map to big endian */ 956 for (i = 0; i < 10; i++) { 957 irq_map[i] = cpu_to_be32(map[i]); 958 } 959 irq_map += 10; 960 } 961 } 962 963 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map", 964 full_irq_map, sizeof(full_irq_map)); 965 966 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask", 967 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 968 0x7 /* PCI irq */); 969 } 970 971 static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) 972 { 973 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 974 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 975 hwaddr base_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].base; 976 hwaddr size_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].size; 977 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 978 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 979 hwaddr base_ecam = vms->memmap[VIRT_PCIE_ECAM].base; 980 hwaddr size_ecam = vms->memmap[VIRT_PCIE_ECAM].size; 981 hwaddr base = base_mmio; 982 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 983 int irq = vms->irqmap[VIRT_PCIE]; 984 MemoryRegion *mmio_alias; 985 MemoryRegion *mmio_reg; 986 MemoryRegion *ecam_alias; 987 MemoryRegion *ecam_reg; 988 DeviceState *dev; 989 char *nodename; 990 int i; 991 PCIHostState *pci; 992 993 dev = qdev_create(NULL, TYPE_GPEX_HOST); 994 qdev_init_nofail(dev); 995 996 /* Map only the first size_ecam bytes of ECAM space */ 997 ecam_alias = g_new0(MemoryRegion, 1); 998 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 999 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1000 ecam_reg, 0, size_ecam); 1001 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1002 1003 /* Map the MMIO window into system address space so as to expose 1004 * the section of PCI MMIO space which starts at the same base address 1005 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1006 * the window). 1007 */ 1008 mmio_alias = g_new0(MemoryRegion, 1); 1009 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1010 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1011 mmio_reg, base_mmio, size_mmio); 1012 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1013 1014 if (vms->highmem) { 1015 /* Map high MMIO space */ 1016 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1017 1018 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1019 mmio_reg, base_mmio_high, size_mmio_high); 1020 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1021 high_mmio_alias); 1022 } 1023 1024 /* Map IO port space */ 1025 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1026 1027 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1028 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 1029 } 1030 1031 pci = PCI_HOST_BRIDGE(dev); 1032 if (pci->bus) { 1033 for (i = 0; i < nb_nics; i++) { 1034 NICInfo *nd = &nd_table[i]; 1035 1036 if (!nd->model) { 1037 nd->model = g_strdup("virtio"); 1038 } 1039 1040 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1041 } 1042 } 1043 1044 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1045 qemu_fdt_add_subnode(vms->fdt, nodename); 1046 qemu_fdt_setprop_string(vms->fdt, nodename, 1047 "compatible", "pci-host-ecam-generic"); 1048 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci"); 1049 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3); 1050 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2); 1051 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0, 1052 nr_pcie_buses - 1); 1053 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1054 1055 if (vms->msi_phandle) { 1056 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", 1057 vms->msi_phandle); 1058 } 1059 1060 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1061 2, base_ecam, 2, size_ecam); 1062 1063 if (vms->highmem) { 1064 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1065 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1066 2, base_pio, 2, size_pio, 1067 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1068 2, base_mmio, 2, size_mmio, 1069 1, FDT_PCI_RANGE_MMIO_64BIT, 1070 2, base_mmio_high, 1071 2, base_mmio_high, 2, size_mmio_high); 1072 } else { 1073 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1074 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1075 2, base_pio, 2, size_pio, 1076 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1077 2, base_mmio, 2, size_mmio); 1078 } 1079 1080 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); 1081 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); 1082 1083 g_free(nodename); 1084 } 1085 1086 static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic) 1087 { 1088 DeviceState *dev; 1089 SysBusDevice *s; 1090 int i; 1091 ARMPlatformBusFDTParams *fdt_params = g_new(ARMPlatformBusFDTParams, 1); 1092 MemoryRegion *sysmem = get_system_memory(); 1093 1094 platform_bus_params.platform_bus_base = vms->memmap[VIRT_PLATFORM_BUS].base; 1095 platform_bus_params.platform_bus_size = vms->memmap[VIRT_PLATFORM_BUS].size; 1096 platform_bus_params.platform_bus_first_irq = vms->irqmap[VIRT_PLATFORM_BUS]; 1097 platform_bus_params.platform_bus_num_irqs = PLATFORM_BUS_NUM_IRQS; 1098 1099 fdt_params->system_params = &platform_bus_params; 1100 fdt_params->binfo = &vms->bootinfo; 1101 fdt_params->intc = "/intc"; 1102 /* 1103 * register a machine init done notifier that creates the device tree 1104 * nodes of the platform bus and its children dynamic sysbus devices 1105 */ 1106 arm_register_platform_bus_fdt_creator(fdt_params); 1107 1108 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1109 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1110 qdev_prop_set_uint32(dev, "num_irqs", 1111 platform_bus_params.platform_bus_num_irqs); 1112 qdev_prop_set_uint32(dev, "mmio_size", 1113 platform_bus_params.platform_bus_size); 1114 qdev_init_nofail(dev); 1115 s = SYS_BUS_DEVICE(dev); 1116 1117 for (i = 0; i < platform_bus_params.platform_bus_num_irqs; i++) { 1118 int irqn = platform_bus_params.platform_bus_first_irq + i; 1119 sysbus_connect_irq(s, i, pic[irqn]); 1120 } 1121 1122 memory_region_add_subregion(sysmem, 1123 platform_bus_params.platform_bus_base, 1124 sysbus_mmio_get_region(s, 0)); 1125 } 1126 1127 static void create_secure_ram(VirtMachineState *vms, 1128 MemoryRegion *secure_sysmem) 1129 { 1130 MemoryRegion *secram = g_new(MemoryRegion, 1); 1131 char *nodename; 1132 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1133 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1134 1135 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, &error_fatal); 1136 vmstate_register_ram_global(secram); 1137 memory_region_add_subregion(secure_sysmem, base, secram); 1138 1139 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1140 qemu_fdt_add_subnode(vms->fdt, nodename); 1141 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory"); 1142 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size); 1143 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1144 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1145 1146 g_free(nodename); 1147 } 1148 1149 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1150 { 1151 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1152 bootinfo); 1153 1154 *fdt_size = board->fdt_size; 1155 return board->fdt; 1156 } 1157 1158 static void virt_build_smbios(VirtMachineState *vms) 1159 { 1160 uint8_t *smbios_tables, *smbios_anchor; 1161 size_t smbios_tables_len, smbios_anchor_len; 1162 const char *product = "QEMU Virtual Machine"; 1163 1164 if (!vms->fw_cfg) { 1165 return; 1166 } 1167 1168 if (kvm_enabled()) { 1169 product = "KVM Virtual Machine"; 1170 } 1171 1172 smbios_set_defaults("QEMU", product, 1173 "1.0", false, true, SMBIOS_ENTRY_POINT_30); 1174 1175 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, 1176 &smbios_anchor, &smbios_anchor_len); 1177 1178 if (smbios_anchor) { 1179 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1180 smbios_tables, smbios_tables_len); 1181 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1182 smbios_anchor, smbios_anchor_len); 1183 } 1184 } 1185 1186 static 1187 void virt_machine_done(Notifier *notifier, void *data) 1188 { 1189 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1190 machine_done); 1191 1192 virt_acpi_setup(vms); 1193 virt_build_smbios(vms); 1194 } 1195 1196 static void machvirt_init(MachineState *machine) 1197 { 1198 VirtMachineState *vms = VIRT_MACHINE(machine); 1199 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1200 qemu_irq pic[NUM_IRQS]; 1201 MemoryRegion *sysmem = get_system_memory(); 1202 MemoryRegion *secure_sysmem = NULL; 1203 int n, virt_max_cpus; 1204 MemoryRegion *ram = g_new(MemoryRegion, 1); 1205 const char *cpu_model = machine->cpu_model; 1206 char **cpustr; 1207 ObjectClass *oc; 1208 const char *typename; 1209 CPUClass *cc; 1210 Error *err = NULL; 1211 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); 1212 uint8_t clustersz; 1213 1214 if (!cpu_model) { 1215 cpu_model = "cortex-a15"; 1216 } 1217 1218 /* We can probe only here because during property set 1219 * KVM is not available yet 1220 */ 1221 if (!vms->gic_version) { 1222 if (!kvm_enabled()) { 1223 error_report("gic-version=host requires KVM"); 1224 exit(1); 1225 } 1226 1227 vms->gic_version = kvm_arm_vgic_probe(); 1228 if (!vms->gic_version) { 1229 error_report("Unable to determine GIC version supported by host"); 1230 exit(1); 1231 } 1232 } 1233 1234 /* Separate the actual CPU model name from any appended features */ 1235 cpustr = g_strsplit(cpu_model, ",", 2); 1236 1237 if (!cpuname_valid(cpustr[0])) { 1238 error_report("mach-virt: CPU %s not supported", cpustr[0]); 1239 exit(1); 1240 } 1241 1242 /* If we have an EL3 boot ROM then the assumption is that it will 1243 * implement PSCI itself, so disable QEMU's internal implementation 1244 * so it doesn't get in the way. Instead of starting secondary 1245 * CPUs in PSCI powerdown state we will start them all running and 1246 * let the boot ROM sort them out. 1247 * The usual case is that we do use QEMU's PSCI implementation; 1248 * if the guest has EL2 then we will use SMC as the conduit, 1249 * and otherwise we will use HVC (for backwards compatibility and 1250 * because if we're using KVM then we must use HVC). 1251 */ 1252 if (vms->secure && firmware_loaded) { 1253 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1254 } else if (vms->virt) { 1255 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 1256 } else { 1257 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 1258 } 1259 1260 /* The maximum number of CPUs depends on the GIC version, or on how 1261 * many redistributors we can fit into the memory map. 1262 */ 1263 if (vms->gic_version == 3) { 1264 virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / 0x20000; 1265 clustersz = GICV3_TARGETLIST_BITS; 1266 } else { 1267 virt_max_cpus = GIC_NCPU; 1268 clustersz = GIC_TARGETLIST_BITS; 1269 } 1270 1271 if (max_cpus > virt_max_cpus) { 1272 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1273 "supported by machine 'mach-virt' (%d)", 1274 max_cpus, virt_max_cpus); 1275 exit(1); 1276 } 1277 1278 vms->smp_cpus = smp_cpus; 1279 1280 if (machine->ram_size > vms->memmap[VIRT_MEM].size) { 1281 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB); 1282 exit(1); 1283 } 1284 1285 if (vms->virt && kvm_enabled()) { 1286 error_report("mach-virt: KVM does not support providing " 1287 "Virtualization extensions to the guest CPU"); 1288 exit(1); 1289 } 1290 1291 if (vms->secure) { 1292 if (kvm_enabled()) { 1293 error_report("mach-virt: KVM does not support Security extensions"); 1294 exit(1); 1295 } 1296 1297 /* The Secure view of the world is the same as the NonSecure, 1298 * but with a few extra devices. Create it as a container region 1299 * containing the system memory at low priority; any secure-only 1300 * devices go in at higher priority and take precedence. 1301 */ 1302 secure_sysmem = g_new(MemoryRegion, 1); 1303 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1304 UINT64_MAX); 1305 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1306 } 1307 1308 create_fdt(vms); 1309 1310 oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); 1311 if (!oc) { 1312 error_report("Unable to find CPU definition"); 1313 exit(1); 1314 } 1315 typename = object_class_get_name(oc); 1316 1317 /* convert -smp CPU options specified by the user into global props */ 1318 cc = CPU_CLASS(oc); 1319 cc->parse_features(typename, cpustr[1], &err); 1320 g_strfreev(cpustr); 1321 if (err) { 1322 error_report_err(err); 1323 exit(1); 1324 } 1325 1326 for (n = 0; n < smp_cpus; n++) { 1327 Object *cpuobj = object_new(typename); 1328 if (!vmc->disallow_affinity_adjustment) { 1329 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1330 * GIC's target-list limitations. 32-bit KVM hosts currently 1331 * always create clusters of 4 CPUs, but that is expected to 1332 * change when they gain support for gicv3. When KVM is enabled 1333 * it will override the changes we make here, therefore our 1334 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1335 * and to improve SGI efficiency. 1336 */ 1337 uint8_t aff1 = n / clustersz; 1338 uint8_t aff0 = n % clustersz; 1339 object_property_set_int(cpuobj, (aff1 << ARM_AFF1_SHIFT) | aff0, 1340 "mp-affinity", NULL); 1341 } 1342 1343 if (!vms->secure) { 1344 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1345 } 1346 1347 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { 1348 object_property_set_bool(cpuobj, false, "has_el2", NULL); 1349 } 1350 1351 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1352 object_property_set_int(cpuobj, vms->psci_conduit, 1353 "psci-conduit", NULL); 1354 1355 /* Secondary CPUs start in PSCI powered-down state */ 1356 if (n > 0) { 1357 object_property_set_bool(cpuobj, true, 1358 "start-powered-off", NULL); 1359 } 1360 } 1361 1362 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { 1363 object_property_set_bool(cpuobj, false, "pmu", NULL); 1364 } 1365 1366 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1367 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, 1368 "reset-cbar", &error_abort); 1369 } 1370 1371 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1372 &error_abort); 1373 if (vms->secure) { 1374 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1375 "secure-memory", &error_abort); 1376 } 1377 1378 object_property_set_bool(cpuobj, true, "realized", NULL); 1379 } 1380 fdt_add_timer_nodes(vms); 1381 fdt_add_cpu_nodes(vms); 1382 fdt_add_psci_node(vms); 1383 1384 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", 1385 machine->ram_size); 1386 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); 1387 1388 create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem); 1389 1390 create_gic(vms, pic); 1391 1392 fdt_add_pmu_nodes(vms); 1393 1394 create_uart(vms, pic, VIRT_UART, sysmem, serial_hds[0]); 1395 1396 if (vms->secure) { 1397 create_secure_ram(vms, secure_sysmem); 1398 create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hds[1]); 1399 } 1400 1401 create_rtc(vms, pic); 1402 1403 create_pcie(vms, pic); 1404 1405 create_gpio(vms, pic); 1406 1407 /* Create mmio transports, so the user can create virtio backends 1408 * (which will be automatically plugged in to the transports). If 1409 * no backend is created the transport will just sit harmlessly idle. 1410 */ 1411 create_virtio_devices(vms, pic); 1412 1413 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 1414 rom_set_fw(vms->fw_cfg); 1415 1416 vms->machine_done.notify = virt_machine_done; 1417 qemu_add_machine_init_done_notifier(&vms->machine_done); 1418 1419 vms->bootinfo.ram_size = machine->ram_size; 1420 vms->bootinfo.kernel_filename = machine->kernel_filename; 1421 vms->bootinfo.kernel_cmdline = machine->kernel_cmdline; 1422 vms->bootinfo.initrd_filename = machine->initrd_filename; 1423 vms->bootinfo.nb_cpus = smp_cpus; 1424 vms->bootinfo.board_id = -1; 1425 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 1426 vms->bootinfo.get_dtb = machvirt_dtb; 1427 vms->bootinfo.firmware_loaded = firmware_loaded; 1428 arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo); 1429 1430 /* 1431 * arm_load_kernel machine init done notifier registration must 1432 * happen before the platform_bus_create call. In this latter, 1433 * another notifier is registered which adds platform bus nodes. 1434 * Notifiers are executed in registration reverse order. 1435 */ 1436 create_platform_bus(vms, pic); 1437 } 1438 1439 static bool virt_get_secure(Object *obj, Error **errp) 1440 { 1441 VirtMachineState *vms = VIRT_MACHINE(obj); 1442 1443 return vms->secure; 1444 } 1445 1446 static void virt_set_secure(Object *obj, bool value, Error **errp) 1447 { 1448 VirtMachineState *vms = VIRT_MACHINE(obj); 1449 1450 vms->secure = value; 1451 } 1452 1453 static bool virt_get_virt(Object *obj, Error **errp) 1454 { 1455 VirtMachineState *vms = VIRT_MACHINE(obj); 1456 1457 return vms->virt; 1458 } 1459 1460 static void virt_set_virt(Object *obj, bool value, Error **errp) 1461 { 1462 VirtMachineState *vms = VIRT_MACHINE(obj); 1463 1464 vms->virt = value; 1465 } 1466 1467 static bool virt_get_highmem(Object *obj, Error **errp) 1468 { 1469 VirtMachineState *vms = VIRT_MACHINE(obj); 1470 1471 return vms->highmem; 1472 } 1473 1474 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1475 { 1476 VirtMachineState *vms = VIRT_MACHINE(obj); 1477 1478 vms->highmem = value; 1479 } 1480 1481 static char *virt_get_gic_version(Object *obj, Error **errp) 1482 { 1483 VirtMachineState *vms = VIRT_MACHINE(obj); 1484 const char *val = vms->gic_version == 3 ? "3" : "2"; 1485 1486 return g_strdup(val); 1487 } 1488 1489 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 1490 { 1491 VirtMachineState *vms = VIRT_MACHINE(obj); 1492 1493 if (!strcmp(value, "3")) { 1494 vms->gic_version = 3; 1495 } else if (!strcmp(value, "2")) { 1496 vms->gic_version = 2; 1497 } else if (!strcmp(value, "host")) { 1498 vms->gic_version = 0; /* Will probe later */ 1499 } else { 1500 error_setg(errp, "Invalid gic-version value"); 1501 error_append_hint(errp, "Valid values are 3, 2, host.\n"); 1502 } 1503 } 1504 1505 static void virt_machine_class_init(ObjectClass *oc, void *data) 1506 { 1507 MachineClass *mc = MACHINE_CLASS(oc); 1508 1509 mc->init = machvirt_init; 1510 /* Start max_cpus at the maximum QEMU supports. We'll further restrict 1511 * it later in machvirt_init, where we have more information about the 1512 * configuration of the particular instance. 1513 */ 1514 mc->max_cpus = 255; 1515 mc->has_dynamic_sysbus = true; 1516 mc->block_default_type = IF_VIRTIO; 1517 mc->no_cdrom = 1; 1518 mc->pci_allow_0_address = true; 1519 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 1520 mc->minimum_page_bits = 12; 1521 } 1522 1523 static const TypeInfo virt_machine_info = { 1524 .name = TYPE_VIRT_MACHINE, 1525 .parent = TYPE_MACHINE, 1526 .abstract = true, 1527 .instance_size = sizeof(VirtMachineState), 1528 .class_size = sizeof(VirtMachineClass), 1529 .class_init = virt_machine_class_init, 1530 }; 1531 1532 static void machvirt_machine_init(void) 1533 { 1534 type_register_static(&virt_machine_info); 1535 } 1536 type_init(machvirt_machine_init); 1537 1538 static void virt_2_9_instance_init(Object *obj) 1539 { 1540 VirtMachineState *vms = VIRT_MACHINE(obj); 1541 1542 /* EL3 is disabled by default on virt: this makes us consistent 1543 * between KVM and TCG for this board, and it also allows us to 1544 * boot UEFI blobs which assume no TrustZone support. 1545 */ 1546 vms->secure = false; 1547 object_property_add_bool(obj, "secure", virt_get_secure, 1548 virt_set_secure, NULL); 1549 object_property_set_description(obj, "secure", 1550 "Set on/off to enable/disable the ARM " 1551 "Security Extensions (TrustZone)", 1552 NULL); 1553 1554 /* EL2 is also disabled by default, for similar reasons */ 1555 vms->virt = false; 1556 object_property_add_bool(obj, "virtualization", virt_get_virt, 1557 virt_set_virt, NULL); 1558 object_property_set_description(obj, "virtualization", 1559 "Set on/off to enable/disable emulating a " 1560 "guest CPU which implements the ARM " 1561 "Virtualization Extensions", 1562 NULL); 1563 1564 /* High memory is enabled by default */ 1565 vms->highmem = true; 1566 object_property_add_bool(obj, "highmem", virt_get_highmem, 1567 virt_set_highmem, NULL); 1568 object_property_set_description(obj, "highmem", 1569 "Set on/off to enable/disable using " 1570 "physical address space above 32 bits", 1571 NULL); 1572 /* Default GIC type is v2 */ 1573 vms->gic_version = 2; 1574 object_property_add_str(obj, "gic-version", virt_get_gic_version, 1575 virt_set_gic_version, NULL); 1576 object_property_set_description(obj, "gic-version", 1577 "Set GIC version. " 1578 "Valid values are 2, 3 and host", NULL); 1579 1580 vms->memmap = a15memmap; 1581 vms->irqmap = a15irqmap; 1582 } 1583 1584 static void virt_machine_2_9_options(MachineClass *mc) 1585 { 1586 } 1587 DEFINE_VIRT_MACHINE_AS_LATEST(2, 9) 1588 1589 #define VIRT_COMPAT_2_8 \ 1590 HW_COMPAT_2_8 1591 1592 static void virt_2_8_instance_init(Object *obj) 1593 { 1594 virt_2_9_instance_init(obj); 1595 } 1596 1597 static void virt_machine_2_8_options(MachineClass *mc) 1598 { 1599 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1600 1601 virt_machine_2_9_options(mc); 1602 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_8); 1603 /* For 2.8 and earlier we falsely claimed in the DT that 1604 * our timers were edge-triggered, not level-triggered. 1605 */ 1606 vmc->claim_edge_triggered_timers = true; 1607 } 1608 DEFINE_VIRT_MACHINE(2, 8) 1609 1610 #define VIRT_COMPAT_2_7 \ 1611 HW_COMPAT_2_7 1612 1613 static void virt_2_7_instance_init(Object *obj) 1614 { 1615 virt_2_8_instance_init(obj); 1616 } 1617 1618 static void virt_machine_2_7_options(MachineClass *mc) 1619 { 1620 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1621 1622 virt_machine_2_8_options(mc); 1623 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_7); 1624 /* ITS was introduced with 2.8 */ 1625 vmc->no_its = true; 1626 /* Stick with 1K pages for migration compatibility */ 1627 mc->minimum_page_bits = 0; 1628 } 1629 DEFINE_VIRT_MACHINE(2, 7) 1630 1631 #define VIRT_COMPAT_2_6 \ 1632 HW_COMPAT_2_6 1633 1634 static void virt_2_6_instance_init(Object *obj) 1635 { 1636 virt_2_7_instance_init(obj); 1637 } 1638 1639 static void virt_machine_2_6_options(MachineClass *mc) 1640 { 1641 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1642 1643 virt_machine_2_7_options(mc); 1644 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6); 1645 vmc->disallow_affinity_adjustment = true; 1646 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 1647 vmc->no_pmu = true; 1648 } 1649 DEFINE_VIRT_MACHINE(2, 6) 1650