1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qapi/error.h" 33 #include "hw/sysbus.h" 34 #include "hw/arm/arm.h" 35 #include "hw/arm/primecell.h" 36 #include "hw/arm/virt.h" 37 #include "hw/devices.h" 38 #include "net/net.h" 39 #include "sysemu/block-backend.h" 40 #include "sysemu/device_tree.h" 41 #include "sysemu/numa.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/kvm.h" 44 #include "hw/compat.h" 45 #include "hw/loader.h" 46 #include "exec/address-spaces.h" 47 #include "qemu/bitops.h" 48 #include "qemu/error-report.h" 49 #include "hw/pci-host/gpex.h" 50 #include "hw/arm/sysbus-fdt.h" 51 #include "hw/platform-bus.h" 52 #include "hw/arm/fdt.h" 53 #include "hw/intc/arm_gic.h" 54 #include "hw/intc/arm_gicv3_common.h" 55 #include "kvm_arm.h" 56 #include "hw/smbios/smbios.h" 57 #include "qapi/visitor.h" 58 #include "standard-headers/linux/input.h" 59 60 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 61 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 62 void *data) \ 63 { \ 64 MachineClass *mc = MACHINE_CLASS(oc); \ 65 virt_machine_##major##_##minor##_options(mc); \ 66 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 67 if (latest) { \ 68 mc->alias = "virt"; \ 69 } \ 70 } \ 71 static const TypeInfo machvirt_##major##_##minor##_info = { \ 72 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 73 .parent = TYPE_VIRT_MACHINE, \ 74 .instance_init = virt_##major##_##minor##_instance_init, \ 75 .class_init = virt_##major##_##minor##_class_init, \ 76 }; \ 77 static void machvirt_machine_##major##_##minor##_init(void) \ 78 { \ 79 type_register_static(&machvirt_##major##_##minor##_info); \ 80 } \ 81 type_init(machvirt_machine_##major##_##minor##_init); 82 83 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 84 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 85 #define DEFINE_VIRT_MACHINE(major, minor) \ 86 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 87 88 89 /* Number of external interrupt lines to configure the GIC with */ 90 #define NUM_IRQS 256 91 92 #define PLATFORM_BUS_NUM_IRQS 64 93 94 static ARMPlatformBusSystemParams platform_bus_params; 95 96 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means 97 * RAM can go up to the 256GB mark, leaving 256GB of the physical 98 * address space unallocated and free for future use between 256G and 512G. 99 * If we need to provide more RAM to VMs in the future then we need to: 100 * * allocate a second bank of RAM starting at 2TB and working up 101 * * fix the DT and ACPI table generation code in QEMU to correctly 102 * report two split lumps of RAM to the guest 103 * * fix KVM in the host kernel to allow guests with >40 bit address spaces 104 * (We don't want to fill all the way up to 512GB with RAM because 105 * we might want it for non-RAM purposes later. Conversely it seems 106 * reasonable to assume that anybody configuring a VM with a quarter 107 * of a terabyte of RAM will be doing it on a host with more than a 108 * terabyte of physical address space.) 109 */ 110 #define RAMLIMIT_GB 255 111 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) 112 113 /* Addresses and sizes of our components. 114 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 115 * 128MB..256MB is used for miscellaneous device I/O. 116 * 256MB..1GB is reserved for possible future PCI support (ie where the 117 * PCI memory window will go if we add a PCI host controller). 118 * 1GB and up is RAM (which may happily spill over into the 119 * high memory region beyond 4GB). 120 * This represents a compromise between how much RAM can be given to 121 * a 32 bit VM and leaving space for expansion and in particular for PCI. 122 * Note that devices should generally be placed at multiples of 0x10000, 123 * to accommodate guests using 64K pages. 124 */ 125 static const MemMapEntry a15memmap[] = { 126 /* Space up to 0x8000000 is reserved for a boot ROM */ 127 [VIRT_FLASH] = { 0, 0x08000000 }, 128 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 129 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 130 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 131 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 132 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 133 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 134 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 135 /* This redistributor space allows up to 2*64kB*123 CPUs */ 136 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 137 [VIRT_UART] = { 0x09000000, 0x00001000 }, 138 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 139 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 140 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 141 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 142 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 143 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 144 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 145 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 146 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 147 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 148 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 149 [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES }, 150 /* Second PCIe window, 512GB wide at the 512GB boundary */ 151 [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL }, 152 }; 153 154 static const int a15irqmap[] = { 155 [VIRT_UART] = 1, 156 [VIRT_RTC] = 2, 157 [VIRT_PCIE] = 3, /* ... to 6 */ 158 [VIRT_GPIO] = 7, 159 [VIRT_SECURE_UART] = 8, 160 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 161 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 162 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 163 }; 164 165 static const char *valid_cpus[] = { 166 "cortex-a15", 167 "cortex-a53", 168 "cortex-a57", 169 "host", 170 }; 171 172 static bool cpuname_valid(const char *cpu) 173 { 174 int i; 175 176 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 177 if (strcmp(cpu, valid_cpus[i]) == 0) { 178 return true; 179 } 180 } 181 return false; 182 } 183 184 static void create_fdt(VirtMachineState *vms) 185 { 186 void *fdt = create_device_tree(&vms->fdt_size); 187 188 if (!fdt) { 189 error_report("create_device_tree() failed"); 190 exit(1); 191 } 192 193 vms->fdt = fdt; 194 195 /* Header */ 196 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 197 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 198 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 199 200 /* 201 * /chosen and /memory nodes must exist for load_dtb 202 * to fill in necessary properties later 203 */ 204 qemu_fdt_add_subnode(fdt, "/chosen"); 205 qemu_fdt_add_subnode(fdt, "/memory"); 206 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 207 208 /* Clock node, for the benefit of the UART. The kernel device tree 209 * binding documentation claims the PL011 node clock properties are 210 * optional but in practice if you omit them the kernel refuses to 211 * probe for the device. 212 */ 213 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 214 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 215 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 216 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 217 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 218 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 219 "clk24mhz"); 220 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 221 222 if (have_numa_distance) { 223 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 224 uint32_t *matrix = g_malloc0(size); 225 int idx, i, j; 226 227 for (i = 0; i < nb_numa_nodes; i++) { 228 for (j = 0; j < nb_numa_nodes; j++) { 229 idx = (i * nb_numa_nodes + j) * 3; 230 matrix[idx + 0] = cpu_to_be32(i); 231 matrix[idx + 1] = cpu_to_be32(j); 232 matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]); 233 } 234 } 235 236 qemu_fdt_add_subnode(fdt, "/distance-map"); 237 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 238 "numa-distance-map-v1"); 239 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 240 matrix, size); 241 g_free(matrix); 242 } 243 } 244 245 static void fdt_add_psci_node(const VirtMachineState *vms) 246 { 247 uint32_t cpu_suspend_fn; 248 uint32_t cpu_off_fn; 249 uint32_t cpu_on_fn; 250 uint32_t migrate_fn; 251 void *fdt = vms->fdt; 252 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 253 const char *psci_method; 254 255 switch (vms->psci_conduit) { 256 case QEMU_PSCI_CONDUIT_DISABLED: 257 return; 258 case QEMU_PSCI_CONDUIT_HVC: 259 psci_method = "hvc"; 260 break; 261 case QEMU_PSCI_CONDUIT_SMC: 262 psci_method = "smc"; 263 break; 264 default: 265 g_assert_not_reached(); 266 } 267 268 qemu_fdt_add_subnode(fdt, "/psci"); 269 if (armcpu->psci_version == 2) { 270 const char comp[] = "arm,psci-0.2\0arm,psci"; 271 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 272 273 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 274 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 275 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 276 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 277 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 278 } else { 279 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 280 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 281 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 282 } 283 } else { 284 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 285 286 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 287 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 288 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 289 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 290 } 291 292 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 293 * to the instruction that should be used to invoke PSCI functions. 294 * However, the device tree binding uses 'method' instead, so that is 295 * what we should use here. 296 */ 297 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 298 299 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 300 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 301 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 302 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 303 } 304 305 static void fdt_add_timer_nodes(const VirtMachineState *vms) 306 { 307 /* On real hardware these interrupts are level-triggered. 308 * On KVM they were edge-triggered before host kernel version 4.4, 309 * and level-triggered afterwards. 310 * On emulated QEMU they are level-triggered. 311 * 312 * Getting the DTB info about them wrong is awkward for some 313 * guest kernels: 314 * pre-4.8 ignore the DT and leave the interrupt configured 315 * with whatever the GIC reset value (or the bootloader) left it at 316 * 4.8 before rc6 honour the incorrect data by programming it back 317 * into the GIC, causing problems 318 * 4.8rc6 and later ignore the DT and always write "level triggered" 319 * into the GIC 320 * 321 * For backwards-compatibility, virt-2.8 and earlier will continue 322 * to say these are edge-triggered, but later machines will report 323 * the correct information. 324 */ 325 ARMCPU *armcpu; 326 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 327 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 328 329 if (vmc->claim_edge_triggered_timers) { 330 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 331 } 332 333 if (vms->gic_version == 2) { 334 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 335 GIC_FDT_IRQ_PPI_CPU_WIDTH, 336 (1 << vms->smp_cpus) - 1); 337 } 338 339 qemu_fdt_add_subnode(vms->fdt, "/timer"); 340 341 armcpu = ARM_CPU(qemu_get_cpu(0)); 342 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 343 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 344 qemu_fdt_setprop(vms->fdt, "/timer", "compatible", 345 compat, sizeof(compat)); 346 } else { 347 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible", 348 "arm,armv7-timer"); 349 } 350 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0); 351 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts", 352 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 353 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 354 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 355 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 356 } 357 358 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 359 { 360 int cpu; 361 int addr_cells = 1; 362 const MachineState *ms = MACHINE(vms); 363 364 /* 365 * From Documentation/devicetree/bindings/arm/cpus.txt 366 * On ARM v8 64-bit systems value should be set to 2, 367 * that corresponds to the MPIDR_EL1 register size. 368 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 369 * in the system, #address-cells can be set to 1, since 370 * MPIDR_EL1[63:32] bits are not used for CPUs 371 * identification. 372 * 373 * Here we actually don't know whether our system is 32- or 64-bit one. 374 * The simplest way to go is to examine affinity IDs of all our CPUs. If 375 * at least one of them has Aff3 populated, we set #address-cells to 2. 376 */ 377 for (cpu = 0; cpu < vms->smp_cpus; cpu++) { 378 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 379 380 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 381 addr_cells = 2; 382 break; 383 } 384 } 385 386 qemu_fdt_add_subnode(vms->fdt, "/cpus"); 387 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); 388 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); 389 390 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { 391 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 392 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 393 CPUState *cs = CPU(armcpu); 394 395 qemu_fdt_add_subnode(vms->fdt, nodename); 396 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); 397 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 398 armcpu->dtb_compatible); 399 400 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED 401 && vms->smp_cpus > 1) { 402 qemu_fdt_setprop_string(vms->fdt, nodename, 403 "enable-method", "psci"); 404 } 405 406 if (addr_cells == 2) { 407 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", 408 armcpu->mp_affinity); 409 } else { 410 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", 411 armcpu->mp_affinity); 412 } 413 414 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 415 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", 416 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 417 } 418 419 g_free(nodename); 420 } 421 } 422 423 static void fdt_add_its_gic_node(VirtMachineState *vms) 424 { 425 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 426 qemu_fdt_add_subnode(vms->fdt, "/intc/its"); 427 qemu_fdt_setprop_string(vms->fdt, "/intc/its", "compatible", 428 "arm,gic-v3-its"); 429 qemu_fdt_setprop(vms->fdt, "/intc/its", "msi-controller", NULL, 0); 430 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/its", "reg", 431 2, vms->memmap[VIRT_GIC_ITS].base, 432 2, vms->memmap[VIRT_GIC_ITS].size); 433 qemu_fdt_setprop_cell(vms->fdt, "/intc/its", "phandle", vms->msi_phandle); 434 } 435 436 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 437 { 438 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 439 qemu_fdt_add_subnode(vms->fdt, "/intc/v2m"); 440 qemu_fdt_setprop_string(vms->fdt, "/intc/v2m", "compatible", 441 "arm,gic-v2m-frame"); 442 qemu_fdt_setprop(vms->fdt, "/intc/v2m", "msi-controller", NULL, 0); 443 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/v2m", "reg", 444 2, vms->memmap[VIRT_GIC_V2M].base, 445 2, vms->memmap[VIRT_GIC_V2M].size); 446 qemu_fdt_setprop_cell(vms->fdt, "/intc/v2m", "phandle", vms->msi_phandle); 447 } 448 449 static void fdt_add_gic_node(VirtMachineState *vms) 450 { 451 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt); 452 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle); 453 454 qemu_fdt_add_subnode(vms->fdt, "/intc"); 455 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#interrupt-cells", 3); 456 qemu_fdt_setprop(vms->fdt, "/intc", "interrupt-controller", NULL, 0); 457 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#address-cells", 0x2); 458 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#size-cells", 0x2); 459 qemu_fdt_setprop(vms->fdt, "/intc", "ranges", NULL, 0); 460 if (vms->gic_version == 3) { 461 qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", 462 "arm,gic-v3"); 463 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", 464 2, vms->memmap[VIRT_GIC_DIST].base, 465 2, vms->memmap[VIRT_GIC_DIST].size, 466 2, vms->memmap[VIRT_GIC_REDIST].base, 467 2, vms->memmap[VIRT_GIC_REDIST].size); 468 if (vms->virt) { 469 qemu_fdt_setprop_cells(vms->fdt, "/intc", "interrupts", 470 GIC_FDT_IRQ_TYPE_PPI, ARCH_GICV3_MAINT_IRQ, 471 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 472 } 473 } else { 474 /* 'cortex-a15-gic' means 'GIC v2' */ 475 qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", 476 "arm,cortex-a15-gic"); 477 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", 478 2, vms->memmap[VIRT_GIC_DIST].base, 479 2, vms->memmap[VIRT_GIC_DIST].size, 480 2, vms->memmap[VIRT_GIC_CPU].base, 481 2, vms->memmap[VIRT_GIC_CPU].size); 482 } 483 484 qemu_fdt_setprop_cell(vms->fdt, "/intc", "phandle", vms->gic_phandle); 485 } 486 487 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 488 { 489 CPUState *cpu; 490 ARMCPU *armcpu; 491 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 492 493 CPU_FOREACH(cpu) { 494 armcpu = ARM_CPU(cpu); 495 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU) || 496 (kvm_enabled() && !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ)))) { 497 return; 498 } 499 } 500 501 if (vms->gic_version == 2) { 502 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 503 GIC_FDT_IRQ_PPI_CPU_WIDTH, 504 (1 << vms->smp_cpus) - 1); 505 } 506 507 armcpu = ARM_CPU(qemu_get_cpu(0)); 508 qemu_fdt_add_subnode(vms->fdt, "/pmu"); 509 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 510 const char compat[] = "arm,armv8-pmuv3"; 511 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible", 512 compat, sizeof(compat)); 513 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts", 514 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 515 } 516 } 517 518 static void create_its(VirtMachineState *vms, DeviceState *gicdev) 519 { 520 const char *itsclass = its_class_name(); 521 DeviceState *dev; 522 523 if (!itsclass) { 524 /* Do nothing if not supported */ 525 return; 526 } 527 528 dev = qdev_create(NULL, itsclass); 529 530 object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3", 531 &error_abort); 532 qdev_init_nofail(dev); 533 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 534 535 fdt_add_its_gic_node(vms); 536 } 537 538 static void create_v2m(VirtMachineState *vms, qemu_irq *pic) 539 { 540 int i; 541 int irq = vms->irqmap[VIRT_GIC_V2M]; 542 DeviceState *dev; 543 544 dev = qdev_create(NULL, "arm-gicv2m"); 545 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 546 qdev_prop_set_uint32(dev, "base-spi", irq); 547 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 548 qdev_init_nofail(dev); 549 550 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 551 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 552 } 553 554 fdt_add_v2m_gic_node(vms); 555 } 556 557 static void create_gic(VirtMachineState *vms, qemu_irq *pic) 558 { 559 /* We create a standalone GIC */ 560 DeviceState *gicdev; 561 SysBusDevice *gicbusdev; 562 const char *gictype; 563 int type = vms->gic_version, i; 564 565 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 566 567 gicdev = qdev_create(NULL, gictype); 568 qdev_prop_set_uint32(gicdev, "revision", type); 569 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 570 /* Note that the num-irq property counts both internal and external 571 * interrupts; there are always 32 of the former (mandated by GIC spec). 572 */ 573 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 574 if (!kvm_irqchip_in_kernel()) { 575 qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure); 576 } 577 qdev_init_nofail(gicdev); 578 gicbusdev = SYS_BUS_DEVICE(gicdev); 579 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 580 if (type == 3) { 581 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 582 } else { 583 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 584 } 585 586 /* Wire the outputs from each CPU's generic timer and the GICv3 587 * maintenance interrupt signal to the appropriate GIC PPI inputs, 588 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 589 */ 590 for (i = 0; i < smp_cpus; i++) { 591 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 592 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 593 int irq; 594 /* Mapping from the output timer irq lines from the CPU to the 595 * GIC PPI inputs we use for the virt board. 596 */ 597 const int timer_irq[] = { 598 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 599 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 600 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 601 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 602 }; 603 604 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 605 qdev_connect_gpio_out(cpudev, irq, 606 qdev_get_gpio_in(gicdev, 607 ppibase + timer_irq[irq])); 608 } 609 610 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 611 qdev_get_gpio_in(gicdev, ppibase 612 + ARCH_GICV3_MAINT_IRQ)); 613 614 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 615 sysbus_connect_irq(gicbusdev, i + smp_cpus, 616 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 617 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 618 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 619 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 620 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 621 } 622 623 for (i = 0; i < NUM_IRQS; i++) { 624 pic[i] = qdev_get_gpio_in(gicdev, i); 625 } 626 627 fdt_add_gic_node(vms); 628 629 if (type == 3 && vms->its) { 630 create_its(vms, gicdev); 631 } else if (type == 2) { 632 create_v2m(vms, pic); 633 } 634 } 635 636 static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart, 637 MemoryRegion *mem, Chardev *chr) 638 { 639 char *nodename; 640 hwaddr base = vms->memmap[uart].base; 641 hwaddr size = vms->memmap[uart].size; 642 int irq = vms->irqmap[uart]; 643 const char compat[] = "arm,pl011\0arm,primecell"; 644 const char clocknames[] = "uartclk\0apb_pclk"; 645 DeviceState *dev = qdev_create(NULL, "pl011"); 646 SysBusDevice *s = SYS_BUS_DEVICE(dev); 647 648 qdev_prop_set_chr(dev, "chardev", chr); 649 qdev_init_nofail(dev); 650 memory_region_add_subregion(mem, base, 651 sysbus_mmio_get_region(s, 0)); 652 sysbus_connect_irq(s, 0, pic[irq]); 653 654 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 655 qemu_fdt_add_subnode(vms->fdt, nodename); 656 /* Note that we can't use setprop_string because of the embedded NUL */ 657 qemu_fdt_setprop(vms->fdt, nodename, "compatible", 658 compat, sizeof(compat)); 659 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 660 2, base, 2, size); 661 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 662 GIC_FDT_IRQ_TYPE_SPI, irq, 663 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 664 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks", 665 vms->clock_phandle, vms->clock_phandle); 666 qemu_fdt_setprop(vms->fdt, nodename, "clock-names", 667 clocknames, sizeof(clocknames)); 668 669 if (uart == VIRT_UART) { 670 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); 671 } else { 672 /* Mark as not usable by the normal world */ 673 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 674 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 675 } 676 677 g_free(nodename); 678 } 679 680 static void create_rtc(const VirtMachineState *vms, qemu_irq *pic) 681 { 682 char *nodename; 683 hwaddr base = vms->memmap[VIRT_RTC].base; 684 hwaddr size = vms->memmap[VIRT_RTC].size; 685 int irq = vms->irqmap[VIRT_RTC]; 686 const char compat[] = "arm,pl031\0arm,primecell"; 687 688 sysbus_create_simple("pl031", base, pic[irq]); 689 690 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 691 qemu_fdt_add_subnode(vms->fdt, nodename); 692 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 693 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 694 2, base, 2, size); 695 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 696 GIC_FDT_IRQ_TYPE_SPI, irq, 697 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 698 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 699 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 700 g_free(nodename); 701 } 702 703 static DeviceState *gpio_key_dev; 704 static void virt_powerdown_req(Notifier *n, void *opaque) 705 { 706 /* use gpio Pin 3 for power button event */ 707 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 708 } 709 710 static Notifier virt_system_powerdown_notifier = { 711 .notify = virt_powerdown_req 712 }; 713 714 static void create_gpio(const VirtMachineState *vms, qemu_irq *pic) 715 { 716 char *nodename; 717 DeviceState *pl061_dev; 718 hwaddr base = vms->memmap[VIRT_GPIO].base; 719 hwaddr size = vms->memmap[VIRT_GPIO].size; 720 int irq = vms->irqmap[VIRT_GPIO]; 721 const char compat[] = "arm,pl061\0arm,primecell"; 722 723 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); 724 725 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); 726 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 727 qemu_fdt_add_subnode(vms->fdt, nodename); 728 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 729 2, base, 2, size); 730 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 731 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); 732 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); 733 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 734 GIC_FDT_IRQ_TYPE_SPI, irq, 735 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 736 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 737 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 738 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); 739 740 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 741 qdev_get_gpio_in(pl061_dev, 3)); 742 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); 743 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); 744 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); 745 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); 746 747 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); 748 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", 749 "label", "GPIO Key Poweroff"); 750 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", 751 KEY_POWER); 752 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", 753 "gpios", phandle, 3, 0); 754 755 /* connect powerdown request */ 756 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier); 757 758 g_free(nodename); 759 } 760 761 static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic) 762 { 763 int i; 764 hwaddr size = vms->memmap[VIRT_MMIO].size; 765 766 /* We create the transports in forwards order. Since qbus_realize() 767 * prepends (not appends) new child buses, the incrementing loop below will 768 * create a list of virtio-mmio buses with decreasing base addresses. 769 * 770 * When a -device option is processed from the command line, 771 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 772 * order. The upshot is that -device options in increasing command line 773 * order are mapped to virtio-mmio buses with decreasing base addresses. 774 * 775 * When this code was originally written, that arrangement ensured that the 776 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 777 * the first -device on the command line. (The end-to-end order is a 778 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 779 * guest kernel's name-to-address assignment strategy.) 780 * 781 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 782 * the message, if not necessarily the code, of commit 70161ff336. 783 * Therefore the loop now establishes the inverse of the original intent. 784 * 785 * Unfortunately, we can't counteract the kernel change by reversing the 786 * loop; it would break existing command lines. 787 * 788 * In any case, the kernel makes no guarantee about the stability of 789 * enumeration order of virtio devices (as demonstrated by it changing 790 * between kernel versions). For reliable and stable identification 791 * of disks users must use UUIDs or similar mechanisms. 792 */ 793 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 794 int irq = vms->irqmap[VIRT_MMIO] + i; 795 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 796 797 sysbus_create_simple("virtio-mmio", base, pic[irq]); 798 } 799 800 /* We add dtb nodes in reverse order so that they appear in the finished 801 * device tree lowest address first. 802 * 803 * Note that this mapping is independent of the loop above. The previous 804 * loop influences virtio device to virtio transport assignment, whereas 805 * this loop controls how virtio transports are laid out in the dtb. 806 */ 807 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 808 char *nodename; 809 int irq = vms->irqmap[VIRT_MMIO] + i; 810 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 811 812 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 813 qemu_fdt_add_subnode(vms->fdt, nodename); 814 qemu_fdt_setprop_string(vms->fdt, nodename, 815 "compatible", "virtio,mmio"); 816 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 817 2, base, 2, size); 818 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 819 GIC_FDT_IRQ_TYPE_SPI, irq, 820 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 821 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 822 g_free(nodename); 823 } 824 } 825 826 static void create_one_flash(const char *name, hwaddr flashbase, 827 hwaddr flashsize, const char *file, 828 MemoryRegion *sysmem) 829 { 830 /* Create and map a single flash device. We use the same 831 * parameters as the flash devices on the Versatile Express board. 832 */ 833 DriveInfo *dinfo = drive_get_next(IF_PFLASH); 834 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 835 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 836 const uint64_t sectorlength = 256 * 1024; 837 838 if (dinfo) { 839 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 840 &error_abort); 841 } 842 843 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); 844 qdev_prop_set_uint64(dev, "sector-length", sectorlength); 845 qdev_prop_set_uint8(dev, "width", 4); 846 qdev_prop_set_uint8(dev, "device-width", 2); 847 qdev_prop_set_bit(dev, "big-endian", false); 848 qdev_prop_set_uint16(dev, "id0", 0x89); 849 qdev_prop_set_uint16(dev, "id1", 0x18); 850 qdev_prop_set_uint16(dev, "id2", 0x00); 851 qdev_prop_set_uint16(dev, "id3", 0x00); 852 qdev_prop_set_string(dev, "name", name); 853 qdev_init_nofail(dev); 854 855 memory_region_add_subregion(sysmem, flashbase, 856 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 857 858 if (file) { 859 char *fn; 860 int image_size; 861 862 if (drive_get(IF_PFLASH, 0, 0)) { 863 error_report("The contents of the first flash device may be " 864 "specified with -bios or with -drive if=pflash... " 865 "but you cannot use both options at once"); 866 exit(1); 867 } 868 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file); 869 if (!fn) { 870 error_report("Could not find ROM image '%s'", file); 871 exit(1); 872 } 873 image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0)); 874 g_free(fn); 875 if (image_size < 0) { 876 error_report("Could not load ROM image '%s'", file); 877 exit(1); 878 } 879 } 880 } 881 882 static void create_flash(const VirtMachineState *vms, 883 MemoryRegion *sysmem, 884 MemoryRegion *secure_sysmem) 885 { 886 /* Create two flash devices to fill the VIRT_FLASH space in the memmap. 887 * Any file passed via -bios goes in the first of these. 888 * sysmem is the system memory space. secure_sysmem is the secure view 889 * of the system, and the first flash device should be made visible only 890 * there. The second flash device is visible to both secure and nonsecure. 891 * If sysmem == secure_sysmem this means there is no separate Secure 892 * address space and both flash devices are generally visible. 893 */ 894 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 895 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 896 char *nodename; 897 898 create_one_flash("virt.flash0", flashbase, flashsize, 899 bios_name, secure_sysmem); 900 create_one_flash("virt.flash1", flashbase + flashsize, flashsize, 901 NULL, sysmem); 902 903 if (sysmem == secure_sysmem) { 904 /* Report both flash devices as a single node in the DT */ 905 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 906 qemu_fdt_add_subnode(vms->fdt, nodename); 907 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 908 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 909 2, flashbase, 2, flashsize, 910 2, flashbase + flashsize, 2, flashsize); 911 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 912 g_free(nodename); 913 } else { 914 /* Report the devices as separate nodes so we can mark one as 915 * only visible to the secure world. 916 */ 917 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 918 qemu_fdt_add_subnode(vms->fdt, nodename); 919 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 920 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 921 2, flashbase, 2, flashsize); 922 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 923 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 924 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 925 g_free(nodename); 926 927 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 928 qemu_fdt_add_subnode(vms->fdt, nodename); 929 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 930 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 931 2, flashbase + flashsize, 2, flashsize); 932 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 933 g_free(nodename); 934 } 935 } 936 937 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 938 { 939 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 940 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 941 FWCfgState *fw_cfg; 942 char *nodename; 943 944 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 945 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 946 947 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 948 qemu_fdt_add_subnode(vms->fdt, nodename); 949 qemu_fdt_setprop_string(vms->fdt, nodename, 950 "compatible", "qemu,fw-cfg-mmio"); 951 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 952 2, base, 2, size); 953 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 954 g_free(nodename); 955 return fw_cfg; 956 } 957 958 static void create_pcie_irq_map(const VirtMachineState *vms, 959 uint32_t gic_phandle, 960 int first_irq, const char *nodename) 961 { 962 int devfn, pin; 963 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 964 uint32_t *irq_map = full_irq_map; 965 966 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 967 for (pin = 0; pin < 4; pin++) { 968 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 969 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 970 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 971 int i; 972 973 uint32_t map[] = { 974 devfn << 8, 0, 0, /* devfn */ 975 pin + 1, /* PCI pin */ 976 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 977 978 /* Convert map to big endian */ 979 for (i = 0; i < 10; i++) { 980 irq_map[i] = cpu_to_be32(map[i]); 981 } 982 irq_map += 10; 983 } 984 } 985 986 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map", 987 full_irq_map, sizeof(full_irq_map)); 988 989 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask", 990 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 991 0x7 /* PCI irq */); 992 } 993 994 static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) 995 { 996 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 997 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 998 hwaddr base_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].base; 999 hwaddr size_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].size; 1000 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1001 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1002 hwaddr base_ecam = vms->memmap[VIRT_PCIE_ECAM].base; 1003 hwaddr size_ecam = vms->memmap[VIRT_PCIE_ECAM].size; 1004 hwaddr base = base_mmio; 1005 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1006 int irq = vms->irqmap[VIRT_PCIE]; 1007 MemoryRegion *mmio_alias; 1008 MemoryRegion *mmio_reg; 1009 MemoryRegion *ecam_alias; 1010 MemoryRegion *ecam_reg; 1011 DeviceState *dev; 1012 char *nodename; 1013 int i; 1014 PCIHostState *pci; 1015 1016 dev = qdev_create(NULL, TYPE_GPEX_HOST); 1017 qdev_init_nofail(dev); 1018 1019 /* Map only the first size_ecam bytes of ECAM space */ 1020 ecam_alias = g_new0(MemoryRegion, 1); 1021 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1022 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1023 ecam_reg, 0, size_ecam); 1024 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1025 1026 /* Map the MMIO window into system address space so as to expose 1027 * the section of PCI MMIO space which starts at the same base address 1028 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1029 * the window). 1030 */ 1031 mmio_alias = g_new0(MemoryRegion, 1); 1032 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1033 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1034 mmio_reg, base_mmio, size_mmio); 1035 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1036 1037 if (vms->highmem) { 1038 /* Map high MMIO space */ 1039 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1040 1041 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1042 mmio_reg, base_mmio_high, size_mmio_high); 1043 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1044 high_mmio_alias); 1045 } 1046 1047 /* Map IO port space */ 1048 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1049 1050 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1051 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 1052 } 1053 1054 pci = PCI_HOST_BRIDGE(dev); 1055 if (pci->bus) { 1056 for (i = 0; i < nb_nics; i++) { 1057 NICInfo *nd = &nd_table[i]; 1058 1059 if (!nd->model) { 1060 nd->model = g_strdup("virtio"); 1061 } 1062 1063 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1064 } 1065 } 1066 1067 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1068 qemu_fdt_add_subnode(vms->fdt, nodename); 1069 qemu_fdt_setprop_string(vms->fdt, nodename, 1070 "compatible", "pci-host-ecam-generic"); 1071 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci"); 1072 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3); 1073 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2); 1074 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0, 1075 nr_pcie_buses - 1); 1076 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1077 1078 if (vms->msi_phandle) { 1079 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", 1080 vms->msi_phandle); 1081 } 1082 1083 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1084 2, base_ecam, 2, size_ecam); 1085 1086 if (vms->highmem) { 1087 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1088 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1089 2, base_pio, 2, size_pio, 1090 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1091 2, base_mmio, 2, size_mmio, 1092 1, FDT_PCI_RANGE_MMIO_64BIT, 1093 2, base_mmio_high, 1094 2, base_mmio_high, 2, size_mmio_high); 1095 } else { 1096 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1097 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1098 2, base_pio, 2, size_pio, 1099 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1100 2, base_mmio, 2, size_mmio); 1101 } 1102 1103 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); 1104 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); 1105 1106 g_free(nodename); 1107 } 1108 1109 static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic) 1110 { 1111 DeviceState *dev; 1112 SysBusDevice *s; 1113 int i; 1114 ARMPlatformBusFDTParams *fdt_params = g_new(ARMPlatformBusFDTParams, 1); 1115 MemoryRegion *sysmem = get_system_memory(); 1116 1117 platform_bus_params.platform_bus_base = vms->memmap[VIRT_PLATFORM_BUS].base; 1118 platform_bus_params.platform_bus_size = vms->memmap[VIRT_PLATFORM_BUS].size; 1119 platform_bus_params.platform_bus_first_irq = vms->irqmap[VIRT_PLATFORM_BUS]; 1120 platform_bus_params.platform_bus_num_irqs = PLATFORM_BUS_NUM_IRQS; 1121 1122 fdt_params->system_params = &platform_bus_params; 1123 fdt_params->binfo = &vms->bootinfo; 1124 fdt_params->intc = "/intc"; 1125 /* 1126 * register a machine init done notifier that creates the device tree 1127 * nodes of the platform bus and its children dynamic sysbus devices 1128 */ 1129 arm_register_platform_bus_fdt_creator(fdt_params); 1130 1131 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1132 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1133 qdev_prop_set_uint32(dev, "num_irqs", 1134 platform_bus_params.platform_bus_num_irqs); 1135 qdev_prop_set_uint32(dev, "mmio_size", 1136 platform_bus_params.platform_bus_size); 1137 qdev_init_nofail(dev); 1138 s = SYS_BUS_DEVICE(dev); 1139 1140 for (i = 0; i < platform_bus_params.platform_bus_num_irqs; i++) { 1141 int irqn = platform_bus_params.platform_bus_first_irq + i; 1142 sysbus_connect_irq(s, i, pic[irqn]); 1143 } 1144 1145 memory_region_add_subregion(sysmem, 1146 platform_bus_params.platform_bus_base, 1147 sysbus_mmio_get_region(s, 0)); 1148 } 1149 1150 static void create_secure_ram(VirtMachineState *vms, 1151 MemoryRegion *secure_sysmem) 1152 { 1153 MemoryRegion *secram = g_new(MemoryRegion, 1); 1154 char *nodename; 1155 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1156 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1157 1158 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1159 &error_fatal); 1160 memory_region_add_subregion(secure_sysmem, base, secram); 1161 1162 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1163 qemu_fdt_add_subnode(vms->fdt, nodename); 1164 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory"); 1165 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size); 1166 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1167 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1168 1169 g_free(nodename); 1170 } 1171 1172 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1173 { 1174 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1175 bootinfo); 1176 1177 *fdt_size = board->fdt_size; 1178 return board->fdt; 1179 } 1180 1181 static void virt_build_smbios(VirtMachineState *vms) 1182 { 1183 uint8_t *smbios_tables, *smbios_anchor; 1184 size_t smbios_tables_len, smbios_anchor_len; 1185 const char *product = "QEMU Virtual Machine"; 1186 1187 if (!vms->fw_cfg) { 1188 return; 1189 } 1190 1191 if (kvm_enabled()) { 1192 product = "KVM Virtual Machine"; 1193 } 1194 1195 smbios_set_defaults("QEMU", product, 1196 "1.0", false, true, SMBIOS_ENTRY_POINT_30); 1197 1198 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, 1199 &smbios_anchor, &smbios_anchor_len); 1200 1201 if (smbios_anchor) { 1202 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1203 smbios_tables, smbios_tables_len); 1204 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1205 smbios_anchor, smbios_anchor_len); 1206 } 1207 } 1208 1209 static 1210 void virt_machine_done(Notifier *notifier, void *data) 1211 { 1212 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1213 machine_done); 1214 1215 virt_acpi_setup(vms); 1216 virt_build_smbios(vms); 1217 } 1218 1219 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1220 { 1221 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1222 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1223 1224 if (!vmc->disallow_affinity_adjustment) { 1225 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1226 * GIC's target-list limitations. 32-bit KVM hosts currently 1227 * always create clusters of 4 CPUs, but that is expected to 1228 * change when they gain support for gicv3. When KVM is enabled 1229 * it will override the changes we make here, therefore our 1230 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1231 * and to improve SGI efficiency. 1232 */ 1233 if (vms->gic_version == 3) { 1234 clustersz = GICV3_TARGETLIST_BITS; 1235 } else { 1236 clustersz = GIC_TARGETLIST_BITS; 1237 } 1238 } 1239 return arm_cpu_mp_affinity(idx, clustersz); 1240 } 1241 1242 static void machvirt_init(MachineState *machine) 1243 { 1244 VirtMachineState *vms = VIRT_MACHINE(machine); 1245 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1246 MachineClass *mc = MACHINE_GET_CLASS(machine); 1247 const CPUArchIdList *possible_cpus; 1248 qemu_irq pic[NUM_IRQS]; 1249 MemoryRegion *sysmem = get_system_memory(); 1250 MemoryRegion *secure_sysmem = NULL; 1251 int n, virt_max_cpus; 1252 MemoryRegion *ram = g_new(MemoryRegion, 1); 1253 const char *cpu_model = machine->cpu_model; 1254 char **cpustr; 1255 ObjectClass *oc; 1256 const char *typename; 1257 CPUClass *cc; 1258 Error *err = NULL; 1259 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); 1260 1261 if (!cpu_model) { 1262 cpu_model = "cortex-a15"; 1263 } 1264 1265 /* We can probe only here because during property set 1266 * KVM is not available yet 1267 */ 1268 if (!vms->gic_version) { 1269 if (!kvm_enabled()) { 1270 error_report("gic-version=host requires KVM"); 1271 exit(1); 1272 } 1273 1274 vms->gic_version = kvm_arm_vgic_probe(); 1275 if (!vms->gic_version) { 1276 error_report("Unable to determine GIC version supported by host"); 1277 exit(1); 1278 } 1279 } 1280 1281 /* Separate the actual CPU model name from any appended features */ 1282 cpustr = g_strsplit(cpu_model, ",", 2); 1283 1284 if (!cpuname_valid(cpustr[0])) { 1285 error_report("mach-virt: CPU %s not supported", cpustr[0]); 1286 exit(1); 1287 } 1288 1289 /* If we have an EL3 boot ROM then the assumption is that it will 1290 * implement PSCI itself, so disable QEMU's internal implementation 1291 * so it doesn't get in the way. Instead of starting secondary 1292 * CPUs in PSCI powerdown state we will start them all running and 1293 * let the boot ROM sort them out. 1294 * The usual case is that we do use QEMU's PSCI implementation; 1295 * if the guest has EL2 then we will use SMC as the conduit, 1296 * and otherwise we will use HVC (for backwards compatibility and 1297 * because if we're using KVM then we must use HVC). 1298 */ 1299 if (vms->secure && firmware_loaded) { 1300 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1301 } else if (vms->virt) { 1302 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 1303 } else { 1304 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 1305 } 1306 1307 /* The maximum number of CPUs depends on the GIC version, or on how 1308 * many redistributors we can fit into the memory map. 1309 */ 1310 if (vms->gic_version == 3) { 1311 virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / 0x20000; 1312 } else { 1313 virt_max_cpus = GIC_NCPU; 1314 } 1315 1316 if (max_cpus > virt_max_cpus) { 1317 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1318 "supported by machine 'mach-virt' (%d)", 1319 max_cpus, virt_max_cpus); 1320 exit(1); 1321 } 1322 1323 vms->smp_cpus = smp_cpus; 1324 1325 if (machine->ram_size > vms->memmap[VIRT_MEM].size) { 1326 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB); 1327 exit(1); 1328 } 1329 1330 if (vms->virt && kvm_enabled()) { 1331 error_report("mach-virt: KVM does not support providing " 1332 "Virtualization extensions to the guest CPU"); 1333 exit(1); 1334 } 1335 1336 if (vms->secure) { 1337 if (kvm_enabled()) { 1338 error_report("mach-virt: KVM does not support Security extensions"); 1339 exit(1); 1340 } 1341 1342 /* The Secure view of the world is the same as the NonSecure, 1343 * but with a few extra devices. Create it as a container region 1344 * containing the system memory at low priority; any secure-only 1345 * devices go in at higher priority and take precedence. 1346 */ 1347 secure_sysmem = g_new(MemoryRegion, 1); 1348 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1349 UINT64_MAX); 1350 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1351 } 1352 1353 create_fdt(vms); 1354 1355 oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); 1356 if (!oc) { 1357 error_report("Unable to find CPU definition"); 1358 exit(1); 1359 } 1360 typename = object_class_get_name(oc); 1361 1362 /* convert -smp CPU options specified by the user into global props */ 1363 cc = CPU_CLASS(oc); 1364 cc->parse_features(typename, cpustr[1], &err); 1365 g_strfreev(cpustr); 1366 if (err) { 1367 error_report_err(err); 1368 exit(1); 1369 } 1370 1371 possible_cpus = mc->possible_cpu_arch_ids(machine); 1372 for (n = 0; n < possible_cpus->len; n++) { 1373 Object *cpuobj; 1374 CPUState *cs; 1375 1376 if (n >= smp_cpus) { 1377 break; 1378 } 1379 1380 cpuobj = object_new(typename); 1381 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 1382 "mp-affinity", NULL); 1383 1384 cs = CPU(cpuobj); 1385 cs->cpu_index = n; 1386 1387 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 1388 &error_fatal); 1389 1390 if (!vms->secure) { 1391 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1392 } 1393 1394 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { 1395 object_property_set_bool(cpuobj, false, "has_el2", NULL); 1396 } 1397 1398 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1399 object_property_set_int(cpuobj, vms->psci_conduit, 1400 "psci-conduit", NULL); 1401 1402 /* Secondary CPUs start in PSCI powered-down state */ 1403 if (n > 0) { 1404 object_property_set_bool(cpuobj, true, 1405 "start-powered-off", NULL); 1406 } 1407 } 1408 1409 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { 1410 object_property_set_bool(cpuobj, false, "pmu", NULL); 1411 } 1412 1413 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1414 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, 1415 "reset-cbar", &error_abort); 1416 } 1417 1418 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1419 &error_abort); 1420 if (vms->secure) { 1421 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1422 "secure-memory", &error_abort); 1423 } 1424 1425 object_property_set_bool(cpuobj, true, "realized", NULL); 1426 object_unref(cpuobj); 1427 } 1428 fdt_add_timer_nodes(vms); 1429 fdt_add_cpu_nodes(vms); 1430 fdt_add_psci_node(vms); 1431 1432 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", 1433 machine->ram_size); 1434 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); 1435 1436 create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem); 1437 1438 create_gic(vms, pic); 1439 1440 fdt_add_pmu_nodes(vms); 1441 1442 create_uart(vms, pic, VIRT_UART, sysmem, serial_hds[0]); 1443 1444 if (vms->secure) { 1445 create_secure_ram(vms, secure_sysmem); 1446 create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hds[1]); 1447 } 1448 1449 create_rtc(vms, pic); 1450 1451 create_pcie(vms, pic); 1452 1453 create_gpio(vms, pic); 1454 1455 /* Create mmio transports, so the user can create virtio backends 1456 * (which will be automatically plugged in to the transports). If 1457 * no backend is created the transport will just sit harmlessly idle. 1458 */ 1459 create_virtio_devices(vms, pic); 1460 1461 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 1462 rom_set_fw(vms->fw_cfg); 1463 1464 vms->machine_done.notify = virt_machine_done; 1465 qemu_add_machine_init_done_notifier(&vms->machine_done); 1466 1467 vms->bootinfo.ram_size = machine->ram_size; 1468 vms->bootinfo.kernel_filename = machine->kernel_filename; 1469 vms->bootinfo.kernel_cmdline = machine->kernel_cmdline; 1470 vms->bootinfo.initrd_filename = machine->initrd_filename; 1471 vms->bootinfo.nb_cpus = smp_cpus; 1472 vms->bootinfo.board_id = -1; 1473 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 1474 vms->bootinfo.get_dtb = machvirt_dtb; 1475 vms->bootinfo.firmware_loaded = firmware_loaded; 1476 arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo); 1477 1478 /* 1479 * arm_load_kernel machine init done notifier registration must 1480 * happen before the platform_bus_create call. In this latter, 1481 * another notifier is registered which adds platform bus nodes. 1482 * Notifiers are executed in registration reverse order. 1483 */ 1484 create_platform_bus(vms, pic); 1485 } 1486 1487 static bool virt_get_secure(Object *obj, Error **errp) 1488 { 1489 VirtMachineState *vms = VIRT_MACHINE(obj); 1490 1491 return vms->secure; 1492 } 1493 1494 static void virt_set_secure(Object *obj, bool value, Error **errp) 1495 { 1496 VirtMachineState *vms = VIRT_MACHINE(obj); 1497 1498 vms->secure = value; 1499 } 1500 1501 static bool virt_get_virt(Object *obj, Error **errp) 1502 { 1503 VirtMachineState *vms = VIRT_MACHINE(obj); 1504 1505 return vms->virt; 1506 } 1507 1508 static void virt_set_virt(Object *obj, bool value, Error **errp) 1509 { 1510 VirtMachineState *vms = VIRT_MACHINE(obj); 1511 1512 vms->virt = value; 1513 } 1514 1515 static bool virt_get_highmem(Object *obj, Error **errp) 1516 { 1517 VirtMachineState *vms = VIRT_MACHINE(obj); 1518 1519 return vms->highmem; 1520 } 1521 1522 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1523 { 1524 VirtMachineState *vms = VIRT_MACHINE(obj); 1525 1526 vms->highmem = value; 1527 } 1528 1529 static bool virt_get_its(Object *obj, Error **errp) 1530 { 1531 VirtMachineState *vms = VIRT_MACHINE(obj); 1532 1533 return vms->its; 1534 } 1535 1536 static void virt_set_its(Object *obj, bool value, Error **errp) 1537 { 1538 VirtMachineState *vms = VIRT_MACHINE(obj); 1539 1540 vms->its = value; 1541 } 1542 1543 static char *virt_get_gic_version(Object *obj, Error **errp) 1544 { 1545 VirtMachineState *vms = VIRT_MACHINE(obj); 1546 const char *val = vms->gic_version == 3 ? "3" : "2"; 1547 1548 return g_strdup(val); 1549 } 1550 1551 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 1552 { 1553 VirtMachineState *vms = VIRT_MACHINE(obj); 1554 1555 if (!strcmp(value, "3")) { 1556 vms->gic_version = 3; 1557 } else if (!strcmp(value, "2")) { 1558 vms->gic_version = 2; 1559 } else if (!strcmp(value, "host")) { 1560 vms->gic_version = 0; /* Will probe later */ 1561 } else { 1562 error_setg(errp, "Invalid gic-version value"); 1563 error_append_hint(errp, "Valid values are 3, 2, host.\n"); 1564 } 1565 } 1566 1567 static CpuInstanceProperties 1568 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1569 { 1570 MachineClass *mc = MACHINE_GET_CLASS(ms); 1571 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1572 1573 assert(cpu_index < possible_cpus->len); 1574 return possible_cpus->cpus[cpu_index].props; 1575 } 1576 1577 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1578 { 1579 int n; 1580 VirtMachineState *vms = VIRT_MACHINE(ms); 1581 1582 if (ms->possible_cpus) { 1583 assert(ms->possible_cpus->len == max_cpus); 1584 return ms->possible_cpus; 1585 } 1586 1587 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1588 sizeof(CPUArchId) * max_cpus); 1589 ms->possible_cpus->len = max_cpus; 1590 for (n = 0; n < ms->possible_cpus->len; n++) { 1591 ms->possible_cpus->cpus[n].arch_id = 1592 virt_cpu_mp_affinity(vms, n); 1593 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1594 ms->possible_cpus->cpus[n].props.thread_id = n; 1595 1596 /* default distribution of CPUs over NUMA nodes */ 1597 if (nb_numa_nodes) { 1598 /* preset values but do not enable them i.e. 'has_node_id = false', 1599 * numa init code will enable them later if manual mapping wasn't 1600 * present on CLI */ 1601 ms->possible_cpus->cpus[n].props.node_id = n % nb_numa_nodes; 1602 } 1603 } 1604 return ms->possible_cpus; 1605 } 1606 1607 static void virt_machine_class_init(ObjectClass *oc, void *data) 1608 { 1609 MachineClass *mc = MACHINE_CLASS(oc); 1610 1611 mc->init = machvirt_init; 1612 /* Start max_cpus at the maximum QEMU supports. We'll further restrict 1613 * it later in machvirt_init, where we have more information about the 1614 * configuration of the particular instance. 1615 */ 1616 mc->max_cpus = 255; 1617 mc->has_dynamic_sysbus = true; 1618 mc->block_default_type = IF_VIRTIO; 1619 mc->no_cdrom = 1; 1620 mc->pci_allow_0_address = true; 1621 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 1622 mc->minimum_page_bits = 12; 1623 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1624 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1625 } 1626 1627 static const TypeInfo virt_machine_info = { 1628 .name = TYPE_VIRT_MACHINE, 1629 .parent = TYPE_MACHINE, 1630 .abstract = true, 1631 .instance_size = sizeof(VirtMachineState), 1632 .class_size = sizeof(VirtMachineClass), 1633 .class_init = virt_machine_class_init, 1634 }; 1635 1636 static void machvirt_machine_init(void) 1637 { 1638 type_register_static(&virt_machine_info); 1639 } 1640 type_init(machvirt_machine_init); 1641 1642 static void virt_2_10_instance_init(Object *obj) 1643 { 1644 VirtMachineState *vms = VIRT_MACHINE(obj); 1645 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1646 1647 /* EL3 is disabled by default on virt: this makes us consistent 1648 * between KVM and TCG for this board, and it also allows us to 1649 * boot UEFI blobs which assume no TrustZone support. 1650 */ 1651 vms->secure = false; 1652 object_property_add_bool(obj, "secure", virt_get_secure, 1653 virt_set_secure, NULL); 1654 object_property_set_description(obj, "secure", 1655 "Set on/off to enable/disable the ARM " 1656 "Security Extensions (TrustZone)", 1657 NULL); 1658 1659 /* EL2 is also disabled by default, for similar reasons */ 1660 vms->virt = false; 1661 object_property_add_bool(obj, "virtualization", virt_get_virt, 1662 virt_set_virt, NULL); 1663 object_property_set_description(obj, "virtualization", 1664 "Set on/off to enable/disable emulating a " 1665 "guest CPU which implements the ARM " 1666 "Virtualization Extensions", 1667 NULL); 1668 1669 /* High memory is enabled by default */ 1670 vms->highmem = true; 1671 object_property_add_bool(obj, "highmem", virt_get_highmem, 1672 virt_set_highmem, NULL); 1673 object_property_set_description(obj, "highmem", 1674 "Set on/off to enable/disable using " 1675 "physical address space above 32 bits", 1676 NULL); 1677 /* Default GIC type is v2 */ 1678 vms->gic_version = 2; 1679 object_property_add_str(obj, "gic-version", virt_get_gic_version, 1680 virt_set_gic_version, NULL); 1681 object_property_set_description(obj, "gic-version", 1682 "Set GIC version. " 1683 "Valid values are 2, 3 and host", NULL); 1684 1685 if (vmc->no_its) { 1686 vms->its = false; 1687 } else { 1688 /* Default allows ITS instantiation */ 1689 vms->its = true; 1690 object_property_add_bool(obj, "its", virt_get_its, 1691 virt_set_its, NULL); 1692 object_property_set_description(obj, "its", 1693 "Set on/off to enable/disable " 1694 "ITS instantiation", 1695 NULL); 1696 } 1697 1698 vms->memmap = a15memmap; 1699 vms->irqmap = a15irqmap; 1700 } 1701 1702 static void virt_machine_2_10_options(MachineClass *mc) 1703 { 1704 } 1705 DEFINE_VIRT_MACHINE_AS_LATEST(2, 10) 1706 1707 #define VIRT_COMPAT_2_9 \ 1708 HW_COMPAT_2_9 1709 1710 static void virt_2_9_instance_init(Object *obj) 1711 { 1712 virt_2_10_instance_init(obj); 1713 } 1714 1715 static void virt_machine_2_9_options(MachineClass *mc) 1716 { 1717 virt_machine_2_10_options(mc); 1718 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_9); 1719 } 1720 DEFINE_VIRT_MACHINE(2, 9) 1721 1722 #define VIRT_COMPAT_2_8 \ 1723 HW_COMPAT_2_8 1724 1725 static void virt_2_8_instance_init(Object *obj) 1726 { 1727 virt_2_9_instance_init(obj); 1728 } 1729 1730 static void virt_machine_2_8_options(MachineClass *mc) 1731 { 1732 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1733 1734 virt_machine_2_9_options(mc); 1735 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_8); 1736 /* For 2.8 and earlier we falsely claimed in the DT that 1737 * our timers were edge-triggered, not level-triggered. 1738 */ 1739 vmc->claim_edge_triggered_timers = true; 1740 } 1741 DEFINE_VIRT_MACHINE(2, 8) 1742 1743 #define VIRT_COMPAT_2_7 \ 1744 HW_COMPAT_2_7 1745 1746 static void virt_2_7_instance_init(Object *obj) 1747 { 1748 virt_2_8_instance_init(obj); 1749 } 1750 1751 static void virt_machine_2_7_options(MachineClass *mc) 1752 { 1753 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1754 1755 virt_machine_2_8_options(mc); 1756 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_7); 1757 /* ITS was introduced with 2.8 */ 1758 vmc->no_its = true; 1759 /* Stick with 1K pages for migration compatibility */ 1760 mc->minimum_page_bits = 0; 1761 } 1762 DEFINE_VIRT_MACHINE(2, 7) 1763 1764 #define VIRT_COMPAT_2_6 \ 1765 HW_COMPAT_2_6 1766 1767 static void virt_2_6_instance_init(Object *obj) 1768 { 1769 virt_2_7_instance_init(obj); 1770 } 1771 1772 static void virt_machine_2_6_options(MachineClass *mc) 1773 { 1774 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1775 1776 virt_machine_2_7_options(mc); 1777 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6); 1778 vmc->disallow_affinity_adjustment = true; 1779 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 1780 vmc->no_pmu = true; 1781 } 1782 DEFINE_VIRT_MACHINE(2, 6) 1783