1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/units.h" 33 #include "qemu/option.h" 34 #include "qapi/error.h" 35 #include "hw/sysbus.h" 36 #include "hw/arm/boot.h" 37 #include "hw/arm/primecell.h" 38 #include "hw/arm/virt.h" 39 #include "hw/block/flash.h" 40 #include "hw/vfio/vfio-calxeda-xgmac.h" 41 #include "hw/vfio/vfio-amd-xgbe.h" 42 #include "hw/display/ramfb.h" 43 #include "net/net.h" 44 #include "sysemu/device_tree.h" 45 #include "sysemu/numa.h" 46 #include "sysemu/sysemu.h" 47 #include "sysemu/kvm.h" 48 #include "hw/loader.h" 49 #include "exec/address-spaces.h" 50 #include "qemu/bitops.h" 51 #include "qemu/error-report.h" 52 #include "hw/pci-host/gpex.h" 53 #include "hw/arm/sysbus-fdt.h" 54 #include "hw/platform-bus.h" 55 #include "hw/arm/fdt.h" 56 #include "hw/intc/arm_gic.h" 57 #include "hw/intc/arm_gicv3_common.h" 58 #include "kvm_arm.h" 59 #include "hw/firmware/smbios.h" 60 #include "qapi/visitor.h" 61 #include "standard-headers/linux/input.h" 62 #include "hw/arm/smmuv3.h" 63 #include "hw/acpi/acpi.h" 64 #include "target/arm/internals.h" 65 66 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 67 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 68 void *data) \ 69 { \ 70 MachineClass *mc = MACHINE_CLASS(oc); \ 71 virt_machine_##major##_##minor##_options(mc); \ 72 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 73 if (latest) { \ 74 mc->alias = "virt"; \ 75 } \ 76 } \ 77 static const TypeInfo machvirt_##major##_##minor##_info = { \ 78 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 79 .parent = TYPE_VIRT_MACHINE, \ 80 .class_init = virt_##major##_##minor##_class_init, \ 81 }; \ 82 static void machvirt_machine_##major##_##minor##_init(void) \ 83 { \ 84 type_register_static(&machvirt_##major##_##minor##_info); \ 85 } \ 86 type_init(machvirt_machine_##major##_##minor##_init); 87 88 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 89 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 90 #define DEFINE_VIRT_MACHINE(major, minor) \ 91 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 92 93 94 /* Number of external interrupt lines to configure the GIC with */ 95 #define NUM_IRQS 256 96 97 #define PLATFORM_BUS_NUM_IRQS 64 98 99 /* Legacy RAM limit in GB (< version 4.0) */ 100 #define LEGACY_RAMLIMIT_GB 255 101 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 102 103 /* Addresses and sizes of our components. 104 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 105 * 128MB..256MB is used for miscellaneous device I/O. 106 * 256MB..1GB is reserved for possible future PCI support (ie where the 107 * PCI memory window will go if we add a PCI host controller). 108 * 1GB and up is RAM (which may happily spill over into the 109 * high memory region beyond 4GB). 110 * This represents a compromise between how much RAM can be given to 111 * a 32 bit VM and leaving space for expansion and in particular for PCI. 112 * Note that devices should generally be placed at multiples of 0x10000, 113 * to accommodate guests using 64K pages. 114 */ 115 static const MemMapEntry base_memmap[] = { 116 /* Space up to 0x8000000 is reserved for a boot ROM */ 117 [VIRT_FLASH] = { 0, 0x08000000 }, 118 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 119 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 120 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 121 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 122 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 123 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 124 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 125 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 126 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 127 /* This redistributor space allows up to 2*64kB*123 CPUs */ 128 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 129 [VIRT_UART] = { 0x09000000, 0x00001000 }, 130 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 131 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 132 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 133 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 134 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 135 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 136 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 137 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 138 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 139 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 140 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 141 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 142 /* Actual RAM size depends on initial RAM and device memory settings */ 143 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 144 }; 145 146 /* 147 * Highmem IO Regions: This memory map is floating, located after the RAM. 148 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 149 * top of the RAM, so that its base get the same alignment as the size, 150 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 151 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 152 * Note the extended_memmap is sized so that it eventually also includes the 153 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 154 * index of base_memmap). 155 */ 156 static MemMapEntry extended_memmap[] = { 157 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 158 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 159 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 160 /* Second PCIe window */ 161 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 162 }; 163 164 static const int a15irqmap[] = { 165 [VIRT_UART] = 1, 166 [VIRT_RTC] = 2, 167 [VIRT_PCIE] = 3, /* ... to 6 */ 168 [VIRT_GPIO] = 7, 169 [VIRT_SECURE_UART] = 8, 170 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 171 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 172 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 173 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 174 }; 175 176 static const char *valid_cpus[] = { 177 ARM_CPU_TYPE_NAME("cortex-a15"), 178 ARM_CPU_TYPE_NAME("cortex-a53"), 179 ARM_CPU_TYPE_NAME("cortex-a57"), 180 ARM_CPU_TYPE_NAME("cortex-a72"), 181 ARM_CPU_TYPE_NAME("host"), 182 ARM_CPU_TYPE_NAME("max"), 183 }; 184 185 static bool cpu_type_valid(const char *cpu) 186 { 187 int i; 188 189 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 190 if (strcmp(cpu, valid_cpus[i]) == 0) { 191 return true; 192 } 193 } 194 return false; 195 } 196 197 static void create_fdt(VirtMachineState *vms) 198 { 199 void *fdt = create_device_tree(&vms->fdt_size); 200 201 if (!fdt) { 202 error_report("create_device_tree() failed"); 203 exit(1); 204 } 205 206 vms->fdt = fdt; 207 208 /* Header */ 209 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 210 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 211 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 212 213 /* /chosen must exist for load_dtb to fill in necessary properties later */ 214 qemu_fdt_add_subnode(fdt, "/chosen"); 215 216 /* Clock node, for the benefit of the UART. The kernel device tree 217 * binding documentation claims the PL011 node clock properties are 218 * optional but in practice if you omit them the kernel refuses to 219 * probe for the device. 220 */ 221 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 222 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 223 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 224 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 225 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 226 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 227 "clk24mhz"); 228 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 229 230 if (have_numa_distance) { 231 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 232 uint32_t *matrix = g_malloc0(size); 233 int idx, i, j; 234 235 for (i = 0; i < nb_numa_nodes; i++) { 236 for (j = 0; j < nb_numa_nodes; j++) { 237 idx = (i * nb_numa_nodes + j) * 3; 238 matrix[idx + 0] = cpu_to_be32(i); 239 matrix[idx + 1] = cpu_to_be32(j); 240 matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]); 241 } 242 } 243 244 qemu_fdt_add_subnode(fdt, "/distance-map"); 245 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 246 "numa-distance-map-v1"); 247 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 248 matrix, size); 249 g_free(matrix); 250 } 251 } 252 253 static void fdt_add_timer_nodes(const VirtMachineState *vms) 254 { 255 /* On real hardware these interrupts are level-triggered. 256 * On KVM they were edge-triggered before host kernel version 4.4, 257 * and level-triggered afterwards. 258 * On emulated QEMU they are level-triggered. 259 * 260 * Getting the DTB info about them wrong is awkward for some 261 * guest kernels: 262 * pre-4.8 ignore the DT and leave the interrupt configured 263 * with whatever the GIC reset value (or the bootloader) left it at 264 * 4.8 before rc6 honour the incorrect data by programming it back 265 * into the GIC, causing problems 266 * 4.8rc6 and later ignore the DT and always write "level triggered" 267 * into the GIC 268 * 269 * For backwards-compatibility, virt-2.8 and earlier will continue 270 * to say these are edge-triggered, but later machines will report 271 * the correct information. 272 */ 273 ARMCPU *armcpu; 274 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 275 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 276 277 if (vmc->claim_edge_triggered_timers) { 278 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 279 } 280 281 if (vms->gic_version == 2) { 282 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 283 GIC_FDT_IRQ_PPI_CPU_WIDTH, 284 (1 << vms->smp_cpus) - 1); 285 } 286 287 qemu_fdt_add_subnode(vms->fdt, "/timer"); 288 289 armcpu = ARM_CPU(qemu_get_cpu(0)); 290 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 291 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 292 qemu_fdt_setprop(vms->fdt, "/timer", "compatible", 293 compat, sizeof(compat)); 294 } else { 295 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible", 296 "arm,armv7-timer"); 297 } 298 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0); 299 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts", 300 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 301 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 302 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 303 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 304 } 305 306 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 307 { 308 int cpu; 309 int addr_cells = 1; 310 const MachineState *ms = MACHINE(vms); 311 312 /* 313 * From Documentation/devicetree/bindings/arm/cpus.txt 314 * On ARM v8 64-bit systems value should be set to 2, 315 * that corresponds to the MPIDR_EL1 register size. 316 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 317 * in the system, #address-cells can be set to 1, since 318 * MPIDR_EL1[63:32] bits are not used for CPUs 319 * identification. 320 * 321 * Here we actually don't know whether our system is 32- or 64-bit one. 322 * The simplest way to go is to examine affinity IDs of all our CPUs. If 323 * at least one of them has Aff3 populated, we set #address-cells to 2. 324 */ 325 for (cpu = 0; cpu < vms->smp_cpus; cpu++) { 326 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 327 328 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 329 addr_cells = 2; 330 break; 331 } 332 } 333 334 qemu_fdt_add_subnode(vms->fdt, "/cpus"); 335 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); 336 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); 337 338 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { 339 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 340 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 341 CPUState *cs = CPU(armcpu); 342 343 qemu_fdt_add_subnode(vms->fdt, nodename); 344 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); 345 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 346 armcpu->dtb_compatible); 347 348 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED 349 && vms->smp_cpus > 1) { 350 qemu_fdt_setprop_string(vms->fdt, nodename, 351 "enable-method", "psci"); 352 } 353 354 if (addr_cells == 2) { 355 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", 356 armcpu->mp_affinity); 357 } else { 358 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", 359 armcpu->mp_affinity); 360 } 361 362 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 363 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", 364 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 365 } 366 367 g_free(nodename); 368 } 369 } 370 371 static void fdt_add_its_gic_node(VirtMachineState *vms) 372 { 373 char *nodename; 374 375 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 376 nodename = g_strdup_printf("/intc/its@%" PRIx64, 377 vms->memmap[VIRT_GIC_ITS].base); 378 qemu_fdt_add_subnode(vms->fdt, nodename); 379 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 380 "arm,gic-v3-its"); 381 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); 382 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 383 2, vms->memmap[VIRT_GIC_ITS].base, 384 2, vms->memmap[VIRT_GIC_ITS].size); 385 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); 386 g_free(nodename); 387 } 388 389 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 390 { 391 char *nodename; 392 393 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 394 vms->memmap[VIRT_GIC_V2M].base); 395 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 396 qemu_fdt_add_subnode(vms->fdt, nodename); 397 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 398 "arm,gic-v2m-frame"); 399 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); 400 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 401 2, vms->memmap[VIRT_GIC_V2M].base, 402 2, vms->memmap[VIRT_GIC_V2M].size); 403 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); 404 g_free(nodename); 405 } 406 407 static void fdt_add_gic_node(VirtMachineState *vms) 408 { 409 char *nodename; 410 411 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt); 412 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle); 413 414 nodename = g_strdup_printf("/intc@%" PRIx64, 415 vms->memmap[VIRT_GIC_DIST].base); 416 qemu_fdt_add_subnode(vms->fdt, nodename); 417 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 3); 418 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-controller", NULL, 0); 419 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2); 420 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2); 421 qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0); 422 if (vms->gic_version == 3) { 423 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 424 425 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 426 "arm,gic-v3"); 427 428 qemu_fdt_setprop_cell(vms->fdt, nodename, 429 "#redistributor-regions", nb_redist_regions); 430 431 if (nb_redist_regions == 1) { 432 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 433 2, vms->memmap[VIRT_GIC_DIST].base, 434 2, vms->memmap[VIRT_GIC_DIST].size, 435 2, vms->memmap[VIRT_GIC_REDIST].base, 436 2, vms->memmap[VIRT_GIC_REDIST].size); 437 } else { 438 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 439 2, vms->memmap[VIRT_GIC_DIST].base, 440 2, vms->memmap[VIRT_GIC_DIST].size, 441 2, vms->memmap[VIRT_GIC_REDIST].base, 442 2, vms->memmap[VIRT_GIC_REDIST].size, 443 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 444 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 445 } 446 447 if (vms->virt) { 448 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 449 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 450 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 451 } 452 } else { 453 /* 'cortex-a15-gic' means 'GIC v2' */ 454 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 455 "arm,cortex-a15-gic"); 456 if (!vms->virt) { 457 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 458 2, vms->memmap[VIRT_GIC_DIST].base, 459 2, vms->memmap[VIRT_GIC_DIST].size, 460 2, vms->memmap[VIRT_GIC_CPU].base, 461 2, vms->memmap[VIRT_GIC_CPU].size); 462 } else { 463 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 464 2, vms->memmap[VIRT_GIC_DIST].base, 465 2, vms->memmap[VIRT_GIC_DIST].size, 466 2, vms->memmap[VIRT_GIC_CPU].base, 467 2, vms->memmap[VIRT_GIC_CPU].size, 468 2, vms->memmap[VIRT_GIC_HYP].base, 469 2, vms->memmap[VIRT_GIC_HYP].size, 470 2, vms->memmap[VIRT_GIC_VCPU].base, 471 2, vms->memmap[VIRT_GIC_VCPU].size); 472 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 473 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 474 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 475 } 476 } 477 478 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle); 479 g_free(nodename); 480 } 481 482 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 483 { 484 CPUState *cpu; 485 ARMCPU *armcpu; 486 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 487 488 CPU_FOREACH(cpu) { 489 armcpu = ARM_CPU(cpu); 490 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 491 return; 492 } 493 if (kvm_enabled()) { 494 if (kvm_irqchip_in_kernel()) { 495 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 496 } 497 kvm_arm_pmu_init(cpu); 498 } 499 } 500 501 if (vms->gic_version == 2) { 502 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 503 GIC_FDT_IRQ_PPI_CPU_WIDTH, 504 (1 << vms->smp_cpus) - 1); 505 } 506 507 armcpu = ARM_CPU(qemu_get_cpu(0)); 508 qemu_fdt_add_subnode(vms->fdt, "/pmu"); 509 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 510 const char compat[] = "arm,armv8-pmuv3"; 511 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible", 512 compat, sizeof(compat)); 513 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts", 514 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 515 } 516 } 517 518 static void create_its(VirtMachineState *vms, DeviceState *gicdev) 519 { 520 const char *itsclass = its_class_name(); 521 DeviceState *dev; 522 523 if (!itsclass) { 524 /* Do nothing if not supported */ 525 return; 526 } 527 528 dev = qdev_create(NULL, itsclass); 529 530 object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3", 531 &error_abort); 532 qdev_init_nofail(dev); 533 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 534 535 fdt_add_its_gic_node(vms); 536 } 537 538 static void create_v2m(VirtMachineState *vms, qemu_irq *pic) 539 { 540 int i; 541 int irq = vms->irqmap[VIRT_GIC_V2M]; 542 DeviceState *dev; 543 544 dev = qdev_create(NULL, "arm-gicv2m"); 545 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 546 qdev_prop_set_uint32(dev, "base-spi", irq); 547 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 548 qdev_init_nofail(dev); 549 550 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 551 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 552 } 553 554 fdt_add_v2m_gic_node(vms); 555 } 556 557 static void create_gic(VirtMachineState *vms, qemu_irq *pic) 558 { 559 /* We create a standalone GIC */ 560 DeviceState *gicdev; 561 SysBusDevice *gicbusdev; 562 const char *gictype; 563 int type = vms->gic_version, i; 564 uint32_t nb_redist_regions = 0; 565 566 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 567 568 gicdev = qdev_create(NULL, gictype); 569 qdev_prop_set_uint32(gicdev, "revision", type); 570 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 571 /* Note that the num-irq property counts both internal and external 572 * interrupts; there are always 32 of the former (mandated by GIC spec). 573 */ 574 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 575 if (!kvm_irqchip_in_kernel()) { 576 qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure); 577 } 578 579 if (type == 3) { 580 uint32_t redist0_capacity = 581 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 582 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 583 584 nb_redist_regions = virt_gicv3_redist_region_count(vms); 585 586 qdev_prop_set_uint32(gicdev, "len-redist-region-count", 587 nb_redist_regions); 588 qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count); 589 590 if (nb_redist_regions == 2) { 591 uint32_t redist1_capacity = 592 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; 593 594 qdev_prop_set_uint32(gicdev, "redist-region-count[1]", 595 MIN(smp_cpus - redist0_count, redist1_capacity)); 596 } 597 } else { 598 if (!kvm_irqchip_in_kernel()) { 599 qdev_prop_set_bit(gicdev, "has-virtualization-extensions", 600 vms->virt); 601 } 602 } 603 qdev_init_nofail(gicdev); 604 gicbusdev = SYS_BUS_DEVICE(gicdev); 605 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 606 if (type == 3) { 607 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 608 if (nb_redist_regions == 2) { 609 sysbus_mmio_map(gicbusdev, 2, 610 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 611 } 612 } else { 613 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 614 if (vms->virt) { 615 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 616 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 617 } 618 } 619 620 /* Wire the outputs from each CPU's generic timer and the GICv3 621 * maintenance interrupt signal to the appropriate GIC PPI inputs, 622 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 623 */ 624 for (i = 0; i < smp_cpus; i++) { 625 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 626 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 627 int irq; 628 /* Mapping from the output timer irq lines from the CPU to the 629 * GIC PPI inputs we use for the virt board. 630 */ 631 const int timer_irq[] = { 632 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 633 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 634 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 635 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 636 }; 637 638 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 639 qdev_connect_gpio_out(cpudev, irq, 640 qdev_get_gpio_in(gicdev, 641 ppibase + timer_irq[irq])); 642 } 643 644 if (type == 3) { 645 qemu_irq irq = qdev_get_gpio_in(gicdev, 646 ppibase + ARCH_GIC_MAINT_IRQ); 647 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 648 0, irq); 649 } else if (vms->virt) { 650 qemu_irq irq = qdev_get_gpio_in(gicdev, 651 ppibase + ARCH_GIC_MAINT_IRQ); 652 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 653 } 654 655 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 656 qdev_get_gpio_in(gicdev, ppibase 657 + VIRTUAL_PMU_IRQ)); 658 659 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 660 sysbus_connect_irq(gicbusdev, i + smp_cpus, 661 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 662 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 663 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 664 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 665 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 666 } 667 668 for (i = 0; i < NUM_IRQS; i++) { 669 pic[i] = qdev_get_gpio_in(gicdev, i); 670 } 671 672 fdt_add_gic_node(vms); 673 674 if (type == 3 && vms->its) { 675 create_its(vms, gicdev); 676 } else if (type == 2) { 677 create_v2m(vms, pic); 678 } 679 } 680 681 static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart, 682 MemoryRegion *mem, Chardev *chr) 683 { 684 char *nodename; 685 hwaddr base = vms->memmap[uart].base; 686 hwaddr size = vms->memmap[uart].size; 687 int irq = vms->irqmap[uart]; 688 const char compat[] = "arm,pl011\0arm,primecell"; 689 const char clocknames[] = "uartclk\0apb_pclk"; 690 DeviceState *dev = qdev_create(NULL, "pl011"); 691 SysBusDevice *s = SYS_BUS_DEVICE(dev); 692 693 qdev_prop_set_chr(dev, "chardev", chr); 694 qdev_init_nofail(dev); 695 memory_region_add_subregion(mem, base, 696 sysbus_mmio_get_region(s, 0)); 697 sysbus_connect_irq(s, 0, pic[irq]); 698 699 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 700 qemu_fdt_add_subnode(vms->fdt, nodename); 701 /* Note that we can't use setprop_string because of the embedded NUL */ 702 qemu_fdt_setprop(vms->fdt, nodename, "compatible", 703 compat, sizeof(compat)); 704 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 705 2, base, 2, size); 706 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 707 GIC_FDT_IRQ_TYPE_SPI, irq, 708 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 709 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks", 710 vms->clock_phandle, vms->clock_phandle); 711 qemu_fdt_setprop(vms->fdt, nodename, "clock-names", 712 clocknames, sizeof(clocknames)); 713 714 if (uart == VIRT_UART) { 715 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); 716 } else { 717 /* Mark as not usable by the normal world */ 718 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 719 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 720 721 qemu_fdt_add_subnode(vms->fdt, "/secure-chosen"); 722 qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path", 723 nodename); 724 } 725 726 g_free(nodename); 727 } 728 729 static void create_rtc(const VirtMachineState *vms, qemu_irq *pic) 730 { 731 char *nodename; 732 hwaddr base = vms->memmap[VIRT_RTC].base; 733 hwaddr size = vms->memmap[VIRT_RTC].size; 734 int irq = vms->irqmap[VIRT_RTC]; 735 const char compat[] = "arm,pl031\0arm,primecell"; 736 737 sysbus_create_simple("pl031", base, pic[irq]); 738 739 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 740 qemu_fdt_add_subnode(vms->fdt, nodename); 741 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 742 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 743 2, base, 2, size); 744 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 745 GIC_FDT_IRQ_TYPE_SPI, irq, 746 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 747 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 748 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 749 g_free(nodename); 750 } 751 752 static DeviceState *gpio_key_dev; 753 static void virt_powerdown_req(Notifier *n, void *opaque) 754 { 755 /* use gpio Pin 3 for power button event */ 756 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 757 } 758 759 static Notifier virt_system_powerdown_notifier = { 760 .notify = virt_powerdown_req 761 }; 762 763 static void create_gpio(const VirtMachineState *vms, qemu_irq *pic) 764 { 765 char *nodename; 766 DeviceState *pl061_dev; 767 hwaddr base = vms->memmap[VIRT_GPIO].base; 768 hwaddr size = vms->memmap[VIRT_GPIO].size; 769 int irq = vms->irqmap[VIRT_GPIO]; 770 const char compat[] = "arm,pl061\0arm,primecell"; 771 772 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); 773 774 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); 775 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 776 qemu_fdt_add_subnode(vms->fdt, nodename); 777 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 778 2, base, 2, size); 779 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 780 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); 781 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); 782 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 783 GIC_FDT_IRQ_TYPE_SPI, irq, 784 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 785 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 786 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 787 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); 788 789 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 790 qdev_get_gpio_in(pl061_dev, 3)); 791 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); 792 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); 793 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); 794 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); 795 796 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); 797 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", 798 "label", "GPIO Key Poweroff"); 799 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", 800 KEY_POWER); 801 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", 802 "gpios", phandle, 3, 0); 803 804 /* connect powerdown request */ 805 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier); 806 807 g_free(nodename); 808 } 809 810 static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic) 811 { 812 int i; 813 hwaddr size = vms->memmap[VIRT_MMIO].size; 814 815 /* We create the transports in forwards order. Since qbus_realize() 816 * prepends (not appends) new child buses, the incrementing loop below will 817 * create a list of virtio-mmio buses with decreasing base addresses. 818 * 819 * When a -device option is processed from the command line, 820 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 821 * order. The upshot is that -device options in increasing command line 822 * order are mapped to virtio-mmio buses with decreasing base addresses. 823 * 824 * When this code was originally written, that arrangement ensured that the 825 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 826 * the first -device on the command line. (The end-to-end order is a 827 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 828 * guest kernel's name-to-address assignment strategy.) 829 * 830 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 831 * the message, if not necessarily the code, of commit 70161ff336. 832 * Therefore the loop now establishes the inverse of the original intent. 833 * 834 * Unfortunately, we can't counteract the kernel change by reversing the 835 * loop; it would break existing command lines. 836 * 837 * In any case, the kernel makes no guarantee about the stability of 838 * enumeration order of virtio devices (as demonstrated by it changing 839 * between kernel versions). For reliable and stable identification 840 * of disks users must use UUIDs or similar mechanisms. 841 */ 842 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 843 int irq = vms->irqmap[VIRT_MMIO] + i; 844 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 845 846 sysbus_create_simple("virtio-mmio", base, pic[irq]); 847 } 848 849 /* We add dtb nodes in reverse order so that they appear in the finished 850 * device tree lowest address first. 851 * 852 * Note that this mapping is independent of the loop above. The previous 853 * loop influences virtio device to virtio transport assignment, whereas 854 * this loop controls how virtio transports are laid out in the dtb. 855 */ 856 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 857 char *nodename; 858 int irq = vms->irqmap[VIRT_MMIO] + i; 859 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 860 861 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 862 qemu_fdt_add_subnode(vms->fdt, nodename); 863 qemu_fdt_setprop_string(vms->fdt, nodename, 864 "compatible", "virtio,mmio"); 865 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 866 2, base, 2, size); 867 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 868 GIC_FDT_IRQ_TYPE_SPI, irq, 869 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 870 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 871 g_free(nodename); 872 } 873 } 874 875 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 876 877 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 878 const char *name, 879 const char *alias_prop_name) 880 { 881 /* 882 * Create a single flash device. We use the same parameters as 883 * the flash devices on the Versatile Express board. 884 */ 885 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01); 886 887 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 888 qdev_prop_set_uint8(dev, "width", 4); 889 qdev_prop_set_uint8(dev, "device-width", 2); 890 qdev_prop_set_bit(dev, "big-endian", false); 891 qdev_prop_set_uint16(dev, "id0", 0x89); 892 qdev_prop_set_uint16(dev, "id1", 0x18); 893 qdev_prop_set_uint16(dev, "id2", 0x00); 894 qdev_prop_set_uint16(dev, "id3", 0x00); 895 qdev_prop_set_string(dev, "name", name); 896 object_property_add_child(OBJECT(vms), name, OBJECT(dev), 897 &error_abort); 898 object_property_add_alias(OBJECT(vms), alias_prop_name, 899 OBJECT(dev), "drive", &error_abort); 900 return PFLASH_CFI01(dev); 901 } 902 903 static void virt_flash_create(VirtMachineState *vms) 904 { 905 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 906 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 907 } 908 909 static void virt_flash_map1(PFlashCFI01 *flash, 910 hwaddr base, hwaddr size, 911 MemoryRegion *sysmem) 912 { 913 DeviceState *dev = DEVICE(flash); 914 915 assert(size % VIRT_FLASH_SECTOR_SIZE == 0); 916 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 917 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 918 qdev_init_nofail(dev); 919 920 memory_region_add_subregion(sysmem, base, 921 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 922 0)); 923 } 924 925 static void virt_flash_map(VirtMachineState *vms, 926 MemoryRegion *sysmem, 927 MemoryRegion *secure_sysmem) 928 { 929 /* 930 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 931 * sysmem is the system memory space. secure_sysmem is the secure view 932 * of the system, and the first flash device should be made visible only 933 * there. The second flash device is visible to both secure and nonsecure. 934 * If sysmem == secure_sysmem this means there is no separate Secure 935 * address space and both flash devices are generally visible. 936 */ 937 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 938 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 939 940 virt_flash_map1(vms->flash[0], flashbase, flashsize, 941 secure_sysmem); 942 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 943 sysmem); 944 } 945 946 static void virt_flash_fdt(VirtMachineState *vms, 947 MemoryRegion *sysmem, 948 MemoryRegion *secure_sysmem) 949 { 950 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 951 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 952 char *nodename; 953 954 if (sysmem == secure_sysmem) { 955 /* Report both flash devices as a single node in the DT */ 956 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 957 qemu_fdt_add_subnode(vms->fdt, nodename); 958 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 959 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 960 2, flashbase, 2, flashsize, 961 2, flashbase + flashsize, 2, flashsize); 962 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 963 g_free(nodename); 964 } else { 965 /* 966 * Report the devices as separate nodes so we can mark one as 967 * only visible to the secure world. 968 */ 969 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 970 qemu_fdt_add_subnode(vms->fdt, nodename); 971 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 972 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 973 2, flashbase, 2, flashsize); 974 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 975 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 976 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 977 g_free(nodename); 978 979 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 980 qemu_fdt_add_subnode(vms->fdt, nodename); 981 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 982 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 983 2, flashbase + flashsize, 2, flashsize); 984 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 985 g_free(nodename); 986 } 987 } 988 989 static bool virt_firmware_init(VirtMachineState *vms, 990 MemoryRegion *sysmem, 991 MemoryRegion *secure_sysmem) 992 { 993 int i; 994 BlockBackend *pflash_blk0; 995 996 /* Map legacy -drive if=pflash to machine properties */ 997 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 998 pflash_cfi01_legacy_drive(vms->flash[i], 999 drive_get(IF_PFLASH, 0, i)); 1000 } 1001 1002 virt_flash_map(vms, sysmem, secure_sysmem); 1003 1004 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1005 1006 if (bios_name) { 1007 char *fname; 1008 MemoryRegion *mr; 1009 int image_size; 1010 1011 if (pflash_blk0) { 1012 error_report("The contents of the first flash device may be " 1013 "specified with -bios or with -drive if=pflash... " 1014 "but you cannot use both options at once"); 1015 exit(1); 1016 } 1017 1018 /* Fall back to -bios */ 1019 1020 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1021 if (!fname) { 1022 error_report("Could not find ROM image '%s'", bios_name); 1023 exit(1); 1024 } 1025 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1026 image_size = load_image_mr(fname, mr); 1027 g_free(fname); 1028 if (image_size < 0) { 1029 error_report("Could not load ROM image '%s'", bios_name); 1030 exit(1); 1031 } 1032 } 1033 1034 return pflash_blk0 || bios_name; 1035 } 1036 1037 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1038 { 1039 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1040 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1041 FWCfgState *fw_cfg; 1042 char *nodename; 1043 1044 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1045 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 1046 1047 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1048 qemu_fdt_add_subnode(vms->fdt, nodename); 1049 qemu_fdt_setprop_string(vms->fdt, nodename, 1050 "compatible", "qemu,fw-cfg-mmio"); 1051 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1052 2, base, 2, size); 1053 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1054 g_free(nodename); 1055 return fw_cfg; 1056 } 1057 1058 static void create_pcie_irq_map(const VirtMachineState *vms, 1059 uint32_t gic_phandle, 1060 int first_irq, const char *nodename) 1061 { 1062 int devfn, pin; 1063 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1064 uint32_t *irq_map = full_irq_map; 1065 1066 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1067 for (pin = 0; pin < 4; pin++) { 1068 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1069 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1070 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1071 int i; 1072 1073 uint32_t map[] = { 1074 devfn << 8, 0, 0, /* devfn */ 1075 pin + 1, /* PCI pin */ 1076 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1077 1078 /* Convert map to big endian */ 1079 for (i = 0; i < 10; i++) { 1080 irq_map[i] = cpu_to_be32(map[i]); 1081 } 1082 irq_map += 10; 1083 } 1084 } 1085 1086 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map", 1087 full_irq_map, sizeof(full_irq_map)); 1088 1089 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask", 1090 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 1091 0x7 /* PCI irq */); 1092 } 1093 1094 static void create_smmu(const VirtMachineState *vms, qemu_irq *pic, 1095 PCIBus *bus) 1096 { 1097 char *node; 1098 const char compat[] = "arm,smmu-v3"; 1099 int irq = vms->irqmap[VIRT_SMMU]; 1100 int i; 1101 hwaddr base = vms->memmap[VIRT_SMMU].base; 1102 hwaddr size = vms->memmap[VIRT_SMMU].size; 1103 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1104 DeviceState *dev; 1105 1106 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1107 return; 1108 } 1109 1110 dev = qdev_create(NULL, "arm-smmuv3"); 1111 1112 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", 1113 &error_abort); 1114 qdev_init_nofail(dev); 1115 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1116 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1117 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 1118 } 1119 1120 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1121 qemu_fdt_add_subnode(vms->fdt, node); 1122 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat)); 1123 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size); 1124 1125 qemu_fdt_setprop_cells(vms->fdt, node, "interrupts", 1126 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1127 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1128 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1129 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1130 1131 qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names, 1132 sizeof(irq_names)); 1133 1134 qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle); 1135 qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk"); 1136 qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0); 1137 1138 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1); 1139 1140 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle); 1141 g_free(node); 1142 } 1143 1144 static void create_pcie(VirtMachineState *vms, qemu_irq *pic) 1145 { 1146 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1147 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1148 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1149 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1150 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1151 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1152 hwaddr base_ecam, size_ecam; 1153 hwaddr base = base_mmio; 1154 int nr_pcie_buses; 1155 int irq = vms->irqmap[VIRT_PCIE]; 1156 MemoryRegion *mmio_alias; 1157 MemoryRegion *mmio_reg; 1158 MemoryRegion *ecam_alias; 1159 MemoryRegion *ecam_reg; 1160 DeviceState *dev; 1161 char *nodename; 1162 int i, ecam_id; 1163 PCIHostState *pci; 1164 1165 dev = qdev_create(NULL, TYPE_GPEX_HOST); 1166 qdev_init_nofail(dev); 1167 1168 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1169 base_ecam = vms->memmap[ecam_id].base; 1170 size_ecam = vms->memmap[ecam_id].size; 1171 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1172 /* Map only the first size_ecam bytes of ECAM space */ 1173 ecam_alias = g_new0(MemoryRegion, 1); 1174 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1175 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1176 ecam_reg, 0, size_ecam); 1177 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1178 1179 /* Map the MMIO window into system address space so as to expose 1180 * the section of PCI MMIO space which starts at the same base address 1181 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1182 * the window). 1183 */ 1184 mmio_alias = g_new0(MemoryRegion, 1); 1185 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1186 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1187 mmio_reg, base_mmio, size_mmio); 1188 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1189 1190 if (vms->highmem) { 1191 /* Map high MMIO space */ 1192 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1193 1194 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1195 mmio_reg, base_mmio_high, size_mmio_high); 1196 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1197 high_mmio_alias); 1198 } 1199 1200 /* Map IO port space */ 1201 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1202 1203 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1204 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 1205 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1206 } 1207 1208 pci = PCI_HOST_BRIDGE(dev); 1209 if (pci->bus) { 1210 for (i = 0; i < nb_nics; i++) { 1211 NICInfo *nd = &nd_table[i]; 1212 1213 if (!nd->model) { 1214 nd->model = g_strdup("virtio"); 1215 } 1216 1217 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1218 } 1219 } 1220 1221 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1222 qemu_fdt_add_subnode(vms->fdt, nodename); 1223 qemu_fdt_setprop_string(vms->fdt, nodename, 1224 "compatible", "pci-host-ecam-generic"); 1225 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci"); 1226 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3); 1227 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2); 1228 qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0); 1229 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0, 1230 nr_pcie_buses - 1); 1231 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1232 1233 if (vms->msi_phandle) { 1234 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", 1235 vms->msi_phandle); 1236 } 1237 1238 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1239 2, base_ecam, 2, size_ecam); 1240 1241 if (vms->highmem) { 1242 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1243 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1244 2, base_pio, 2, size_pio, 1245 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1246 2, base_mmio, 2, size_mmio, 1247 1, FDT_PCI_RANGE_MMIO_64BIT, 1248 2, base_mmio_high, 1249 2, base_mmio_high, 2, size_mmio_high); 1250 } else { 1251 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1252 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1253 2, base_pio, 2, size_pio, 1254 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1255 2, base_mmio, 2, size_mmio); 1256 } 1257 1258 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); 1259 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); 1260 1261 if (vms->iommu) { 1262 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt); 1263 1264 create_smmu(vms, pic, pci->bus); 1265 1266 qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map", 1267 0x0, vms->iommu_phandle, 0x0, 0x10000); 1268 } 1269 1270 g_free(nodename); 1271 } 1272 1273 static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic) 1274 { 1275 DeviceState *dev; 1276 SysBusDevice *s; 1277 int i; 1278 MemoryRegion *sysmem = get_system_memory(); 1279 1280 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1281 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1282 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1283 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1284 qdev_init_nofail(dev); 1285 vms->platform_bus_dev = dev; 1286 1287 s = SYS_BUS_DEVICE(dev); 1288 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1289 int irqn = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1290 sysbus_connect_irq(s, i, pic[irqn]); 1291 } 1292 1293 memory_region_add_subregion(sysmem, 1294 vms->memmap[VIRT_PLATFORM_BUS].base, 1295 sysbus_mmio_get_region(s, 0)); 1296 } 1297 1298 static void create_secure_ram(VirtMachineState *vms, 1299 MemoryRegion *secure_sysmem) 1300 { 1301 MemoryRegion *secram = g_new(MemoryRegion, 1); 1302 char *nodename; 1303 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1304 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1305 1306 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1307 &error_fatal); 1308 memory_region_add_subregion(secure_sysmem, base, secram); 1309 1310 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1311 qemu_fdt_add_subnode(vms->fdt, nodename); 1312 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory"); 1313 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size); 1314 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1315 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1316 1317 g_free(nodename); 1318 } 1319 1320 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1321 { 1322 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1323 bootinfo); 1324 1325 *fdt_size = board->fdt_size; 1326 return board->fdt; 1327 } 1328 1329 static void virt_build_smbios(VirtMachineState *vms) 1330 { 1331 MachineClass *mc = MACHINE_GET_CLASS(vms); 1332 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1333 uint8_t *smbios_tables, *smbios_anchor; 1334 size_t smbios_tables_len, smbios_anchor_len; 1335 const char *product = "QEMU Virtual Machine"; 1336 1337 if (kvm_enabled()) { 1338 product = "KVM Virtual Machine"; 1339 } 1340 1341 smbios_set_defaults("QEMU", product, 1342 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1343 true, SMBIOS_ENTRY_POINT_30); 1344 1345 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, 1346 &smbios_anchor, &smbios_anchor_len); 1347 1348 if (smbios_anchor) { 1349 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1350 smbios_tables, smbios_tables_len); 1351 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1352 smbios_anchor, smbios_anchor_len); 1353 } 1354 } 1355 1356 static 1357 void virt_machine_done(Notifier *notifier, void *data) 1358 { 1359 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1360 machine_done); 1361 ARMCPU *cpu = ARM_CPU(first_cpu); 1362 struct arm_boot_info *info = &vms->bootinfo; 1363 AddressSpace *as = arm_boot_address_space(cpu, info); 1364 1365 /* 1366 * If the user provided a dtb, we assume the dynamic sysbus nodes 1367 * already are integrated there. This corresponds to a use case where 1368 * the dynamic sysbus nodes are complex and their generation is not yet 1369 * supported. In that case the user can take charge of the guest dt 1370 * while qemu takes charge of the qom stuff. 1371 */ 1372 if (info->dtb_filename == NULL) { 1373 platform_bus_add_all_fdt_nodes(vms->fdt, "/intc", 1374 vms->memmap[VIRT_PLATFORM_BUS].base, 1375 vms->memmap[VIRT_PLATFORM_BUS].size, 1376 vms->irqmap[VIRT_PLATFORM_BUS]); 1377 } 1378 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) { 1379 exit(1); 1380 } 1381 1382 virt_acpi_setup(vms); 1383 virt_build_smbios(vms); 1384 } 1385 1386 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1387 { 1388 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1389 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1390 1391 if (!vmc->disallow_affinity_adjustment) { 1392 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1393 * GIC's target-list limitations. 32-bit KVM hosts currently 1394 * always create clusters of 4 CPUs, but that is expected to 1395 * change when they gain support for gicv3. When KVM is enabled 1396 * it will override the changes we make here, therefore our 1397 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1398 * and to improve SGI efficiency. 1399 */ 1400 if (vms->gic_version == 3) { 1401 clustersz = GICV3_TARGETLIST_BITS; 1402 } else { 1403 clustersz = GIC_TARGETLIST_BITS; 1404 } 1405 } 1406 return arm_cpu_mp_affinity(idx, clustersz); 1407 } 1408 1409 static void virt_set_memmap(VirtMachineState *vms) 1410 { 1411 MachineState *ms = MACHINE(vms); 1412 hwaddr base, device_memory_base, device_memory_size; 1413 int i; 1414 1415 vms->memmap = extended_memmap; 1416 1417 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1418 vms->memmap[i] = base_memmap[i]; 1419 } 1420 1421 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1422 error_report("unsupported number of memory slots: %"PRIu64, 1423 ms->ram_slots); 1424 exit(EXIT_FAILURE); 1425 } 1426 1427 /* 1428 * We compute the base of the high IO region depending on the 1429 * amount of initial and device memory. The device memory start/size 1430 * is aligned on 1GiB. We never put the high IO region below 256GiB 1431 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1432 * The device region size assumes 1GiB page max alignment per slot. 1433 */ 1434 device_memory_base = 1435 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1436 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1437 1438 /* Base address of the high IO region */ 1439 base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1440 if (base < device_memory_base) { 1441 error_report("maxmem/slots too huge"); 1442 exit(EXIT_FAILURE); 1443 } 1444 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1445 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1446 } 1447 1448 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1449 hwaddr size = extended_memmap[i].size; 1450 1451 base = ROUND_UP(base, size); 1452 vms->memmap[i].base = base; 1453 vms->memmap[i].size = size; 1454 base += size; 1455 } 1456 vms->highest_gpa = base - 1; 1457 if (device_memory_size > 0) { 1458 ms->device_memory = g_malloc0(sizeof(*ms->device_memory)); 1459 ms->device_memory->base = device_memory_base; 1460 memory_region_init(&ms->device_memory->mr, OBJECT(vms), 1461 "device-memory", device_memory_size); 1462 } 1463 } 1464 1465 static void machvirt_init(MachineState *machine) 1466 { 1467 VirtMachineState *vms = VIRT_MACHINE(machine); 1468 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1469 MachineClass *mc = MACHINE_GET_CLASS(machine); 1470 const CPUArchIdList *possible_cpus; 1471 qemu_irq pic[NUM_IRQS]; 1472 MemoryRegion *sysmem = get_system_memory(); 1473 MemoryRegion *secure_sysmem = NULL; 1474 int n, virt_max_cpus; 1475 MemoryRegion *ram = g_new(MemoryRegion, 1); 1476 bool firmware_loaded; 1477 bool aarch64 = true; 1478 1479 /* 1480 * In accelerated mode, the memory map is computed earlier in kvm_type() 1481 * to create a VM with the right number of IPA bits. 1482 */ 1483 if (!vms->memmap) { 1484 virt_set_memmap(vms); 1485 } 1486 1487 /* We can probe only here because during property set 1488 * KVM is not available yet 1489 */ 1490 if (vms->gic_version <= 0) { 1491 /* "host" or "max" */ 1492 if (!kvm_enabled()) { 1493 if (vms->gic_version == 0) { 1494 error_report("gic-version=host requires KVM"); 1495 exit(1); 1496 } else { 1497 /* "max": currently means 3 for TCG */ 1498 vms->gic_version = 3; 1499 } 1500 } else { 1501 vms->gic_version = kvm_arm_vgic_probe(); 1502 if (!vms->gic_version) { 1503 error_report( 1504 "Unable to determine GIC version supported by host"); 1505 exit(1); 1506 } 1507 } 1508 } 1509 1510 if (!cpu_type_valid(machine->cpu_type)) { 1511 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 1512 exit(1); 1513 } 1514 1515 if (vms->secure) { 1516 if (kvm_enabled()) { 1517 error_report("mach-virt: KVM does not support Security extensions"); 1518 exit(1); 1519 } 1520 1521 /* 1522 * The Secure view of the world is the same as the NonSecure, 1523 * but with a few extra devices. Create it as a container region 1524 * containing the system memory at low priority; any secure-only 1525 * devices go in at higher priority and take precedence. 1526 */ 1527 secure_sysmem = g_new(MemoryRegion, 1); 1528 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1529 UINT64_MAX); 1530 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1531 } 1532 1533 firmware_loaded = virt_firmware_init(vms, sysmem, 1534 secure_sysmem ?: sysmem); 1535 1536 /* If we have an EL3 boot ROM then the assumption is that it will 1537 * implement PSCI itself, so disable QEMU's internal implementation 1538 * so it doesn't get in the way. Instead of starting secondary 1539 * CPUs in PSCI powerdown state we will start them all running and 1540 * let the boot ROM sort them out. 1541 * The usual case is that we do use QEMU's PSCI implementation; 1542 * if the guest has EL2 then we will use SMC as the conduit, 1543 * and otherwise we will use HVC (for backwards compatibility and 1544 * because if we're using KVM then we must use HVC). 1545 */ 1546 if (vms->secure && firmware_loaded) { 1547 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1548 } else if (vms->virt) { 1549 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 1550 } else { 1551 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 1552 } 1553 1554 /* The maximum number of CPUs depends on the GIC version, or on how 1555 * many redistributors we can fit into the memory map. 1556 */ 1557 if (vms->gic_version == 3) { 1558 virt_max_cpus = 1559 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 1560 virt_max_cpus += 1561 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; 1562 } else { 1563 virt_max_cpus = GIC_NCPU; 1564 } 1565 1566 if (max_cpus > virt_max_cpus) { 1567 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1568 "supported by machine 'mach-virt' (%d)", 1569 max_cpus, virt_max_cpus); 1570 exit(1); 1571 } 1572 1573 vms->smp_cpus = smp_cpus; 1574 1575 if (vms->virt && kvm_enabled()) { 1576 error_report("mach-virt: KVM does not support providing " 1577 "Virtualization extensions to the guest CPU"); 1578 exit(1); 1579 } 1580 1581 create_fdt(vms); 1582 1583 possible_cpus = mc->possible_cpu_arch_ids(machine); 1584 for (n = 0; n < possible_cpus->len; n++) { 1585 Object *cpuobj; 1586 CPUState *cs; 1587 1588 if (n >= smp_cpus) { 1589 break; 1590 } 1591 1592 cpuobj = object_new(possible_cpus->cpus[n].type); 1593 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 1594 "mp-affinity", NULL); 1595 1596 cs = CPU(cpuobj); 1597 cs->cpu_index = n; 1598 1599 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 1600 &error_fatal); 1601 1602 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 1603 1604 if (!vms->secure) { 1605 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1606 } 1607 1608 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { 1609 object_property_set_bool(cpuobj, false, "has_el2", NULL); 1610 } 1611 1612 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1613 object_property_set_int(cpuobj, vms->psci_conduit, 1614 "psci-conduit", NULL); 1615 1616 /* Secondary CPUs start in PSCI powered-down state */ 1617 if (n > 0) { 1618 object_property_set_bool(cpuobj, true, 1619 "start-powered-off", NULL); 1620 } 1621 } 1622 1623 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { 1624 object_property_set_bool(cpuobj, false, "pmu", NULL); 1625 } 1626 1627 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1628 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, 1629 "reset-cbar", &error_abort); 1630 } 1631 1632 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1633 &error_abort); 1634 if (vms->secure) { 1635 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1636 "secure-memory", &error_abort); 1637 } 1638 1639 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 1640 object_unref(cpuobj); 1641 } 1642 fdt_add_timer_nodes(vms); 1643 fdt_add_cpu_nodes(vms); 1644 1645 if (!kvm_enabled()) { 1646 ARMCPU *cpu = ARM_CPU(first_cpu); 1647 bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL); 1648 1649 if (aarch64 && vms->highmem) { 1650 int requested_pa_size, pamax = arm_pamax(cpu); 1651 1652 requested_pa_size = 64 - clz64(vms->highest_gpa); 1653 if (pamax < requested_pa_size) { 1654 error_report("VCPU supports less PA bits (%d) than requested " 1655 "by the memory map (%d)", pamax, requested_pa_size); 1656 exit(1); 1657 } 1658 } 1659 } 1660 1661 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", 1662 machine->ram_size); 1663 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); 1664 if (machine->device_memory) { 1665 memory_region_add_subregion(sysmem, machine->device_memory->base, 1666 &machine->device_memory->mr); 1667 } 1668 1669 virt_flash_fdt(vms, sysmem, secure_sysmem); 1670 1671 create_gic(vms, pic); 1672 1673 fdt_add_pmu_nodes(vms); 1674 1675 create_uart(vms, pic, VIRT_UART, sysmem, serial_hd(0)); 1676 1677 if (vms->secure) { 1678 create_secure_ram(vms, secure_sysmem); 1679 create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 1680 } 1681 1682 vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64); 1683 1684 create_rtc(vms, pic); 1685 1686 create_pcie(vms, pic); 1687 1688 create_gpio(vms, pic); 1689 1690 /* Create mmio transports, so the user can create virtio backends 1691 * (which will be automatically plugged in to the transports). If 1692 * no backend is created the transport will just sit harmlessly idle. 1693 */ 1694 create_virtio_devices(vms, pic); 1695 1696 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 1697 rom_set_fw(vms->fw_cfg); 1698 1699 create_platform_bus(vms, pic); 1700 1701 vms->bootinfo.ram_size = machine->ram_size; 1702 vms->bootinfo.kernel_filename = machine->kernel_filename; 1703 vms->bootinfo.kernel_cmdline = machine->kernel_cmdline; 1704 vms->bootinfo.initrd_filename = machine->initrd_filename; 1705 vms->bootinfo.nb_cpus = smp_cpus; 1706 vms->bootinfo.board_id = -1; 1707 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 1708 vms->bootinfo.get_dtb = machvirt_dtb; 1709 vms->bootinfo.skip_dtb_autoload = true; 1710 vms->bootinfo.firmware_loaded = firmware_loaded; 1711 arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo); 1712 1713 vms->machine_done.notify = virt_machine_done; 1714 qemu_add_machine_init_done_notifier(&vms->machine_done); 1715 } 1716 1717 static bool virt_get_secure(Object *obj, Error **errp) 1718 { 1719 VirtMachineState *vms = VIRT_MACHINE(obj); 1720 1721 return vms->secure; 1722 } 1723 1724 static void virt_set_secure(Object *obj, bool value, Error **errp) 1725 { 1726 VirtMachineState *vms = VIRT_MACHINE(obj); 1727 1728 vms->secure = value; 1729 } 1730 1731 static bool virt_get_virt(Object *obj, Error **errp) 1732 { 1733 VirtMachineState *vms = VIRT_MACHINE(obj); 1734 1735 return vms->virt; 1736 } 1737 1738 static void virt_set_virt(Object *obj, bool value, Error **errp) 1739 { 1740 VirtMachineState *vms = VIRT_MACHINE(obj); 1741 1742 vms->virt = value; 1743 } 1744 1745 static bool virt_get_highmem(Object *obj, Error **errp) 1746 { 1747 VirtMachineState *vms = VIRT_MACHINE(obj); 1748 1749 return vms->highmem; 1750 } 1751 1752 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1753 { 1754 VirtMachineState *vms = VIRT_MACHINE(obj); 1755 1756 vms->highmem = value; 1757 } 1758 1759 static bool virt_get_its(Object *obj, Error **errp) 1760 { 1761 VirtMachineState *vms = VIRT_MACHINE(obj); 1762 1763 return vms->its; 1764 } 1765 1766 static void virt_set_its(Object *obj, bool value, Error **errp) 1767 { 1768 VirtMachineState *vms = VIRT_MACHINE(obj); 1769 1770 vms->its = value; 1771 } 1772 1773 static char *virt_get_gic_version(Object *obj, Error **errp) 1774 { 1775 VirtMachineState *vms = VIRT_MACHINE(obj); 1776 const char *val = vms->gic_version == 3 ? "3" : "2"; 1777 1778 return g_strdup(val); 1779 } 1780 1781 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 1782 { 1783 VirtMachineState *vms = VIRT_MACHINE(obj); 1784 1785 if (!strcmp(value, "3")) { 1786 vms->gic_version = 3; 1787 } else if (!strcmp(value, "2")) { 1788 vms->gic_version = 2; 1789 } else if (!strcmp(value, "host")) { 1790 vms->gic_version = 0; /* Will probe later */ 1791 } else if (!strcmp(value, "max")) { 1792 vms->gic_version = -1; /* Will probe later */ 1793 } else { 1794 error_setg(errp, "Invalid gic-version value"); 1795 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 1796 } 1797 } 1798 1799 static char *virt_get_iommu(Object *obj, Error **errp) 1800 { 1801 VirtMachineState *vms = VIRT_MACHINE(obj); 1802 1803 switch (vms->iommu) { 1804 case VIRT_IOMMU_NONE: 1805 return g_strdup("none"); 1806 case VIRT_IOMMU_SMMUV3: 1807 return g_strdup("smmuv3"); 1808 default: 1809 g_assert_not_reached(); 1810 } 1811 } 1812 1813 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 1814 { 1815 VirtMachineState *vms = VIRT_MACHINE(obj); 1816 1817 if (!strcmp(value, "smmuv3")) { 1818 vms->iommu = VIRT_IOMMU_SMMUV3; 1819 } else if (!strcmp(value, "none")) { 1820 vms->iommu = VIRT_IOMMU_NONE; 1821 } else { 1822 error_setg(errp, "Invalid iommu value"); 1823 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 1824 } 1825 } 1826 1827 static CpuInstanceProperties 1828 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1829 { 1830 MachineClass *mc = MACHINE_GET_CLASS(ms); 1831 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1832 1833 assert(cpu_index < possible_cpus->len); 1834 return possible_cpus->cpus[cpu_index].props; 1835 } 1836 1837 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1838 { 1839 return idx % nb_numa_nodes; 1840 } 1841 1842 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1843 { 1844 int n; 1845 VirtMachineState *vms = VIRT_MACHINE(ms); 1846 1847 if (ms->possible_cpus) { 1848 assert(ms->possible_cpus->len == max_cpus); 1849 return ms->possible_cpus; 1850 } 1851 1852 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1853 sizeof(CPUArchId) * max_cpus); 1854 ms->possible_cpus->len = max_cpus; 1855 for (n = 0; n < ms->possible_cpus->len; n++) { 1856 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1857 ms->possible_cpus->cpus[n].arch_id = 1858 virt_cpu_mp_affinity(vms, n); 1859 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1860 ms->possible_cpus->cpus[n].props.thread_id = n; 1861 } 1862 return ms->possible_cpus; 1863 } 1864 1865 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1866 DeviceState *dev, Error **errp) 1867 { 1868 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 1869 1870 if (vms->platform_bus_dev) { 1871 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) { 1872 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 1873 SYS_BUS_DEVICE(dev)); 1874 } 1875 } 1876 } 1877 1878 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1879 DeviceState *dev) 1880 { 1881 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) { 1882 return HOTPLUG_HANDLER(machine); 1883 } 1884 1885 return NULL; 1886 } 1887 1888 /* 1889 * for arm64 kvm_type [7-0] encodes the requested number of bits 1890 * in the IPA address space 1891 */ 1892 static int virt_kvm_type(MachineState *ms, const char *type_str) 1893 { 1894 VirtMachineState *vms = VIRT_MACHINE(ms); 1895 int max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms); 1896 int requested_pa_size; 1897 1898 /* we freeze the memory map to compute the highest gpa */ 1899 virt_set_memmap(vms); 1900 1901 requested_pa_size = 64 - clz64(vms->highest_gpa); 1902 1903 if (requested_pa_size > max_vm_pa_size) { 1904 error_report("-m and ,maxmem option values " 1905 "require an IPA range (%d bits) larger than " 1906 "the one supported by the host (%d bits)", 1907 requested_pa_size, max_vm_pa_size); 1908 exit(1); 1909 } 1910 /* 1911 * By default we return 0 which corresponds to an implicit legacy 1912 * 40b IPA setting. Otherwise we return the actual requested PA 1913 * logsize 1914 */ 1915 return requested_pa_size > 40 ? requested_pa_size : 0; 1916 } 1917 1918 static void virt_machine_class_init(ObjectClass *oc, void *data) 1919 { 1920 MachineClass *mc = MACHINE_CLASS(oc); 1921 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1922 1923 mc->init = machvirt_init; 1924 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 1925 * The value may be reduced later when we have more information about the 1926 * configuration of the particular instance. 1927 */ 1928 mc->max_cpus = 512; 1929 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 1930 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 1931 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1932 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 1933 mc->block_default_type = IF_VIRTIO; 1934 mc->no_cdrom = 1; 1935 mc->pci_allow_0_address = true; 1936 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 1937 mc->minimum_page_bits = 12; 1938 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1939 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1940 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 1941 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1942 mc->kvm_type = virt_kvm_type; 1943 assert(!mc->get_hotplug_handler); 1944 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1945 hc->plug = virt_machine_device_plug_cb; 1946 } 1947 1948 static void virt_instance_init(Object *obj) 1949 { 1950 VirtMachineState *vms = VIRT_MACHINE(obj); 1951 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1952 1953 /* EL3 is disabled by default on virt: this makes us consistent 1954 * between KVM and TCG for this board, and it also allows us to 1955 * boot UEFI blobs which assume no TrustZone support. 1956 */ 1957 vms->secure = false; 1958 object_property_add_bool(obj, "secure", virt_get_secure, 1959 virt_set_secure, NULL); 1960 object_property_set_description(obj, "secure", 1961 "Set on/off to enable/disable the ARM " 1962 "Security Extensions (TrustZone)", 1963 NULL); 1964 1965 /* EL2 is also disabled by default, for similar reasons */ 1966 vms->virt = false; 1967 object_property_add_bool(obj, "virtualization", virt_get_virt, 1968 virt_set_virt, NULL); 1969 object_property_set_description(obj, "virtualization", 1970 "Set on/off to enable/disable emulating a " 1971 "guest CPU which implements the ARM " 1972 "Virtualization Extensions", 1973 NULL); 1974 1975 /* High memory is enabled by default */ 1976 vms->highmem = true; 1977 object_property_add_bool(obj, "highmem", virt_get_highmem, 1978 virt_set_highmem, NULL); 1979 object_property_set_description(obj, "highmem", 1980 "Set on/off to enable/disable using " 1981 "physical address space above 32 bits", 1982 NULL); 1983 /* Default GIC type is v2 */ 1984 vms->gic_version = 2; 1985 object_property_add_str(obj, "gic-version", virt_get_gic_version, 1986 virt_set_gic_version, NULL); 1987 object_property_set_description(obj, "gic-version", 1988 "Set GIC version. " 1989 "Valid values are 2, 3 and host", NULL); 1990 1991 vms->highmem_ecam = !vmc->no_highmem_ecam; 1992 1993 if (vmc->no_its) { 1994 vms->its = false; 1995 } else { 1996 /* Default allows ITS instantiation */ 1997 vms->its = true; 1998 object_property_add_bool(obj, "its", virt_get_its, 1999 virt_set_its, NULL); 2000 object_property_set_description(obj, "its", 2001 "Set on/off to enable/disable " 2002 "ITS instantiation", 2003 NULL); 2004 } 2005 2006 /* Default disallows iommu instantiation */ 2007 vms->iommu = VIRT_IOMMU_NONE; 2008 object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu, NULL); 2009 object_property_set_description(obj, "iommu", 2010 "Set the IOMMU type. " 2011 "Valid values are none and smmuv3", 2012 NULL); 2013 2014 vms->irqmap = a15irqmap; 2015 2016 virt_flash_create(vms); 2017 } 2018 2019 static const TypeInfo virt_machine_info = { 2020 .name = TYPE_VIRT_MACHINE, 2021 .parent = TYPE_MACHINE, 2022 .abstract = true, 2023 .instance_size = sizeof(VirtMachineState), 2024 .class_size = sizeof(VirtMachineClass), 2025 .class_init = virt_machine_class_init, 2026 .instance_init = virt_instance_init, 2027 .interfaces = (InterfaceInfo[]) { 2028 { TYPE_HOTPLUG_HANDLER }, 2029 { } 2030 }, 2031 }; 2032 2033 static void machvirt_machine_init(void) 2034 { 2035 type_register_static(&virt_machine_info); 2036 } 2037 type_init(machvirt_machine_init); 2038 2039 static void virt_machine_4_1_options(MachineClass *mc) 2040 { 2041 } 2042 DEFINE_VIRT_MACHINE_AS_LATEST(4, 1) 2043 2044 static void virt_machine_4_0_options(MachineClass *mc) 2045 { 2046 virt_machine_4_1_options(mc); 2047 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 2048 } 2049 DEFINE_VIRT_MACHINE(4, 0) 2050 2051 static void virt_machine_3_1_options(MachineClass *mc) 2052 { 2053 virt_machine_4_0_options(mc); 2054 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 2055 } 2056 DEFINE_VIRT_MACHINE(3, 1) 2057 2058 static void virt_machine_3_0_options(MachineClass *mc) 2059 { 2060 virt_machine_3_1_options(mc); 2061 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 2062 } 2063 DEFINE_VIRT_MACHINE(3, 0) 2064 2065 static void virt_machine_2_12_options(MachineClass *mc) 2066 { 2067 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2068 2069 virt_machine_3_0_options(mc); 2070 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 2071 vmc->no_highmem_ecam = true; 2072 mc->max_cpus = 255; 2073 } 2074 DEFINE_VIRT_MACHINE(2, 12) 2075 2076 static void virt_machine_2_11_options(MachineClass *mc) 2077 { 2078 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2079 2080 virt_machine_2_12_options(mc); 2081 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 2082 vmc->smbios_old_sys_ver = true; 2083 } 2084 DEFINE_VIRT_MACHINE(2, 11) 2085 2086 static void virt_machine_2_10_options(MachineClass *mc) 2087 { 2088 virt_machine_2_11_options(mc); 2089 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 2090 /* before 2.11 we never faulted accesses to bad addresses */ 2091 mc->ignore_memory_transaction_failures = true; 2092 } 2093 DEFINE_VIRT_MACHINE(2, 10) 2094 2095 static void virt_machine_2_9_options(MachineClass *mc) 2096 { 2097 virt_machine_2_10_options(mc); 2098 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 2099 } 2100 DEFINE_VIRT_MACHINE(2, 9) 2101 2102 static void virt_machine_2_8_options(MachineClass *mc) 2103 { 2104 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2105 2106 virt_machine_2_9_options(mc); 2107 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 2108 /* For 2.8 and earlier we falsely claimed in the DT that 2109 * our timers were edge-triggered, not level-triggered. 2110 */ 2111 vmc->claim_edge_triggered_timers = true; 2112 } 2113 DEFINE_VIRT_MACHINE(2, 8) 2114 2115 static void virt_machine_2_7_options(MachineClass *mc) 2116 { 2117 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2118 2119 virt_machine_2_8_options(mc); 2120 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 2121 /* ITS was introduced with 2.8 */ 2122 vmc->no_its = true; 2123 /* Stick with 1K pages for migration compatibility */ 2124 mc->minimum_page_bits = 0; 2125 } 2126 DEFINE_VIRT_MACHINE(2, 7) 2127 2128 static void virt_machine_2_6_options(MachineClass *mc) 2129 { 2130 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2131 2132 virt_machine_2_7_options(mc); 2133 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 2134 vmc->disallow_affinity_adjustment = true; 2135 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 2136 vmc->no_pmu = true; 2137 } 2138 DEFINE_VIRT_MACHINE(2, 6) 2139