1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qapi/error.h" 33 #include "hw/sysbus.h" 34 #include "hw/arm/arm.h" 35 #include "hw/arm/primecell.h" 36 #include "hw/arm/virt.h" 37 #include "hw/devices.h" 38 #include "net/net.h" 39 #include "sysemu/block-backend.h" 40 #include "sysemu/device_tree.h" 41 #include "sysemu/numa.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/kvm.h" 44 #include "hw/compat.h" 45 #include "hw/loader.h" 46 #include "exec/address-spaces.h" 47 #include "qemu/bitops.h" 48 #include "qemu/error-report.h" 49 #include "hw/pci-host/gpex.h" 50 #include "hw/arm/sysbus-fdt.h" 51 #include "hw/platform-bus.h" 52 #include "hw/arm/fdt.h" 53 #include "hw/intc/arm_gic.h" 54 #include "hw/intc/arm_gicv3_common.h" 55 #include "kvm_arm.h" 56 #include "hw/smbios/smbios.h" 57 #include "qapi/visitor.h" 58 #include "standard-headers/linux/input.h" 59 60 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 61 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 62 void *data) \ 63 { \ 64 MachineClass *mc = MACHINE_CLASS(oc); \ 65 virt_machine_##major##_##minor##_options(mc); \ 66 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 67 if (latest) { \ 68 mc->alias = "virt"; \ 69 } \ 70 } \ 71 static const TypeInfo machvirt_##major##_##minor##_info = { \ 72 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 73 .parent = TYPE_VIRT_MACHINE, \ 74 .instance_init = virt_##major##_##minor##_instance_init, \ 75 .class_init = virt_##major##_##minor##_class_init, \ 76 }; \ 77 static void machvirt_machine_##major##_##minor##_init(void) \ 78 { \ 79 type_register_static(&machvirt_##major##_##minor##_info); \ 80 } \ 81 type_init(machvirt_machine_##major##_##minor##_init); 82 83 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 84 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 85 #define DEFINE_VIRT_MACHINE(major, minor) \ 86 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 87 88 89 /* Number of external interrupt lines to configure the GIC with */ 90 #define NUM_IRQS 256 91 92 #define PLATFORM_BUS_NUM_IRQS 64 93 94 static ARMPlatformBusSystemParams platform_bus_params; 95 96 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means 97 * RAM can go up to the 256GB mark, leaving 256GB of the physical 98 * address space unallocated and free for future use between 256G and 512G. 99 * If we need to provide more RAM to VMs in the future then we need to: 100 * * allocate a second bank of RAM starting at 2TB and working up 101 * * fix the DT and ACPI table generation code in QEMU to correctly 102 * report two split lumps of RAM to the guest 103 * * fix KVM in the host kernel to allow guests with >40 bit address spaces 104 * (We don't want to fill all the way up to 512GB with RAM because 105 * we might want it for non-RAM purposes later. Conversely it seems 106 * reasonable to assume that anybody configuring a VM with a quarter 107 * of a terabyte of RAM will be doing it on a host with more than a 108 * terabyte of physical address space.) 109 */ 110 #define RAMLIMIT_GB 255 111 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) 112 113 /* Addresses and sizes of our components. 114 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 115 * 128MB..256MB is used for miscellaneous device I/O. 116 * 256MB..1GB is reserved for possible future PCI support (ie where the 117 * PCI memory window will go if we add a PCI host controller). 118 * 1GB and up is RAM (which may happily spill over into the 119 * high memory region beyond 4GB). 120 * This represents a compromise between how much RAM can be given to 121 * a 32 bit VM and leaving space for expansion and in particular for PCI. 122 * Note that devices should generally be placed at multiples of 0x10000, 123 * to accommodate guests using 64K pages. 124 */ 125 static const MemMapEntry a15memmap[] = { 126 /* Space up to 0x8000000 is reserved for a boot ROM */ 127 [VIRT_FLASH] = { 0, 0x08000000 }, 128 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 129 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 130 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 131 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 132 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 133 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 134 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 135 /* This redistributor space allows up to 2*64kB*123 CPUs */ 136 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 137 [VIRT_UART] = { 0x09000000, 0x00001000 }, 138 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 139 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 140 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 141 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 142 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 143 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 144 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 145 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 146 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 147 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 148 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 149 [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES }, 150 /* Second PCIe window, 512GB wide at the 512GB boundary */ 151 [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL }, 152 }; 153 154 static const int a15irqmap[] = { 155 [VIRT_UART] = 1, 156 [VIRT_RTC] = 2, 157 [VIRT_PCIE] = 3, /* ... to 6 */ 158 [VIRT_GPIO] = 7, 159 [VIRT_SECURE_UART] = 8, 160 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 161 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 162 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 163 }; 164 165 static const char *valid_cpus[] = { 166 "cortex-a15", 167 "cortex-a53", 168 "cortex-a57", 169 "host", 170 }; 171 172 static bool cpuname_valid(const char *cpu) 173 { 174 int i; 175 176 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 177 if (strcmp(cpu, valid_cpus[i]) == 0) { 178 return true; 179 } 180 } 181 return false; 182 } 183 184 static void create_fdt(VirtMachineState *vms) 185 { 186 void *fdt = create_device_tree(&vms->fdt_size); 187 188 if (!fdt) { 189 error_report("create_device_tree() failed"); 190 exit(1); 191 } 192 193 vms->fdt = fdt; 194 195 /* Header */ 196 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 197 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 198 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 199 200 /* 201 * /chosen and /memory nodes must exist for load_dtb 202 * to fill in necessary properties later 203 */ 204 qemu_fdt_add_subnode(fdt, "/chosen"); 205 qemu_fdt_add_subnode(fdt, "/memory"); 206 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 207 208 /* Clock node, for the benefit of the UART. The kernel device tree 209 * binding documentation claims the PL011 node clock properties are 210 * optional but in practice if you omit them the kernel refuses to 211 * probe for the device. 212 */ 213 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 214 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 215 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 216 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 217 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 218 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 219 "clk24mhz"); 220 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 221 222 } 223 224 static void fdt_add_psci_node(const VirtMachineState *vms) 225 { 226 uint32_t cpu_suspend_fn; 227 uint32_t cpu_off_fn; 228 uint32_t cpu_on_fn; 229 uint32_t migrate_fn; 230 void *fdt = vms->fdt; 231 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 232 const char *psci_method; 233 234 switch (vms->psci_conduit) { 235 case QEMU_PSCI_CONDUIT_DISABLED: 236 return; 237 case QEMU_PSCI_CONDUIT_HVC: 238 psci_method = "hvc"; 239 break; 240 case QEMU_PSCI_CONDUIT_SMC: 241 psci_method = "smc"; 242 break; 243 default: 244 g_assert_not_reached(); 245 } 246 247 qemu_fdt_add_subnode(fdt, "/psci"); 248 if (armcpu->psci_version == 2) { 249 const char comp[] = "arm,psci-0.2\0arm,psci"; 250 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 251 252 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 253 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 254 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 255 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 256 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 257 } else { 258 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 259 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 260 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 261 } 262 } else { 263 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 264 265 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 266 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 267 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 268 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 269 } 270 271 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 272 * to the instruction that should be used to invoke PSCI functions. 273 * However, the device tree binding uses 'method' instead, so that is 274 * what we should use here. 275 */ 276 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 277 278 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 279 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 280 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 281 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 282 } 283 284 static void fdt_add_timer_nodes(const VirtMachineState *vms) 285 { 286 /* On real hardware these interrupts are level-triggered. 287 * On KVM they were edge-triggered before host kernel version 4.4, 288 * and level-triggered afterwards. 289 * On emulated QEMU they are level-triggered. 290 * 291 * Getting the DTB info about them wrong is awkward for some 292 * guest kernels: 293 * pre-4.8 ignore the DT and leave the interrupt configured 294 * with whatever the GIC reset value (or the bootloader) left it at 295 * 4.8 before rc6 honour the incorrect data by programming it back 296 * into the GIC, causing problems 297 * 4.8rc6 and later ignore the DT and always write "level triggered" 298 * into the GIC 299 * 300 * For backwards-compatibility, virt-2.8 and earlier will continue 301 * to say these are edge-triggered, but later machines will report 302 * the correct information. 303 */ 304 ARMCPU *armcpu; 305 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 306 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 307 308 if (vmc->claim_edge_triggered_timers) { 309 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 310 } 311 312 if (vms->gic_version == 2) { 313 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 314 GIC_FDT_IRQ_PPI_CPU_WIDTH, 315 (1 << vms->smp_cpus) - 1); 316 } 317 318 qemu_fdt_add_subnode(vms->fdt, "/timer"); 319 320 armcpu = ARM_CPU(qemu_get_cpu(0)); 321 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 322 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 323 qemu_fdt_setprop(vms->fdt, "/timer", "compatible", 324 compat, sizeof(compat)); 325 } else { 326 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible", 327 "arm,armv7-timer"); 328 } 329 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0); 330 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts", 331 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 332 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 333 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 334 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 335 } 336 337 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 338 { 339 int cpu; 340 int addr_cells = 1; 341 const MachineState *ms = MACHINE(vms); 342 343 /* 344 * From Documentation/devicetree/bindings/arm/cpus.txt 345 * On ARM v8 64-bit systems value should be set to 2, 346 * that corresponds to the MPIDR_EL1 register size. 347 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 348 * in the system, #address-cells can be set to 1, since 349 * MPIDR_EL1[63:32] bits are not used for CPUs 350 * identification. 351 * 352 * Here we actually don't know whether our system is 32- or 64-bit one. 353 * The simplest way to go is to examine affinity IDs of all our CPUs. If 354 * at least one of them has Aff3 populated, we set #address-cells to 2. 355 */ 356 for (cpu = 0; cpu < vms->smp_cpus; cpu++) { 357 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 358 359 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 360 addr_cells = 2; 361 break; 362 } 363 } 364 365 qemu_fdt_add_subnode(vms->fdt, "/cpus"); 366 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); 367 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); 368 369 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { 370 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 371 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 372 CPUState *cs = CPU(armcpu); 373 374 qemu_fdt_add_subnode(vms->fdt, nodename); 375 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); 376 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 377 armcpu->dtb_compatible); 378 379 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED 380 && vms->smp_cpus > 1) { 381 qemu_fdt_setprop_string(vms->fdt, nodename, 382 "enable-method", "psci"); 383 } 384 385 if (addr_cells == 2) { 386 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", 387 armcpu->mp_affinity); 388 } else { 389 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", 390 armcpu->mp_affinity); 391 } 392 393 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 394 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", 395 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 396 } 397 398 g_free(nodename); 399 } 400 } 401 402 static void fdt_add_its_gic_node(VirtMachineState *vms) 403 { 404 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 405 qemu_fdt_add_subnode(vms->fdt, "/intc/its"); 406 qemu_fdt_setprop_string(vms->fdt, "/intc/its", "compatible", 407 "arm,gic-v3-its"); 408 qemu_fdt_setprop(vms->fdt, "/intc/its", "msi-controller", NULL, 0); 409 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/its", "reg", 410 2, vms->memmap[VIRT_GIC_ITS].base, 411 2, vms->memmap[VIRT_GIC_ITS].size); 412 qemu_fdt_setprop_cell(vms->fdt, "/intc/its", "phandle", vms->msi_phandle); 413 } 414 415 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 416 { 417 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 418 qemu_fdt_add_subnode(vms->fdt, "/intc/v2m"); 419 qemu_fdt_setprop_string(vms->fdt, "/intc/v2m", "compatible", 420 "arm,gic-v2m-frame"); 421 qemu_fdt_setprop(vms->fdt, "/intc/v2m", "msi-controller", NULL, 0); 422 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/v2m", "reg", 423 2, vms->memmap[VIRT_GIC_V2M].base, 424 2, vms->memmap[VIRT_GIC_V2M].size); 425 qemu_fdt_setprop_cell(vms->fdt, "/intc/v2m", "phandle", vms->msi_phandle); 426 } 427 428 static void fdt_add_gic_node(VirtMachineState *vms) 429 { 430 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt); 431 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle); 432 433 qemu_fdt_add_subnode(vms->fdt, "/intc"); 434 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#interrupt-cells", 3); 435 qemu_fdt_setprop(vms->fdt, "/intc", "interrupt-controller", NULL, 0); 436 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#address-cells", 0x2); 437 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#size-cells", 0x2); 438 qemu_fdt_setprop(vms->fdt, "/intc", "ranges", NULL, 0); 439 if (vms->gic_version == 3) { 440 qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", 441 "arm,gic-v3"); 442 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", 443 2, vms->memmap[VIRT_GIC_DIST].base, 444 2, vms->memmap[VIRT_GIC_DIST].size, 445 2, vms->memmap[VIRT_GIC_REDIST].base, 446 2, vms->memmap[VIRT_GIC_REDIST].size); 447 if (vms->virt) { 448 qemu_fdt_setprop_cells(vms->fdt, "/intc", "interrupts", 449 GIC_FDT_IRQ_TYPE_PPI, ARCH_GICV3_MAINT_IRQ, 450 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 451 } 452 } else { 453 /* 'cortex-a15-gic' means 'GIC v2' */ 454 qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", 455 "arm,cortex-a15-gic"); 456 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", 457 2, vms->memmap[VIRT_GIC_DIST].base, 458 2, vms->memmap[VIRT_GIC_DIST].size, 459 2, vms->memmap[VIRT_GIC_CPU].base, 460 2, vms->memmap[VIRT_GIC_CPU].size); 461 } 462 463 qemu_fdt_setprop_cell(vms->fdt, "/intc", "phandle", vms->gic_phandle); 464 } 465 466 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 467 { 468 CPUState *cpu; 469 ARMCPU *armcpu; 470 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 471 472 CPU_FOREACH(cpu) { 473 armcpu = ARM_CPU(cpu); 474 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU) || 475 (kvm_enabled() && !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ)))) { 476 return; 477 } 478 } 479 480 if (vms->gic_version == 2) { 481 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 482 GIC_FDT_IRQ_PPI_CPU_WIDTH, 483 (1 << vms->smp_cpus) - 1); 484 } 485 486 armcpu = ARM_CPU(qemu_get_cpu(0)); 487 qemu_fdt_add_subnode(vms->fdt, "/pmu"); 488 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 489 const char compat[] = "arm,armv8-pmuv3"; 490 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible", 491 compat, sizeof(compat)); 492 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts", 493 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 494 } 495 } 496 497 static void create_its(VirtMachineState *vms, DeviceState *gicdev) 498 { 499 const char *itsclass = its_class_name(); 500 DeviceState *dev; 501 502 if (!itsclass) { 503 /* Do nothing if not supported */ 504 return; 505 } 506 507 dev = qdev_create(NULL, itsclass); 508 509 object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3", 510 &error_abort); 511 qdev_init_nofail(dev); 512 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 513 514 fdt_add_its_gic_node(vms); 515 } 516 517 static void create_v2m(VirtMachineState *vms, qemu_irq *pic) 518 { 519 int i; 520 int irq = vms->irqmap[VIRT_GIC_V2M]; 521 DeviceState *dev; 522 523 dev = qdev_create(NULL, "arm-gicv2m"); 524 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 525 qdev_prop_set_uint32(dev, "base-spi", irq); 526 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 527 qdev_init_nofail(dev); 528 529 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 530 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 531 } 532 533 fdt_add_v2m_gic_node(vms); 534 } 535 536 static void create_gic(VirtMachineState *vms, qemu_irq *pic) 537 { 538 /* We create a standalone GIC */ 539 DeviceState *gicdev; 540 SysBusDevice *gicbusdev; 541 const char *gictype; 542 int type = vms->gic_version, i; 543 544 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 545 546 gicdev = qdev_create(NULL, gictype); 547 qdev_prop_set_uint32(gicdev, "revision", type); 548 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 549 /* Note that the num-irq property counts both internal and external 550 * interrupts; there are always 32 of the former (mandated by GIC spec). 551 */ 552 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 553 if (!kvm_irqchip_in_kernel()) { 554 qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure); 555 } 556 qdev_init_nofail(gicdev); 557 gicbusdev = SYS_BUS_DEVICE(gicdev); 558 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 559 if (type == 3) { 560 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 561 } else { 562 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 563 } 564 565 /* Wire the outputs from each CPU's generic timer and the GICv3 566 * maintenance interrupt signal to the appropriate GIC PPI inputs, 567 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 568 */ 569 for (i = 0; i < smp_cpus; i++) { 570 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 571 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 572 int irq; 573 /* Mapping from the output timer irq lines from the CPU to the 574 * GIC PPI inputs we use for the virt board. 575 */ 576 const int timer_irq[] = { 577 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 578 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 579 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 580 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 581 }; 582 583 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 584 qdev_connect_gpio_out(cpudev, irq, 585 qdev_get_gpio_in(gicdev, 586 ppibase + timer_irq[irq])); 587 } 588 589 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 590 qdev_get_gpio_in(gicdev, ppibase 591 + ARCH_GICV3_MAINT_IRQ)); 592 593 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 594 sysbus_connect_irq(gicbusdev, i + smp_cpus, 595 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 596 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 597 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 598 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 599 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 600 } 601 602 for (i = 0; i < NUM_IRQS; i++) { 603 pic[i] = qdev_get_gpio_in(gicdev, i); 604 } 605 606 fdt_add_gic_node(vms); 607 608 if (type == 3 && vms->its) { 609 create_its(vms, gicdev); 610 } else if (type == 2) { 611 create_v2m(vms, pic); 612 } 613 } 614 615 static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart, 616 MemoryRegion *mem, Chardev *chr) 617 { 618 char *nodename; 619 hwaddr base = vms->memmap[uart].base; 620 hwaddr size = vms->memmap[uart].size; 621 int irq = vms->irqmap[uart]; 622 const char compat[] = "arm,pl011\0arm,primecell"; 623 const char clocknames[] = "uartclk\0apb_pclk"; 624 DeviceState *dev = qdev_create(NULL, "pl011"); 625 SysBusDevice *s = SYS_BUS_DEVICE(dev); 626 627 qdev_prop_set_chr(dev, "chardev", chr); 628 qdev_init_nofail(dev); 629 memory_region_add_subregion(mem, base, 630 sysbus_mmio_get_region(s, 0)); 631 sysbus_connect_irq(s, 0, pic[irq]); 632 633 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 634 qemu_fdt_add_subnode(vms->fdt, nodename); 635 /* Note that we can't use setprop_string because of the embedded NUL */ 636 qemu_fdt_setprop(vms->fdt, nodename, "compatible", 637 compat, sizeof(compat)); 638 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 639 2, base, 2, size); 640 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 641 GIC_FDT_IRQ_TYPE_SPI, irq, 642 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 643 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks", 644 vms->clock_phandle, vms->clock_phandle); 645 qemu_fdt_setprop(vms->fdt, nodename, "clock-names", 646 clocknames, sizeof(clocknames)); 647 648 if (uart == VIRT_UART) { 649 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); 650 } else { 651 /* Mark as not usable by the normal world */ 652 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 653 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 654 } 655 656 g_free(nodename); 657 } 658 659 static void create_rtc(const VirtMachineState *vms, qemu_irq *pic) 660 { 661 char *nodename; 662 hwaddr base = vms->memmap[VIRT_RTC].base; 663 hwaddr size = vms->memmap[VIRT_RTC].size; 664 int irq = vms->irqmap[VIRT_RTC]; 665 const char compat[] = "arm,pl031\0arm,primecell"; 666 667 sysbus_create_simple("pl031", base, pic[irq]); 668 669 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 670 qemu_fdt_add_subnode(vms->fdt, nodename); 671 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 672 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 673 2, base, 2, size); 674 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 675 GIC_FDT_IRQ_TYPE_SPI, irq, 676 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 677 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 678 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 679 g_free(nodename); 680 } 681 682 static DeviceState *gpio_key_dev; 683 static void virt_powerdown_req(Notifier *n, void *opaque) 684 { 685 /* use gpio Pin 3 for power button event */ 686 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 687 } 688 689 static Notifier virt_system_powerdown_notifier = { 690 .notify = virt_powerdown_req 691 }; 692 693 static void create_gpio(const VirtMachineState *vms, qemu_irq *pic) 694 { 695 char *nodename; 696 DeviceState *pl061_dev; 697 hwaddr base = vms->memmap[VIRT_GPIO].base; 698 hwaddr size = vms->memmap[VIRT_GPIO].size; 699 int irq = vms->irqmap[VIRT_GPIO]; 700 const char compat[] = "arm,pl061\0arm,primecell"; 701 702 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); 703 704 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); 705 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 706 qemu_fdt_add_subnode(vms->fdt, nodename); 707 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 708 2, base, 2, size); 709 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 710 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); 711 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); 712 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 713 GIC_FDT_IRQ_TYPE_SPI, irq, 714 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 715 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 716 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 717 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); 718 719 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 720 qdev_get_gpio_in(pl061_dev, 3)); 721 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); 722 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); 723 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); 724 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); 725 726 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); 727 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", 728 "label", "GPIO Key Poweroff"); 729 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", 730 KEY_POWER); 731 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", 732 "gpios", phandle, 3, 0); 733 734 /* connect powerdown request */ 735 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier); 736 737 g_free(nodename); 738 } 739 740 static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic) 741 { 742 int i; 743 hwaddr size = vms->memmap[VIRT_MMIO].size; 744 745 /* We create the transports in forwards order. Since qbus_realize() 746 * prepends (not appends) new child buses, the incrementing loop below will 747 * create a list of virtio-mmio buses with decreasing base addresses. 748 * 749 * When a -device option is processed from the command line, 750 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 751 * order. The upshot is that -device options in increasing command line 752 * order are mapped to virtio-mmio buses with decreasing base addresses. 753 * 754 * When this code was originally written, that arrangement ensured that the 755 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 756 * the first -device on the command line. (The end-to-end order is a 757 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 758 * guest kernel's name-to-address assignment strategy.) 759 * 760 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 761 * the message, if not necessarily the code, of commit 70161ff336. 762 * Therefore the loop now establishes the inverse of the original intent. 763 * 764 * Unfortunately, we can't counteract the kernel change by reversing the 765 * loop; it would break existing command lines. 766 * 767 * In any case, the kernel makes no guarantee about the stability of 768 * enumeration order of virtio devices (as demonstrated by it changing 769 * between kernel versions). For reliable and stable identification 770 * of disks users must use UUIDs or similar mechanisms. 771 */ 772 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 773 int irq = vms->irqmap[VIRT_MMIO] + i; 774 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 775 776 sysbus_create_simple("virtio-mmio", base, pic[irq]); 777 } 778 779 /* We add dtb nodes in reverse order so that they appear in the finished 780 * device tree lowest address first. 781 * 782 * Note that this mapping is independent of the loop above. The previous 783 * loop influences virtio device to virtio transport assignment, whereas 784 * this loop controls how virtio transports are laid out in the dtb. 785 */ 786 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 787 char *nodename; 788 int irq = vms->irqmap[VIRT_MMIO] + i; 789 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 790 791 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 792 qemu_fdt_add_subnode(vms->fdt, nodename); 793 qemu_fdt_setprop_string(vms->fdt, nodename, 794 "compatible", "virtio,mmio"); 795 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 796 2, base, 2, size); 797 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 798 GIC_FDT_IRQ_TYPE_SPI, irq, 799 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 800 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 801 g_free(nodename); 802 } 803 } 804 805 static void create_one_flash(const char *name, hwaddr flashbase, 806 hwaddr flashsize, const char *file, 807 MemoryRegion *sysmem) 808 { 809 /* Create and map a single flash device. We use the same 810 * parameters as the flash devices on the Versatile Express board. 811 */ 812 DriveInfo *dinfo = drive_get_next(IF_PFLASH); 813 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 814 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 815 const uint64_t sectorlength = 256 * 1024; 816 817 if (dinfo) { 818 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 819 &error_abort); 820 } 821 822 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); 823 qdev_prop_set_uint64(dev, "sector-length", sectorlength); 824 qdev_prop_set_uint8(dev, "width", 4); 825 qdev_prop_set_uint8(dev, "device-width", 2); 826 qdev_prop_set_bit(dev, "big-endian", false); 827 qdev_prop_set_uint16(dev, "id0", 0x89); 828 qdev_prop_set_uint16(dev, "id1", 0x18); 829 qdev_prop_set_uint16(dev, "id2", 0x00); 830 qdev_prop_set_uint16(dev, "id3", 0x00); 831 qdev_prop_set_string(dev, "name", name); 832 qdev_init_nofail(dev); 833 834 memory_region_add_subregion(sysmem, flashbase, 835 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 836 837 if (file) { 838 char *fn; 839 int image_size; 840 841 if (drive_get(IF_PFLASH, 0, 0)) { 842 error_report("The contents of the first flash device may be " 843 "specified with -bios or with -drive if=pflash... " 844 "but you cannot use both options at once"); 845 exit(1); 846 } 847 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file); 848 if (!fn) { 849 error_report("Could not find ROM image '%s'", file); 850 exit(1); 851 } 852 image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0)); 853 g_free(fn); 854 if (image_size < 0) { 855 error_report("Could not load ROM image '%s'", file); 856 exit(1); 857 } 858 } 859 } 860 861 static void create_flash(const VirtMachineState *vms, 862 MemoryRegion *sysmem, 863 MemoryRegion *secure_sysmem) 864 { 865 /* Create two flash devices to fill the VIRT_FLASH space in the memmap. 866 * Any file passed via -bios goes in the first of these. 867 * sysmem is the system memory space. secure_sysmem is the secure view 868 * of the system, and the first flash device should be made visible only 869 * there. The second flash device is visible to both secure and nonsecure. 870 * If sysmem == secure_sysmem this means there is no separate Secure 871 * address space and both flash devices are generally visible. 872 */ 873 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 874 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 875 char *nodename; 876 877 create_one_flash("virt.flash0", flashbase, flashsize, 878 bios_name, secure_sysmem); 879 create_one_flash("virt.flash1", flashbase + flashsize, flashsize, 880 NULL, sysmem); 881 882 if (sysmem == secure_sysmem) { 883 /* Report both flash devices as a single node in the DT */ 884 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 885 qemu_fdt_add_subnode(vms->fdt, nodename); 886 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 887 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 888 2, flashbase, 2, flashsize, 889 2, flashbase + flashsize, 2, flashsize); 890 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 891 g_free(nodename); 892 } else { 893 /* Report the devices as separate nodes so we can mark one as 894 * only visible to the secure world. 895 */ 896 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 897 qemu_fdt_add_subnode(vms->fdt, nodename); 898 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 899 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 900 2, flashbase, 2, flashsize); 901 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 902 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 903 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 904 g_free(nodename); 905 906 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 907 qemu_fdt_add_subnode(vms->fdt, nodename); 908 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 909 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 910 2, flashbase + flashsize, 2, flashsize); 911 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 912 g_free(nodename); 913 } 914 } 915 916 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 917 { 918 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 919 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 920 FWCfgState *fw_cfg; 921 char *nodename; 922 923 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 924 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 925 926 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 927 qemu_fdt_add_subnode(vms->fdt, nodename); 928 qemu_fdt_setprop_string(vms->fdt, nodename, 929 "compatible", "qemu,fw-cfg-mmio"); 930 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 931 2, base, 2, size); 932 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 933 g_free(nodename); 934 return fw_cfg; 935 } 936 937 static void create_pcie_irq_map(const VirtMachineState *vms, 938 uint32_t gic_phandle, 939 int first_irq, const char *nodename) 940 { 941 int devfn, pin; 942 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 943 uint32_t *irq_map = full_irq_map; 944 945 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 946 for (pin = 0; pin < 4; pin++) { 947 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 948 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 949 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 950 int i; 951 952 uint32_t map[] = { 953 devfn << 8, 0, 0, /* devfn */ 954 pin + 1, /* PCI pin */ 955 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 956 957 /* Convert map to big endian */ 958 for (i = 0; i < 10; i++) { 959 irq_map[i] = cpu_to_be32(map[i]); 960 } 961 irq_map += 10; 962 } 963 } 964 965 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map", 966 full_irq_map, sizeof(full_irq_map)); 967 968 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask", 969 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 970 0x7 /* PCI irq */); 971 } 972 973 static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) 974 { 975 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 976 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 977 hwaddr base_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].base; 978 hwaddr size_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].size; 979 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 980 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 981 hwaddr base_ecam = vms->memmap[VIRT_PCIE_ECAM].base; 982 hwaddr size_ecam = vms->memmap[VIRT_PCIE_ECAM].size; 983 hwaddr base = base_mmio; 984 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 985 int irq = vms->irqmap[VIRT_PCIE]; 986 MemoryRegion *mmio_alias; 987 MemoryRegion *mmio_reg; 988 MemoryRegion *ecam_alias; 989 MemoryRegion *ecam_reg; 990 DeviceState *dev; 991 char *nodename; 992 int i; 993 PCIHostState *pci; 994 995 dev = qdev_create(NULL, TYPE_GPEX_HOST); 996 qdev_init_nofail(dev); 997 998 /* Map only the first size_ecam bytes of ECAM space */ 999 ecam_alias = g_new0(MemoryRegion, 1); 1000 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1001 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1002 ecam_reg, 0, size_ecam); 1003 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1004 1005 /* Map the MMIO window into system address space so as to expose 1006 * the section of PCI MMIO space which starts at the same base address 1007 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1008 * the window). 1009 */ 1010 mmio_alias = g_new0(MemoryRegion, 1); 1011 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1012 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1013 mmio_reg, base_mmio, size_mmio); 1014 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1015 1016 if (vms->highmem) { 1017 /* Map high MMIO space */ 1018 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1019 1020 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1021 mmio_reg, base_mmio_high, size_mmio_high); 1022 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1023 high_mmio_alias); 1024 } 1025 1026 /* Map IO port space */ 1027 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1028 1029 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1030 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 1031 } 1032 1033 pci = PCI_HOST_BRIDGE(dev); 1034 if (pci->bus) { 1035 for (i = 0; i < nb_nics; i++) { 1036 NICInfo *nd = &nd_table[i]; 1037 1038 if (!nd->model) { 1039 nd->model = g_strdup("virtio"); 1040 } 1041 1042 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1043 } 1044 } 1045 1046 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1047 qemu_fdt_add_subnode(vms->fdt, nodename); 1048 qemu_fdt_setprop_string(vms->fdt, nodename, 1049 "compatible", "pci-host-ecam-generic"); 1050 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci"); 1051 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3); 1052 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2); 1053 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0, 1054 nr_pcie_buses - 1); 1055 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1056 1057 if (vms->msi_phandle) { 1058 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", 1059 vms->msi_phandle); 1060 } 1061 1062 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1063 2, base_ecam, 2, size_ecam); 1064 1065 if (vms->highmem) { 1066 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1067 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1068 2, base_pio, 2, size_pio, 1069 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1070 2, base_mmio, 2, size_mmio, 1071 1, FDT_PCI_RANGE_MMIO_64BIT, 1072 2, base_mmio_high, 1073 2, base_mmio_high, 2, size_mmio_high); 1074 } else { 1075 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1076 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1077 2, base_pio, 2, size_pio, 1078 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1079 2, base_mmio, 2, size_mmio); 1080 } 1081 1082 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); 1083 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); 1084 1085 g_free(nodename); 1086 } 1087 1088 static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic) 1089 { 1090 DeviceState *dev; 1091 SysBusDevice *s; 1092 int i; 1093 ARMPlatformBusFDTParams *fdt_params = g_new(ARMPlatformBusFDTParams, 1); 1094 MemoryRegion *sysmem = get_system_memory(); 1095 1096 platform_bus_params.platform_bus_base = vms->memmap[VIRT_PLATFORM_BUS].base; 1097 platform_bus_params.platform_bus_size = vms->memmap[VIRT_PLATFORM_BUS].size; 1098 platform_bus_params.platform_bus_first_irq = vms->irqmap[VIRT_PLATFORM_BUS]; 1099 platform_bus_params.platform_bus_num_irqs = PLATFORM_BUS_NUM_IRQS; 1100 1101 fdt_params->system_params = &platform_bus_params; 1102 fdt_params->binfo = &vms->bootinfo; 1103 fdt_params->intc = "/intc"; 1104 /* 1105 * register a machine init done notifier that creates the device tree 1106 * nodes of the platform bus and its children dynamic sysbus devices 1107 */ 1108 arm_register_platform_bus_fdt_creator(fdt_params); 1109 1110 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1111 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1112 qdev_prop_set_uint32(dev, "num_irqs", 1113 platform_bus_params.platform_bus_num_irqs); 1114 qdev_prop_set_uint32(dev, "mmio_size", 1115 platform_bus_params.platform_bus_size); 1116 qdev_init_nofail(dev); 1117 s = SYS_BUS_DEVICE(dev); 1118 1119 for (i = 0; i < platform_bus_params.platform_bus_num_irqs; i++) { 1120 int irqn = platform_bus_params.platform_bus_first_irq + i; 1121 sysbus_connect_irq(s, i, pic[irqn]); 1122 } 1123 1124 memory_region_add_subregion(sysmem, 1125 platform_bus_params.platform_bus_base, 1126 sysbus_mmio_get_region(s, 0)); 1127 } 1128 1129 static void create_secure_ram(VirtMachineState *vms, 1130 MemoryRegion *secure_sysmem) 1131 { 1132 MemoryRegion *secram = g_new(MemoryRegion, 1); 1133 char *nodename; 1134 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1135 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1136 1137 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, &error_fatal); 1138 vmstate_register_ram_global(secram); 1139 memory_region_add_subregion(secure_sysmem, base, secram); 1140 1141 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1142 qemu_fdt_add_subnode(vms->fdt, nodename); 1143 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory"); 1144 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size); 1145 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1146 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1147 1148 g_free(nodename); 1149 } 1150 1151 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1152 { 1153 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1154 bootinfo); 1155 1156 *fdt_size = board->fdt_size; 1157 return board->fdt; 1158 } 1159 1160 static void virt_build_smbios(VirtMachineState *vms) 1161 { 1162 uint8_t *smbios_tables, *smbios_anchor; 1163 size_t smbios_tables_len, smbios_anchor_len; 1164 const char *product = "QEMU Virtual Machine"; 1165 1166 if (!vms->fw_cfg) { 1167 return; 1168 } 1169 1170 if (kvm_enabled()) { 1171 product = "KVM Virtual Machine"; 1172 } 1173 1174 smbios_set_defaults("QEMU", product, 1175 "1.0", false, true, SMBIOS_ENTRY_POINT_30); 1176 1177 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, 1178 &smbios_anchor, &smbios_anchor_len); 1179 1180 if (smbios_anchor) { 1181 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1182 smbios_tables, smbios_tables_len); 1183 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1184 smbios_anchor, smbios_anchor_len); 1185 } 1186 } 1187 1188 static 1189 void virt_machine_done(Notifier *notifier, void *data) 1190 { 1191 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1192 machine_done); 1193 1194 virt_acpi_setup(vms); 1195 virt_build_smbios(vms); 1196 } 1197 1198 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1199 { 1200 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1201 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1202 1203 if (!vmc->disallow_affinity_adjustment) { 1204 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1205 * GIC's target-list limitations. 32-bit KVM hosts currently 1206 * always create clusters of 4 CPUs, but that is expected to 1207 * change when they gain support for gicv3. When KVM is enabled 1208 * it will override the changes we make here, therefore our 1209 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1210 * and to improve SGI efficiency. 1211 */ 1212 if (vms->gic_version == 3) { 1213 clustersz = GICV3_TARGETLIST_BITS; 1214 } else { 1215 clustersz = GIC_TARGETLIST_BITS; 1216 } 1217 } 1218 return arm_cpu_mp_affinity(idx, clustersz); 1219 } 1220 1221 static void machvirt_init(MachineState *machine) 1222 { 1223 VirtMachineState *vms = VIRT_MACHINE(machine); 1224 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1225 MachineClass *mc = MACHINE_GET_CLASS(machine); 1226 const CPUArchIdList *possible_cpus; 1227 qemu_irq pic[NUM_IRQS]; 1228 MemoryRegion *sysmem = get_system_memory(); 1229 MemoryRegion *secure_sysmem = NULL; 1230 int n, virt_max_cpus; 1231 MemoryRegion *ram = g_new(MemoryRegion, 1); 1232 const char *cpu_model = machine->cpu_model; 1233 char **cpustr; 1234 ObjectClass *oc; 1235 const char *typename; 1236 CPUClass *cc; 1237 Error *err = NULL; 1238 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); 1239 1240 if (!cpu_model) { 1241 cpu_model = "cortex-a15"; 1242 } 1243 1244 /* We can probe only here because during property set 1245 * KVM is not available yet 1246 */ 1247 if (!vms->gic_version) { 1248 if (!kvm_enabled()) { 1249 error_report("gic-version=host requires KVM"); 1250 exit(1); 1251 } 1252 1253 vms->gic_version = kvm_arm_vgic_probe(); 1254 if (!vms->gic_version) { 1255 error_report("Unable to determine GIC version supported by host"); 1256 exit(1); 1257 } 1258 } 1259 1260 /* Separate the actual CPU model name from any appended features */ 1261 cpustr = g_strsplit(cpu_model, ",", 2); 1262 1263 if (!cpuname_valid(cpustr[0])) { 1264 error_report("mach-virt: CPU %s not supported", cpustr[0]); 1265 exit(1); 1266 } 1267 1268 /* If we have an EL3 boot ROM then the assumption is that it will 1269 * implement PSCI itself, so disable QEMU's internal implementation 1270 * so it doesn't get in the way. Instead of starting secondary 1271 * CPUs in PSCI powerdown state we will start them all running and 1272 * let the boot ROM sort them out. 1273 * The usual case is that we do use QEMU's PSCI implementation; 1274 * if the guest has EL2 then we will use SMC as the conduit, 1275 * and otherwise we will use HVC (for backwards compatibility and 1276 * because if we're using KVM then we must use HVC). 1277 */ 1278 if (vms->secure && firmware_loaded) { 1279 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1280 } else if (vms->virt) { 1281 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 1282 } else { 1283 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 1284 } 1285 1286 /* The maximum number of CPUs depends on the GIC version, or on how 1287 * many redistributors we can fit into the memory map. 1288 */ 1289 if (vms->gic_version == 3) { 1290 virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / 0x20000; 1291 } else { 1292 virt_max_cpus = GIC_NCPU; 1293 } 1294 1295 if (max_cpus > virt_max_cpus) { 1296 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1297 "supported by machine 'mach-virt' (%d)", 1298 max_cpus, virt_max_cpus); 1299 exit(1); 1300 } 1301 1302 vms->smp_cpus = smp_cpus; 1303 1304 if (machine->ram_size > vms->memmap[VIRT_MEM].size) { 1305 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB); 1306 exit(1); 1307 } 1308 1309 if (vms->virt && kvm_enabled()) { 1310 error_report("mach-virt: KVM does not support providing " 1311 "Virtualization extensions to the guest CPU"); 1312 exit(1); 1313 } 1314 1315 if (vms->secure) { 1316 if (kvm_enabled()) { 1317 error_report("mach-virt: KVM does not support Security extensions"); 1318 exit(1); 1319 } 1320 1321 /* The Secure view of the world is the same as the NonSecure, 1322 * but with a few extra devices. Create it as a container region 1323 * containing the system memory at low priority; any secure-only 1324 * devices go in at higher priority and take precedence. 1325 */ 1326 secure_sysmem = g_new(MemoryRegion, 1); 1327 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1328 UINT64_MAX); 1329 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1330 } 1331 1332 create_fdt(vms); 1333 1334 oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); 1335 if (!oc) { 1336 error_report("Unable to find CPU definition"); 1337 exit(1); 1338 } 1339 typename = object_class_get_name(oc); 1340 1341 /* convert -smp CPU options specified by the user into global props */ 1342 cc = CPU_CLASS(oc); 1343 cc->parse_features(typename, cpustr[1], &err); 1344 g_strfreev(cpustr); 1345 if (err) { 1346 error_report_err(err); 1347 exit(1); 1348 } 1349 1350 possible_cpus = mc->possible_cpu_arch_ids(machine); 1351 for (n = 0; n < possible_cpus->len; n++) { 1352 Object *cpuobj; 1353 CPUState *cs; 1354 int node_id; 1355 1356 if (n >= smp_cpus) { 1357 break; 1358 } 1359 1360 cpuobj = object_new(typename); 1361 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 1362 "mp-affinity", NULL); 1363 1364 cs = CPU(cpuobj); 1365 cs->cpu_index = n; 1366 1367 node_id = possible_cpus->cpus[cs->cpu_index].props.node_id; 1368 if (!possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 1369 /* by default CPUState::numa_node was 0 if it's not set via CLI 1370 * keep it this way for now but in future we probably should 1371 * refuse to start up with incomplete numa mapping */ 1372 node_id = 0; 1373 } 1374 if (cs->numa_node == CPU_UNSET_NUMA_NODE_ID) { 1375 cs->numa_node = node_id; 1376 } else { 1377 /* CPU isn't device_add compatible yet, this shouldn't happen */ 1378 error_setg(&error_abort, "user set node-id not implemented"); 1379 } 1380 1381 if (!vms->secure) { 1382 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1383 } 1384 1385 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { 1386 object_property_set_bool(cpuobj, false, "has_el2", NULL); 1387 } 1388 1389 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1390 object_property_set_int(cpuobj, vms->psci_conduit, 1391 "psci-conduit", NULL); 1392 1393 /* Secondary CPUs start in PSCI powered-down state */ 1394 if (n > 0) { 1395 object_property_set_bool(cpuobj, true, 1396 "start-powered-off", NULL); 1397 } 1398 } 1399 1400 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { 1401 object_property_set_bool(cpuobj, false, "pmu", NULL); 1402 } 1403 1404 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1405 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, 1406 "reset-cbar", &error_abort); 1407 } 1408 1409 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1410 &error_abort); 1411 if (vms->secure) { 1412 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1413 "secure-memory", &error_abort); 1414 } 1415 1416 object_property_set_bool(cpuobj, true, "realized", NULL); 1417 object_unref(cpuobj); 1418 } 1419 fdt_add_timer_nodes(vms); 1420 fdt_add_cpu_nodes(vms); 1421 fdt_add_psci_node(vms); 1422 1423 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", 1424 machine->ram_size); 1425 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); 1426 1427 create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem); 1428 1429 create_gic(vms, pic); 1430 1431 fdt_add_pmu_nodes(vms); 1432 1433 create_uart(vms, pic, VIRT_UART, sysmem, serial_hds[0]); 1434 1435 if (vms->secure) { 1436 create_secure_ram(vms, secure_sysmem); 1437 create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hds[1]); 1438 } 1439 1440 create_rtc(vms, pic); 1441 1442 create_pcie(vms, pic); 1443 1444 create_gpio(vms, pic); 1445 1446 /* Create mmio transports, so the user can create virtio backends 1447 * (which will be automatically plugged in to the transports). If 1448 * no backend is created the transport will just sit harmlessly idle. 1449 */ 1450 create_virtio_devices(vms, pic); 1451 1452 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 1453 rom_set_fw(vms->fw_cfg); 1454 1455 vms->machine_done.notify = virt_machine_done; 1456 qemu_add_machine_init_done_notifier(&vms->machine_done); 1457 1458 vms->bootinfo.ram_size = machine->ram_size; 1459 vms->bootinfo.kernel_filename = machine->kernel_filename; 1460 vms->bootinfo.kernel_cmdline = machine->kernel_cmdline; 1461 vms->bootinfo.initrd_filename = machine->initrd_filename; 1462 vms->bootinfo.nb_cpus = smp_cpus; 1463 vms->bootinfo.board_id = -1; 1464 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 1465 vms->bootinfo.get_dtb = machvirt_dtb; 1466 vms->bootinfo.firmware_loaded = firmware_loaded; 1467 arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo); 1468 1469 /* 1470 * arm_load_kernel machine init done notifier registration must 1471 * happen before the platform_bus_create call. In this latter, 1472 * another notifier is registered which adds platform bus nodes. 1473 * Notifiers are executed in registration reverse order. 1474 */ 1475 create_platform_bus(vms, pic); 1476 } 1477 1478 static bool virt_get_secure(Object *obj, Error **errp) 1479 { 1480 VirtMachineState *vms = VIRT_MACHINE(obj); 1481 1482 return vms->secure; 1483 } 1484 1485 static void virt_set_secure(Object *obj, bool value, Error **errp) 1486 { 1487 VirtMachineState *vms = VIRT_MACHINE(obj); 1488 1489 vms->secure = value; 1490 } 1491 1492 static bool virt_get_virt(Object *obj, Error **errp) 1493 { 1494 VirtMachineState *vms = VIRT_MACHINE(obj); 1495 1496 return vms->virt; 1497 } 1498 1499 static void virt_set_virt(Object *obj, bool value, Error **errp) 1500 { 1501 VirtMachineState *vms = VIRT_MACHINE(obj); 1502 1503 vms->virt = value; 1504 } 1505 1506 static bool virt_get_highmem(Object *obj, Error **errp) 1507 { 1508 VirtMachineState *vms = VIRT_MACHINE(obj); 1509 1510 return vms->highmem; 1511 } 1512 1513 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1514 { 1515 VirtMachineState *vms = VIRT_MACHINE(obj); 1516 1517 vms->highmem = value; 1518 } 1519 1520 static bool virt_get_its(Object *obj, Error **errp) 1521 { 1522 VirtMachineState *vms = VIRT_MACHINE(obj); 1523 1524 return vms->its; 1525 } 1526 1527 static void virt_set_its(Object *obj, bool value, Error **errp) 1528 { 1529 VirtMachineState *vms = VIRT_MACHINE(obj); 1530 1531 vms->its = value; 1532 } 1533 1534 static char *virt_get_gic_version(Object *obj, Error **errp) 1535 { 1536 VirtMachineState *vms = VIRT_MACHINE(obj); 1537 const char *val = vms->gic_version == 3 ? "3" : "2"; 1538 1539 return g_strdup(val); 1540 } 1541 1542 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 1543 { 1544 VirtMachineState *vms = VIRT_MACHINE(obj); 1545 1546 if (!strcmp(value, "3")) { 1547 vms->gic_version = 3; 1548 } else if (!strcmp(value, "2")) { 1549 vms->gic_version = 2; 1550 } else if (!strcmp(value, "host")) { 1551 vms->gic_version = 0; /* Will probe later */ 1552 } else { 1553 error_setg(errp, "Invalid gic-version value"); 1554 error_append_hint(errp, "Valid values are 3, 2, host.\n"); 1555 } 1556 } 1557 1558 static CpuInstanceProperties 1559 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1560 { 1561 MachineClass *mc = MACHINE_GET_CLASS(ms); 1562 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1563 1564 assert(cpu_index < possible_cpus->len); 1565 return possible_cpus->cpus[cpu_index].props; 1566 } 1567 1568 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1569 { 1570 int n; 1571 VirtMachineState *vms = VIRT_MACHINE(ms); 1572 1573 if (ms->possible_cpus) { 1574 assert(ms->possible_cpus->len == max_cpus); 1575 return ms->possible_cpus; 1576 } 1577 1578 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1579 sizeof(CPUArchId) * max_cpus); 1580 ms->possible_cpus->len = max_cpus; 1581 for (n = 0; n < ms->possible_cpus->len; n++) { 1582 ms->possible_cpus->cpus[n].arch_id = 1583 virt_cpu_mp_affinity(vms, n); 1584 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1585 ms->possible_cpus->cpus[n].props.thread_id = n; 1586 1587 /* default distribution of CPUs over NUMA nodes */ 1588 if (nb_numa_nodes) { 1589 /* preset values but do not enable them i.e. 'has_node_id = false', 1590 * numa init code will enable them later if manual mapping wasn't 1591 * present on CLI */ 1592 ms->possible_cpus->cpus[n].props.node_id = n % nb_numa_nodes; 1593 } 1594 } 1595 return ms->possible_cpus; 1596 } 1597 1598 static void virt_machine_class_init(ObjectClass *oc, void *data) 1599 { 1600 MachineClass *mc = MACHINE_CLASS(oc); 1601 1602 mc->init = machvirt_init; 1603 /* Start max_cpus at the maximum QEMU supports. We'll further restrict 1604 * it later in machvirt_init, where we have more information about the 1605 * configuration of the particular instance. 1606 */ 1607 mc->max_cpus = 255; 1608 mc->has_dynamic_sysbus = true; 1609 mc->block_default_type = IF_VIRTIO; 1610 mc->no_cdrom = 1; 1611 mc->pci_allow_0_address = true; 1612 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 1613 mc->minimum_page_bits = 12; 1614 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1615 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1616 } 1617 1618 static const TypeInfo virt_machine_info = { 1619 .name = TYPE_VIRT_MACHINE, 1620 .parent = TYPE_MACHINE, 1621 .abstract = true, 1622 .instance_size = sizeof(VirtMachineState), 1623 .class_size = sizeof(VirtMachineClass), 1624 .class_init = virt_machine_class_init, 1625 }; 1626 1627 static void machvirt_machine_init(void) 1628 { 1629 type_register_static(&virt_machine_info); 1630 } 1631 type_init(machvirt_machine_init); 1632 1633 static void virt_2_9_instance_init(Object *obj) 1634 { 1635 VirtMachineState *vms = VIRT_MACHINE(obj); 1636 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1637 1638 /* EL3 is disabled by default on virt: this makes us consistent 1639 * between KVM and TCG for this board, and it also allows us to 1640 * boot UEFI blobs which assume no TrustZone support. 1641 */ 1642 vms->secure = false; 1643 object_property_add_bool(obj, "secure", virt_get_secure, 1644 virt_set_secure, NULL); 1645 object_property_set_description(obj, "secure", 1646 "Set on/off to enable/disable the ARM " 1647 "Security Extensions (TrustZone)", 1648 NULL); 1649 1650 /* EL2 is also disabled by default, for similar reasons */ 1651 vms->virt = false; 1652 object_property_add_bool(obj, "virtualization", virt_get_virt, 1653 virt_set_virt, NULL); 1654 object_property_set_description(obj, "virtualization", 1655 "Set on/off to enable/disable emulating a " 1656 "guest CPU which implements the ARM " 1657 "Virtualization Extensions", 1658 NULL); 1659 1660 /* High memory is enabled by default */ 1661 vms->highmem = true; 1662 object_property_add_bool(obj, "highmem", virt_get_highmem, 1663 virt_set_highmem, NULL); 1664 object_property_set_description(obj, "highmem", 1665 "Set on/off to enable/disable using " 1666 "physical address space above 32 bits", 1667 NULL); 1668 /* Default GIC type is v2 */ 1669 vms->gic_version = 2; 1670 object_property_add_str(obj, "gic-version", virt_get_gic_version, 1671 virt_set_gic_version, NULL); 1672 object_property_set_description(obj, "gic-version", 1673 "Set GIC version. " 1674 "Valid values are 2, 3 and host", NULL); 1675 1676 if (vmc->no_its) { 1677 vms->its = false; 1678 } else { 1679 /* Default allows ITS instantiation */ 1680 vms->its = true; 1681 object_property_add_bool(obj, "its", virt_get_its, 1682 virt_set_its, NULL); 1683 object_property_set_description(obj, "its", 1684 "Set on/off to enable/disable " 1685 "ITS instantiation", 1686 NULL); 1687 } 1688 1689 vms->memmap = a15memmap; 1690 vms->irqmap = a15irqmap; 1691 } 1692 1693 static void virt_machine_2_9_options(MachineClass *mc) 1694 { 1695 } 1696 DEFINE_VIRT_MACHINE_AS_LATEST(2, 9) 1697 1698 #define VIRT_COMPAT_2_8 \ 1699 HW_COMPAT_2_8 1700 1701 static void virt_2_8_instance_init(Object *obj) 1702 { 1703 virt_2_9_instance_init(obj); 1704 } 1705 1706 static void virt_machine_2_8_options(MachineClass *mc) 1707 { 1708 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1709 1710 virt_machine_2_9_options(mc); 1711 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_8); 1712 /* For 2.8 and earlier we falsely claimed in the DT that 1713 * our timers were edge-triggered, not level-triggered. 1714 */ 1715 vmc->claim_edge_triggered_timers = true; 1716 } 1717 DEFINE_VIRT_MACHINE(2, 8) 1718 1719 #define VIRT_COMPAT_2_7 \ 1720 HW_COMPAT_2_7 1721 1722 static void virt_2_7_instance_init(Object *obj) 1723 { 1724 virt_2_8_instance_init(obj); 1725 } 1726 1727 static void virt_machine_2_7_options(MachineClass *mc) 1728 { 1729 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1730 1731 virt_machine_2_8_options(mc); 1732 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_7); 1733 /* ITS was introduced with 2.8 */ 1734 vmc->no_its = true; 1735 /* Stick with 1K pages for migration compatibility */ 1736 mc->minimum_page_bits = 0; 1737 } 1738 DEFINE_VIRT_MACHINE(2, 7) 1739 1740 #define VIRT_COMPAT_2_6 \ 1741 HW_COMPAT_2_6 1742 1743 static void virt_2_6_instance_init(Object *obj) 1744 { 1745 virt_2_7_instance_init(obj); 1746 } 1747 1748 static void virt_machine_2_6_options(MachineClass *mc) 1749 { 1750 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1751 1752 virt_machine_2_7_options(mc); 1753 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6); 1754 vmc->disallow_affinity_adjustment = true; 1755 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 1756 vmc->no_pmu = true; 1757 } 1758 DEFINE_VIRT_MACHINE(2, 6) 1759