1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/datadir.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "qapi/error.h" 37 #include "hw/sysbus.h" 38 #include "hw/arm/boot.h" 39 #include "hw/arm/primecell.h" 40 #include "hw/arm/virt.h" 41 #include "hw/block/flash.h" 42 #include "hw/vfio/vfio-calxeda-xgmac.h" 43 #include "hw/vfio/vfio-amd-xgbe.h" 44 #include "hw/display/ramfb.h" 45 #include "net/net.h" 46 #include "sysemu/device_tree.h" 47 #include "sysemu/numa.h" 48 #include "sysemu/runstate.h" 49 #include "sysemu/tpm.h" 50 #include "sysemu/kvm.h" 51 #include "sysemu/hvf.h" 52 #include "hw/loader.h" 53 #include "qapi/error.h" 54 #include "qemu/bitops.h" 55 #include "qemu/error-report.h" 56 #include "qemu/module.h" 57 #include "hw/pci-host/gpex.h" 58 #include "hw/virtio/virtio-pci.h" 59 #include "hw/arm/sysbus-fdt.h" 60 #include "hw/platform-bus.h" 61 #include "hw/qdev-properties.h" 62 #include "hw/arm/fdt.h" 63 #include "hw/intc/arm_gic.h" 64 #include "hw/intc/arm_gicv3_common.h" 65 #include "hw/irq.h" 66 #include "kvm_arm.h" 67 #include "hw/firmware/smbios.h" 68 #include "qapi/visitor.h" 69 #include "qapi/qapi-visit-common.h" 70 #include "standard-headers/linux/input.h" 71 #include "hw/arm/smmuv3.h" 72 #include "hw/acpi/acpi.h" 73 #include "target/arm/internals.h" 74 #include "hw/mem/memory-device.h" 75 #include "hw/mem/pc-dimm.h" 76 #include "hw/mem/nvdimm.h" 77 #include "hw/acpi/generic_event_device.h" 78 #include "hw/virtio/virtio-mem-pci.h" 79 #include "hw/virtio/virtio-iommu.h" 80 #include "hw/char/pl011.h" 81 #include "qemu/guest-random.h" 82 83 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 84 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 85 void *data) \ 86 { \ 87 MachineClass *mc = MACHINE_CLASS(oc); \ 88 virt_machine_##major##_##minor##_options(mc); \ 89 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 90 if (latest) { \ 91 mc->alias = "virt"; \ 92 } \ 93 } \ 94 static const TypeInfo machvirt_##major##_##minor##_info = { \ 95 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 96 .parent = TYPE_VIRT_MACHINE, \ 97 .class_init = virt_##major##_##minor##_class_init, \ 98 }; \ 99 static void machvirt_machine_##major##_##minor##_init(void) \ 100 { \ 101 type_register_static(&machvirt_##major##_##minor##_info); \ 102 } \ 103 type_init(machvirt_machine_##major##_##minor##_init); 104 105 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 106 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 107 #define DEFINE_VIRT_MACHINE(major, minor) \ 108 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 109 110 111 /* Number of external interrupt lines to configure the GIC with */ 112 #define NUM_IRQS 256 113 114 #define PLATFORM_BUS_NUM_IRQS 64 115 116 /* Legacy RAM limit in GB (< version 4.0) */ 117 #define LEGACY_RAMLIMIT_GB 255 118 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 119 120 /* Addresses and sizes of our components. 121 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 122 * 128MB..256MB is used for miscellaneous device I/O. 123 * 256MB..1GB is reserved for possible future PCI support (ie where the 124 * PCI memory window will go if we add a PCI host controller). 125 * 1GB and up is RAM (which may happily spill over into the 126 * high memory region beyond 4GB). 127 * This represents a compromise between how much RAM can be given to 128 * a 32 bit VM and leaving space for expansion and in particular for PCI. 129 * Note that devices should generally be placed at multiples of 0x10000, 130 * to accommodate guests using 64K pages. 131 */ 132 static const MemMapEntry base_memmap[] = { 133 /* Space up to 0x8000000 is reserved for a boot ROM */ 134 [VIRT_FLASH] = { 0, 0x08000000 }, 135 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 136 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 137 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 138 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 139 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 140 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 141 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 142 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 143 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 144 /* This redistributor space allows up to 2*64kB*123 CPUs */ 145 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 146 [VIRT_UART] = { 0x09000000, 0x00001000 }, 147 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 148 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 149 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 150 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 151 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 152 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 153 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 154 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 155 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, 156 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, 157 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 158 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 159 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 160 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 161 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 162 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 163 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 164 /* Actual RAM size depends on initial RAM and device memory settings */ 165 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 166 }; 167 168 /* 169 * Highmem IO Regions: This memory map is floating, located after the RAM. 170 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 171 * top of the RAM, so that its base get the same alignment as the size, 172 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 173 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 174 * Note the extended_memmap is sized so that it eventually also includes the 175 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 176 * index of base_memmap). 177 */ 178 static MemMapEntry extended_memmap[] = { 179 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 180 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 181 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 182 /* Second PCIe window */ 183 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 184 }; 185 186 static const int a15irqmap[] = { 187 [VIRT_UART] = 1, 188 [VIRT_RTC] = 2, 189 [VIRT_PCIE] = 3, /* ... to 6 */ 190 [VIRT_GPIO] = 7, 191 [VIRT_SECURE_UART] = 8, 192 [VIRT_ACPI_GED] = 9, 193 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 194 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 195 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 196 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 197 }; 198 199 static const char *valid_cpus[] = { 200 ARM_CPU_TYPE_NAME("cortex-a7"), 201 ARM_CPU_TYPE_NAME("cortex-a15"), 202 ARM_CPU_TYPE_NAME("cortex-a53"), 203 ARM_CPU_TYPE_NAME("cortex-a57"), 204 ARM_CPU_TYPE_NAME("cortex-a72"), 205 ARM_CPU_TYPE_NAME("a64fx"), 206 ARM_CPU_TYPE_NAME("host"), 207 ARM_CPU_TYPE_NAME("max"), 208 }; 209 210 static bool cpu_type_valid(const char *cpu) 211 { 212 int i; 213 214 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 215 if (strcmp(cpu, valid_cpus[i]) == 0) { 216 return true; 217 } 218 } 219 return false; 220 } 221 222 static void create_kaslr_seed(MachineState *ms, const char *node) 223 { 224 uint64_t seed; 225 226 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { 227 return; 228 } 229 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed); 230 } 231 232 static void create_fdt(VirtMachineState *vms) 233 { 234 MachineState *ms = MACHINE(vms); 235 int nb_numa_nodes = ms->numa_state->num_nodes; 236 void *fdt = create_device_tree(&vms->fdt_size); 237 238 if (!fdt) { 239 error_report("create_device_tree() failed"); 240 exit(1); 241 } 242 243 ms->fdt = fdt; 244 245 /* Header */ 246 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 247 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 248 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 249 250 /* /chosen must exist for load_dtb to fill in necessary properties later */ 251 qemu_fdt_add_subnode(fdt, "/chosen"); 252 if (vms->dtb_kaslr_seed) { 253 create_kaslr_seed(ms, "/chosen"); 254 } 255 256 if (vms->secure) { 257 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 258 if (vms->dtb_kaslr_seed) { 259 create_kaslr_seed(ms, "/secure-chosen"); 260 } 261 } 262 263 /* Clock node, for the benefit of the UART. The kernel device tree 264 * binding documentation claims the PL011 node clock properties are 265 * optional but in practice if you omit them the kernel refuses to 266 * probe for the device. 267 */ 268 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 269 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 270 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 271 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 272 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 273 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 274 "clk24mhz"); 275 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 276 277 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 278 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 279 uint32_t *matrix = g_malloc0(size); 280 int idx, i, j; 281 282 for (i = 0; i < nb_numa_nodes; i++) { 283 for (j = 0; j < nb_numa_nodes; j++) { 284 idx = (i * nb_numa_nodes + j) * 3; 285 matrix[idx + 0] = cpu_to_be32(i); 286 matrix[idx + 1] = cpu_to_be32(j); 287 matrix[idx + 2] = 288 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 289 } 290 } 291 292 qemu_fdt_add_subnode(fdt, "/distance-map"); 293 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 294 "numa-distance-map-v1"); 295 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 296 matrix, size); 297 g_free(matrix); 298 } 299 } 300 301 static void fdt_add_timer_nodes(const VirtMachineState *vms) 302 { 303 /* On real hardware these interrupts are level-triggered. 304 * On KVM they were edge-triggered before host kernel version 4.4, 305 * and level-triggered afterwards. 306 * On emulated QEMU they are level-triggered. 307 * 308 * Getting the DTB info about them wrong is awkward for some 309 * guest kernels: 310 * pre-4.8 ignore the DT and leave the interrupt configured 311 * with whatever the GIC reset value (or the bootloader) left it at 312 * 4.8 before rc6 honour the incorrect data by programming it back 313 * into the GIC, causing problems 314 * 4.8rc6 and later ignore the DT and always write "level triggered" 315 * into the GIC 316 * 317 * For backwards-compatibility, virt-2.8 and earlier will continue 318 * to say these are edge-triggered, but later machines will report 319 * the correct information. 320 */ 321 ARMCPU *armcpu; 322 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 323 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 324 MachineState *ms = MACHINE(vms); 325 326 if (vmc->claim_edge_triggered_timers) { 327 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 328 } 329 330 if (vms->gic_version == VIRT_GIC_VERSION_2) { 331 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 332 GIC_FDT_IRQ_PPI_CPU_WIDTH, 333 (1 << MACHINE(vms)->smp.cpus) - 1); 334 } 335 336 qemu_fdt_add_subnode(ms->fdt, "/timer"); 337 338 armcpu = ARM_CPU(qemu_get_cpu(0)); 339 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 340 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 341 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", 342 compat, sizeof(compat)); 343 } else { 344 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", 345 "arm,armv7-timer"); 346 } 347 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); 348 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 349 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 350 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 351 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 352 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 353 } 354 355 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 356 { 357 int cpu; 358 int addr_cells = 1; 359 const MachineState *ms = MACHINE(vms); 360 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 361 int smp_cpus = ms->smp.cpus; 362 363 /* 364 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml 365 * On ARM v8 64-bit systems value should be set to 2, 366 * that corresponds to the MPIDR_EL1 register size. 367 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 368 * in the system, #address-cells can be set to 1, since 369 * MPIDR_EL1[63:32] bits are not used for CPUs 370 * identification. 371 * 372 * Here we actually don't know whether our system is 32- or 64-bit one. 373 * The simplest way to go is to examine affinity IDs of all our CPUs. If 374 * at least one of them has Aff3 populated, we set #address-cells to 2. 375 */ 376 for (cpu = 0; cpu < smp_cpus; cpu++) { 377 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 378 379 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 380 addr_cells = 2; 381 break; 382 } 383 } 384 385 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 386 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); 387 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 388 389 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 390 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 391 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 392 CPUState *cs = CPU(armcpu); 393 394 qemu_fdt_add_subnode(ms->fdt, nodename); 395 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 396 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 397 armcpu->dtb_compatible); 398 399 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { 400 qemu_fdt_setprop_string(ms->fdt, nodename, 401 "enable-method", "psci"); 402 } 403 404 if (addr_cells == 2) { 405 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", 406 armcpu->mp_affinity); 407 } else { 408 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", 409 armcpu->mp_affinity); 410 } 411 412 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 413 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 414 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 415 } 416 417 if (!vmc->no_cpu_topology) { 418 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 419 qemu_fdt_alloc_phandle(ms->fdt)); 420 } 421 422 g_free(nodename); 423 } 424 425 if (!vmc->no_cpu_topology) { 426 /* 427 * Add vCPU topology description through fdt node cpu-map. 428 * 429 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt 430 * In a SMP system, the hierarchy of CPUs can be defined through 431 * four entities that are used to describe the layout of CPUs in 432 * the system: socket/cluster/core/thread. 433 * 434 * A socket node represents the boundary of system physical package 435 * and its child nodes must be one or more cluster nodes. A system 436 * can contain several layers of clustering within a single physical 437 * package and cluster nodes can be contained in parent cluster nodes. 438 * 439 * Note: currently we only support one layer of clustering within 440 * each physical package. 441 */ 442 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 443 444 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 445 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); 446 char *map_path; 447 448 if (ms->smp.threads > 1) { 449 map_path = g_strdup_printf( 450 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", 451 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), 452 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, 453 (cpu / ms->smp.threads) % ms->smp.cores, 454 cpu % ms->smp.threads); 455 } else { 456 map_path = g_strdup_printf( 457 "/cpus/cpu-map/socket%d/cluster%d/core%d", 458 cpu / (ms->smp.clusters * ms->smp.cores), 459 (cpu / ms->smp.cores) % ms->smp.clusters, 460 cpu % ms->smp.cores); 461 } 462 qemu_fdt_add_path(ms->fdt, map_path); 463 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 464 465 g_free(map_path); 466 g_free(cpu_path); 467 } 468 } 469 } 470 471 static void fdt_add_its_gic_node(VirtMachineState *vms) 472 { 473 char *nodename; 474 MachineState *ms = MACHINE(vms); 475 476 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 477 nodename = g_strdup_printf("/intc/its@%" PRIx64, 478 vms->memmap[VIRT_GIC_ITS].base); 479 qemu_fdt_add_subnode(ms->fdt, nodename); 480 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 481 "arm,gic-v3-its"); 482 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 483 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 484 2, vms->memmap[VIRT_GIC_ITS].base, 485 2, vms->memmap[VIRT_GIC_ITS].size); 486 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 487 g_free(nodename); 488 } 489 490 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 491 { 492 MachineState *ms = MACHINE(vms); 493 char *nodename; 494 495 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 496 vms->memmap[VIRT_GIC_V2M].base); 497 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 498 qemu_fdt_add_subnode(ms->fdt, nodename); 499 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 500 "arm,gic-v2m-frame"); 501 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 502 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 503 2, vms->memmap[VIRT_GIC_V2M].base, 504 2, vms->memmap[VIRT_GIC_V2M].size); 505 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 506 g_free(nodename); 507 } 508 509 static void fdt_add_gic_node(VirtMachineState *vms) 510 { 511 MachineState *ms = MACHINE(vms); 512 char *nodename; 513 514 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 515 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); 516 517 nodename = g_strdup_printf("/intc@%" PRIx64, 518 vms->memmap[VIRT_GIC_DIST].base); 519 qemu_fdt_add_subnode(ms->fdt, nodename); 520 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 521 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 522 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 523 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 524 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 525 if (vms->gic_version == VIRT_GIC_VERSION_3) { 526 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 527 528 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 529 "arm,gic-v3"); 530 531 qemu_fdt_setprop_cell(ms->fdt, nodename, 532 "#redistributor-regions", nb_redist_regions); 533 534 if (nb_redist_regions == 1) { 535 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 536 2, vms->memmap[VIRT_GIC_DIST].base, 537 2, vms->memmap[VIRT_GIC_DIST].size, 538 2, vms->memmap[VIRT_GIC_REDIST].base, 539 2, vms->memmap[VIRT_GIC_REDIST].size); 540 } else { 541 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 542 2, vms->memmap[VIRT_GIC_DIST].base, 543 2, vms->memmap[VIRT_GIC_DIST].size, 544 2, vms->memmap[VIRT_GIC_REDIST].base, 545 2, vms->memmap[VIRT_GIC_REDIST].size, 546 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 547 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 548 } 549 550 if (vms->virt) { 551 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 552 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 553 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 554 } 555 } else { 556 /* 'cortex-a15-gic' means 'GIC v2' */ 557 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 558 "arm,cortex-a15-gic"); 559 if (!vms->virt) { 560 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 561 2, vms->memmap[VIRT_GIC_DIST].base, 562 2, vms->memmap[VIRT_GIC_DIST].size, 563 2, vms->memmap[VIRT_GIC_CPU].base, 564 2, vms->memmap[VIRT_GIC_CPU].size); 565 } else { 566 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 567 2, vms->memmap[VIRT_GIC_DIST].base, 568 2, vms->memmap[VIRT_GIC_DIST].size, 569 2, vms->memmap[VIRT_GIC_CPU].base, 570 2, vms->memmap[VIRT_GIC_CPU].size, 571 2, vms->memmap[VIRT_GIC_HYP].base, 572 2, vms->memmap[VIRT_GIC_HYP].size, 573 2, vms->memmap[VIRT_GIC_VCPU].base, 574 2, vms->memmap[VIRT_GIC_VCPU].size); 575 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 576 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 577 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 578 } 579 } 580 581 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); 582 g_free(nodename); 583 } 584 585 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 586 { 587 ARMCPU *armcpu = ARM_CPU(first_cpu); 588 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 589 MachineState *ms = MACHINE(vms); 590 591 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 592 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); 593 return; 594 } 595 596 if (vms->gic_version == VIRT_GIC_VERSION_2) { 597 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 598 GIC_FDT_IRQ_PPI_CPU_WIDTH, 599 (1 << MACHINE(vms)->smp.cpus) - 1); 600 } 601 602 qemu_fdt_add_subnode(ms->fdt, "/pmu"); 603 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 604 const char compat[] = "arm,armv8-pmuv3"; 605 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", 606 compat, sizeof(compat)); 607 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", 608 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 609 } 610 } 611 612 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 613 { 614 DeviceState *dev; 615 MachineState *ms = MACHINE(vms); 616 int irq = vms->irqmap[VIRT_ACPI_GED]; 617 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 618 619 if (ms->ram_slots) { 620 event |= ACPI_GED_MEM_HOTPLUG_EVT; 621 } 622 623 if (ms->nvdimms_state->is_enabled) { 624 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 625 } 626 627 dev = qdev_new(TYPE_ACPI_GED); 628 qdev_prop_set_uint32(dev, "ged-event", event); 629 630 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 631 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 632 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 633 634 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 635 636 return dev; 637 } 638 639 static void create_its(VirtMachineState *vms) 640 { 641 const char *itsclass = its_class_name(); 642 DeviceState *dev; 643 644 if (!strcmp(itsclass, "arm-gicv3-its")) { 645 if (!vms->tcg_its) { 646 itsclass = NULL; 647 } 648 } 649 650 if (!itsclass) { 651 /* Do nothing if not supported */ 652 return; 653 } 654 655 dev = qdev_new(itsclass); 656 657 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 658 &error_abort); 659 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 660 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 661 662 fdt_add_its_gic_node(vms); 663 vms->msi_controller = VIRT_MSI_CTRL_ITS; 664 } 665 666 static void create_v2m(VirtMachineState *vms) 667 { 668 int i; 669 int irq = vms->irqmap[VIRT_GIC_V2M]; 670 DeviceState *dev; 671 672 dev = qdev_new("arm-gicv2m"); 673 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 674 qdev_prop_set_uint32(dev, "base-spi", irq); 675 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 676 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 677 678 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 679 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 680 qdev_get_gpio_in(vms->gic, irq + i)); 681 } 682 683 fdt_add_v2m_gic_node(vms); 684 vms->msi_controller = VIRT_MSI_CTRL_GICV2M; 685 } 686 687 static void create_gic(VirtMachineState *vms, MemoryRegion *mem) 688 { 689 MachineState *ms = MACHINE(vms); 690 /* We create a standalone GIC */ 691 SysBusDevice *gicbusdev; 692 const char *gictype; 693 int type = vms->gic_version, i; 694 unsigned int smp_cpus = ms->smp.cpus; 695 uint32_t nb_redist_regions = 0; 696 697 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 698 699 vms->gic = qdev_new(gictype); 700 qdev_prop_set_uint32(vms->gic, "revision", type); 701 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 702 /* Note that the num-irq property counts both internal and external 703 * interrupts; there are always 32 of the former (mandated by GIC spec). 704 */ 705 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 706 if (!kvm_irqchip_in_kernel()) { 707 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 708 } 709 710 if (type == 3) { 711 uint32_t redist0_capacity = 712 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 713 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 714 715 nb_redist_regions = virt_gicv3_redist_region_count(vms); 716 717 qdev_prop_set_uint32(vms->gic, "len-redist-region-count", 718 nb_redist_regions); 719 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count); 720 721 if (!kvm_irqchip_in_kernel()) { 722 if (vms->tcg_its) { 723 object_property_set_link(OBJECT(vms->gic), "sysmem", 724 OBJECT(mem), &error_fatal); 725 qdev_prop_set_bit(vms->gic, "has-lpi", true); 726 } 727 } 728 729 if (nb_redist_regions == 2) { 730 uint32_t redist1_capacity = 731 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; 732 733 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", 734 MIN(smp_cpus - redist0_count, redist1_capacity)); 735 } 736 } else { 737 if (!kvm_irqchip_in_kernel()) { 738 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 739 vms->virt); 740 } 741 } 742 gicbusdev = SYS_BUS_DEVICE(vms->gic); 743 sysbus_realize_and_unref(gicbusdev, &error_fatal); 744 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 745 if (type == 3) { 746 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 747 if (nb_redist_regions == 2) { 748 sysbus_mmio_map(gicbusdev, 2, 749 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 750 } 751 } else { 752 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 753 if (vms->virt) { 754 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 755 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 756 } 757 } 758 759 /* Wire the outputs from each CPU's generic timer and the GICv3 760 * maintenance interrupt signal to the appropriate GIC PPI inputs, 761 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 762 */ 763 for (i = 0; i < smp_cpus; i++) { 764 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 765 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 766 int irq; 767 /* Mapping from the output timer irq lines from the CPU to the 768 * GIC PPI inputs we use for the virt board. 769 */ 770 const int timer_irq[] = { 771 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 772 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 773 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 774 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 775 }; 776 777 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 778 qdev_connect_gpio_out(cpudev, irq, 779 qdev_get_gpio_in(vms->gic, 780 ppibase + timer_irq[irq])); 781 } 782 783 if (type == 3) { 784 qemu_irq irq = qdev_get_gpio_in(vms->gic, 785 ppibase + ARCH_GIC_MAINT_IRQ); 786 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 787 0, irq); 788 } else if (vms->virt) { 789 qemu_irq irq = qdev_get_gpio_in(vms->gic, 790 ppibase + ARCH_GIC_MAINT_IRQ); 791 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 792 } 793 794 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 795 qdev_get_gpio_in(vms->gic, ppibase 796 + VIRTUAL_PMU_IRQ)); 797 798 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 799 sysbus_connect_irq(gicbusdev, i + smp_cpus, 800 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 801 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 802 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 803 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 804 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 805 } 806 807 fdt_add_gic_node(vms); 808 809 if (type == 3 && vms->its) { 810 create_its(vms); 811 } else if (type == 2) { 812 create_v2m(vms); 813 } 814 } 815 816 static void create_uart(const VirtMachineState *vms, int uart, 817 MemoryRegion *mem, Chardev *chr) 818 { 819 char *nodename; 820 hwaddr base = vms->memmap[uart].base; 821 hwaddr size = vms->memmap[uart].size; 822 int irq = vms->irqmap[uart]; 823 const char compat[] = "arm,pl011\0arm,primecell"; 824 const char clocknames[] = "uartclk\0apb_pclk"; 825 DeviceState *dev = qdev_new(TYPE_PL011); 826 SysBusDevice *s = SYS_BUS_DEVICE(dev); 827 MachineState *ms = MACHINE(vms); 828 829 qdev_prop_set_chr(dev, "chardev", chr); 830 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 831 memory_region_add_subregion(mem, base, 832 sysbus_mmio_get_region(s, 0)); 833 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 834 835 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 836 qemu_fdt_add_subnode(ms->fdt, nodename); 837 /* Note that we can't use setprop_string because of the embedded NUL */ 838 qemu_fdt_setprop(ms->fdt, nodename, "compatible", 839 compat, sizeof(compat)); 840 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 841 2, base, 2, size); 842 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 843 GIC_FDT_IRQ_TYPE_SPI, irq, 844 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 845 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", 846 vms->clock_phandle, vms->clock_phandle); 847 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", 848 clocknames, sizeof(clocknames)); 849 850 if (uart == VIRT_UART) { 851 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 852 } else { 853 /* Mark as not usable by the normal world */ 854 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 855 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 856 857 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", 858 nodename); 859 } 860 861 g_free(nodename); 862 } 863 864 static void create_rtc(const VirtMachineState *vms) 865 { 866 char *nodename; 867 hwaddr base = vms->memmap[VIRT_RTC].base; 868 hwaddr size = vms->memmap[VIRT_RTC].size; 869 int irq = vms->irqmap[VIRT_RTC]; 870 const char compat[] = "arm,pl031\0arm,primecell"; 871 MachineState *ms = MACHINE(vms); 872 873 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 874 875 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 876 qemu_fdt_add_subnode(ms->fdt, nodename); 877 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 878 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 879 2, base, 2, size); 880 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 881 GIC_FDT_IRQ_TYPE_SPI, irq, 882 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 883 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 884 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 885 g_free(nodename); 886 } 887 888 static DeviceState *gpio_key_dev; 889 static void virt_powerdown_req(Notifier *n, void *opaque) 890 { 891 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 892 893 if (s->acpi_dev) { 894 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 895 } else { 896 /* use gpio Pin 3 for power button event */ 897 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 898 } 899 } 900 901 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, 902 uint32_t phandle) 903 { 904 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 905 qdev_get_gpio_in(pl061_dev, 3)); 906 907 qemu_fdt_add_subnode(fdt, "/gpio-keys"); 908 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); 909 qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#size-cells", 0); 910 qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#address-cells", 1); 911 912 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); 913 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", 914 "label", "GPIO Key Poweroff"); 915 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", 916 KEY_POWER); 917 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", 918 "gpios", phandle, 3, 0); 919 } 920 921 #define SECURE_GPIO_POWEROFF 0 922 #define SECURE_GPIO_RESET 1 923 924 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, 925 uint32_t phandle) 926 { 927 DeviceState *gpio_pwr_dev; 928 929 /* gpio-pwr */ 930 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); 931 932 /* connect secure pl061 to gpio-pwr */ 933 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, 934 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); 935 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, 936 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); 937 938 qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); 939 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", 940 "gpio-poweroff"); 941 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", 942 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); 943 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); 944 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", 945 "okay"); 946 947 qemu_fdt_add_subnode(fdt, "/gpio-restart"); 948 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", 949 "gpio-restart"); 950 qemu_fdt_setprop_cells(fdt, "/gpio-restart", 951 "gpios", phandle, SECURE_GPIO_RESET, 0); 952 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); 953 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", 954 "okay"); 955 } 956 957 static void create_gpio_devices(const VirtMachineState *vms, int gpio, 958 MemoryRegion *mem) 959 { 960 char *nodename; 961 DeviceState *pl061_dev; 962 hwaddr base = vms->memmap[gpio].base; 963 hwaddr size = vms->memmap[gpio].size; 964 int irq = vms->irqmap[gpio]; 965 const char compat[] = "arm,pl061\0arm,primecell"; 966 SysBusDevice *s; 967 MachineState *ms = MACHINE(vms); 968 969 pl061_dev = qdev_new("pl061"); 970 /* Pull lines down to 0 if not driven by the PL061 */ 971 qdev_prop_set_uint32(pl061_dev, "pullups", 0); 972 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); 973 s = SYS_BUS_DEVICE(pl061_dev); 974 sysbus_realize_and_unref(s, &error_fatal); 975 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); 976 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 977 978 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); 979 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 980 qemu_fdt_add_subnode(ms->fdt, nodename); 981 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 982 2, base, 2, size); 983 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 984 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); 985 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); 986 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 987 GIC_FDT_IRQ_TYPE_SPI, irq, 988 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 989 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 990 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 991 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); 992 993 if (gpio != VIRT_GPIO) { 994 /* Mark as not usable by the normal world */ 995 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 996 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 997 } 998 g_free(nodename); 999 1000 /* Child gpio devices */ 1001 if (gpio == VIRT_GPIO) { 1002 create_gpio_keys(ms->fdt, pl061_dev, phandle); 1003 } else { 1004 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); 1005 } 1006 } 1007 1008 static void create_virtio_devices(const VirtMachineState *vms) 1009 { 1010 int i; 1011 hwaddr size = vms->memmap[VIRT_MMIO].size; 1012 MachineState *ms = MACHINE(vms); 1013 1014 /* We create the transports in forwards order. Since qbus_realize() 1015 * prepends (not appends) new child buses, the incrementing loop below will 1016 * create a list of virtio-mmio buses with decreasing base addresses. 1017 * 1018 * When a -device option is processed from the command line, 1019 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 1020 * order. The upshot is that -device options in increasing command line 1021 * order are mapped to virtio-mmio buses with decreasing base addresses. 1022 * 1023 * When this code was originally written, that arrangement ensured that the 1024 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 1025 * the first -device on the command line. (The end-to-end order is a 1026 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 1027 * guest kernel's name-to-address assignment strategy.) 1028 * 1029 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 1030 * the message, if not necessarily the code, of commit 70161ff336. 1031 * Therefore the loop now establishes the inverse of the original intent. 1032 * 1033 * Unfortunately, we can't counteract the kernel change by reversing the 1034 * loop; it would break existing command lines. 1035 * 1036 * In any case, the kernel makes no guarantee about the stability of 1037 * enumeration order of virtio devices (as demonstrated by it changing 1038 * between kernel versions). For reliable and stable identification 1039 * of disks users must use UUIDs or similar mechanisms. 1040 */ 1041 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 1042 int irq = vms->irqmap[VIRT_MMIO] + i; 1043 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1044 1045 sysbus_create_simple("virtio-mmio", base, 1046 qdev_get_gpio_in(vms->gic, irq)); 1047 } 1048 1049 /* We add dtb nodes in reverse order so that they appear in the finished 1050 * device tree lowest address first. 1051 * 1052 * Note that this mapping is independent of the loop above. The previous 1053 * loop influences virtio device to virtio transport assignment, whereas 1054 * this loop controls how virtio transports are laid out in the dtb. 1055 */ 1056 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 1057 char *nodename; 1058 int irq = vms->irqmap[VIRT_MMIO] + i; 1059 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1060 1061 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 1062 qemu_fdt_add_subnode(ms->fdt, nodename); 1063 qemu_fdt_setprop_string(ms->fdt, nodename, 1064 "compatible", "virtio,mmio"); 1065 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1066 2, base, 2, size); 1067 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1068 GIC_FDT_IRQ_TYPE_SPI, irq, 1069 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1070 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1071 g_free(nodename); 1072 } 1073 } 1074 1075 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 1076 1077 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 1078 const char *name, 1079 const char *alias_prop_name) 1080 { 1081 /* 1082 * Create a single flash device. We use the same parameters as 1083 * the flash devices on the Versatile Express board. 1084 */ 1085 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 1086 1087 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 1088 qdev_prop_set_uint8(dev, "width", 4); 1089 qdev_prop_set_uint8(dev, "device-width", 2); 1090 qdev_prop_set_bit(dev, "big-endian", false); 1091 qdev_prop_set_uint16(dev, "id0", 0x89); 1092 qdev_prop_set_uint16(dev, "id1", 0x18); 1093 qdev_prop_set_uint16(dev, "id2", 0x00); 1094 qdev_prop_set_uint16(dev, "id3", 0x00); 1095 qdev_prop_set_string(dev, "name", name); 1096 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 1097 object_property_add_alias(OBJECT(vms), alias_prop_name, 1098 OBJECT(dev), "drive"); 1099 return PFLASH_CFI01(dev); 1100 } 1101 1102 static void virt_flash_create(VirtMachineState *vms) 1103 { 1104 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 1105 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 1106 } 1107 1108 static void virt_flash_map1(PFlashCFI01 *flash, 1109 hwaddr base, hwaddr size, 1110 MemoryRegion *sysmem) 1111 { 1112 DeviceState *dev = DEVICE(flash); 1113 1114 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 1115 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 1116 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 1117 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1118 1119 memory_region_add_subregion(sysmem, base, 1120 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1121 0)); 1122 } 1123 1124 static void virt_flash_map(VirtMachineState *vms, 1125 MemoryRegion *sysmem, 1126 MemoryRegion *secure_sysmem) 1127 { 1128 /* 1129 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 1130 * sysmem is the system memory space. secure_sysmem is the secure view 1131 * of the system, and the first flash device should be made visible only 1132 * there. The second flash device is visible to both secure and nonsecure. 1133 * If sysmem == secure_sysmem this means there is no separate Secure 1134 * address space and both flash devices are generally visible. 1135 */ 1136 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1137 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1138 1139 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1140 secure_sysmem); 1141 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1142 sysmem); 1143 } 1144 1145 static void virt_flash_fdt(VirtMachineState *vms, 1146 MemoryRegion *sysmem, 1147 MemoryRegion *secure_sysmem) 1148 { 1149 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1150 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1151 MachineState *ms = MACHINE(vms); 1152 char *nodename; 1153 1154 if (sysmem == secure_sysmem) { 1155 /* Report both flash devices as a single node in the DT */ 1156 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1157 qemu_fdt_add_subnode(ms->fdt, nodename); 1158 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1159 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1160 2, flashbase, 2, flashsize, 1161 2, flashbase + flashsize, 2, flashsize); 1162 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1163 g_free(nodename); 1164 } else { 1165 /* 1166 * Report the devices as separate nodes so we can mark one as 1167 * only visible to the secure world. 1168 */ 1169 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1170 qemu_fdt_add_subnode(ms->fdt, nodename); 1171 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1172 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1173 2, flashbase, 2, flashsize); 1174 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1175 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1176 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1177 g_free(nodename); 1178 1179 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1180 qemu_fdt_add_subnode(ms->fdt, nodename); 1181 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1182 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1183 2, flashbase + flashsize, 2, flashsize); 1184 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1185 g_free(nodename); 1186 } 1187 } 1188 1189 static bool virt_firmware_init(VirtMachineState *vms, 1190 MemoryRegion *sysmem, 1191 MemoryRegion *secure_sysmem) 1192 { 1193 int i; 1194 const char *bios_name; 1195 BlockBackend *pflash_blk0; 1196 1197 /* Map legacy -drive if=pflash to machine properties */ 1198 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1199 pflash_cfi01_legacy_drive(vms->flash[i], 1200 drive_get(IF_PFLASH, 0, i)); 1201 } 1202 1203 virt_flash_map(vms, sysmem, secure_sysmem); 1204 1205 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1206 1207 bios_name = MACHINE(vms)->firmware; 1208 if (bios_name) { 1209 char *fname; 1210 MemoryRegion *mr; 1211 int image_size; 1212 1213 if (pflash_blk0) { 1214 error_report("The contents of the first flash device may be " 1215 "specified with -bios or with -drive if=pflash... " 1216 "but you cannot use both options at once"); 1217 exit(1); 1218 } 1219 1220 /* Fall back to -bios */ 1221 1222 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1223 if (!fname) { 1224 error_report("Could not find ROM image '%s'", bios_name); 1225 exit(1); 1226 } 1227 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1228 image_size = load_image_mr(fname, mr); 1229 g_free(fname); 1230 if (image_size < 0) { 1231 error_report("Could not load ROM image '%s'", bios_name); 1232 exit(1); 1233 } 1234 } 1235 1236 return pflash_blk0 || bios_name; 1237 } 1238 1239 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1240 { 1241 MachineState *ms = MACHINE(vms); 1242 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1243 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1244 FWCfgState *fw_cfg; 1245 char *nodename; 1246 1247 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1248 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1249 1250 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1251 qemu_fdt_add_subnode(ms->fdt, nodename); 1252 qemu_fdt_setprop_string(ms->fdt, nodename, 1253 "compatible", "qemu,fw-cfg-mmio"); 1254 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1255 2, base, 2, size); 1256 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1257 g_free(nodename); 1258 return fw_cfg; 1259 } 1260 1261 static void create_pcie_irq_map(const MachineState *ms, 1262 uint32_t gic_phandle, 1263 int first_irq, const char *nodename) 1264 { 1265 int devfn, pin; 1266 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1267 uint32_t *irq_map = full_irq_map; 1268 1269 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1270 for (pin = 0; pin < 4; pin++) { 1271 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1272 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1273 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1274 int i; 1275 1276 uint32_t map[] = { 1277 devfn << 8, 0, 0, /* devfn */ 1278 pin + 1, /* PCI pin */ 1279 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1280 1281 /* Convert map to big endian */ 1282 for (i = 0; i < 10; i++) { 1283 irq_map[i] = cpu_to_be32(map[i]); 1284 } 1285 irq_map += 10; 1286 } 1287 } 1288 1289 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", 1290 full_irq_map, sizeof(full_irq_map)); 1291 1292 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 1293 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ 1294 0, 0, 1295 0x7 /* PCI irq */); 1296 } 1297 1298 static void create_smmu(const VirtMachineState *vms, 1299 PCIBus *bus) 1300 { 1301 char *node; 1302 const char compat[] = "arm,smmu-v3"; 1303 int irq = vms->irqmap[VIRT_SMMU]; 1304 int i; 1305 hwaddr base = vms->memmap[VIRT_SMMU].base; 1306 hwaddr size = vms->memmap[VIRT_SMMU].size; 1307 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1308 DeviceState *dev; 1309 MachineState *ms = MACHINE(vms); 1310 1311 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1312 return; 1313 } 1314 1315 dev = qdev_new("arm-smmuv3"); 1316 1317 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1318 &error_abort); 1319 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1320 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1321 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1322 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1323 qdev_get_gpio_in(vms->gic, irq + i)); 1324 } 1325 1326 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1327 qemu_fdt_add_subnode(ms->fdt, node); 1328 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1329 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); 1330 1331 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", 1332 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1333 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1334 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1335 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1336 1337 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, 1338 sizeof(irq_names)); 1339 1340 qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle); 1341 qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk"); 1342 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); 1343 1344 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1345 1346 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1347 g_free(node); 1348 } 1349 1350 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1351 { 1352 const char compat[] = "virtio,pci-iommu"; 1353 uint16_t bdf = vms->virtio_iommu_bdf; 1354 MachineState *ms = MACHINE(vms); 1355 char *node; 1356 1357 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1358 1359 node = g_strdup_printf("%s/virtio_iommu@%d", vms->pciehb_nodename, bdf); 1360 qemu_fdt_add_subnode(ms->fdt, node); 1361 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1362 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 1363 1, bdf << 8, 1, 0, 1, 0, 1364 1, 0, 1, 0); 1365 1366 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1367 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1368 g_free(node); 1369 1370 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", 1371 0x0, vms->iommu_phandle, 0x0, bdf, 1372 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1373 } 1374 1375 static void create_pcie(VirtMachineState *vms) 1376 { 1377 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1378 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1379 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1380 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1381 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1382 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1383 hwaddr base_ecam, size_ecam; 1384 hwaddr base = base_mmio; 1385 int nr_pcie_buses; 1386 int irq = vms->irqmap[VIRT_PCIE]; 1387 MemoryRegion *mmio_alias; 1388 MemoryRegion *mmio_reg; 1389 MemoryRegion *ecam_alias; 1390 MemoryRegion *ecam_reg; 1391 DeviceState *dev; 1392 char *nodename; 1393 int i, ecam_id; 1394 PCIHostState *pci; 1395 MachineState *ms = MACHINE(vms); 1396 1397 dev = qdev_new(TYPE_GPEX_HOST); 1398 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1399 1400 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1401 base_ecam = vms->memmap[ecam_id].base; 1402 size_ecam = vms->memmap[ecam_id].size; 1403 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1404 /* Map only the first size_ecam bytes of ECAM space */ 1405 ecam_alias = g_new0(MemoryRegion, 1); 1406 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1407 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1408 ecam_reg, 0, size_ecam); 1409 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1410 1411 /* Map the MMIO window into system address space so as to expose 1412 * the section of PCI MMIO space which starts at the same base address 1413 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1414 * the window). 1415 */ 1416 mmio_alias = g_new0(MemoryRegion, 1); 1417 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1418 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1419 mmio_reg, base_mmio, size_mmio); 1420 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1421 1422 if (vms->highmem_mmio) { 1423 /* Map high MMIO space */ 1424 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1425 1426 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1427 mmio_reg, base_mmio_high, size_mmio_high); 1428 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1429 high_mmio_alias); 1430 } 1431 1432 /* Map IO port space */ 1433 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1434 1435 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1436 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1437 qdev_get_gpio_in(vms->gic, irq + i)); 1438 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1439 } 1440 1441 pci = PCI_HOST_BRIDGE(dev); 1442 pci->bypass_iommu = vms->default_bus_bypass_iommu; 1443 vms->bus = pci->bus; 1444 if (vms->bus) { 1445 for (i = 0; i < nb_nics; i++) { 1446 NICInfo *nd = &nd_table[i]; 1447 1448 if (!nd->model) { 1449 nd->model = g_strdup("virtio"); 1450 } 1451 1452 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1453 } 1454 } 1455 1456 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1457 qemu_fdt_add_subnode(ms->fdt, nodename); 1458 qemu_fdt_setprop_string(ms->fdt, nodename, 1459 "compatible", "pci-host-ecam-generic"); 1460 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 1461 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 1462 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 1463 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 1464 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 1465 nr_pcie_buses - 1); 1466 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1467 1468 if (vms->msi_phandle) { 1469 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent", 1470 vms->msi_phandle); 1471 } 1472 1473 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1474 2, base_ecam, 2, size_ecam); 1475 1476 if (vms->highmem_mmio) { 1477 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1478 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1479 2, base_pio, 2, size_pio, 1480 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1481 2, base_mmio, 2, size_mmio, 1482 1, FDT_PCI_RANGE_MMIO_64BIT, 1483 2, base_mmio_high, 1484 2, base_mmio_high, 2, size_mmio_high); 1485 } else { 1486 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1487 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1488 2, base_pio, 2, size_pio, 1489 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1490 2, base_mmio, 2, size_mmio); 1491 } 1492 1493 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 1494 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); 1495 1496 if (vms->iommu) { 1497 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1498 1499 switch (vms->iommu) { 1500 case VIRT_IOMMU_SMMUV3: 1501 create_smmu(vms, vms->bus); 1502 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 1503 0x0, vms->iommu_phandle, 0x0, 0x10000); 1504 break; 1505 default: 1506 g_assert_not_reached(); 1507 } 1508 } 1509 } 1510 1511 static void create_platform_bus(VirtMachineState *vms) 1512 { 1513 DeviceState *dev; 1514 SysBusDevice *s; 1515 int i; 1516 MemoryRegion *sysmem = get_system_memory(); 1517 1518 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1519 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1520 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1521 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1522 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1523 vms->platform_bus_dev = dev; 1524 1525 s = SYS_BUS_DEVICE(dev); 1526 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1527 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1528 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1529 } 1530 1531 memory_region_add_subregion(sysmem, 1532 vms->memmap[VIRT_PLATFORM_BUS].base, 1533 sysbus_mmio_get_region(s, 0)); 1534 } 1535 1536 static void create_tag_ram(MemoryRegion *tag_sysmem, 1537 hwaddr base, hwaddr size, 1538 const char *name) 1539 { 1540 MemoryRegion *tagram = g_new(MemoryRegion, 1); 1541 1542 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); 1543 memory_region_add_subregion(tag_sysmem, base / 32, tagram); 1544 } 1545 1546 static void create_secure_ram(VirtMachineState *vms, 1547 MemoryRegion *secure_sysmem, 1548 MemoryRegion *secure_tag_sysmem) 1549 { 1550 MemoryRegion *secram = g_new(MemoryRegion, 1); 1551 char *nodename; 1552 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1553 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1554 MachineState *ms = MACHINE(vms); 1555 1556 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1557 &error_fatal); 1558 memory_region_add_subregion(secure_sysmem, base, secram); 1559 1560 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1561 qemu_fdt_add_subnode(ms->fdt, nodename); 1562 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 1563 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 1564 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1565 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1566 1567 if (secure_tag_sysmem) { 1568 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); 1569 } 1570 1571 g_free(nodename); 1572 } 1573 1574 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1575 { 1576 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1577 bootinfo); 1578 MachineState *ms = MACHINE(board); 1579 1580 1581 *fdt_size = board->fdt_size; 1582 return ms->fdt; 1583 } 1584 1585 static void virt_build_smbios(VirtMachineState *vms) 1586 { 1587 MachineClass *mc = MACHINE_GET_CLASS(vms); 1588 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1589 uint8_t *smbios_tables, *smbios_anchor; 1590 size_t smbios_tables_len, smbios_anchor_len; 1591 const char *product = "QEMU Virtual Machine"; 1592 1593 if (kvm_enabled()) { 1594 product = "KVM Virtual Machine"; 1595 } 1596 1597 smbios_set_defaults("QEMU", product, 1598 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1599 true, SMBIOS_ENTRY_POINT_TYPE_64); 1600 1601 smbios_get_tables(MACHINE(vms), NULL, 0, 1602 &smbios_tables, &smbios_tables_len, 1603 &smbios_anchor, &smbios_anchor_len, 1604 &error_fatal); 1605 1606 if (smbios_anchor) { 1607 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1608 smbios_tables, smbios_tables_len); 1609 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1610 smbios_anchor, smbios_anchor_len); 1611 } 1612 } 1613 1614 static 1615 void virt_machine_done(Notifier *notifier, void *data) 1616 { 1617 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1618 machine_done); 1619 MachineState *ms = MACHINE(vms); 1620 ARMCPU *cpu = ARM_CPU(first_cpu); 1621 struct arm_boot_info *info = &vms->bootinfo; 1622 AddressSpace *as = arm_boot_address_space(cpu, info); 1623 1624 /* 1625 * If the user provided a dtb, we assume the dynamic sysbus nodes 1626 * already are integrated there. This corresponds to a use case where 1627 * the dynamic sysbus nodes are complex and their generation is not yet 1628 * supported. In that case the user can take charge of the guest dt 1629 * while qemu takes charge of the qom stuff. 1630 */ 1631 if (info->dtb_filename == NULL) { 1632 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", 1633 vms->memmap[VIRT_PLATFORM_BUS].base, 1634 vms->memmap[VIRT_PLATFORM_BUS].size, 1635 vms->irqmap[VIRT_PLATFORM_BUS]); 1636 } 1637 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1638 exit(1); 1639 } 1640 1641 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg); 1642 1643 virt_acpi_setup(vms); 1644 virt_build_smbios(vms); 1645 } 1646 1647 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1648 { 1649 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1650 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1651 1652 if (!vmc->disallow_affinity_adjustment) { 1653 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1654 * GIC's target-list limitations. 32-bit KVM hosts currently 1655 * always create clusters of 4 CPUs, but that is expected to 1656 * change when they gain support for gicv3. When KVM is enabled 1657 * it will override the changes we make here, therefore our 1658 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1659 * and to improve SGI efficiency. 1660 */ 1661 if (vms->gic_version == VIRT_GIC_VERSION_3) { 1662 clustersz = GICV3_TARGETLIST_BITS; 1663 } else { 1664 clustersz = GIC_TARGETLIST_BITS; 1665 } 1666 } 1667 return arm_cpu_mp_affinity(idx, clustersz); 1668 } 1669 1670 static void virt_set_memmap(VirtMachineState *vms, int pa_bits) 1671 { 1672 MachineState *ms = MACHINE(vms); 1673 hwaddr base, device_memory_base, device_memory_size, memtop; 1674 int i; 1675 1676 vms->memmap = extended_memmap; 1677 1678 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1679 vms->memmap[i] = base_memmap[i]; 1680 } 1681 1682 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1683 error_report("unsupported number of memory slots: %"PRIu64, 1684 ms->ram_slots); 1685 exit(EXIT_FAILURE); 1686 } 1687 1688 /* 1689 * !highmem is exactly the same as limiting the PA space to 32bit, 1690 * irrespective of the underlying capabilities of the HW. 1691 */ 1692 if (!vms->highmem) { 1693 pa_bits = 32; 1694 } 1695 1696 /* 1697 * We compute the base of the high IO region depending on the 1698 * amount of initial and device memory. The device memory start/size 1699 * is aligned on 1GiB. We never put the high IO region below 256GiB 1700 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1701 * The device region size assumes 1GiB page max alignment per slot. 1702 */ 1703 device_memory_base = 1704 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1705 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1706 1707 /* Base address of the high IO region */ 1708 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1709 if (memtop > BIT_ULL(pa_bits)) { 1710 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n", 1711 pa_bits, memtop - BIT_ULL(pa_bits)); 1712 exit(EXIT_FAILURE); 1713 } 1714 if (base < device_memory_base) { 1715 error_report("maxmem/slots too huge"); 1716 exit(EXIT_FAILURE); 1717 } 1718 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1719 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1720 } 1721 1722 /* We know for sure that at least the memory fits in the PA space */ 1723 vms->highest_gpa = memtop - 1; 1724 1725 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1726 hwaddr size = extended_memmap[i].size; 1727 bool fits; 1728 1729 base = ROUND_UP(base, size); 1730 vms->memmap[i].base = base; 1731 vms->memmap[i].size = size; 1732 1733 /* 1734 * Check each device to see if they fit in the PA space, 1735 * moving highest_gpa as we go. 1736 * 1737 * For each device that doesn't fit, disable it. 1738 */ 1739 fits = (base + size) <= BIT_ULL(pa_bits); 1740 if (fits) { 1741 vms->highest_gpa = base + size - 1; 1742 } 1743 1744 switch (i) { 1745 case VIRT_HIGH_GIC_REDIST2: 1746 vms->highmem_redists &= fits; 1747 break; 1748 case VIRT_HIGH_PCIE_ECAM: 1749 vms->highmem_ecam &= fits; 1750 break; 1751 case VIRT_HIGH_PCIE_MMIO: 1752 vms->highmem_mmio &= fits; 1753 break; 1754 } 1755 1756 base += size; 1757 } 1758 1759 if (device_memory_size > 0) { 1760 ms->device_memory = g_malloc0(sizeof(*ms->device_memory)); 1761 ms->device_memory->base = device_memory_base; 1762 memory_region_init(&ms->device_memory->mr, OBJECT(vms), 1763 "device-memory", device_memory_size); 1764 } 1765 } 1766 1767 /* 1768 * finalize_gic_version - Determines the final gic_version 1769 * according to the gic-version property 1770 * 1771 * Default GIC type is v2 1772 */ 1773 static void finalize_gic_version(VirtMachineState *vms) 1774 { 1775 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 1776 1777 if (kvm_enabled()) { 1778 int probe_bitmap; 1779 1780 if (!kvm_irqchip_in_kernel()) { 1781 switch (vms->gic_version) { 1782 case VIRT_GIC_VERSION_HOST: 1783 warn_report( 1784 "gic-version=host not relevant with kernel-irqchip=off " 1785 "as only userspace GICv2 is supported. Using v2 ..."); 1786 return; 1787 case VIRT_GIC_VERSION_MAX: 1788 case VIRT_GIC_VERSION_NOSEL: 1789 vms->gic_version = VIRT_GIC_VERSION_2; 1790 return; 1791 case VIRT_GIC_VERSION_2: 1792 return; 1793 case VIRT_GIC_VERSION_3: 1794 error_report( 1795 "gic-version=3 is not supported with kernel-irqchip=off"); 1796 exit(1); 1797 } 1798 } 1799 1800 probe_bitmap = kvm_arm_vgic_probe(); 1801 if (!probe_bitmap) { 1802 error_report("Unable to determine GIC version supported by host"); 1803 exit(1); 1804 } 1805 1806 switch (vms->gic_version) { 1807 case VIRT_GIC_VERSION_HOST: 1808 case VIRT_GIC_VERSION_MAX: 1809 if (probe_bitmap & KVM_ARM_VGIC_V3) { 1810 vms->gic_version = VIRT_GIC_VERSION_3; 1811 } else { 1812 vms->gic_version = VIRT_GIC_VERSION_2; 1813 } 1814 return; 1815 case VIRT_GIC_VERSION_NOSEL: 1816 if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) { 1817 vms->gic_version = VIRT_GIC_VERSION_2; 1818 } else if (probe_bitmap & KVM_ARM_VGIC_V3) { 1819 /* 1820 * in case the host does not support v2 in-kernel emulation or 1821 * the end-user requested more than 8 VCPUs we now default 1822 * to v3. In any case defaulting to v2 would be broken. 1823 */ 1824 vms->gic_version = VIRT_GIC_VERSION_3; 1825 } else if (max_cpus > GIC_NCPU) { 1826 error_report("host only supports in-kernel GICv2 emulation " 1827 "but more than 8 vcpus are requested"); 1828 exit(1); 1829 } 1830 break; 1831 case VIRT_GIC_VERSION_2: 1832 case VIRT_GIC_VERSION_3: 1833 break; 1834 } 1835 1836 /* Check chosen version is effectively supported by the host */ 1837 if (vms->gic_version == VIRT_GIC_VERSION_2 && 1838 !(probe_bitmap & KVM_ARM_VGIC_V2)) { 1839 error_report("host does not support in-kernel GICv2 emulation"); 1840 exit(1); 1841 } else if (vms->gic_version == VIRT_GIC_VERSION_3 && 1842 !(probe_bitmap & KVM_ARM_VGIC_V3)) { 1843 error_report("host does not support in-kernel GICv3 emulation"); 1844 exit(1); 1845 } 1846 return; 1847 } 1848 1849 /* TCG mode */ 1850 switch (vms->gic_version) { 1851 case VIRT_GIC_VERSION_NOSEL: 1852 vms->gic_version = VIRT_GIC_VERSION_2; 1853 break; 1854 case VIRT_GIC_VERSION_MAX: 1855 if (module_object_class_by_name("arm-gicv3")) { 1856 /* CONFIG_ARM_GICV3_TCG was set */ 1857 vms->gic_version = VIRT_GIC_VERSION_3; 1858 } else { 1859 vms->gic_version = VIRT_GIC_VERSION_2; 1860 } 1861 break; 1862 case VIRT_GIC_VERSION_HOST: 1863 error_report("gic-version=host requires KVM"); 1864 exit(1); 1865 case VIRT_GIC_VERSION_2: 1866 case VIRT_GIC_VERSION_3: 1867 break; 1868 } 1869 } 1870 1871 /* 1872 * virt_cpu_post_init() must be called after the CPUs have 1873 * been realized and the GIC has been created. 1874 */ 1875 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) 1876 { 1877 int max_cpus = MACHINE(vms)->smp.max_cpus; 1878 bool aarch64, pmu, steal_time; 1879 CPUState *cpu; 1880 1881 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); 1882 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); 1883 steal_time = object_property_get_bool(OBJECT(first_cpu), 1884 "kvm-steal-time", NULL); 1885 1886 if (kvm_enabled()) { 1887 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; 1888 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; 1889 1890 if (steal_time) { 1891 MemoryRegion *pvtime = g_new(MemoryRegion, 1); 1892 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; 1893 1894 /* The memory region size must be a multiple of host page size. */ 1895 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); 1896 1897 if (pvtime_size > pvtime_reg_size) { 1898 error_report("pvtime requires a %" HWADDR_PRId 1899 " byte memory region for %d CPUs," 1900 " but only %" HWADDR_PRId " has been reserved", 1901 pvtime_size, max_cpus, pvtime_reg_size); 1902 exit(1); 1903 } 1904 1905 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); 1906 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); 1907 } 1908 1909 CPU_FOREACH(cpu) { 1910 if (pmu) { 1911 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); 1912 if (kvm_irqchip_in_kernel()) { 1913 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 1914 } 1915 kvm_arm_pmu_init(cpu); 1916 } 1917 if (steal_time) { 1918 kvm_arm_pvtime_init(cpu, pvtime_reg_base + 1919 cpu->cpu_index * PVTIME_SIZE_PER_CPU); 1920 } 1921 } 1922 } else { 1923 if (aarch64 && vms->highmem) { 1924 int requested_pa_size = 64 - clz64(vms->highest_gpa); 1925 int pamax = arm_pamax(ARM_CPU(first_cpu)); 1926 1927 if (pamax < requested_pa_size) { 1928 error_report("VCPU supports less PA bits (%d) than " 1929 "requested by the memory map (%d)", 1930 pamax, requested_pa_size); 1931 exit(1); 1932 } 1933 } 1934 } 1935 } 1936 1937 static void machvirt_init(MachineState *machine) 1938 { 1939 VirtMachineState *vms = VIRT_MACHINE(machine); 1940 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1941 MachineClass *mc = MACHINE_GET_CLASS(machine); 1942 const CPUArchIdList *possible_cpus; 1943 MemoryRegion *sysmem = get_system_memory(); 1944 MemoryRegion *secure_sysmem = NULL; 1945 MemoryRegion *tag_sysmem = NULL; 1946 MemoryRegion *secure_tag_sysmem = NULL; 1947 int n, virt_max_cpus; 1948 bool firmware_loaded; 1949 bool aarch64 = true; 1950 bool has_ged = !vmc->no_ged; 1951 unsigned int smp_cpus = machine->smp.cpus; 1952 unsigned int max_cpus = machine->smp.max_cpus; 1953 1954 if (!cpu_type_valid(machine->cpu_type)) { 1955 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 1956 exit(1); 1957 } 1958 1959 possible_cpus = mc->possible_cpu_arch_ids(machine); 1960 1961 /* 1962 * In accelerated mode, the memory map is computed earlier in kvm_type() 1963 * to create a VM with the right number of IPA bits. 1964 */ 1965 if (!vms->memmap) { 1966 Object *cpuobj; 1967 ARMCPU *armcpu; 1968 int pa_bits; 1969 1970 /* 1971 * Instanciate a temporary CPU object to find out about what 1972 * we are about to deal with. Once this is done, get rid of 1973 * the object. 1974 */ 1975 cpuobj = object_new(possible_cpus->cpus[0].type); 1976 armcpu = ARM_CPU(cpuobj); 1977 1978 if (object_property_get_bool(cpuobj, "aarch64", NULL)) { 1979 pa_bits = arm_pamax(armcpu); 1980 } else if (arm_feature(&armcpu->env, ARM_FEATURE_LPAE)) { 1981 /* v7 with LPAE */ 1982 pa_bits = 40; 1983 } else { 1984 /* Anything else */ 1985 pa_bits = 32; 1986 } 1987 1988 object_unref(cpuobj); 1989 1990 virt_set_memmap(vms, pa_bits); 1991 } 1992 1993 /* We can probe only here because during property set 1994 * KVM is not available yet 1995 */ 1996 finalize_gic_version(vms); 1997 1998 if (vms->secure) { 1999 /* 2000 * The Secure view of the world is the same as the NonSecure, 2001 * but with a few extra devices. Create it as a container region 2002 * containing the system memory at low priority; any secure-only 2003 * devices go in at higher priority and take precedence. 2004 */ 2005 secure_sysmem = g_new(MemoryRegion, 1); 2006 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 2007 UINT64_MAX); 2008 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 2009 } 2010 2011 firmware_loaded = virt_firmware_init(vms, sysmem, 2012 secure_sysmem ?: sysmem); 2013 2014 /* If we have an EL3 boot ROM then the assumption is that it will 2015 * implement PSCI itself, so disable QEMU's internal implementation 2016 * so it doesn't get in the way. Instead of starting secondary 2017 * CPUs in PSCI powerdown state we will start them all running and 2018 * let the boot ROM sort them out. 2019 * The usual case is that we do use QEMU's PSCI implementation; 2020 * if the guest has EL2 then we will use SMC as the conduit, 2021 * and otherwise we will use HVC (for backwards compatibility and 2022 * because if we're using KVM then we must use HVC). 2023 */ 2024 if (vms->secure && firmware_loaded) { 2025 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 2026 } else if (vms->virt) { 2027 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 2028 } else { 2029 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 2030 } 2031 2032 /* The maximum number of CPUs depends on the GIC version, or on how 2033 * many redistributors we can fit into the memory map. 2034 */ 2035 if (vms->gic_version == VIRT_GIC_VERSION_3) { 2036 virt_max_cpus = 2037 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 2038 virt_max_cpus += 2039 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; 2040 } else { 2041 virt_max_cpus = GIC_NCPU; 2042 } 2043 2044 if (max_cpus > virt_max_cpus) { 2045 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 2046 "supported by machine 'mach-virt' (%d)", 2047 max_cpus, virt_max_cpus); 2048 exit(1); 2049 } 2050 2051 if (vms->virt && (kvm_enabled() || hvf_enabled())) { 2052 error_report("mach-virt: %s does not support providing " 2053 "Virtualization extensions to the guest CPU", 2054 kvm_enabled() ? "KVM" : "HVF"); 2055 exit(1); 2056 } 2057 2058 if (vms->mte && (kvm_enabled() || hvf_enabled())) { 2059 error_report("mach-virt: %s does not support providing " 2060 "MTE to the guest CPU", 2061 kvm_enabled() ? "KVM" : "HVF"); 2062 exit(1); 2063 } 2064 2065 create_fdt(vms); 2066 2067 assert(possible_cpus->len == max_cpus); 2068 for (n = 0; n < possible_cpus->len; n++) { 2069 Object *cpuobj; 2070 CPUState *cs; 2071 2072 if (n >= smp_cpus) { 2073 break; 2074 } 2075 2076 cpuobj = object_new(possible_cpus->cpus[n].type); 2077 object_property_set_int(cpuobj, "mp-affinity", 2078 possible_cpus->cpus[n].arch_id, NULL); 2079 2080 cs = CPU(cpuobj); 2081 cs->cpu_index = n; 2082 2083 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 2084 &error_fatal); 2085 2086 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 2087 2088 if (!vms->secure) { 2089 object_property_set_bool(cpuobj, "has_el3", false, NULL); 2090 } 2091 2092 if (!vms->virt && object_property_find(cpuobj, "has_el2")) { 2093 object_property_set_bool(cpuobj, "has_el2", false, NULL); 2094 } 2095 2096 if (vmc->kvm_no_adjvtime && 2097 object_property_find(cpuobj, "kvm-no-adjvtime")) { 2098 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 2099 } 2100 2101 if (vmc->no_kvm_steal_time && 2102 object_property_find(cpuobj, "kvm-steal-time")) { 2103 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); 2104 } 2105 2106 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { 2107 object_property_set_bool(cpuobj, "pmu", false, NULL); 2108 } 2109 2110 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { 2111 object_property_set_bool(cpuobj, "lpa2", false, NULL); 2112 } 2113 2114 if (object_property_find(cpuobj, "reset-cbar")) { 2115 object_property_set_int(cpuobj, "reset-cbar", 2116 vms->memmap[VIRT_CPUPERIPHS].base, 2117 &error_abort); 2118 } 2119 2120 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 2121 &error_abort); 2122 if (vms->secure) { 2123 object_property_set_link(cpuobj, "secure-memory", 2124 OBJECT(secure_sysmem), &error_abort); 2125 } 2126 2127 if (vms->mte) { 2128 /* Create the memory region only once, but link to all cpus. */ 2129 if (!tag_sysmem) { 2130 /* 2131 * The property exists only if MemTag is supported. 2132 * If it is, we must allocate the ram to back that up. 2133 */ 2134 if (!object_property_find(cpuobj, "tag-memory")) { 2135 error_report("MTE requested, but not supported " 2136 "by the guest CPU"); 2137 exit(1); 2138 } 2139 2140 tag_sysmem = g_new(MemoryRegion, 1); 2141 memory_region_init(tag_sysmem, OBJECT(machine), 2142 "tag-memory", UINT64_MAX / 32); 2143 2144 if (vms->secure) { 2145 secure_tag_sysmem = g_new(MemoryRegion, 1); 2146 memory_region_init(secure_tag_sysmem, OBJECT(machine), 2147 "secure-tag-memory", UINT64_MAX / 32); 2148 2149 /* As with ram, secure-tag takes precedence over tag. */ 2150 memory_region_add_subregion_overlap(secure_tag_sysmem, 0, 2151 tag_sysmem, -1); 2152 } 2153 } 2154 2155 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem), 2156 &error_abort); 2157 if (vms->secure) { 2158 object_property_set_link(cpuobj, "secure-tag-memory", 2159 OBJECT(secure_tag_sysmem), 2160 &error_abort); 2161 } 2162 } 2163 2164 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 2165 object_unref(cpuobj); 2166 } 2167 fdt_add_timer_nodes(vms); 2168 fdt_add_cpu_nodes(vms); 2169 2170 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 2171 machine->ram); 2172 if (machine->device_memory) { 2173 memory_region_add_subregion(sysmem, machine->device_memory->base, 2174 &machine->device_memory->mr); 2175 } 2176 2177 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 2178 2179 create_gic(vms, sysmem); 2180 2181 virt_cpu_post_init(vms, sysmem); 2182 2183 fdt_add_pmu_nodes(vms); 2184 2185 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 2186 2187 if (vms->secure) { 2188 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); 2189 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 2190 } 2191 2192 if (tag_sysmem) { 2193 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, 2194 machine->ram_size, "mach-virt.tag"); 2195 } 2196 2197 vms->highmem_ecam &= (!firmware_loaded || aarch64); 2198 2199 create_rtc(vms); 2200 2201 create_pcie(vms); 2202 2203 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 2204 vms->acpi_dev = create_acpi_ged(vms); 2205 } else { 2206 create_gpio_devices(vms, VIRT_GPIO, sysmem); 2207 } 2208 2209 if (vms->secure && !vmc->no_secure_gpio) { 2210 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); 2211 } 2212 2213 /* connect powerdown request */ 2214 vms->powerdown_notifier.notify = virt_powerdown_req; 2215 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 2216 2217 /* Create mmio transports, so the user can create virtio backends 2218 * (which will be automatically plugged in to the transports). If 2219 * no backend is created the transport will just sit harmlessly idle. 2220 */ 2221 create_virtio_devices(vms); 2222 2223 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 2224 rom_set_fw(vms->fw_cfg); 2225 2226 create_platform_bus(vms); 2227 2228 if (machine->nvdimms_state->is_enabled) { 2229 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 2230 .space_id = AML_AS_SYSTEM_MEMORY, 2231 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 2232 .bit_width = NVDIMM_ACPI_IO_LEN << 3 2233 }; 2234 2235 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 2236 arm_virt_nvdimm_acpi_dsmio, 2237 vms->fw_cfg, OBJECT(vms)); 2238 } 2239 2240 vms->bootinfo.ram_size = machine->ram_size; 2241 vms->bootinfo.board_id = -1; 2242 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 2243 vms->bootinfo.get_dtb = machvirt_dtb; 2244 vms->bootinfo.skip_dtb_autoload = true; 2245 vms->bootinfo.firmware_loaded = firmware_loaded; 2246 vms->bootinfo.psci_conduit = vms->psci_conduit; 2247 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 2248 2249 vms->machine_done.notify = virt_machine_done; 2250 qemu_add_machine_init_done_notifier(&vms->machine_done); 2251 } 2252 2253 static bool virt_get_secure(Object *obj, Error **errp) 2254 { 2255 VirtMachineState *vms = VIRT_MACHINE(obj); 2256 2257 return vms->secure; 2258 } 2259 2260 static void virt_set_secure(Object *obj, bool value, Error **errp) 2261 { 2262 VirtMachineState *vms = VIRT_MACHINE(obj); 2263 2264 vms->secure = value; 2265 } 2266 2267 static bool virt_get_virt(Object *obj, Error **errp) 2268 { 2269 VirtMachineState *vms = VIRT_MACHINE(obj); 2270 2271 return vms->virt; 2272 } 2273 2274 static void virt_set_virt(Object *obj, bool value, Error **errp) 2275 { 2276 VirtMachineState *vms = VIRT_MACHINE(obj); 2277 2278 vms->virt = value; 2279 } 2280 2281 static bool virt_get_highmem(Object *obj, Error **errp) 2282 { 2283 VirtMachineState *vms = VIRT_MACHINE(obj); 2284 2285 return vms->highmem; 2286 } 2287 2288 static void virt_set_highmem(Object *obj, bool value, Error **errp) 2289 { 2290 VirtMachineState *vms = VIRT_MACHINE(obj); 2291 2292 vms->highmem = value; 2293 } 2294 2295 static bool virt_get_its(Object *obj, Error **errp) 2296 { 2297 VirtMachineState *vms = VIRT_MACHINE(obj); 2298 2299 return vms->its; 2300 } 2301 2302 static void virt_set_its(Object *obj, bool value, Error **errp) 2303 { 2304 VirtMachineState *vms = VIRT_MACHINE(obj); 2305 2306 vms->its = value; 2307 } 2308 2309 static bool virt_get_dtb_kaslr_seed(Object *obj, Error **errp) 2310 { 2311 VirtMachineState *vms = VIRT_MACHINE(obj); 2312 2313 return vms->dtb_kaslr_seed; 2314 } 2315 2316 static void virt_set_dtb_kaslr_seed(Object *obj, bool value, Error **errp) 2317 { 2318 VirtMachineState *vms = VIRT_MACHINE(obj); 2319 2320 vms->dtb_kaslr_seed = value; 2321 } 2322 2323 static char *virt_get_oem_id(Object *obj, Error **errp) 2324 { 2325 VirtMachineState *vms = VIRT_MACHINE(obj); 2326 2327 return g_strdup(vms->oem_id); 2328 } 2329 2330 static void virt_set_oem_id(Object *obj, const char *value, Error **errp) 2331 { 2332 VirtMachineState *vms = VIRT_MACHINE(obj); 2333 size_t len = strlen(value); 2334 2335 if (len > 6) { 2336 error_setg(errp, 2337 "User specified oem-id value is bigger than 6 bytes in size"); 2338 return; 2339 } 2340 2341 strncpy(vms->oem_id, value, 6); 2342 } 2343 2344 static char *virt_get_oem_table_id(Object *obj, Error **errp) 2345 { 2346 VirtMachineState *vms = VIRT_MACHINE(obj); 2347 2348 return g_strdup(vms->oem_table_id); 2349 } 2350 2351 static void virt_set_oem_table_id(Object *obj, const char *value, 2352 Error **errp) 2353 { 2354 VirtMachineState *vms = VIRT_MACHINE(obj); 2355 size_t len = strlen(value); 2356 2357 if (len > 8) { 2358 error_setg(errp, 2359 "User specified oem-table-id value is bigger than 8 bytes in size"); 2360 return; 2361 } 2362 strncpy(vms->oem_table_id, value, 8); 2363 } 2364 2365 2366 bool virt_is_acpi_enabled(VirtMachineState *vms) 2367 { 2368 if (vms->acpi == ON_OFF_AUTO_OFF) { 2369 return false; 2370 } 2371 return true; 2372 } 2373 2374 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 2375 void *opaque, Error **errp) 2376 { 2377 VirtMachineState *vms = VIRT_MACHINE(obj); 2378 OnOffAuto acpi = vms->acpi; 2379 2380 visit_type_OnOffAuto(v, name, &acpi, errp); 2381 } 2382 2383 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 2384 void *opaque, Error **errp) 2385 { 2386 VirtMachineState *vms = VIRT_MACHINE(obj); 2387 2388 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 2389 } 2390 2391 static bool virt_get_ras(Object *obj, Error **errp) 2392 { 2393 VirtMachineState *vms = VIRT_MACHINE(obj); 2394 2395 return vms->ras; 2396 } 2397 2398 static void virt_set_ras(Object *obj, bool value, Error **errp) 2399 { 2400 VirtMachineState *vms = VIRT_MACHINE(obj); 2401 2402 vms->ras = value; 2403 } 2404 2405 static bool virt_get_mte(Object *obj, Error **errp) 2406 { 2407 VirtMachineState *vms = VIRT_MACHINE(obj); 2408 2409 return vms->mte; 2410 } 2411 2412 static void virt_set_mte(Object *obj, bool value, Error **errp) 2413 { 2414 VirtMachineState *vms = VIRT_MACHINE(obj); 2415 2416 vms->mte = value; 2417 } 2418 2419 static char *virt_get_gic_version(Object *obj, Error **errp) 2420 { 2421 VirtMachineState *vms = VIRT_MACHINE(obj); 2422 const char *val = vms->gic_version == VIRT_GIC_VERSION_3 ? "3" : "2"; 2423 2424 return g_strdup(val); 2425 } 2426 2427 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2428 { 2429 VirtMachineState *vms = VIRT_MACHINE(obj); 2430 2431 if (!strcmp(value, "3")) { 2432 vms->gic_version = VIRT_GIC_VERSION_3; 2433 } else if (!strcmp(value, "2")) { 2434 vms->gic_version = VIRT_GIC_VERSION_2; 2435 } else if (!strcmp(value, "host")) { 2436 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2437 } else if (!strcmp(value, "max")) { 2438 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2439 } else { 2440 error_setg(errp, "Invalid gic-version value"); 2441 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2442 } 2443 } 2444 2445 static char *virt_get_iommu(Object *obj, Error **errp) 2446 { 2447 VirtMachineState *vms = VIRT_MACHINE(obj); 2448 2449 switch (vms->iommu) { 2450 case VIRT_IOMMU_NONE: 2451 return g_strdup("none"); 2452 case VIRT_IOMMU_SMMUV3: 2453 return g_strdup("smmuv3"); 2454 default: 2455 g_assert_not_reached(); 2456 } 2457 } 2458 2459 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2460 { 2461 VirtMachineState *vms = VIRT_MACHINE(obj); 2462 2463 if (!strcmp(value, "smmuv3")) { 2464 vms->iommu = VIRT_IOMMU_SMMUV3; 2465 } else if (!strcmp(value, "none")) { 2466 vms->iommu = VIRT_IOMMU_NONE; 2467 } else { 2468 error_setg(errp, "Invalid iommu value"); 2469 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2470 } 2471 } 2472 2473 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp) 2474 { 2475 VirtMachineState *vms = VIRT_MACHINE(obj); 2476 2477 return vms->default_bus_bypass_iommu; 2478 } 2479 2480 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value, 2481 Error **errp) 2482 { 2483 VirtMachineState *vms = VIRT_MACHINE(obj); 2484 2485 vms->default_bus_bypass_iommu = value; 2486 } 2487 2488 static CpuInstanceProperties 2489 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2490 { 2491 MachineClass *mc = MACHINE_GET_CLASS(ms); 2492 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2493 2494 assert(cpu_index < possible_cpus->len); 2495 return possible_cpus->cpus[cpu_index].props; 2496 } 2497 2498 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2499 { 2500 return idx % ms->numa_state->num_nodes; 2501 } 2502 2503 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2504 { 2505 int n; 2506 unsigned int max_cpus = ms->smp.max_cpus; 2507 VirtMachineState *vms = VIRT_MACHINE(ms); 2508 2509 if (ms->possible_cpus) { 2510 assert(ms->possible_cpus->len == max_cpus); 2511 return ms->possible_cpus; 2512 } 2513 2514 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2515 sizeof(CPUArchId) * max_cpus); 2516 ms->possible_cpus->len = max_cpus; 2517 for (n = 0; n < ms->possible_cpus->len; n++) { 2518 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2519 ms->possible_cpus->cpus[n].arch_id = 2520 virt_cpu_mp_affinity(vms, n); 2521 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2522 ms->possible_cpus->cpus[n].props.thread_id = n; 2523 } 2524 return ms->possible_cpus; 2525 } 2526 2527 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2528 Error **errp) 2529 { 2530 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2531 const MachineState *ms = MACHINE(hotplug_dev); 2532 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2533 2534 if (!vms->acpi_dev) { 2535 error_setg(errp, 2536 "memory hotplug is not enabled: missing acpi-ged device"); 2537 return; 2538 } 2539 2540 if (vms->mte) { 2541 error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); 2542 return; 2543 } 2544 2545 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2546 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2547 return; 2548 } 2549 2550 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 2551 } 2552 2553 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2554 DeviceState *dev, Error **errp) 2555 { 2556 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2557 MachineState *ms = MACHINE(hotplug_dev); 2558 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2559 2560 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); 2561 2562 if (is_nvdimm) { 2563 nvdimm_plug(ms->nvdimms_state); 2564 } 2565 2566 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2567 dev, &error_abort); 2568 } 2569 2570 static void virt_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 2571 DeviceState *dev, Error **errp) 2572 { 2573 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2574 Error *local_err = NULL; 2575 2576 if (!hotplug_dev2 && dev->hotplugged) { 2577 /* 2578 * Without a bus hotplug handler, we cannot control the plug/unplug 2579 * order. We should never reach this point when hotplugging on ARM. 2580 * However, it's nice to add a safety net, similar to what we have 2581 * on x86. 2582 */ 2583 error_setg(errp, "hotplug of virtio based memory devices not supported" 2584 " on this bus."); 2585 return; 2586 } 2587 /* 2588 * First, see if we can plug this memory device at all. If that 2589 * succeeds, branch of to the actual hotplug handler. 2590 */ 2591 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 2592 &local_err); 2593 if (!local_err && hotplug_dev2) { 2594 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 2595 } 2596 error_propagate(errp, local_err); 2597 } 2598 2599 static void virt_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 2600 DeviceState *dev, Error **errp) 2601 { 2602 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2603 Error *local_err = NULL; 2604 2605 /* 2606 * Plug the memory device first and then branch off to the actual 2607 * hotplug handler. If that one fails, we can easily undo the memory 2608 * device bits. 2609 */ 2610 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2611 if (hotplug_dev2) { 2612 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 2613 if (local_err) { 2614 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2615 } 2616 } 2617 error_propagate(errp, local_err); 2618 } 2619 2620 static void virt_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 2621 DeviceState *dev, Error **errp) 2622 { 2623 /* We don't support hot unplug of virtio based memory devices */ 2624 error_setg(errp, "virtio based memory devices cannot be unplugged."); 2625 } 2626 2627 2628 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2629 DeviceState *dev, Error **errp) 2630 { 2631 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2632 2633 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2634 virt_memory_pre_plug(hotplug_dev, dev, errp); 2635 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2636 virt_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 2637 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2638 hwaddr db_start = 0, db_end = 0; 2639 char *resv_prop_str; 2640 2641 if (vms->iommu != VIRT_IOMMU_NONE) { 2642 error_setg(errp, "virt machine does not support multiple IOMMUs"); 2643 return; 2644 } 2645 2646 switch (vms->msi_controller) { 2647 case VIRT_MSI_CTRL_NONE: 2648 return; 2649 case VIRT_MSI_CTRL_ITS: 2650 /* GITS_TRANSLATER page */ 2651 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; 2652 db_end = base_memmap[VIRT_GIC_ITS].base + 2653 base_memmap[VIRT_GIC_ITS].size - 1; 2654 break; 2655 case VIRT_MSI_CTRL_GICV2M: 2656 /* MSI_SETSPI_NS page */ 2657 db_start = base_memmap[VIRT_GIC_V2M].base; 2658 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; 2659 break; 2660 } 2661 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", 2662 db_start, db_end, 2663 VIRTIO_IOMMU_RESV_MEM_T_MSI); 2664 2665 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 2666 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 2667 resv_prop_str, errp); 2668 g_free(resv_prop_str); 2669 } 2670 } 2671 2672 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2673 DeviceState *dev, Error **errp) 2674 { 2675 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2676 2677 if (vms->platform_bus_dev) { 2678 MachineClass *mc = MACHINE_GET_CLASS(vms); 2679 2680 if (device_is_dynamic_sysbus(mc, dev)) { 2681 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2682 SYS_BUS_DEVICE(dev)); 2683 } 2684 } 2685 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2686 virt_memory_plug(hotplug_dev, dev, errp); 2687 } 2688 2689 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2690 virt_virtio_md_pci_plug(hotplug_dev, dev, errp); 2691 } 2692 2693 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2694 PCIDevice *pdev = PCI_DEVICE(dev); 2695 2696 vms->iommu = VIRT_IOMMU_VIRTIO; 2697 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2698 create_virtio_iommu_dt_bindings(vms); 2699 } 2700 } 2701 2702 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, 2703 DeviceState *dev, Error **errp) 2704 { 2705 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2706 Error *local_err = NULL; 2707 2708 if (!vms->acpi_dev) { 2709 error_setg(&local_err, 2710 "memory hotplug is not enabled: missing acpi-ged device"); 2711 goto out; 2712 } 2713 2714 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2715 error_setg(&local_err, 2716 "nvdimm device hot unplug is not supported yet."); 2717 goto out; 2718 } 2719 2720 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, 2721 &local_err); 2722 out: 2723 error_propagate(errp, local_err); 2724 } 2725 2726 static void virt_dimm_unplug(HotplugHandler *hotplug_dev, 2727 DeviceState *dev, Error **errp) 2728 { 2729 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2730 Error *local_err = NULL; 2731 2732 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); 2733 if (local_err) { 2734 goto out; 2735 } 2736 2737 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); 2738 qdev_unrealize(dev); 2739 2740 out: 2741 error_propagate(errp, local_err); 2742 } 2743 2744 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2745 DeviceState *dev, Error **errp) 2746 { 2747 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2748 virt_dimm_unplug_request(hotplug_dev, dev, errp); 2749 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2750 virt_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 2751 } else { 2752 error_setg(errp, "device unplug request for unsupported device" 2753 " type: %s", object_get_typename(OBJECT(dev))); 2754 } 2755 } 2756 2757 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2758 DeviceState *dev, Error **errp) 2759 { 2760 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2761 virt_dimm_unplug(hotplug_dev, dev, errp); 2762 } else { 2763 error_setg(errp, "virt: device unplug for unsupported device" 2764 " type: %s", object_get_typename(OBJECT(dev))); 2765 } 2766 } 2767 2768 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2769 DeviceState *dev) 2770 { 2771 MachineClass *mc = MACHINE_GET_CLASS(machine); 2772 2773 if (device_is_dynamic_sysbus(mc, dev) || 2774 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2775 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 2776 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2777 return HOTPLUG_HANDLER(machine); 2778 } 2779 return NULL; 2780 } 2781 2782 /* 2783 * for arm64 kvm_type [7-0] encodes the requested number of bits 2784 * in the IPA address space 2785 */ 2786 static int virt_kvm_type(MachineState *ms, const char *type_str) 2787 { 2788 VirtMachineState *vms = VIRT_MACHINE(ms); 2789 int max_vm_pa_size, requested_pa_size; 2790 bool fixed_ipa; 2791 2792 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 2793 2794 /* we freeze the memory map to compute the highest gpa */ 2795 virt_set_memmap(vms, max_vm_pa_size); 2796 2797 requested_pa_size = 64 - clz64(vms->highest_gpa); 2798 2799 /* 2800 * KVM requires the IPA size to be at least 32 bits. 2801 */ 2802 if (requested_pa_size < 32) { 2803 requested_pa_size = 32; 2804 } 2805 2806 if (requested_pa_size > max_vm_pa_size) { 2807 error_report("-m and ,maxmem option values " 2808 "require an IPA range (%d bits) larger than " 2809 "the one supported by the host (%d bits)", 2810 requested_pa_size, max_vm_pa_size); 2811 exit(1); 2812 } 2813 /* 2814 * We return the requested PA log size, unless KVM only supports 2815 * the implicit legacy 40b IPA setting, in which case the kvm_type 2816 * must be 0. 2817 */ 2818 return fixed_ipa ? 0 : requested_pa_size; 2819 } 2820 2821 static void virt_machine_class_init(ObjectClass *oc, void *data) 2822 { 2823 MachineClass *mc = MACHINE_CLASS(oc); 2824 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2825 2826 mc->init = machvirt_init; 2827 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 2828 * The value may be reduced later when we have more information about the 2829 * configuration of the particular instance. 2830 */ 2831 mc->max_cpus = 512; 2832 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 2833 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 2834 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 2835 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 2836 #ifdef CONFIG_TPM 2837 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 2838 #endif 2839 mc->block_default_type = IF_VIRTIO; 2840 mc->no_cdrom = 1; 2841 mc->pci_allow_0_address = true; 2842 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 2843 mc->minimum_page_bits = 12; 2844 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 2845 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 2846 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 2847 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 2848 mc->kvm_type = virt_kvm_type; 2849 assert(!mc->get_hotplug_handler); 2850 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 2851 hc->pre_plug = virt_machine_device_pre_plug_cb; 2852 hc->plug = virt_machine_device_plug_cb; 2853 hc->unplug_request = virt_machine_device_unplug_request_cb; 2854 hc->unplug = virt_machine_device_unplug_cb; 2855 mc->nvdimm_supported = true; 2856 mc->smp_props.clusters_supported = true; 2857 mc->auto_enable_numa_with_memhp = true; 2858 mc->auto_enable_numa_with_memdev = true; 2859 mc->default_ram_id = "mach-virt.ram"; 2860 2861 object_class_property_add(oc, "acpi", "OnOffAuto", 2862 virt_get_acpi, virt_set_acpi, 2863 NULL, NULL); 2864 object_class_property_set_description(oc, "acpi", 2865 "Enable ACPI"); 2866 object_class_property_add_bool(oc, "secure", virt_get_secure, 2867 virt_set_secure); 2868 object_class_property_set_description(oc, "secure", 2869 "Set on/off to enable/disable the ARM " 2870 "Security Extensions (TrustZone)"); 2871 2872 object_class_property_add_bool(oc, "virtualization", virt_get_virt, 2873 virt_set_virt); 2874 object_class_property_set_description(oc, "virtualization", 2875 "Set on/off to enable/disable emulating a " 2876 "guest CPU which implements the ARM " 2877 "Virtualization Extensions"); 2878 2879 object_class_property_add_bool(oc, "highmem", virt_get_highmem, 2880 virt_set_highmem); 2881 object_class_property_set_description(oc, "highmem", 2882 "Set on/off to enable/disable using " 2883 "physical address space above 32 bits"); 2884 2885 object_class_property_add_str(oc, "gic-version", virt_get_gic_version, 2886 virt_set_gic_version); 2887 object_class_property_set_description(oc, "gic-version", 2888 "Set GIC version. " 2889 "Valid values are 2, 3, host and max"); 2890 2891 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); 2892 object_class_property_set_description(oc, "iommu", 2893 "Set the IOMMU type. " 2894 "Valid values are none and smmuv3"); 2895 2896 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 2897 virt_get_default_bus_bypass_iommu, 2898 virt_set_default_bus_bypass_iommu); 2899 object_class_property_set_description(oc, "default-bus-bypass-iommu", 2900 "Set on/off to enable/disable " 2901 "bypass_iommu for default root bus"); 2902 2903 object_class_property_add_bool(oc, "ras", virt_get_ras, 2904 virt_set_ras); 2905 object_class_property_set_description(oc, "ras", 2906 "Set on/off to enable/disable reporting host memory errors " 2907 "to a KVM guest using ACPI and guest external abort exceptions"); 2908 2909 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); 2910 object_class_property_set_description(oc, "mte", 2911 "Set on/off to enable/disable emulating a " 2912 "guest CPU which implements the ARM " 2913 "Memory Tagging Extension"); 2914 2915 object_class_property_add_bool(oc, "its", virt_get_its, 2916 virt_set_its); 2917 object_class_property_set_description(oc, "its", 2918 "Set on/off to enable/disable " 2919 "ITS instantiation"); 2920 2921 object_class_property_add_bool(oc, "dtb-kaslr-seed", 2922 virt_get_dtb_kaslr_seed, 2923 virt_set_dtb_kaslr_seed); 2924 object_class_property_set_description(oc, "dtb-kaslr-seed", 2925 "Set off to disable passing of kaslr-seed " 2926 "dtb node to guest"); 2927 2928 object_class_property_add_str(oc, "x-oem-id", 2929 virt_get_oem_id, 2930 virt_set_oem_id); 2931 object_class_property_set_description(oc, "x-oem-id", 2932 "Override the default value of field OEMID " 2933 "in ACPI table header." 2934 "The string may be up to 6 bytes in size"); 2935 2936 2937 object_class_property_add_str(oc, "x-oem-table-id", 2938 virt_get_oem_table_id, 2939 virt_set_oem_table_id); 2940 object_class_property_set_description(oc, "x-oem-table-id", 2941 "Override the default value of field OEM Table ID " 2942 "in ACPI table header." 2943 "The string may be up to 8 bytes in size"); 2944 2945 } 2946 2947 static void virt_instance_init(Object *obj) 2948 { 2949 VirtMachineState *vms = VIRT_MACHINE(obj); 2950 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 2951 2952 /* EL3 is disabled by default on virt: this makes us consistent 2953 * between KVM and TCG for this board, and it also allows us to 2954 * boot UEFI blobs which assume no TrustZone support. 2955 */ 2956 vms->secure = false; 2957 2958 /* EL2 is also disabled by default, for similar reasons */ 2959 vms->virt = false; 2960 2961 /* High memory is enabled by default */ 2962 vms->highmem = true; 2963 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 2964 2965 vms->highmem_ecam = !vmc->no_highmem_ecam; 2966 vms->highmem_mmio = true; 2967 vms->highmem_redists = true; 2968 2969 if (vmc->no_its) { 2970 vms->its = false; 2971 } else { 2972 /* Default allows ITS instantiation */ 2973 vms->its = true; 2974 2975 if (vmc->no_tcg_its) { 2976 vms->tcg_its = false; 2977 } else { 2978 vms->tcg_its = true; 2979 } 2980 } 2981 2982 /* Default disallows iommu instantiation */ 2983 vms->iommu = VIRT_IOMMU_NONE; 2984 2985 /* The default root bus is attached to iommu by default */ 2986 vms->default_bus_bypass_iommu = false; 2987 2988 /* Default disallows RAS instantiation */ 2989 vms->ras = false; 2990 2991 /* MTE is disabled by default. */ 2992 vms->mte = false; 2993 2994 /* Supply a kaslr-seed by default */ 2995 vms->dtb_kaslr_seed = true; 2996 2997 vms->irqmap = a15irqmap; 2998 2999 virt_flash_create(vms); 3000 3001 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 3002 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 3003 } 3004 3005 static const TypeInfo virt_machine_info = { 3006 .name = TYPE_VIRT_MACHINE, 3007 .parent = TYPE_MACHINE, 3008 .abstract = true, 3009 .instance_size = sizeof(VirtMachineState), 3010 .class_size = sizeof(VirtMachineClass), 3011 .class_init = virt_machine_class_init, 3012 .instance_init = virt_instance_init, 3013 .interfaces = (InterfaceInfo[]) { 3014 { TYPE_HOTPLUG_HANDLER }, 3015 { } 3016 }, 3017 }; 3018 3019 static void machvirt_machine_init(void) 3020 { 3021 type_register_static(&virt_machine_info); 3022 } 3023 type_init(machvirt_machine_init); 3024 3025 static void virt_machine_7_1_options(MachineClass *mc) 3026 { 3027 } 3028 DEFINE_VIRT_MACHINE_AS_LATEST(7, 1) 3029 3030 static void virt_machine_7_0_options(MachineClass *mc) 3031 { 3032 virt_machine_7_1_options(mc); 3033 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 3034 } 3035 DEFINE_VIRT_MACHINE(7, 0) 3036 3037 static void virt_machine_6_2_options(MachineClass *mc) 3038 { 3039 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3040 3041 virt_machine_7_0_options(mc); 3042 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 3043 vmc->no_tcg_lpa2 = true; 3044 } 3045 DEFINE_VIRT_MACHINE(6, 2) 3046 3047 static void virt_machine_6_1_options(MachineClass *mc) 3048 { 3049 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3050 3051 virt_machine_6_2_options(mc); 3052 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 3053 mc->smp_props.prefer_sockets = true; 3054 vmc->no_cpu_topology = true; 3055 3056 /* qemu ITS was introduced with 6.2 */ 3057 vmc->no_tcg_its = true; 3058 } 3059 DEFINE_VIRT_MACHINE(6, 1) 3060 3061 static void virt_machine_6_0_options(MachineClass *mc) 3062 { 3063 virt_machine_6_1_options(mc); 3064 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 3065 } 3066 DEFINE_VIRT_MACHINE(6, 0) 3067 3068 static void virt_machine_5_2_options(MachineClass *mc) 3069 { 3070 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3071 3072 virt_machine_6_0_options(mc); 3073 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 3074 vmc->no_secure_gpio = true; 3075 } 3076 DEFINE_VIRT_MACHINE(5, 2) 3077 3078 static void virt_machine_5_1_options(MachineClass *mc) 3079 { 3080 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3081 3082 virt_machine_5_2_options(mc); 3083 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 3084 vmc->no_kvm_steal_time = true; 3085 } 3086 DEFINE_VIRT_MACHINE(5, 1) 3087 3088 static void virt_machine_5_0_options(MachineClass *mc) 3089 { 3090 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3091 3092 virt_machine_5_1_options(mc); 3093 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 3094 mc->numa_mem_supported = true; 3095 vmc->acpi_expose_flash = true; 3096 mc->auto_enable_numa_with_memdev = false; 3097 } 3098 DEFINE_VIRT_MACHINE(5, 0) 3099 3100 static void virt_machine_4_2_options(MachineClass *mc) 3101 { 3102 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3103 3104 virt_machine_5_0_options(mc); 3105 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 3106 vmc->kvm_no_adjvtime = true; 3107 } 3108 DEFINE_VIRT_MACHINE(4, 2) 3109 3110 static void virt_machine_4_1_options(MachineClass *mc) 3111 { 3112 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3113 3114 virt_machine_4_2_options(mc); 3115 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 3116 vmc->no_ged = true; 3117 mc->auto_enable_numa_with_memhp = false; 3118 } 3119 DEFINE_VIRT_MACHINE(4, 1) 3120 3121 static void virt_machine_4_0_options(MachineClass *mc) 3122 { 3123 virt_machine_4_1_options(mc); 3124 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 3125 } 3126 DEFINE_VIRT_MACHINE(4, 0) 3127 3128 static void virt_machine_3_1_options(MachineClass *mc) 3129 { 3130 virt_machine_4_0_options(mc); 3131 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 3132 } 3133 DEFINE_VIRT_MACHINE(3, 1) 3134 3135 static void virt_machine_3_0_options(MachineClass *mc) 3136 { 3137 virt_machine_3_1_options(mc); 3138 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 3139 } 3140 DEFINE_VIRT_MACHINE(3, 0) 3141 3142 static void virt_machine_2_12_options(MachineClass *mc) 3143 { 3144 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3145 3146 virt_machine_3_0_options(mc); 3147 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 3148 vmc->no_highmem_ecam = true; 3149 mc->max_cpus = 255; 3150 } 3151 DEFINE_VIRT_MACHINE(2, 12) 3152 3153 static void virt_machine_2_11_options(MachineClass *mc) 3154 { 3155 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3156 3157 virt_machine_2_12_options(mc); 3158 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 3159 vmc->smbios_old_sys_ver = true; 3160 } 3161 DEFINE_VIRT_MACHINE(2, 11) 3162 3163 static void virt_machine_2_10_options(MachineClass *mc) 3164 { 3165 virt_machine_2_11_options(mc); 3166 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 3167 /* before 2.11 we never faulted accesses to bad addresses */ 3168 mc->ignore_memory_transaction_failures = true; 3169 } 3170 DEFINE_VIRT_MACHINE(2, 10) 3171 3172 static void virt_machine_2_9_options(MachineClass *mc) 3173 { 3174 virt_machine_2_10_options(mc); 3175 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 3176 } 3177 DEFINE_VIRT_MACHINE(2, 9) 3178 3179 static void virt_machine_2_8_options(MachineClass *mc) 3180 { 3181 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3182 3183 virt_machine_2_9_options(mc); 3184 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 3185 /* For 2.8 and earlier we falsely claimed in the DT that 3186 * our timers were edge-triggered, not level-triggered. 3187 */ 3188 vmc->claim_edge_triggered_timers = true; 3189 } 3190 DEFINE_VIRT_MACHINE(2, 8) 3191 3192 static void virt_machine_2_7_options(MachineClass *mc) 3193 { 3194 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3195 3196 virt_machine_2_8_options(mc); 3197 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 3198 /* ITS was introduced with 2.8 */ 3199 vmc->no_its = true; 3200 /* Stick with 1K pages for migration compatibility */ 3201 mc->minimum_page_bits = 0; 3202 } 3203 DEFINE_VIRT_MACHINE(2, 7) 3204 3205 static void virt_machine_2_6_options(MachineClass *mc) 3206 { 3207 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3208 3209 virt_machine_2_7_options(mc); 3210 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 3211 vmc->disallow_affinity_adjustment = true; 3212 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 3213 vmc->no_pmu = true; 3214 } 3215 DEFINE_VIRT_MACHINE(2, 6) 3216