xref: /openbmc/qemu/hw/arm/virt.c (revision 6c7937ec)
1 /*
2  * ARM mach-virt emulation
3  *
4  * Copyright (c) 2013 Linaro Limited
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2 or later, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program.  If not, see <http://www.gnu.org/licenses/>.
17  *
18  * Emulate a virtual board which works by passing Linux all the information
19  * it needs about what devices are present via the device tree.
20  * There are some restrictions about what we can do here:
21  *  + we can only present devices whose Linux drivers will work based
22  *    purely on the device tree with no platform data at all
23  *  + we want to present a very stripped-down minimalist platform,
24  *    both because this reduces the security attack surface from the guest
25  *    and also because it reduces our exposure to being broken when
26  *    the kernel updates its device tree bindings and requires further
27  *    information in a device binding that we aren't providing.
28  * This is essentially the same approach kvmtool uses.
29  */
30 
31 #include "qemu/osdep.h"
32 #include "qemu/datadir.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "monitor/qdev.h"
36 #include "hw/sysbus.h"
37 #include "hw/arm/boot.h"
38 #include "hw/arm/primecell.h"
39 #include "hw/arm/virt.h"
40 #include "hw/block/flash.h"
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
43 #include "hw/display/ramfb.h"
44 #include "net/net.h"
45 #include "sysemu/device_tree.h"
46 #include "sysemu/numa.h"
47 #include "sysemu/runstate.h"
48 #include "sysemu/tpm.h"
49 #include "sysemu/tcg.h"
50 #include "sysemu/kvm.h"
51 #include "sysemu/hvf.h"
52 #include "sysemu/qtest.h"
53 #include "hw/loader.h"
54 #include "qapi/error.h"
55 #include "qemu/bitops.h"
56 #include "qemu/error-report.h"
57 #include "qemu/module.h"
58 #include "hw/pci-host/gpex.h"
59 #include "hw/virtio/virtio-pci.h"
60 #include "hw/core/sysbus-fdt.h"
61 #include "hw/platform-bus.h"
62 #include "hw/qdev-properties.h"
63 #include "hw/arm/fdt.h"
64 #include "hw/intc/arm_gic.h"
65 #include "hw/intc/arm_gicv3_common.h"
66 #include "hw/intc/arm_gicv3_its_common.h"
67 #include "hw/irq.h"
68 #include "kvm_arm.h"
69 #include "hw/firmware/smbios.h"
70 #include "qapi/visitor.h"
71 #include "qapi/qapi-visit-common.h"
72 #include "standard-headers/linux/input.h"
73 #include "hw/arm/smmuv3.h"
74 #include "hw/acpi/acpi.h"
75 #include "target/arm/internals.h"
76 #include "hw/mem/pc-dimm.h"
77 #include "hw/mem/nvdimm.h"
78 #include "hw/acpi/generic_event_device.h"
79 #include "hw/virtio/virtio-md-pci.h"
80 #include "hw/virtio/virtio-iommu.h"
81 #include "hw/char/pl011.h"
82 #include "qemu/guest-random.h"
83 
84 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
85     static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
86                                                     void *data) \
87     { \
88         MachineClass *mc = MACHINE_CLASS(oc); \
89         virt_machine_##major##_##minor##_options(mc); \
90         mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
91         if (latest) { \
92             mc->alias = "virt"; \
93         } \
94     } \
95     static const TypeInfo machvirt_##major##_##minor##_info = { \
96         .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
97         .parent = TYPE_VIRT_MACHINE, \
98         .class_init = virt_##major##_##minor##_class_init, \
99     }; \
100     static void machvirt_machine_##major##_##minor##_init(void) \
101     { \
102         type_register_static(&machvirt_##major##_##minor##_info); \
103     } \
104     type_init(machvirt_machine_##major##_##minor##_init);
105 
106 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
107     DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
108 #define DEFINE_VIRT_MACHINE(major, minor) \
109     DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
110 
111 
112 /* Number of external interrupt lines to configure the GIC with */
113 #define NUM_IRQS 256
114 
115 #define PLATFORM_BUS_NUM_IRQS 64
116 
117 /* Legacy RAM limit in GB (< version 4.0) */
118 #define LEGACY_RAMLIMIT_GB 255
119 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
120 
121 /* Addresses and sizes of our components.
122  * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
123  * 128MB..256MB is used for miscellaneous device I/O.
124  * 256MB..1GB is reserved for possible future PCI support (ie where the
125  * PCI memory window will go if we add a PCI host controller).
126  * 1GB and up is RAM (which may happily spill over into the
127  * high memory region beyond 4GB).
128  * This represents a compromise between how much RAM can be given to
129  * a 32 bit VM and leaving space for expansion and in particular for PCI.
130  * Note that devices should generally be placed at multiples of 0x10000,
131  * to accommodate guests using 64K pages.
132  */
133 static const MemMapEntry base_memmap[] = {
134     /* Space up to 0x8000000 is reserved for a boot ROM */
135     [VIRT_FLASH] =              {          0, 0x08000000 },
136     [VIRT_CPUPERIPHS] =         { 0x08000000, 0x00020000 },
137     /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
138     [VIRT_GIC_DIST] =           { 0x08000000, 0x00010000 },
139     [VIRT_GIC_CPU] =            { 0x08010000, 0x00010000 },
140     [VIRT_GIC_V2M] =            { 0x08020000, 0x00001000 },
141     [VIRT_GIC_HYP] =            { 0x08030000, 0x00010000 },
142     [VIRT_GIC_VCPU] =           { 0x08040000, 0x00010000 },
143     /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
144     [VIRT_GIC_ITS] =            { 0x08080000, 0x00020000 },
145     /* This redistributor space allows up to 2*64kB*123 CPUs */
146     [VIRT_GIC_REDIST] =         { 0x080A0000, 0x00F60000 },
147     [VIRT_UART] =               { 0x09000000, 0x00001000 },
148     [VIRT_RTC] =                { 0x09010000, 0x00001000 },
149     [VIRT_FW_CFG] =             { 0x09020000, 0x00000018 },
150     [VIRT_GPIO] =               { 0x09030000, 0x00001000 },
151     [VIRT_SECURE_UART] =        { 0x09040000, 0x00001000 },
152     [VIRT_SMMU] =               { 0x09050000, 0x00020000 },
153     [VIRT_PCDIMM_ACPI] =        { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
154     [VIRT_ACPI_GED] =           { 0x09080000, ACPI_GED_EVT_SEL_LEN },
155     [VIRT_NVDIMM_ACPI] =        { 0x09090000, NVDIMM_ACPI_IO_LEN},
156     [VIRT_PVTIME] =             { 0x090a0000, 0x00010000 },
157     [VIRT_SECURE_GPIO] =        { 0x090b0000, 0x00001000 },
158     [VIRT_MMIO] =               { 0x0a000000, 0x00000200 },
159     /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
160     [VIRT_PLATFORM_BUS] =       { 0x0c000000, 0x02000000 },
161     [VIRT_SECURE_MEM] =         { 0x0e000000, 0x01000000 },
162     [VIRT_PCIE_MMIO] =          { 0x10000000, 0x2eff0000 },
163     [VIRT_PCIE_PIO] =           { 0x3eff0000, 0x00010000 },
164     [VIRT_PCIE_ECAM] =          { 0x3f000000, 0x01000000 },
165     /* Actual RAM size depends on initial RAM and device memory settings */
166     [VIRT_MEM] =                { GiB, LEGACY_RAMLIMIT_BYTES },
167 };
168 
169 /*
170  * Highmem IO Regions: This memory map is floating, located after the RAM.
171  * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
172  * top of the RAM, so that its base get the same alignment as the size,
173  * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
174  * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
175  * Note the extended_memmap is sized so that it eventually also includes the
176  * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
177  * index of base_memmap).
178  *
179  * The memory map for these Highmem IO Regions can be in legacy or compact
180  * layout, depending on 'compact-highmem' property. With legacy layout, the
181  * PA space for one specific region is always reserved, even if the region
182  * has been disabled or doesn't fit into the PA space. However, the PA space
183  * for the region won't be reserved in these circumstances with compact layout.
184  */
185 static MemMapEntry extended_memmap[] = {
186     /* Additional 64 MB redist region (can contain up to 512 redistributors) */
187     [VIRT_HIGH_GIC_REDIST2] =   { 0x0, 64 * MiB },
188     [VIRT_HIGH_PCIE_ECAM] =     { 0x0, 256 * MiB },
189     /* Second PCIe window */
190     [VIRT_HIGH_PCIE_MMIO] =     { 0x0, 512 * GiB },
191 };
192 
193 static const int a15irqmap[] = {
194     [VIRT_UART] = 1,
195     [VIRT_RTC] = 2,
196     [VIRT_PCIE] = 3, /* ... to 6 */
197     [VIRT_GPIO] = 7,
198     [VIRT_SECURE_UART] = 8,
199     [VIRT_ACPI_GED] = 9,
200     [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
201     [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
202     [VIRT_SMMU] = 74,    /* ...to 74 + NUM_SMMU_IRQS - 1 */
203     [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
204 };
205 
206 static const char *valid_cpus[] = {
207 #ifdef CONFIG_TCG
208     ARM_CPU_TYPE_NAME("cortex-a7"),
209     ARM_CPU_TYPE_NAME("cortex-a15"),
210     ARM_CPU_TYPE_NAME("cortex-a35"),
211     ARM_CPU_TYPE_NAME("cortex-a55"),
212     ARM_CPU_TYPE_NAME("cortex-a72"),
213     ARM_CPU_TYPE_NAME("cortex-a76"),
214     ARM_CPU_TYPE_NAME("cortex-a710"),
215     ARM_CPU_TYPE_NAME("a64fx"),
216     ARM_CPU_TYPE_NAME("neoverse-n1"),
217     ARM_CPU_TYPE_NAME("neoverse-v1"),
218     ARM_CPU_TYPE_NAME("neoverse-n2"),
219 #endif
220     ARM_CPU_TYPE_NAME("cortex-a53"),
221     ARM_CPU_TYPE_NAME("cortex-a57"),
222     ARM_CPU_TYPE_NAME("host"),
223     ARM_CPU_TYPE_NAME("max"),
224 };
225 
226 static bool cpu_type_valid(const char *cpu)
227 {
228     int i;
229 
230     for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
231         if (strcmp(cpu, valid_cpus[i]) == 0) {
232             return true;
233         }
234     }
235     return false;
236 }
237 
238 static void create_randomness(MachineState *ms, const char *node)
239 {
240     struct {
241         uint64_t kaslr;
242         uint8_t rng[32];
243     } seed;
244 
245     if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) {
246         return;
247     }
248     qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr);
249     qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
250 }
251 
252 static void create_fdt(VirtMachineState *vms)
253 {
254     MachineState *ms = MACHINE(vms);
255     int nb_numa_nodes = ms->numa_state->num_nodes;
256     void *fdt = create_device_tree(&vms->fdt_size);
257 
258     if (!fdt) {
259         error_report("create_device_tree() failed");
260         exit(1);
261     }
262 
263     ms->fdt = fdt;
264 
265     /* Header */
266     qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
267     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
268     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
269     qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
270 
271     /* /chosen must exist for load_dtb to fill in necessary properties later */
272     qemu_fdt_add_subnode(fdt, "/chosen");
273     if (vms->dtb_randomness) {
274         create_randomness(ms, "/chosen");
275     }
276 
277     if (vms->secure) {
278         qemu_fdt_add_subnode(fdt, "/secure-chosen");
279         if (vms->dtb_randomness) {
280             create_randomness(ms, "/secure-chosen");
281         }
282     }
283 
284     /* Clock node, for the benefit of the UART. The kernel device tree
285      * binding documentation claims the PL011 node clock properties are
286      * optional but in practice if you omit them the kernel refuses to
287      * probe for the device.
288      */
289     vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
290     qemu_fdt_add_subnode(fdt, "/apb-pclk");
291     qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
292     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
293     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
294     qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
295                                 "clk24mhz");
296     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
297 
298     if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
299         int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
300         uint32_t *matrix = g_malloc0(size);
301         int idx, i, j;
302 
303         for (i = 0; i < nb_numa_nodes; i++) {
304             for (j = 0; j < nb_numa_nodes; j++) {
305                 idx = (i * nb_numa_nodes + j) * 3;
306                 matrix[idx + 0] = cpu_to_be32(i);
307                 matrix[idx + 1] = cpu_to_be32(j);
308                 matrix[idx + 2] =
309                     cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
310             }
311         }
312 
313         qemu_fdt_add_subnode(fdt, "/distance-map");
314         qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
315                                 "numa-distance-map-v1");
316         qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
317                          matrix, size);
318         g_free(matrix);
319     }
320 }
321 
322 static void fdt_add_timer_nodes(const VirtMachineState *vms)
323 {
324     /* On real hardware these interrupts are level-triggered.
325      * On KVM they were edge-triggered before host kernel version 4.4,
326      * and level-triggered afterwards.
327      * On emulated QEMU they are level-triggered.
328      *
329      * Getting the DTB info about them wrong is awkward for some
330      * guest kernels:
331      *  pre-4.8 ignore the DT and leave the interrupt configured
332      *   with whatever the GIC reset value (or the bootloader) left it at
333      *  4.8 before rc6 honour the incorrect data by programming it back
334      *   into the GIC, causing problems
335      *  4.8rc6 and later ignore the DT and always write "level triggered"
336      *   into the GIC
337      *
338      * For backwards-compatibility, virt-2.8 and earlier will continue
339      * to say these are edge-triggered, but later machines will report
340      * the correct information.
341      */
342     ARMCPU *armcpu;
343     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
344     uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
345     MachineState *ms = MACHINE(vms);
346 
347     if (vmc->claim_edge_triggered_timers) {
348         irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
349     }
350 
351     if (vms->gic_version == VIRT_GIC_VERSION_2) {
352         irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
353                              GIC_FDT_IRQ_PPI_CPU_WIDTH,
354                              (1 << MACHINE(vms)->smp.cpus) - 1);
355     }
356 
357     qemu_fdt_add_subnode(ms->fdt, "/timer");
358 
359     armcpu = ARM_CPU(qemu_get_cpu(0));
360     if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
361         const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
362         qemu_fdt_setprop(ms->fdt, "/timer", "compatible",
363                          compat, sizeof(compat));
364     } else {
365         qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible",
366                                 "arm,armv7-timer");
367     }
368     qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
369     qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
370                            GIC_FDT_IRQ_TYPE_PPI,
371                            INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
372                            GIC_FDT_IRQ_TYPE_PPI,
373                            INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
374                            GIC_FDT_IRQ_TYPE_PPI,
375                            INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
376                            GIC_FDT_IRQ_TYPE_PPI,
377                            INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
378 }
379 
380 static void fdt_add_cpu_nodes(const VirtMachineState *vms)
381 {
382     int cpu;
383     int addr_cells = 1;
384     const MachineState *ms = MACHINE(vms);
385     const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
386     int smp_cpus = ms->smp.cpus;
387 
388     /*
389      * See Linux Documentation/devicetree/bindings/arm/cpus.yaml
390      * On ARM v8 64-bit systems value should be set to 2,
391      * that corresponds to the MPIDR_EL1 register size.
392      * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
393      * in the system, #address-cells can be set to 1, since
394      * MPIDR_EL1[63:32] bits are not used for CPUs
395      * identification.
396      *
397      * Here we actually don't know whether our system is 32- or 64-bit one.
398      * The simplest way to go is to examine affinity IDs of all our CPUs. If
399      * at least one of them has Aff3 populated, we set #address-cells to 2.
400      */
401     for (cpu = 0; cpu < smp_cpus; cpu++) {
402         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
403 
404         if (armcpu->mp_affinity & ARM_AFF3_MASK) {
405             addr_cells = 2;
406             break;
407         }
408     }
409 
410     qemu_fdt_add_subnode(ms->fdt, "/cpus");
411     qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells);
412     qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
413 
414     for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
415         char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
416         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
417         CPUState *cs = CPU(armcpu);
418 
419         qemu_fdt_add_subnode(ms->fdt, nodename);
420         qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
421         qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
422                                     armcpu->dtb_compatible);
423 
424         if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {
425             qemu_fdt_setprop_string(ms->fdt, nodename,
426                                         "enable-method", "psci");
427         }
428 
429         if (addr_cells == 2) {
430             qemu_fdt_setprop_u64(ms->fdt, nodename, "reg",
431                                  armcpu->mp_affinity);
432         } else {
433             qemu_fdt_setprop_cell(ms->fdt, nodename, "reg",
434                                   armcpu->mp_affinity);
435         }
436 
437         if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
438             qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
439                 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
440         }
441 
442         if (!vmc->no_cpu_topology) {
443             qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
444                                   qemu_fdt_alloc_phandle(ms->fdt));
445         }
446 
447         g_free(nodename);
448     }
449 
450     if (!vmc->no_cpu_topology) {
451         /*
452          * Add vCPU topology description through fdt node cpu-map.
453          *
454          * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
455          * In a SMP system, the hierarchy of CPUs can be defined through
456          * four entities that are used to describe the layout of CPUs in
457          * the system: socket/cluster/core/thread.
458          *
459          * A socket node represents the boundary of system physical package
460          * and its child nodes must be one or more cluster nodes. A system
461          * can contain several layers of clustering within a single physical
462          * package and cluster nodes can be contained in parent cluster nodes.
463          *
464          * Note: currently we only support one layer of clustering within
465          * each physical package.
466          */
467         qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
468 
469         for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
470             char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu);
471             char *map_path;
472 
473             if (ms->smp.threads > 1) {
474                 map_path = g_strdup_printf(
475                     "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
476                     cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads),
477                     (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters,
478                     (cpu / ms->smp.threads) % ms->smp.cores,
479                     cpu % ms->smp.threads);
480             } else {
481                 map_path = g_strdup_printf(
482                     "/cpus/cpu-map/socket%d/cluster%d/core%d",
483                     cpu / (ms->smp.clusters * ms->smp.cores),
484                     (cpu / ms->smp.cores) % ms->smp.clusters,
485                     cpu % ms->smp.cores);
486             }
487             qemu_fdt_add_path(ms->fdt, map_path);
488             qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
489 
490             g_free(map_path);
491             g_free(cpu_path);
492         }
493     }
494 }
495 
496 static void fdt_add_its_gic_node(VirtMachineState *vms)
497 {
498     char *nodename;
499     MachineState *ms = MACHINE(vms);
500 
501     vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
502     nodename = g_strdup_printf("/intc/its@%" PRIx64,
503                                vms->memmap[VIRT_GIC_ITS].base);
504     qemu_fdt_add_subnode(ms->fdt, nodename);
505     qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
506                             "arm,gic-v3-its");
507     qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
508     qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
509     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
510                                  2, vms->memmap[VIRT_GIC_ITS].base,
511                                  2, vms->memmap[VIRT_GIC_ITS].size);
512     qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
513     g_free(nodename);
514 }
515 
516 static void fdt_add_v2m_gic_node(VirtMachineState *vms)
517 {
518     MachineState *ms = MACHINE(vms);
519     char *nodename;
520 
521     nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
522                                vms->memmap[VIRT_GIC_V2M].base);
523     vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
524     qemu_fdt_add_subnode(ms->fdt, nodename);
525     qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
526                             "arm,gic-v2m-frame");
527     qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
528     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
529                                  2, vms->memmap[VIRT_GIC_V2M].base,
530                                  2, vms->memmap[VIRT_GIC_V2M].size);
531     qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
532     g_free(nodename);
533 }
534 
535 static void fdt_add_gic_node(VirtMachineState *vms)
536 {
537     MachineState *ms = MACHINE(vms);
538     char *nodename;
539 
540     vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
541     qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle);
542 
543     nodename = g_strdup_printf("/intc@%" PRIx64,
544                                vms->memmap[VIRT_GIC_DIST].base);
545     qemu_fdt_add_subnode(ms->fdt, nodename);
546     qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);
547     qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
548     qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
549     qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);
550     qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);
551     if (vms->gic_version != VIRT_GIC_VERSION_2) {
552         int nb_redist_regions = virt_gicv3_redist_region_count(vms);
553 
554         qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
555                                 "arm,gic-v3");
556 
557         qemu_fdt_setprop_cell(ms->fdt, nodename,
558                               "#redistributor-regions", nb_redist_regions);
559 
560         if (nb_redist_regions == 1) {
561             qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
562                                          2, vms->memmap[VIRT_GIC_DIST].base,
563                                          2, vms->memmap[VIRT_GIC_DIST].size,
564                                          2, vms->memmap[VIRT_GIC_REDIST].base,
565                                          2, vms->memmap[VIRT_GIC_REDIST].size);
566         } else {
567             qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
568                                  2, vms->memmap[VIRT_GIC_DIST].base,
569                                  2, vms->memmap[VIRT_GIC_DIST].size,
570                                  2, vms->memmap[VIRT_GIC_REDIST].base,
571                                  2, vms->memmap[VIRT_GIC_REDIST].size,
572                                  2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
573                                  2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
574         }
575 
576         if (vms->virt) {
577             qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
578                                    GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
579                                    GIC_FDT_IRQ_FLAGS_LEVEL_HI);
580         }
581     } else {
582         /* 'cortex-a15-gic' means 'GIC v2' */
583         qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
584                                 "arm,cortex-a15-gic");
585         if (!vms->virt) {
586             qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
587                                          2, vms->memmap[VIRT_GIC_DIST].base,
588                                          2, vms->memmap[VIRT_GIC_DIST].size,
589                                          2, vms->memmap[VIRT_GIC_CPU].base,
590                                          2, vms->memmap[VIRT_GIC_CPU].size);
591         } else {
592             qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
593                                          2, vms->memmap[VIRT_GIC_DIST].base,
594                                          2, vms->memmap[VIRT_GIC_DIST].size,
595                                          2, vms->memmap[VIRT_GIC_CPU].base,
596                                          2, vms->memmap[VIRT_GIC_CPU].size,
597                                          2, vms->memmap[VIRT_GIC_HYP].base,
598                                          2, vms->memmap[VIRT_GIC_HYP].size,
599                                          2, vms->memmap[VIRT_GIC_VCPU].base,
600                                          2, vms->memmap[VIRT_GIC_VCPU].size);
601             qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
602                                    GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
603                                    GIC_FDT_IRQ_FLAGS_LEVEL_HI);
604         }
605     }
606 
607     qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle);
608     g_free(nodename);
609 }
610 
611 static void fdt_add_pmu_nodes(const VirtMachineState *vms)
612 {
613     ARMCPU *armcpu = ARM_CPU(first_cpu);
614     uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
615     MachineState *ms = MACHINE(vms);
616 
617     if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
618         assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
619         return;
620     }
621 
622     if (vms->gic_version == VIRT_GIC_VERSION_2) {
623         irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
624                              GIC_FDT_IRQ_PPI_CPU_WIDTH,
625                              (1 << MACHINE(vms)->smp.cpus) - 1);
626     }
627 
628     qemu_fdt_add_subnode(ms->fdt, "/pmu");
629     if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
630         const char compat[] = "arm,armv8-pmuv3";
631         qemu_fdt_setprop(ms->fdt, "/pmu", "compatible",
632                          compat, sizeof(compat));
633         qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts",
634                                GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
635     }
636 }
637 
638 static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
639 {
640     DeviceState *dev;
641     MachineState *ms = MACHINE(vms);
642     int irq = vms->irqmap[VIRT_ACPI_GED];
643     uint32_t event = ACPI_GED_PWR_DOWN_EVT;
644 
645     if (ms->ram_slots) {
646         event |= ACPI_GED_MEM_HOTPLUG_EVT;
647     }
648 
649     if (ms->nvdimms_state->is_enabled) {
650         event |= ACPI_GED_NVDIMM_HOTPLUG_EVT;
651     }
652 
653     dev = qdev_new(TYPE_ACPI_GED);
654     qdev_prop_set_uint32(dev, "ged-event", event);
655     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
656 
657     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
658     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
659     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
660 
661     return dev;
662 }
663 
664 static void create_its(VirtMachineState *vms)
665 {
666     const char *itsclass = its_class_name();
667     DeviceState *dev;
668 
669     if (!strcmp(itsclass, "arm-gicv3-its")) {
670         if (!vms->tcg_its) {
671             itsclass = NULL;
672         }
673     }
674 
675     if (!itsclass) {
676         /* Do nothing if not supported */
677         return;
678     }
679 
680     dev = qdev_new(itsclass);
681 
682     object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic),
683                              &error_abort);
684     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
685     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
686 
687     fdt_add_its_gic_node(vms);
688     vms->msi_controller = VIRT_MSI_CTRL_ITS;
689 }
690 
691 static void create_v2m(VirtMachineState *vms)
692 {
693     int i;
694     int irq = vms->irqmap[VIRT_GIC_V2M];
695     DeviceState *dev;
696 
697     dev = qdev_new("arm-gicv2m");
698     qdev_prop_set_uint32(dev, "base-spi", irq);
699     qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
700     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
701     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
702 
703     for (i = 0; i < NUM_GICV2M_SPIS; i++) {
704         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
705                            qdev_get_gpio_in(vms->gic, irq + i));
706     }
707 
708     fdt_add_v2m_gic_node(vms);
709     vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
710 }
711 
712 static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
713 {
714     MachineState *ms = MACHINE(vms);
715     /* We create a standalone GIC */
716     SysBusDevice *gicbusdev;
717     const char *gictype;
718     int i;
719     unsigned int smp_cpus = ms->smp.cpus;
720     uint32_t nb_redist_regions = 0;
721     int revision;
722 
723     if (vms->gic_version == VIRT_GIC_VERSION_2) {
724         gictype = gic_class_name();
725     } else {
726         gictype = gicv3_class_name();
727     }
728 
729     switch (vms->gic_version) {
730     case VIRT_GIC_VERSION_2:
731         revision = 2;
732         break;
733     case VIRT_GIC_VERSION_3:
734         revision = 3;
735         break;
736     case VIRT_GIC_VERSION_4:
737         revision = 4;
738         break;
739     default:
740         g_assert_not_reached();
741     }
742     vms->gic = qdev_new(gictype);
743     qdev_prop_set_uint32(vms->gic, "revision", revision);
744     qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
745     /* Note that the num-irq property counts both internal and external
746      * interrupts; there are always 32 of the former (mandated by GIC spec).
747      */
748     qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32);
749     if (!kvm_irqchip_in_kernel()) {
750         qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure);
751     }
752 
753     if (vms->gic_version != VIRT_GIC_VERSION_2) {
754         uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST);
755         uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
756 
757         nb_redist_regions = virt_gicv3_redist_region_count(vms);
758 
759         qdev_prop_set_uint32(vms->gic, "len-redist-region-count",
760                              nb_redist_regions);
761         qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count);
762 
763         if (!kvm_irqchip_in_kernel()) {
764             if (vms->tcg_its) {
765                 object_property_set_link(OBJECT(vms->gic), "sysmem",
766                                          OBJECT(mem), &error_fatal);
767                 qdev_prop_set_bit(vms->gic, "has-lpi", true);
768             }
769         }
770 
771         if (nb_redist_regions == 2) {
772             uint32_t redist1_capacity =
773                 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
774 
775             qdev_prop_set_uint32(vms->gic, "redist-region-count[1]",
776                 MIN(smp_cpus - redist0_count, redist1_capacity));
777         }
778     } else {
779         if (!kvm_irqchip_in_kernel()) {
780             qdev_prop_set_bit(vms->gic, "has-virtualization-extensions",
781                               vms->virt);
782         }
783     }
784     gicbusdev = SYS_BUS_DEVICE(vms->gic);
785     sysbus_realize_and_unref(gicbusdev, &error_fatal);
786     sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
787     if (vms->gic_version != VIRT_GIC_VERSION_2) {
788         sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
789         if (nb_redist_regions == 2) {
790             sysbus_mmio_map(gicbusdev, 2,
791                             vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
792         }
793     } else {
794         sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
795         if (vms->virt) {
796             sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
797             sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
798         }
799     }
800 
801     /* Wire the outputs from each CPU's generic timer and the GICv3
802      * maintenance interrupt signal to the appropriate GIC PPI inputs,
803      * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
804      */
805     for (i = 0; i < smp_cpus; i++) {
806         DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
807         int intidbase = NUM_IRQS + i * GIC_INTERNAL;
808         /* Mapping from the output timer irq lines from the CPU to the
809          * GIC PPI inputs we use for the virt board.
810          */
811         const int timer_irq[] = {
812             [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
813             [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
814             [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
815             [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,
816         };
817 
818         for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
819             qdev_connect_gpio_out(cpudev, irq,
820                                   qdev_get_gpio_in(vms->gic,
821                                                    intidbase + timer_irq[irq]));
822         }
823 
824         if (vms->gic_version != VIRT_GIC_VERSION_2) {
825             qemu_irq irq = qdev_get_gpio_in(vms->gic,
826                                             intidbase + ARCH_GIC_MAINT_IRQ);
827             qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
828                                         0, irq);
829         } else if (vms->virt) {
830             qemu_irq irq = qdev_get_gpio_in(vms->gic,
831                                             intidbase + ARCH_GIC_MAINT_IRQ);
832             sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
833         }
834 
835         qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
836                                     qdev_get_gpio_in(vms->gic, intidbase
837                                                      + VIRTUAL_PMU_IRQ));
838 
839         sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
840         sysbus_connect_irq(gicbusdev, i + smp_cpus,
841                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
842         sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
843                            qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
844         sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
845                            qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
846     }
847 
848     fdt_add_gic_node(vms);
849 
850     if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) {
851         create_its(vms);
852     } else if (vms->gic_version == VIRT_GIC_VERSION_2) {
853         create_v2m(vms);
854     }
855 }
856 
857 static void create_uart(const VirtMachineState *vms, int uart,
858                         MemoryRegion *mem, Chardev *chr)
859 {
860     char *nodename;
861     hwaddr base = vms->memmap[uart].base;
862     hwaddr size = vms->memmap[uart].size;
863     int irq = vms->irqmap[uart];
864     const char compat[] = "arm,pl011\0arm,primecell";
865     const char clocknames[] = "uartclk\0apb_pclk";
866     DeviceState *dev = qdev_new(TYPE_PL011);
867     SysBusDevice *s = SYS_BUS_DEVICE(dev);
868     MachineState *ms = MACHINE(vms);
869 
870     qdev_prop_set_chr(dev, "chardev", chr);
871     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
872     memory_region_add_subregion(mem, base,
873                                 sysbus_mmio_get_region(s, 0));
874     sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
875 
876     nodename = g_strdup_printf("/pl011@%" PRIx64, base);
877     qemu_fdt_add_subnode(ms->fdt, nodename);
878     /* Note that we can't use setprop_string because of the embedded NUL */
879     qemu_fdt_setprop(ms->fdt, nodename, "compatible",
880                          compat, sizeof(compat));
881     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
882                                      2, base, 2, size);
883     qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
884                                GIC_FDT_IRQ_TYPE_SPI, irq,
885                                GIC_FDT_IRQ_FLAGS_LEVEL_HI);
886     qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks",
887                                vms->clock_phandle, vms->clock_phandle);
888     qemu_fdt_setprop(ms->fdt, nodename, "clock-names",
889                          clocknames, sizeof(clocknames));
890 
891     if (uart == VIRT_UART) {
892         qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
893     } else {
894         /* Mark as not usable by the normal world */
895         qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
896         qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
897 
898         qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path",
899                                 nodename);
900     }
901 
902     g_free(nodename);
903 }
904 
905 static void create_rtc(const VirtMachineState *vms)
906 {
907     char *nodename;
908     hwaddr base = vms->memmap[VIRT_RTC].base;
909     hwaddr size = vms->memmap[VIRT_RTC].size;
910     int irq = vms->irqmap[VIRT_RTC];
911     const char compat[] = "arm,pl031\0arm,primecell";
912     MachineState *ms = MACHINE(vms);
913 
914     sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq));
915 
916     nodename = g_strdup_printf("/pl031@%" PRIx64, base);
917     qemu_fdt_add_subnode(ms->fdt, nodename);
918     qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
919     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
920                                  2, base, 2, size);
921     qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
922                            GIC_FDT_IRQ_TYPE_SPI, irq,
923                            GIC_FDT_IRQ_FLAGS_LEVEL_HI);
924     qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
925     qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
926     g_free(nodename);
927 }
928 
929 static DeviceState *gpio_key_dev;
930 static void virt_powerdown_req(Notifier *n, void *opaque)
931 {
932     VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier);
933 
934     if (s->acpi_dev) {
935         acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS);
936     } else {
937         /* use gpio Pin 3 for power button event */
938         qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
939     }
940 }
941 
942 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev,
943                              uint32_t phandle)
944 {
945     gpio_key_dev = sysbus_create_simple("gpio-key", -1,
946                                         qdev_get_gpio_in(pl061_dev, 3));
947 
948     qemu_fdt_add_subnode(fdt, "/gpio-keys");
949     qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys");
950 
951     qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff");
952     qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff",
953                             "label", "GPIO Key Poweroff");
954     qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code",
955                           KEY_POWER);
956     qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff",
957                            "gpios", phandle, 3, 0);
958 }
959 
960 #define SECURE_GPIO_POWEROFF 0
961 #define SECURE_GPIO_RESET    1
962 
963 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev,
964                                    uint32_t phandle)
965 {
966     DeviceState *gpio_pwr_dev;
967 
968     /* gpio-pwr */
969     gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL);
970 
971     /* connect secure pl061 to gpio-pwr */
972     qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET,
973                           qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0));
974     qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF,
975                           qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0));
976 
977     qemu_fdt_add_subnode(fdt, "/gpio-poweroff");
978     qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible",
979                             "gpio-poweroff");
980     qemu_fdt_setprop_cells(fdt, "/gpio-poweroff",
981                            "gpios", phandle, SECURE_GPIO_POWEROFF, 0);
982     qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled");
983     qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status",
984                             "okay");
985 
986     qemu_fdt_add_subnode(fdt, "/gpio-restart");
987     qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible",
988                             "gpio-restart");
989     qemu_fdt_setprop_cells(fdt, "/gpio-restart",
990                            "gpios", phandle, SECURE_GPIO_RESET, 0);
991     qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled");
992     qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status",
993                             "okay");
994 }
995 
996 static void create_gpio_devices(const VirtMachineState *vms, int gpio,
997                                 MemoryRegion *mem)
998 {
999     char *nodename;
1000     DeviceState *pl061_dev;
1001     hwaddr base = vms->memmap[gpio].base;
1002     hwaddr size = vms->memmap[gpio].size;
1003     int irq = vms->irqmap[gpio];
1004     const char compat[] = "arm,pl061\0arm,primecell";
1005     SysBusDevice *s;
1006     MachineState *ms = MACHINE(vms);
1007 
1008     pl061_dev = qdev_new("pl061");
1009     /* Pull lines down to 0 if not driven by the PL061 */
1010     qdev_prop_set_uint32(pl061_dev, "pullups", 0);
1011     qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff);
1012     s = SYS_BUS_DEVICE(pl061_dev);
1013     sysbus_realize_and_unref(s, &error_fatal);
1014     memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
1015     sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
1016 
1017     uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt);
1018     nodename = g_strdup_printf("/pl061@%" PRIx64, base);
1019     qemu_fdt_add_subnode(ms->fdt, nodename);
1020     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1021                                  2, base, 2, size);
1022     qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
1023     qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2);
1024     qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0);
1025     qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1026                            GIC_FDT_IRQ_TYPE_SPI, irq,
1027                            GIC_FDT_IRQ_FLAGS_LEVEL_HI);
1028     qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
1029     qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
1030     qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle);
1031 
1032     if (gpio != VIRT_GPIO) {
1033         /* Mark as not usable by the normal world */
1034         qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1035         qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1036     }
1037     g_free(nodename);
1038 
1039     /* Child gpio devices */
1040     if (gpio == VIRT_GPIO) {
1041         create_gpio_keys(ms->fdt, pl061_dev, phandle);
1042     } else {
1043         create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle);
1044     }
1045 }
1046 
1047 static void create_virtio_devices(const VirtMachineState *vms)
1048 {
1049     int i;
1050     hwaddr size = vms->memmap[VIRT_MMIO].size;
1051     MachineState *ms = MACHINE(vms);
1052 
1053     /* We create the transports in forwards order. Since qbus_realize()
1054      * prepends (not appends) new child buses, the incrementing loop below will
1055      * create a list of virtio-mmio buses with decreasing base addresses.
1056      *
1057      * When a -device option is processed from the command line,
1058      * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1059      * order. The upshot is that -device options in increasing command line
1060      * order are mapped to virtio-mmio buses with decreasing base addresses.
1061      *
1062      * When this code was originally written, that arrangement ensured that the
1063      * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
1064      * the first -device on the command line. (The end-to-end order is a
1065      * function of this loop, qbus_realize(), qbus_find_recursive(), and the
1066      * guest kernel's name-to-address assignment strategy.)
1067      *
1068      * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
1069      * the message, if not necessarily the code, of commit 70161ff336.
1070      * Therefore the loop now establishes the inverse of the original intent.
1071      *
1072      * Unfortunately, we can't counteract the kernel change by reversing the
1073      * loop; it would break existing command lines.
1074      *
1075      * In any case, the kernel makes no guarantee about the stability of
1076      * enumeration order of virtio devices (as demonstrated by it changing
1077      * between kernel versions). For reliable and stable identification
1078      * of disks users must use UUIDs or similar mechanisms.
1079      */
1080     for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
1081         int irq = vms->irqmap[VIRT_MMIO] + i;
1082         hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1083 
1084         sysbus_create_simple("virtio-mmio", base,
1085                              qdev_get_gpio_in(vms->gic, irq));
1086     }
1087 
1088     /* We add dtb nodes in reverse order so that they appear in the finished
1089      * device tree lowest address first.
1090      *
1091      * Note that this mapping is independent of the loop above. The previous
1092      * loop influences virtio device to virtio transport assignment, whereas
1093      * this loop controls how virtio transports are laid out in the dtb.
1094      */
1095     for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
1096         char *nodename;
1097         int irq = vms->irqmap[VIRT_MMIO] + i;
1098         hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1099 
1100         nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
1101         qemu_fdt_add_subnode(ms->fdt, nodename);
1102         qemu_fdt_setprop_string(ms->fdt, nodename,
1103                                 "compatible", "virtio,mmio");
1104         qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1105                                      2, base, 2, size);
1106         qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1107                                GIC_FDT_IRQ_TYPE_SPI, irq,
1108                                GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1109         qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1110         g_free(nodename);
1111     }
1112 }
1113 
1114 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1115 
1116 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
1117                                         const char *name,
1118                                         const char *alias_prop_name)
1119 {
1120     /*
1121      * Create a single flash device.  We use the same parameters as
1122      * the flash devices on the Versatile Express board.
1123      */
1124     DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
1125 
1126     qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
1127     qdev_prop_set_uint8(dev, "width", 4);
1128     qdev_prop_set_uint8(dev, "device-width", 2);
1129     qdev_prop_set_bit(dev, "big-endian", false);
1130     qdev_prop_set_uint16(dev, "id0", 0x89);
1131     qdev_prop_set_uint16(dev, "id1", 0x18);
1132     qdev_prop_set_uint16(dev, "id2", 0x00);
1133     qdev_prop_set_uint16(dev, "id3", 0x00);
1134     qdev_prop_set_string(dev, "name", name);
1135     object_property_add_child(OBJECT(vms), name, OBJECT(dev));
1136     object_property_add_alias(OBJECT(vms), alias_prop_name,
1137                               OBJECT(dev), "drive");
1138     return PFLASH_CFI01(dev);
1139 }
1140 
1141 static void virt_flash_create(VirtMachineState *vms)
1142 {
1143     vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
1144     vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
1145 }
1146 
1147 static void virt_flash_map1(PFlashCFI01 *flash,
1148                             hwaddr base, hwaddr size,
1149                             MemoryRegion *sysmem)
1150 {
1151     DeviceState *dev = DEVICE(flash);
1152 
1153     assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
1154     assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
1155     qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
1156     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1157 
1158     memory_region_add_subregion(sysmem, base,
1159                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
1160                                                        0));
1161 }
1162 
1163 static void virt_flash_map(VirtMachineState *vms,
1164                            MemoryRegion *sysmem,
1165                            MemoryRegion *secure_sysmem)
1166 {
1167     /*
1168      * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1169      * sysmem is the system memory space. secure_sysmem is the secure view
1170      * of the system, and the first flash device should be made visible only
1171      * there. The second flash device is visible to both secure and nonsecure.
1172      * If sysmem == secure_sysmem this means there is no separate Secure
1173      * address space and both flash devices are generally visible.
1174      */
1175     hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1176     hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1177 
1178     virt_flash_map1(vms->flash[0], flashbase, flashsize,
1179                     secure_sysmem);
1180     virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
1181                     sysmem);
1182 }
1183 
1184 static void virt_flash_fdt(VirtMachineState *vms,
1185                            MemoryRegion *sysmem,
1186                            MemoryRegion *secure_sysmem)
1187 {
1188     hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1189     hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1190     MachineState *ms = MACHINE(vms);
1191     char *nodename;
1192 
1193     if (sysmem == secure_sysmem) {
1194         /* Report both flash devices as a single node in the DT */
1195         nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1196         qemu_fdt_add_subnode(ms->fdt, nodename);
1197         qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1198         qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1199                                      2, flashbase, 2, flashsize,
1200                                      2, flashbase + flashsize, 2, flashsize);
1201         qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1202         g_free(nodename);
1203     } else {
1204         /*
1205          * Report the devices as separate nodes so we can mark one as
1206          * only visible to the secure world.
1207          */
1208         nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
1209         qemu_fdt_add_subnode(ms->fdt, nodename);
1210         qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1211         qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1212                                      2, flashbase, 2, flashsize);
1213         qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1214         qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1215         qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1216         g_free(nodename);
1217 
1218         nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize);
1219         qemu_fdt_add_subnode(ms->fdt, nodename);
1220         qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1221         qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1222                                      2, flashbase + flashsize, 2, flashsize);
1223         qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1224         g_free(nodename);
1225     }
1226 }
1227 
1228 static bool virt_firmware_init(VirtMachineState *vms,
1229                                MemoryRegion *sysmem,
1230                                MemoryRegion *secure_sysmem)
1231 {
1232     int i;
1233     const char *bios_name;
1234     BlockBackend *pflash_blk0;
1235 
1236     /* Map legacy -drive if=pflash to machine properties */
1237     for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1238         pflash_cfi01_legacy_drive(vms->flash[i],
1239                                   drive_get(IF_PFLASH, 0, i));
1240     }
1241 
1242     virt_flash_map(vms, sysmem, secure_sysmem);
1243 
1244     pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1245 
1246     bios_name = MACHINE(vms)->firmware;
1247     if (bios_name) {
1248         char *fname;
1249         MemoryRegion *mr;
1250         int image_size;
1251 
1252         if (pflash_blk0) {
1253             error_report("The contents of the first flash device may be "
1254                          "specified with -bios or with -drive if=pflash... "
1255                          "but you cannot use both options at once");
1256             exit(1);
1257         }
1258 
1259         /* Fall back to -bios */
1260 
1261         fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1262         if (!fname) {
1263             error_report("Could not find ROM image '%s'", bios_name);
1264             exit(1);
1265         }
1266         mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1267         image_size = load_image_mr(fname, mr);
1268         g_free(fname);
1269         if (image_size < 0) {
1270             error_report("Could not load ROM image '%s'", bios_name);
1271             exit(1);
1272         }
1273     }
1274 
1275     return pflash_blk0 || bios_name;
1276 }
1277 
1278 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
1279 {
1280     MachineState *ms = MACHINE(vms);
1281     hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1282     hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1283     FWCfgState *fw_cfg;
1284     char *nodename;
1285 
1286     fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
1287     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1288 
1289     nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1290     qemu_fdt_add_subnode(ms->fdt, nodename);
1291     qemu_fdt_setprop_string(ms->fdt, nodename,
1292                             "compatible", "qemu,fw-cfg-mmio");
1293     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1294                                  2, base, 2, size);
1295     qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1296     g_free(nodename);
1297     return fw_cfg;
1298 }
1299 
1300 static void create_pcie_irq_map(const MachineState *ms,
1301                                 uint32_t gic_phandle,
1302                                 int first_irq, const char *nodename)
1303 {
1304     int devfn, pin;
1305     uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1306     uint32_t *irq_map = full_irq_map;
1307 
1308     for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1309         for (pin = 0; pin < 4; pin++) {
1310             int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1311             int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1312             int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1313             int i;
1314 
1315             uint32_t map[] = {
1316                 devfn << 8, 0, 0,                           /* devfn */
1317                 pin + 1,                                    /* PCI pin */
1318                 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */
1319 
1320             /* Convert map to big endian */
1321             for (i = 0; i < 10; i++) {
1322                 irq_map[i] = cpu_to_be32(map[i]);
1323             }
1324             irq_map += 10;
1325         }
1326     }
1327 
1328     qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map",
1329                      full_irq_map, sizeof(full_irq_map));
1330 
1331     qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
1332                            cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1333                            0, 0,
1334                            0x7           /* PCI irq */);
1335 }
1336 
1337 static void create_smmu(const VirtMachineState *vms,
1338                         PCIBus *bus)
1339 {
1340     char *node;
1341     const char compat[] = "arm,smmu-v3";
1342     int irq =  vms->irqmap[VIRT_SMMU];
1343     int i;
1344     hwaddr base = vms->memmap[VIRT_SMMU].base;
1345     hwaddr size = vms->memmap[VIRT_SMMU].size;
1346     const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1347     DeviceState *dev;
1348     MachineState *ms = MACHINE(vms);
1349 
1350     if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1351         return;
1352     }
1353 
1354     dev = qdev_new(TYPE_ARM_SMMUV3);
1355 
1356     object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
1357                              &error_abort);
1358     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1359     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1360     for (i = 0; i < NUM_SMMU_IRQS; i++) {
1361         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1362                            qdev_get_gpio_in(vms->gic, irq + i));
1363     }
1364 
1365     node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1366     qemu_fdt_add_subnode(ms->fdt, node);
1367     qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1368     qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size);
1369 
1370     qemu_fdt_setprop_cells(ms->fdt, node, "interrupts",
1371             GIC_FDT_IRQ_TYPE_SPI, irq    , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1372             GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1373             GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1374             GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1375 
1376     qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
1377                      sizeof(irq_names));
1378 
1379     qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
1380 
1381     qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1382 
1383     qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1384     g_free(node);
1385 }
1386 
1387 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms)
1388 {
1389     const char compat[] = "virtio,pci-iommu\0pci1af4,1057";
1390     uint16_t bdf = vms->virtio_iommu_bdf;
1391     MachineState *ms = MACHINE(vms);
1392     char *node;
1393 
1394     vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1395 
1396     node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename,
1397                            PCI_SLOT(bdf), PCI_FUNC(bdf));
1398     qemu_fdt_add_subnode(ms->fdt, node);
1399     qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1400     qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg",
1401                                  1, bdf << 8, 1, 0, 1, 0,
1402                                  1, 0, 1, 0);
1403 
1404     qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1405     qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1406     g_free(node);
1407 
1408     qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map",
1409                            0x0, vms->iommu_phandle, 0x0, bdf,
1410                            bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf);
1411 }
1412 
1413 static void create_pcie(VirtMachineState *vms)
1414 {
1415     hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1416     hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1417     hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1418     hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1419     hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1420     hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1421     hwaddr base_ecam, size_ecam;
1422     hwaddr base = base_mmio;
1423     int nr_pcie_buses;
1424     int irq = vms->irqmap[VIRT_PCIE];
1425     MemoryRegion *mmio_alias;
1426     MemoryRegion *mmio_reg;
1427     MemoryRegion *ecam_alias;
1428     MemoryRegion *ecam_reg;
1429     DeviceState *dev;
1430     char *nodename;
1431     int i, ecam_id;
1432     PCIHostState *pci;
1433     MachineState *ms = MACHINE(vms);
1434     MachineClass *mc = MACHINE_GET_CLASS(ms);
1435 
1436     dev = qdev_new(TYPE_GPEX_HOST);
1437     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1438 
1439     ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1440     base_ecam = vms->memmap[ecam_id].base;
1441     size_ecam = vms->memmap[ecam_id].size;
1442     nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1443     /* Map only the first size_ecam bytes of ECAM space */
1444     ecam_alias = g_new0(MemoryRegion, 1);
1445     ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1446     memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1447                              ecam_reg, 0, size_ecam);
1448     memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1449 
1450     /* Map the MMIO window into system address space so as to expose
1451      * the section of PCI MMIO space which starts at the same base address
1452      * (ie 1:1 mapping for that part of PCI MMIO space visible through
1453      * the window).
1454      */
1455     mmio_alias = g_new0(MemoryRegion, 1);
1456     mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1457     memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1458                              mmio_reg, base_mmio, size_mmio);
1459     memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1460 
1461     if (vms->highmem_mmio) {
1462         /* Map high MMIO space */
1463         MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1464 
1465         memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1466                                  mmio_reg, base_mmio_high, size_mmio_high);
1467         memory_region_add_subregion(get_system_memory(), base_mmio_high,
1468                                     high_mmio_alias);
1469     }
1470 
1471     /* Map IO port space */
1472     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1473 
1474     for (i = 0; i < GPEX_NUM_IRQS; i++) {
1475         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1476                            qdev_get_gpio_in(vms->gic, irq + i));
1477         gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1478     }
1479 
1480     pci = PCI_HOST_BRIDGE(dev);
1481     pci->bypass_iommu = vms->default_bus_bypass_iommu;
1482     vms->bus = pci->bus;
1483     if (vms->bus) {
1484         for (i = 0; i < nb_nics; i++) {
1485             pci_nic_init_nofail(&nd_table[i], pci->bus, mc->default_nic, NULL);
1486         }
1487     }
1488 
1489     nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1490     qemu_fdt_add_subnode(ms->fdt, nodename);
1491     qemu_fdt_setprop_string(ms->fdt, nodename,
1492                             "compatible", "pci-host-ecam-generic");
1493     qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");
1494     qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);
1495     qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
1496     qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
1497     qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
1498                            nr_pcie_buses - 1);
1499     qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1500 
1501     if (vms->msi_phandle) {
1502         qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
1503                                0, vms->msi_phandle, 0, 0x10000);
1504     }
1505 
1506     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1507                                  2, base_ecam, 2, size_ecam);
1508 
1509     if (vms->highmem_mmio) {
1510         qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1511                                      1, FDT_PCI_RANGE_IOPORT, 2, 0,
1512                                      2, base_pio, 2, size_pio,
1513                                      1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1514                                      2, base_mmio, 2, size_mmio,
1515                                      1, FDT_PCI_RANGE_MMIO_64BIT,
1516                                      2, base_mmio_high,
1517                                      2, base_mmio_high, 2, size_mmio_high);
1518     } else {
1519         qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1520                                      1, FDT_PCI_RANGE_IOPORT, 2, 0,
1521                                      2, base_pio, 2, size_pio,
1522                                      1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1523                                      2, base_mmio, 2, size_mmio);
1524     }
1525 
1526     qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
1527     create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename);
1528 
1529     if (vms->iommu) {
1530         vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1531 
1532         switch (vms->iommu) {
1533         case VIRT_IOMMU_SMMUV3:
1534             create_smmu(vms, vms->bus);
1535             qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map",
1536                                    0x0, vms->iommu_phandle, 0x0, 0x10000);
1537             break;
1538         default:
1539             g_assert_not_reached();
1540         }
1541     }
1542 }
1543 
1544 static void create_platform_bus(VirtMachineState *vms)
1545 {
1546     DeviceState *dev;
1547     SysBusDevice *s;
1548     int i;
1549     MemoryRegion *sysmem = get_system_memory();
1550 
1551     dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1552     dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1553     qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1554     qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1555     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1556     vms->platform_bus_dev = dev;
1557 
1558     s = SYS_BUS_DEVICE(dev);
1559     for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1560         int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1561         sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq));
1562     }
1563 
1564     memory_region_add_subregion(sysmem,
1565                                 vms->memmap[VIRT_PLATFORM_BUS].base,
1566                                 sysbus_mmio_get_region(s, 0));
1567 }
1568 
1569 static void create_tag_ram(MemoryRegion *tag_sysmem,
1570                            hwaddr base, hwaddr size,
1571                            const char *name)
1572 {
1573     MemoryRegion *tagram = g_new(MemoryRegion, 1);
1574 
1575     memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal);
1576     memory_region_add_subregion(tag_sysmem, base / 32, tagram);
1577 }
1578 
1579 static void create_secure_ram(VirtMachineState *vms,
1580                               MemoryRegion *secure_sysmem,
1581                               MemoryRegion *secure_tag_sysmem)
1582 {
1583     MemoryRegion *secram = g_new(MemoryRegion, 1);
1584     char *nodename;
1585     hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1586     hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1587     MachineState *ms = MACHINE(vms);
1588 
1589     memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1590                            &error_fatal);
1591     memory_region_add_subregion(secure_sysmem, base, secram);
1592 
1593     nodename = g_strdup_printf("/secram@%" PRIx64, base);
1594     qemu_fdt_add_subnode(ms->fdt, nodename);
1595     qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
1596     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
1597     qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1598     qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1599 
1600     if (secure_tag_sysmem) {
1601         create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag");
1602     }
1603 
1604     g_free(nodename);
1605 }
1606 
1607 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1608 {
1609     const VirtMachineState *board = container_of(binfo, VirtMachineState,
1610                                                  bootinfo);
1611     MachineState *ms = MACHINE(board);
1612 
1613 
1614     *fdt_size = board->fdt_size;
1615     return ms->fdt;
1616 }
1617 
1618 static void virt_build_smbios(VirtMachineState *vms)
1619 {
1620     MachineClass *mc = MACHINE_GET_CLASS(vms);
1621     MachineState *ms = MACHINE(vms);
1622     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1623     uint8_t *smbios_tables, *smbios_anchor;
1624     size_t smbios_tables_len, smbios_anchor_len;
1625     struct smbios_phys_mem_area mem_array;
1626     const char *product = "QEMU Virtual Machine";
1627 
1628     if (kvm_enabled()) {
1629         product = "KVM Virtual Machine";
1630     }
1631 
1632     smbios_set_defaults("QEMU", product,
1633                         vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
1634                         true, SMBIOS_ENTRY_POINT_TYPE_64);
1635 
1636     /* build the array of physical mem area from base_memmap */
1637     mem_array.address = vms->memmap[VIRT_MEM].base;
1638     mem_array.length = ms->ram_size;
1639 
1640     smbios_get_tables(ms, &mem_array, 1,
1641                       &smbios_tables, &smbios_tables_len,
1642                       &smbios_anchor, &smbios_anchor_len,
1643                       &error_fatal);
1644 
1645     if (smbios_anchor) {
1646         fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1647                         smbios_tables, smbios_tables_len);
1648         fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1649                         smbios_anchor, smbios_anchor_len);
1650     }
1651 }
1652 
1653 static
1654 void virt_machine_done(Notifier *notifier, void *data)
1655 {
1656     VirtMachineState *vms = container_of(notifier, VirtMachineState,
1657                                          machine_done);
1658     MachineState *ms = MACHINE(vms);
1659     ARMCPU *cpu = ARM_CPU(first_cpu);
1660     struct arm_boot_info *info = &vms->bootinfo;
1661     AddressSpace *as = arm_boot_address_space(cpu, info);
1662 
1663     /*
1664      * If the user provided a dtb, we assume the dynamic sysbus nodes
1665      * already are integrated there. This corresponds to a use case where
1666      * the dynamic sysbus nodes are complex and their generation is not yet
1667      * supported. In that case the user can take charge of the guest dt
1668      * while qemu takes charge of the qom stuff.
1669      */
1670     if (info->dtb_filename == NULL) {
1671         platform_bus_add_all_fdt_nodes(ms->fdt, "/intc",
1672                                        vms->memmap[VIRT_PLATFORM_BUS].base,
1673                                        vms->memmap[VIRT_PLATFORM_BUS].size,
1674                                        vms->irqmap[VIRT_PLATFORM_BUS]);
1675     }
1676     if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
1677         exit(1);
1678     }
1679 
1680     fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg);
1681 
1682     virt_acpi_setup(vms);
1683     virt_build_smbios(vms);
1684 }
1685 
1686 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1687 {
1688     uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1689     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1690 
1691     if (!vmc->disallow_affinity_adjustment) {
1692         /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1693          * GIC's target-list limitations. 32-bit KVM hosts currently
1694          * always create clusters of 4 CPUs, but that is expected to
1695          * change when they gain support for gicv3. When KVM is enabled
1696          * it will override the changes we make here, therefore our
1697          * purposes are to make TCG consistent (with 64-bit KVM hosts)
1698          * and to improve SGI efficiency.
1699          */
1700         if (vms->gic_version == VIRT_GIC_VERSION_2) {
1701             clustersz = GIC_TARGETLIST_BITS;
1702         } else {
1703             clustersz = GICV3_TARGETLIST_BITS;
1704         }
1705     }
1706     return arm_cpu_mp_affinity(idx, clustersz);
1707 }
1708 
1709 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms,
1710                                                  int index)
1711 {
1712     bool *enabled_array[] = {
1713         &vms->highmem_redists,
1714         &vms->highmem_ecam,
1715         &vms->highmem_mmio,
1716     };
1717 
1718     assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST ==
1719            ARRAY_SIZE(enabled_array));
1720     assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array));
1721 
1722     return enabled_array[index - VIRT_LOWMEMMAP_LAST];
1723 }
1724 
1725 static void virt_set_high_memmap(VirtMachineState *vms,
1726                                  hwaddr base, int pa_bits)
1727 {
1728     hwaddr region_base, region_size;
1729     bool *region_enabled, fits;
1730     int i;
1731 
1732     for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1733         region_enabled = virt_get_high_memmap_enabled(vms, i);
1734         region_base = ROUND_UP(base, extended_memmap[i].size);
1735         region_size = extended_memmap[i].size;
1736 
1737         vms->memmap[i].base = region_base;
1738         vms->memmap[i].size = region_size;
1739 
1740         /*
1741          * Check each device to see if it fits in the PA space,
1742          * moving highest_gpa as we go. For compatibility, move
1743          * highest_gpa for disabled fitting devices as well, if
1744          * the compact layout has been disabled.
1745          *
1746          * For each device that doesn't fit, disable it.
1747          */
1748         fits = (region_base + region_size) <= BIT_ULL(pa_bits);
1749         *region_enabled &= fits;
1750         if (vms->highmem_compact && !*region_enabled) {
1751             continue;
1752         }
1753 
1754         base = region_base + region_size;
1755         if (fits) {
1756             vms->highest_gpa = base - 1;
1757         }
1758     }
1759 }
1760 
1761 static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
1762 {
1763     MachineState *ms = MACHINE(vms);
1764     hwaddr base, device_memory_base, device_memory_size, memtop;
1765     int i;
1766 
1767     vms->memmap = extended_memmap;
1768 
1769     for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1770         vms->memmap[i] = base_memmap[i];
1771     }
1772 
1773     if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1774         error_report("unsupported number of memory slots: %"PRIu64,
1775                      ms->ram_slots);
1776         exit(EXIT_FAILURE);
1777     }
1778 
1779     /*
1780      * !highmem is exactly the same as limiting the PA space to 32bit,
1781      * irrespective of the underlying capabilities of the HW.
1782      */
1783     if (!vms->highmem) {
1784         pa_bits = 32;
1785     }
1786 
1787     /*
1788      * We compute the base of the high IO region depending on the
1789      * amount of initial and device memory. The device memory start/size
1790      * is aligned on 1GiB. We never put the high IO region below 256GiB
1791      * so that if maxram_size is < 255GiB we keep the legacy memory map.
1792      * The device region size assumes 1GiB page max alignment per slot.
1793      */
1794     device_memory_base =
1795         ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1796     device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1797 
1798     /* Base address of the high IO region */
1799     memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1800     if (memtop > BIT_ULL(pa_bits)) {
1801 	    error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n",
1802 			 pa_bits, memtop - BIT_ULL(pa_bits));
1803         exit(EXIT_FAILURE);
1804     }
1805     if (base < device_memory_base) {
1806         error_report("maxmem/slots too huge");
1807         exit(EXIT_FAILURE);
1808     }
1809     if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1810         base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1811     }
1812 
1813     /* We know for sure that at least the memory fits in the PA space */
1814     vms->highest_gpa = memtop - 1;
1815 
1816     virt_set_high_memmap(vms, base, pa_bits);
1817 
1818     if (device_memory_size > 0) {
1819         machine_memory_devices_init(ms, device_memory_base, device_memory_size);
1820     }
1821 }
1822 
1823 static VirtGICType finalize_gic_version_do(const char *accel_name,
1824                                            VirtGICType gic_version,
1825                                            int gics_supported,
1826                                            unsigned int max_cpus)
1827 {
1828     /* Convert host/max/nosel to GIC version number */
1829     switch (gic_version) {
1830     case VIRT_GIC_VERSION_HOST:
1831         if (!kvm_enabled()) {
1832             error_report("gic-version=host requires KVM");
1833             exit(1);
1834         }
1835 
1836         /* For KVM, gic-version=host means gic-version=max */
1837         return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX,
1838                                        gics_supported, max_cpus);
1839     case VIRT_GIC_VERSION_MAX:
1840         if (gics_supported & VIRT_GIC_VERSION_4_MASK) {
1841             gic_version = VIRT_GIC_VERSION_4;
1842         } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
1843             gic_version = VIRT_GIC_VERSION_3;
1844         } else {
1845             gic_version = VIRT_GIC_VERSION_2;
1846         }
1847         break;
1848     case VIRT_GIC_VERSION_NOSEL:
1849         if ((gics_supported & VIRT_GIC_VERSION_2_MASK) &&
1850             max_cpus <= GIC_NCPU) {
1851             gic_version = VIRT_GIC_VERSION_2;
1852         } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
1853             /*
1854              * in case the host does not support v2 emulation or
1855              * the end-user requested more than 8 VCPUs we now default
1856              * to v3. In any case defaulting to v2 would be broken.
1857              */
1858             gic_version = VIRT_GIC_VERSION_3;
1859         } else if (max_cpus > GIC_NCPU) {
1860             error_report("%s only supports GICv2 emulation but more than 8 "
1861                          "vcpus are requested", accel_name);
1862             exit(1);
1863         }
1864         break;
1865     case VIRT_GIC_VERSION_2:
1866     case VIRT_GIC_VERSION_3:
1867     case VIRT_GIC_VERSION_4:
1868         break;
1869     }
1870 
1871     /* Check chosen version is effectively supported */
1872     switch (gic_version) {
1873     case VIRT_GIC_VERSION_2:
1874         if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) {
1875             error_report("%s does not support GICv2 emulation", accel_name);
1876             exit(1);
1877         }
1878         break;
1879     case VIRT_GIC_VERSION_3:
1880         if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) {
1881             error_report("%s does not support GICv3 emulation", accel_name);
1882             exit(1);
1883         }
1884         break;
1885     case VIRT_GIC_VERSION_4:
1886         if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) {
1887             error_report("%s does not support GICv4 emulation, is virtualization=on?",
1888                          accel_name);
1889             exit(1);
1890         }
1891         break;
1892     default:
1893         error_report("logic error in finalize_gic_version");
1894         exit(1);
1895         break;
1896     }
1897 
1898     return gic_version;
1899 }
1900 
1901 /*
1902  * finalize_gic_version - Determines the final gic_version
1903  * according to the gic-version property
1904  *
1905  * Default GIC type is v2
1906  */
1907 static void finalize_gic_version(VirtMachineState *vms)
1908 {
1909     const char *accel_name = current_accel_name();
1910     unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
1911     int gics_supported = 0;
1912 
1913     /* Determine which GIC versions the current environment supports */
1914     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
1915         int probe_bitmap = kvm_arm_vgic_probe();
1916 
1917         if (!probe_bitmap) {
1918             error_report("Unable to determine GIC version supported by host");
1919             exit(1);
1920         }
1921 
1922         if (probe_bitmap & KVM_ARM_VGIC_V2) {
1923             gics_supported |= VIRT_GIC_VERSION_2_MASK;
1924         }
1925         if (probe_bitmap & KVM_ARM_VGIC_V3) {
1926             gics_supported |= VIRT_GIC_VERSION_3_MASK;
1927         }
1928     } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
1929         /* KVM w/o kernel irqchip can only deal with GICv2 */
1930         gics_supported |= VIRT_GIC_VERSION_2_MASK;
1931         accel_name = "KVM with kernel-irqchip=off";
1932     } else if (tcg_enabled() || hvf_enabled() || qtest_enabled())  {
1933         gics_supported |= VIRT_GIC_VERSION_2_MASK;
1934         if (module_object_class_by_name("arm-gicv3")) {
1935             gics_supported |= VIRT_GIC_VERSION_3_MASK;
1936             if (vms->virt) {
1937                 /* GICv4 only makes sense if CPU has EL2 */
1938                 gics_supported |= VIRT_GIC_VERSION_4_MASK;
1939             }
1940         }
1941     } else {
1942         error_report("Unsupported accelerator, can not determine GIC support");
1943         exit(1);
1944     }
1945 
1946     /*
1947      * Then convert helpers like host/max to concrete GIC versions and ensure
1948      * the desired version is supported
1949      */
1950     vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version,
1951                                                gics_supported, max_cpus);
1952 }
1953 
1954 /*
1955  * virt_cpu_post_init() must be called after the CPUs have
1956  * been realized and the GIC has been created.
1957  */
1958 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
1959 {
1960     int max_cpus = MACHINE(vms)->smp.max_cpus;
1961     bool aarch64, pmu, steal_time;
1962     CPUState *cpu;
1963 
1964     aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
1965     pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
1966     steal_time = object_property_get_bool(OBJECT(first_cpu),
1967                                           "kvm-steal-time", NULL);
1968 
1969     if (kvm_enabled()) {
1970         hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
1971         hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
1972 
1973         if (steal_time) {
1974             MemoryRegion *pvtime = g_new(MemoryRegion, 1);
1975             hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
1976 
1977             /* The memory region size must be a multiple of host page size. */
1978             pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
1979 
1980             if (pvtime_size > pvtime_reg_size) {
1981                 error_report("pvtime requires a %" HWADDR_PRId
1982                              " byte memory region for %d CPUs,"
1983                              " but only %" HWADDR_PRId " has been reserved",
1984                              pvtime_size, max_cpus, pvtime_reg_size);
1985                 exit(1);
1986             }
1987 
1988             memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL);
1989             memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
1990         }
1991 
1992         CPU_FOREACH(cpu) {
1993             if (pmu) {
1994                 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
1995                 if (kvm_irqchip_in_kernel()) {
1996                     kvm_arm_pmu_set_irq(cpu, VIRTUAL_PMU_IRQ);
1997                 }
1998                 kvm_arm_pmu_init(cpu);
1999             }
2000             if (steal_time) {
2001                 kvm_arm_pvtime_init(cpu, pvtime_reg_base +
2002                                          cpu->cpu_index * PVTIME_SIZE_PER_CPU);
2003             }
2004         }
2005     } else {
2006         if (aarch64 && vms->highmem) {
2007             int requested_pa_size = 64 - clz64(vms->highest_gpa);
2008             int pamax = arm_pamax(ARM_CPU(first_cpu));
2009 
2010             if (pamax < requested_pa_size) {
2011                 error_report("VCPU supports less PA bits (%d) than "
2012                              "requested by the memory map (%d)",
2013                              pamax, requested_pa_size);
2014                 exit(1);
2015             }
2016         }
2017     }
2018 }
2019 
2020 static void machvirt_init(MachineState *machine)
2021 {
2022     VirtMachineState *vms = VIRT_MACHINE(machine);
2023     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
2024     MachineClass *mc = MACHINE_GET_CLASS(machine);
2025     const CPUArchIdList *possible_cpus;
2026     MemoryRegion *sysmem = get_system_memory();
2027     MemoryRegion *secure_sysmem = NULL;
2028     MemoryRegion *tag_sysmem = NULL;
2029     MemoryRegion *secure_tag_sysmem = NULL;
2030     int n, virt_max_cpus;
2031     bool firmware_loaded;
2032     bool aarch64 = true;
2033     bool has_ged = !vmc->no_ged;
2034     unsigned int smp_cpus = machine->smp.cpus;
2035     unsigned int max_cpus = machine->smp.max_cpus;
2036 
2037     if (!cpu_type_valid(machine->cpu_type)) {
2038         error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
2039         exit(1);
2040     }
2041 
2042     possible_cpus = mc->possible_cpu_arch_ids(machine);
2043 
2044     /*
2045      * In accelerated mode, the memory map is computed earlier in kvm_type()
2046      * to create a VM with the right number of IPA bits.
2047      */
2048     if (!vms->memmap) {
2049         Object *cpuobj;
2050         ARMCPU *armcpu;
2051         int pa_bits;
2052 
2053         /*
2054          * Instantiate a temporary CPU object to find out about what
2055          * we are about to deal with. Once this is done, get rid of
2056          * the object.
2057          */
2058         cpuobj = object_new(possible_cpus->cpus[0].type);
2059         armcpu = ARM_CPU(cpuobj);
2060 
2061         pa_bits = arm_pamax(armcpu);
2062 
2063         object_unref(cpuobj);
2064 
2065         virt_set_memmap(vms, pa_bits);
2066     }
2067 
2068     /* We can probe only here because during property set
2069      * KVM is not available yet
2070      */
2071     finalize_gic_version(vms);
2072 
2073     if (vms->secure) {
2074         /*
2075          * The Secure view of the world is the same as the NonSecure,
2076          * but with a few extra devices. Create it as a container region
2077          * containing the system memory at low priority; any secure-only
2078          * devices go in at higher priority and take precedence.
2079          */
2080         secure_sysmem = g_new(MemoryRegion, 1);
2081         memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
2082                            UINT64_MAX);
2083         memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
2084     }
2085 
2086     firmware_loaded = virt_firmware_init(vms, sysmem,
2087                                          secure_sysmem ?: sysmem);
2088 
2089     /* If we have an EL3 boot ROM then the assumption is that it will
2090      * implement PSCI itself, so disable QEMU's internal implementation
2091      * so it doesn't get in the way. Instead of starting secondary
2092      * CPUs in PSCI powerdown state we will start them all running and
2093      * let the boot ROM sort them out.
2094      * The usual case is that we do use QEMU's PSCI implementation;
2095      * if the guest has EL2 then we will use SMC as the conduit,
2096      * and otherwise we will use HVC (for backwards compatibility and
2097      * because if we're using KVM then we must use HVC).
2098      */
2099     if (vms->secure && firmware_loaded) {
2100         vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
2101     } else if (vms->virt) {
2102         vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
2103     } else {
2104         vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
2105     }
2106 
2107     /*
2108      * The maximum number of CPUs depends on the GIC version, or on how
2109      * many redistributors we can fit into the memory map (which in turn
2110      * depends on whether this is a GICv3 or v4).
2111      */
2112     if (vms->gic_version == VIRT_GIC_VERSION_2) {
2113         virt_max_cpus = GIC_NCPU;
2114     } else {
2115         virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST);
2116         if (vms->highmem_redists) {
2117             virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
2118         }
2119     }
2120 
2121     if (max_cpus > virt_max_cpus) {
2122         error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
2123                      "supported by machine 'mach-virt' (%d)",
2124                      max_cpus, virt_max_cpus);
2125         if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) {
2126             error_printf("Try 'highmem-redists=on' for more CPUs\n");
2127         }
2128 
2129         exit(1);
2130     }
2131 
2132     if (vms->secure && (kvm_enabled() || hvf_enabled())) {
2133         error_report("mach-virt: %s does not support providing "
2134                      "Security extensions (TrustZone) to the guest CPU",
2135                      current_accel_name());
2136         exit(1);
2137     }
2138 
2139     if (vms->virt && (kvm_enabled() || hvf_enabled())) {
2140         error_report("mach-virt: %s does not support providing "
2141                      "Virtualization extensions to the guest CPU",
2142                      current_accel_name());
2143         exit(1);
2144     }
2145 
2146     if (vms->mte && (kvm_enabled() || hvf_enabled())) {
2147         error_report("mach-virt: %s does not support providing "
2148                      "MTE to the guest CPU",
2149                      current_accel_name());
2150         exit(1);
2151     }
2152 
2153     create_fdt(vms);
2154 
2155     assert(possible_cpus->len == max_cpus);
2156     for (n = 0; n < possible_cpus->len; n++) {
2157         Object *cpuobj;
2158         CPUState *cs;
2159 
2160         if (n >= smp_cpus) {
2161             break;
2162         }
2163 
2164         cpuobj = object_new(possible_cpus->cpus[n].type);
2165         object_property_set_int(cpuobj, "mp-affinity",
2166                                 possible_cpus->cpus[n].arch_id, NULL);
2167 
2168         cs = CPU(cpuobj);
2169         cs->cpu_index = n;
2170 
2171         numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
2172                           &error_fatal);
2173 
2174         aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
2175 
2176         if (!vms->secure) {
2177             object_property_set_bool(cpuobj, "has_el3", false, NULL);
2178         }
2179 
2180         if (!vms->virt && object_property_find(cpuobj, "has_el2")) {
2181             object_property_set_bool(cpuobj, "has_el2", false, NULL);
2182         }
2183 
2184         if (vmc->kvm_no_adjvtime &&
2185             object_property_find(cpuobj, "kvm-no-adjvtime")) {
2186             object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
2187         }
2188 
2189         if (vmc->no_kvm_steal_time &&
2190             object_property_find(cpuobj, "kvm-steal-time")) {
2191             object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
2192         }
2193 
2194         if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) {
2195             object_property_set_bool(cpuobj, "pmu", false, NULL);
2196         }
2197 
2198         if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) {
2199             object_property_set_bool(cpuobj, "lpa2", false, NULL);
2200         }
2201 
2202         if (object_property_find(cpuobj, "reset-cbar")) {
2203             object_property_set_int(cpuobj, "reset-cbar",
2204                                     vms->memmap[VIRT_CPUPERIPHS].base,
2205                                     &error_abort);
2206         }
2207 
2208         object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
2209                                  &error_abort);
2210         if (vms->secure) {
2211             object_property_set_link(cpuobj, "secure-memory",
2212                                      OBJECT(secure_sysmem), &error_abort);
2213         }
2214 
2215         if (vms->mte) {
2216             /* Create the memory region only once, but link to all cpus. */
2217             if (!tag_sysmem) {
2218                 /*
2219                  * The property exists only if MemTag is supported.
2220                  * If it is, we must allocate the ram to back that up.
2221                  */
2222                 if (!object_property_find(cpuobj, "tag-memory")) {
2223                     error_report("MTE requested, but not supported "
2224                                  "by the guest CPU");
2225                     exit(1);
2226                 }
2227 
2228                 tag_sysmem = g_new(MemoryRegion, 1);
2229                 memory_region_init(tag_sysmem, OBJECT(machine),
2230                                    "tag-memory", UINT64_MAX / 32);
2231 
2232                 if (vms->secure) {
2233                     secure_tag_sysmem = g_new(MemoryRegion, 1);
2234                     memory_region_init(secure_tag_sysmem, OBJECT(machine),
2235                                        "secure-tag-memory", UINT64_MAX / 32);
2236 
2237                     /* As with ram, secure-tag takes precedence over tag.  */
2238                     memory_region_add_subregion_overlap(secure_tag_sysmem, 0,
2239                                                         tag_sysmem, -1);
2240                 }
2241             }
2242 
2243             object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem),
2244                                      &error_abort);
2245             if (vms->secure) {
2246                 object_property_set_link(cpuobj, "secure-tag-memory",
2247                                          OBJECT(secure_tag_sysmem),
2248                                          &error_abort);
2249             }
2250         }
2251 
2252         qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
2253         object_unref(cpuobj);
2254     }
2255     fdt_add_timer_nodes(vms);
2256     fdt_add_cpu_nodes(vms);
2257 
2258     memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
2259                                 machine->ram);
2260 
2261     virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
2262 
2263     create_gic(vms, sysmem);
2264 
2265     virt_cpu_post_init(vms, sysmem);
2266 
2267     fdt_add_pmu_nodes(vms);
2268 
2269     create_uart(vms, VIRT_UART, sysmem, serial_hd(0));
2270 
2271     if (vms->secure) {
2272         create_secure_ram(vms, secure_sysmem, secure_tag_sysmem);
2273         create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
2274     }
2275 
2276     if (tag_sysmem) {
2277         create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base,
2278                        machine->ram_size, "mach-virt.tag");
2279     }
2280 
2281     vms->highmem_ecam &= (!firmware_loaded || aarch64);
2282 
2283     create_rtc(vms);
2284 
2285     create_pcie(vms);
2286 
2287     if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) {
2288         vms->acpi_dev = create_acpi_ged(vms);
2289     } else {
2290         create_gpio_devices(vms, VIRT_GPIO, sysmem);
2291     }
2292 
2293     if (vms->secure && !vmc->no_secure_gpio) {
2294         create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem);
2295     }
2296 
2297      /* connect powerdown request */
2298      vms->powerdown_notifier.notify = virt_powerdown_req;
2299      qemu_register_powerdown_notifier(&vms->powerdown_notifier);
2300 
2301     /* Create mmio transports, so the user can create virtio backends
2302      * (which will be automatically plugged in to the transports). If
2303      * no backend is created the transport will just sit harmlessly idle.
2304      */
2305     create_virtio_devices(vms);
2306 
2307     vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
2308     rom_set_fw(vms->fw_cfg);
2309 
2310     create_platform_bus(vms);
2311 
2312     if (machine->nvdimms_state->is_enabled) {
2313         const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = {
2314             .space_id = AML_AS_SYSTEM_MEMORY,
2315             .address = vms->memmap[VIRT_NVDIMM_ACPI].base,
2316             .bit_width = NVDIMM_ACPI_IO_LEN << 3
2317         };
2318 
2319         nvdimm_init_acpi_state(machine->nvdimms_state, sysmem,
2320                                arm_virt_nvdimm_acpi_dsmio,
2321                                vms->fw_cfg, OBJECT(vms));
2322     }
2323 
2324     vms->bootinfo.ram_size = machine->ram_size;
2325     vms->bootinfo.board_id = -1;
2326     vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
2327     vms->bootinfo.get_dtb = machvirt_dtb;
2328     vms->bootinfo.skip_dtb_autoload = true;
2329     vms->bootinfo.firmware_loaded = firmware_loaded;
2330     vms->bootinfo.psci_conduit = vms->psci_conduit;
2331     arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
2332 
2333     vms->machine_done.notify = virt_machine_done;
2334     qemu_add_machine_init_done_notifier(&vms->machine_done);
2335 }
2336 
2337 static bool virt_get_secure(Object *obj, Error **errp)
2338 {
2339     VirtMachineState *vms = VIRT_MACHINE(obj);
2340 
2341     return vms->secure;
2342 }
2343 
2344 static void virt_set_secure(Object *obj, bool value, Error **errp)
2345 {
2346     VirtMachineState *vms = VIRT_MACHINE(obj);
2347 
2348     vms->secure = value;
2349 }
2350 
2351 static bool virt_get_virt(Object *obj, Error **errp)
2352 {
2353     VirtMachineState *vms = VIRT_MACHINE(obj);
2354 
2355     return vms->virt;
2356 }
2357 
2358 static void virt_set_virt(Object *obj, bool value, Error **errp)
2359 {
2360     VirtMachineState *vms = VIRT_MACHINE(obj);
2361 
2362     vms->virt = value;
2363 }
2364 
2365 static bool virt_get_highmem(Object *obj, Error **errp)
2366 {
2367     VirtMachineState *vms = VIRT_MACHINE(obj);
2368 
2369     return vms->highmem;
2370 }
2371 
2372 static void virt_set_highmem(Object *obj, bool value, Error **errp)
2373 {
2374     VirtMachineState *vms = VIRT_MACHINE(obj);
2375 
2376     vms->highmem = value;
2377 }
2378 
2379 static bool virt_get_compact_highmem(Object *obj, Error **errp)
2380 {
2381     VirtMachineState *vms = VIRT_MACHINE(obj);
2382 
2383     return vms->highmem_compact;
2384 }
2385 
2386 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp)
2387 {
2388     VirtMachineState *vms = VIRT_MACHINE(obj);
2389 
2390     vms->highmem_compact = value;
2391 }
2392 
2393 static bool virt_get_highmem_redists(Object *obj, Error **errp)
2394 {
2395     VirtMachineState *vms = VIRT_MACHINE(obj);
2396 
2397     return vms->highmem_redists;
2398 }
2399 
2400 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp)
2401 {
2402     VirtMachineState *vms = VIRT_MACHINE(obj);
2403 
2404     vms->highmem_redists = value;
2405 }
2406 
2407 static bool virt_get_highmem_ecam(Object *obj, Error **errp)
2408 {
2409     VirtMachineState *vms = VIRT_MACHINE(obj);
2410 
2411     return vms->highmem_ecam;
2412 }
2413 
2414 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp)
2415 {
2416     VirtMachineState *vms = VIRT_MACHINE(obj);
2417 
2418     vms->highmem_ecam = value;
2419 }
2420 
2421 static bool virt_get_highmem_mmio(Object *obj, Error **errp)
2422 {
2423     VirtMachineState *vms = VIRT_MACHINE(obj);
2424 
2425     return vms->highmem_mmio;
2426 }
2427 
2428 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp)
2429 {
2430     VirtMachineState *vms = VIRT_MACHINE(obj);
2431 
2432     vms->highmem_mmio = value;
2433 }
2434 
2435 
2436 static bool virt_get_its(Object *obj, Error **errp)
2437 {
2438     VirtMachineState *vms = VIRT_MACHINE(obj);
2439 
2440     return vms->its;
2441 }
2442 
2443 static void virt_set_its(Object *obj, bool value, Error **errp)
2444 {
2445     VirtMachineState *vms = VIRT_MACHINE(obj);
2446 
2447     vms->its = value;
2448 }
2449 
2450 static bool virt_get_dtb_randomness(Object *obj, Error **errp)
2451 {
2452     VirtMachineState *vms = VIRT_MACHINE(obj);
2453 
2454     return vms->dtb_randomness;
2455 }
2456 
2457 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp)
2458 {
2459     VirtMachineState *vms = VIRT_MACHINE(obj);
2460 
2461     vms->dtb_randomness = value;
2462 }
2463 
2464 static char *virt_get_oem_id(Object *obj, Error **errp)
2465 {
2466     VirtMachineState *vms = VIRT_MACHINE(obj);
2467 
2468     return g_strdup(vms->oem_id);
2469 }
2470 
2471 static void virt_set_oem_id(Object *obj, const char *value, Error **errp)
2472 {
2473     VirtMachineState *vms = VIRT_MACHINE(obj);
2474     size_t len = strlen(value);
2475 
2476     if (len > 6) {
2477         error_setg(errp,
2478                    "User specified oem-id value is bigger than 6 bytes in size");
2479         return;
2480     }
2481 
2482     strncpy(vms->oem_id, value, 6);
2483 }
2484 
2485 static char *virt_get_oem_table_id(Object *obj, Error **errp)
2486 {
2487     VirtMachineState *vms = VIRT_MACHINE(obj);
2488 
2489     return g_strdup(vms->oem_table_id);
2490 }
2491 
2492 static void virt_set_oem_table_id(Object *obj, const char *value,
2493                                   Error **errp)
2494 {
2495     VirtMachineState *vms = VIRT_MACHINE(obj);
2496     size_t len = strlen(value);
2497 
2498     if (len > 8) {
2499         error_setg(errp,
2500                    "User specified oem-table-id value is bigger than 8 bytes in size");
2501         return;
2502     }
2503     strncpy(vms->oem_table_id, value, 8);
2504 }
2505 
2506 
2507 bool virt_is_acpi_enabled(VirtMachineState *vms)
2508 {
2509     if (vms->acpi == ON_OFF_AUTO_OFF) {
2510         return false;
2511     }
2512     return true;
2513 }
2514 
2515 static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
2516                           void *opaque, Error **errp)
2517 {
2518     VirtMachineState *vms = VIRT_MACHINE(obj);
2519     OnOffAuto acpi = vms->acpi;
2520 
2521     visit_type_OnOffAuto(v, name, &acpi, errp);
2522 }
2523 
2524 static void virt_set_acpi(Object *obj, Visitor *v, const char *name,
2525                           void *opaque, Error **errp)
2526 {
2527     VirtMachineState *vms = VIRT_MACHINE(obj);
2528 
2529     visit_type_OnOffAuto(v, name, &vms->acpi, errp);
2530 }
2531 
2532 static bool virt_get_ras(Object *obj, Error **errp)
2533 {
2534     VirtMachineState *vms = VIRT_MACHINE(obj);
2535 
2536     return vms->ras;
2537 }
2538 
2539 static void virt_set_ras(Object *obj, bool value, Error **errp)
2540 {
2541     VirtMachineState *vms = VIRT_MACHINE(obj);
2542 
2543     vms->ras = value;
2544 }
2545 
2546 static bool virt_get_mte(Object *obj, Error **errp)
2547 {
2548     VirtMachineState *vms = VIRT_MACHINE(obj);
2549 
2550     return vms->mte;
2551 }
2552 
2553 static void virt_set_mte(Object *obj, bool value, Error **errp)
2554 {
2555     VirtMachineState *vms = VIRT_MACHINE(obj);
2556 
2557     vms->mte = value;
2558 }
2559 
2560 static char *virt_get_gic_version(Object *obj, Error **errp)
2561 {
2562     VirtMachineState *vms = VIRT_MACHINE(obj);
2563     const char *val;
2564 
2565     switch (vms->gic_version) {
2566     case VIRT_GIC_VERSION_4:
2567         val = "4";
2568         break;
2569     case VIRT_GIC_VERSION_3:
2570         val = "3";
2571         break;
2572     default:
2573         val = "2";
2574         break;
2575     }
2576     return g_strdup(val);
2577 }
2578 
2579 static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
2580 {
2581     VirtMachineState *vms = VIRT_MACHINE(obj);
2582 
2583     if (!strcmp(value, "4")) {
2584         vms->gic_version = VIRT_GIC_VERSION_4;
2585     } else if (!strcmp(value, "3")) {
2586         vms->gic_version = VIRT_GIC_VERSION_3;
2587     } else if (!strcmp(value, "2")) {
2588         vms->gic_version = VIRT_GIC_VERSION_2;
2589     } else if (!strcmp(value, "host")) {
2590         vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */
2591     } else if (!strcmp(value, "max")) {
2592         vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */
2593     } else {
2594         error_setg(errp, "Invalid gic-version value");
2595         error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
2596     }
2597 }
2598 
2599 static char *virt_get_iommu(Object *obj, Error **errp)
2600 {
2601     VirtMachineState *vms = VIRT_MACHINE(obj);
2602 
2603     switch (vms->iommu) {
2604     case VIRT_IOMMU_NONE:
2605         return g_strdup("none");
2606     case VIRT_IOMMU_SMMUV3:
2607         return g_strdup("smmuv3");
2608     default:
2609         g_assert_not_reached();
2610     }
2611 }
2612 
2613 static void virt_set_iommu(Object *obj, const char *value, Error **errp)
2614 {
2615     VirtMachineState *vms = VIRT_MACHINE(obj);
2616 
2617     if (!strcmp(value, "smmuv3")) {
2618         vms->iommu = VIRT_IOMMU_SMMUV3;
2619     } else if (!strcmp(value, "none")) {
2620         vms->iommu = VIRT_IOMMU_NONE;
2621     } else {
2622         error_setg(errp, "Invalid iommu value");
2623         error_append_hint(errp, "Valid values are none, smmuv3.\n");
2624     }
2625 }
2626 
2627 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp)
2628 {
2629     VirtMachineState *vms = VIRT_MACHINE(obj);
2630 
2631     return vms->default_bus_bypass_iommu;
2632 }
2633 
2634 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value,
2635                                               Error **errp)
2636 {
2637     VirtMachineState *vms = VIRT_MACHINE(obj);
2638 
2639     vms->default_bus_bypass_iommu = value;
2640 }
2641 
2642 static CpuInstanceProperties
2643 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2644 {
2645     MachineClass *mc = MACHINE_GET_CLASS(ms);
2646     const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2647 
2648     assert(cpu_index < possible_cpus->len);
2649     return possible_cpus->cpus[cpu_index].props;
2650 }
2651 
2652 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
2653 {
2654     int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
2655 
2656     return socket_id % ms->numa_state->num_nodes;
2657 }
2658 
2659 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
2660 {
2661     int n;
2662     unsigned int max_cpus = ms->smp.max_cpus;
2663     VirtMachineState *vms = VIRT_MACHINE(ms);
2664     MachineClass *mc = MACHINE_GET_CLASS(vms);
2665 
2666     if (ms->possible_cpus) {
2667         assert(ms->possible_cpus->len == max_cpus);
2668         return ms->possible_cpus;
2669     }
2670 
2671     ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2672                                   sizeof(CPUArchId) * max_cpus);
2673     ms->possible_cpus->len = max_cpus;
2674     for (n = 0; n < ms->possible_cpus->len; n++) {
2675         ms->possible_cpus->cpus[n].type = ms->cpu_type;
2676         ms->possible_cpus->cpus[n].arch_id =
2677             virt_cpu_mp_affinity(vms, n);
2678 
2679         assert(!mc->smp_props.dies_supported);
2680         ms->possible_cpus->cpus[n].props.has_socket_id = true;
2681         ms->possible_cpus->cpus[n].props.socket_id =
2682             n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
2683         ms->possible_cpus->cpus[n].props.has_cluster_id = true;
2684         ms->possible_cpus->cpus[n].props.cluster_id =
2685             (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
2686         ms->possible_cpus->cpus[n].props.has_core_id = true;
2687         ms->possible_cpus->cpus[n].props.core_id =
2688             (n / ms->smp.threads) % ms->smp.cores;
2689         ms->possible_cpus->cpus[n].props.has_thread_id = true;
2690         ms->possible_cpus->cpus[n].props.thread_id =
2691             n % ms->smp.threads;
2692     }
2693     return ms->possible_cpus;
2694 }
2695 
2696 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2697                                  Error **errp)
2698 {
2699     VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2700     const MachineState *ms = MACHINE(hotplug_dev);
2701     const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2702 
2703     if (!vms->acpi_dev) {
2704         error_setg(errp,
2705                    "memory hotplug is not enabled: missing acpi-ged device");
2706         return;
2707     }
2708 
2709     if (vms->mte) {
2710         error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
2711         return;
2712     }
2713 
2714     if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
2715         error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2716         return;
2717     }
2718 
2719     pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp);
2720 }
2721 
2722 static void virt_memory_plug(HotplugHandler *hotplug_dev,
2723                              DeviceState *dev, Error **errp)
2724 {
2725     VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2726     MachineState *ms = MACHINE(hotplug_dev);
2727     bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2728 
2729     pc_dimm_plug(PC_DIMM(dev), MACHINE(vms));
2730 
2731     if (is_nvdimm) {
2732         nvdimm_plug(ms->nvdimms_state);
2733     }
2734 
2735     hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev),
2736                          dev, &error_abort);
2737 }
2738 
2739 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2740                                             DeviceState *dev, Error **errp)
2741 {
2742     VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2743 
2744     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2745         virt_memory_pre_plug(hotplug_dev, dev, errp);
2746     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2747         virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
2748     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2749         hwaddr db_start = 0, db_end = 0;
2750         char *resv_prop_str;
2751 
2752         if (vms->iommu != VIRT_IOMMU_NONE) {
2753             error_setg(errp, "virt machine does not support multiple IOMMUs");
2754             return;
2755         }
2756 
2757         switch (vms->msi_controller) {
2758         case VIRT_MSI_CTRL_NONE:
2759             return;
2760         case VIRT_MSI_CTRL_ITS:
2761             /* GITS_TRANSLATER page */
2762             db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
2763             db_end = base_memmap[VIRT_GIC_ITS].base +
2764                      base_memmap[VIRT_GIC_ITS].size - 1;
2765             break;
2766         case VIRT_MSI_CTRL_GICV2M:
2767             /* MSI_SETSPI_NS page */
2768             db_start = base_memmap[VIRT_GIC_V2M].base;
2769             db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
2770             break;
2771         }
2772         resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
2773                                         db_start, db_end,
2774                                         VIRTIO_IOMMU_RESV_MEM_T_MSI);
2775 
2776         object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
2777         object_property_set_str(OBJECT(dev), "reserved-regions[0]",
2778                                 resv_prop_str, errp);
2779         g_free(resv_prop_str);
2780     }
2781 }
2782 
2783 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2784                                         DeviceState *dev, Error **errp)
2785 {
2786     VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2787 
2788     if (vms->platform_bus_dev) {
2789         MachineClass *mc = MACHINE_GET_CLASS(vms);
2790 
2791         if (device_is_dynamic_sysbus(mc, dev)) {
2792             platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
2793                                      SYS_BUS_DEVICE(dev));
2794         }
2795     }
2796 
2797     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2798         virt_memory_plug(hotplug_dev, dev, errp);
2799     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2800         virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
2801     }
2802 
2803     if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2804         PCIDevice *pdev = PCI_DEVICE(dev);
2805 
2806         vms->iommu = VIRT_IOMMU_VIRTIO;
2807         vms->virtio_iommu_bdf = pci_get_bdf(pdev);
2808         create_virtio_iommu_dt_bindings(vms);
2809     }
2810 }
2811 
2812 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev,
2813                                      DeviceState *dev, Error **errp)
2814 {
2815     VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2816 
2817     if (!vms->acpi_dev) {
2818         error_setg(errp,
2819                    "memory hotplug is not enabled: missing acpi-ged device");
2820         return;
2821     }
2822 
2823     if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2824         error_setg(errp, "nvdimm device hot unplug is not supported yet.");
2825         return;
2826     }
2827 
2828     hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
2829                                    errp);
2830 }
2831 
2832 static void virt_dimm_unplug(HotplugHandler *hotplug_dev,
2833                              DeviceState *dev, Error **errp)
2834 {
2835     VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2836     Error *local_err = NULL;
2837 
2838     hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
2839     if (local_err) {
2840         goto out;
2841     }
2842 
2843     pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms));
2844     qdev_unrealize(dev);
2845 
2846 out:
2847     error_propagate(errp, local_err);
2848 }
2849 
2850 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2851                                           DeviceState *dev, Error **errp)
2852 {
2853     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2854         virt_dimm_unplug_request(hotplug_dev, dev, errp);
2855     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2856         virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev),
2857                                      errp);
2858     } else {
2859         error_setg(errp, "device unplug request for unsupported device"
2860                    " type: %s", object_get_typename(OBJECT(dev)));
2861     }
2862 }
2863 
2864 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2865                                           DeviceState *dev, Error **errp)
2866 {
2867     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2868         virt_dimm_unplug(hotplug_dev, dev, errp);
2869     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2870         virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
2871     } else {
2872         error_setg(errp, "virt: device unplug for unsupported device"
2873                    " type: %s", object_get_typename(OBJECT(dev)));
2874     }
2875 }
2876 
2877 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
2878                                                         DeviceState *dev)
2879 {
2880     MachineClass *mc = MACHINE_GET_CLASS(machine);
2881 
2882     if (device_is_dynamic_sysbus(mc, dev) ||
2883         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2884         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) ||
2885         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2886         return HOTPLUG_HANDLER(machine);
2887     }
2888     return NULL;
2889 }
2890 
2891 /*
2892  * for arm64 kvm_type [7-0] encodes the requested number of bits
2893  * in the IPA address space
2894  */
2895 static int virt_kvm_type(MachineState *ms, const char *type_str)
2896 {
2897     VirtMachineState *vms = VIRT_MACHINE(ms);
2898     int max_vm_pa_size, requested_pa_size;
2899     bool fixed_ipa;
2900 
2901     max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa);
2902 
2903     /* we freeze the memory map to compute the highest gpa */
2904     virt_set_memmap(vms, max_vm_pa_size);
2905 
2906     requested_pa_size = 64 - clz64(vms->highest_gpa);
2907 
2908     /*
2909      * KVM requires the IPA size to be at least 32 bits.
2910      */
2911     if (requested_pa_size < 32) {
2912         requested_pa_size = 32;
2913     }
2914 
2915     if (requested_pa_size > max_vm_pa_size) {
2916         error_report("-m and ,maxmem option values "
2917                      "require an IPA range (%d bits) larger than "
2918                      "the one supported by the host (%d bits)",
2919                      requested_pa_size, max_vm_pa_size);
2920         return -1;
2921     }
2922     /*
2923      * We return the requested PA log size, unless KVM only supports
2924      * the implicit legacy 40b IPA setting, in which case the kvm_type
2925      * must be 0.
2926      */
2927     return fixed_ipa ? 0 : requested_pa_size;
2928 }
2929 
2930 static void virt_machine_class_init(ObjectClass *oc, void *data)
2931 {
2932     MachineClass *mc = MACHINE_CLASS(oc);
2933     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2934 
2935     mc->init = machvirt_init;
2936     /* Start with max_cpus set to 512, which is the maximum supported by KVM.
2937      * The value may be reduced later when we have more information about the
2938      * configuration of the particular instance.
2939      */
2940     mc->max_cpus = 512;
2941     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
2942     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
2943     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
2944     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
2945 #ifdef CONFIG_TPM
2946     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
2947 #endif
2948     mc->block_default_type = IF_VIRTIO;
2949     mc->no_cdrom = 1;
2950     mc->pci_allow_0_address = true;
2951     /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
2952     mc->minimum_page_bits = 12;
2953     mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
2954     mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
2955 #ifdef CONFIG_TCG
2956     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
2957 #else
2958     mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
2959 #endif
2960     mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
2961     mc->kvm_type = virt_kvm_type;
2962     assert(!mc->get_hotplug_handler);
2963     mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
2964     hc->pre_plug = virt_machine_device_pre_plug_cb;
2965     hc->plug = virt_machine_device_plug_cb;
2966     hc->unplug_request = virt_machine_device_unplug_request_cb;
2967     hc->unplug = virt_machine_device_unplug_cb;
2968     mc->nvdimm_supported = true;
2969     mc->smp_props.clusters_supported = true;
2970     mc->auto_enable_numa_with_memhp = true;
2971     mc->auto_enable_numa_with_memdev = true;
2972     /* platform instead of architectural choice */
2973     mc->cpu_cluster_has_numa_boundary = true;
2974     mc->default_ram_id = "mach-virt.ram";
2975     mc->default_nic = "virtio-net-pci";
2976 
2977     object_class_property_add(oc, "acpi", "OnOffAuto",
2978         virt_get_acpi, virt_set_acpi,
2979         NULL, NULL);
2980     object_class_property_set_description(oc, "acpi",
2981         "Enable ACPI");
2982     object_class_property_add_bool(oc, "secure", virt_get_secure,
2983                                    virt_set_secure);
2984     object_class_property_set_description(oc, "secure",
2985                                                 "Set on/off to enable/disable the ARM "
2986                                                 "Security Extensions (TrustZone)");
2987 
2988     object_class_property_add_bool(oc, "virtualization", virt_get_virt,
2989                                    virt_set_virt);
2990     object_class_property_set_description(oc, "virtualization",
2991                                           "Set on/off to enable/disable emulating a "
2992                                           "guest CPU which implements the ARM "
2993                                           "Virtualization Extensions");
2994 
2995     object_class_property_add_bool(oc, "highmem", virt_get_highmem,
2996                                    virt_set_highmem);
2997     object_class_property_set_description(oc, "highmem",
2998                                           "Set on/off to enable/disable using "
2999                                           "physical address space above 32 bits");
3000 
3001     object_class_property_add_bool(oc, "compact-highmem",
3002                                    virt_get_compact_highmem,
3003                                    virt_set_compact_highmem);
3004     object_class_property_set_description(oc, "compact-highmem",
3005                                           "Set on/off to enable/disable compact "
3006                                           "layout for high memory regions");
3007 
3008     object_class_property_add_bool(oc, "highmem-redists",
3009                                    virt_get_highmem_redists,
3010                                    virt_set_highmem_redists);
3011     object_class_property_set_description(oc, "highmem-redists",
3012                                           "Set on/off to enable/disable high "
3013                                           "memory region for GICv3 or GICv4 "
3014                                           "redistributor");
3015 
3016     object_class_property_add_bool(oc, "highmem-ecam",
3017                                    virt_get_highmem_ecam,
3018                                    virt_set_highmem_ecam);
3019     object_class_property_set_description(oc, "highmem-ecam",
3020                                           "Set on/off to enable/disable high "
3021                                           "memory region for PCI ECAM");
3022 
3023     object_class_property_add_bool(oc, "highmem-mmio",
3024                                    virt_get_highmem_mmio,
3025                                    virt_set_highmem_mmio);
3026     object_class_property_set_description(oc, "highmem-mmio",
3027                                           "Set on/off to enable/disable high "
3028                                           "memory region for PCI MMIO");
3029 
3030     object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
3031                                   virt_set_gic_version);
3032     object_class_property_set_description(oc, "gic-version",
3033                                           "Set GIC version. "
3034                                           "Valid values are 2, 3, 4, host and max");
3035 
3036     object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu);
3037     object_class_property_set_description(oc, "iommu",
3038                                           "Set the IOMMU type. "
3039                                           "Valid values are none and smmuv3");
3040 
3041     object_class_property_add_bool(oc, "default-bus-bypass-iommu",
3042                                    virt_get_default_bus_bypass_iommu,
3043                                    virt_set_default_bus_bypass_iommu);
3044     object_class_property_set_description(oc, "default-bus-bypass-iommu",
3045                                           "Set on/off to enable/disable "
3046                                           "bypass_iommu for default root bus");
3047 
3048     object_class_property_add_bool(oc, "ras", virt_get_ras,
3049                                    virt_set_ras);
3050     object_class_property_set_description(oc, "ras",
3051                                           "Set on/off to enable/disable reporting host memory errors "
3052                                           "to a KVM guest using ACPI and guest external abort exceptions");
3053 
3054     object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte);
3055     object_class_property_set_description(oc, "mte",
3056                                           "Set on/off to enable/disable emulating a "
3057                                           "guest CPU which implements the ARM "
3058                                           "Memory Tagging Extension");
3059 
3060     object_class_property_add_bool(oc, "its", virt_get_its,
3061                                    virt_set_its);
3062     object_class_property_set_description(oc, "its",
3063                                           "Set on/off to enable/disable "
3064                                           "ITS instantiation");
3065 
3066     object_class_property_add_bool(oc, "dtb-randomness",
3067                                    virt_get_dtb_randomness,
3068                                    virt_set_dtb_randomness);
3069     object_class_property_set_description(oc, "dtb-randomness",
3070                                           "Set off to disable passing random or "
3071                                           "non-deterministic dtb nodes to guest");
3072 
3073     object_class_property_add_bool(oc, "dtb-kaslr-seed",
3074                                    virt_get_dtb_randomness,
3075                                    virt_set_dtb_randomness);
3076     object_class_property_set_description(oc, "dtb-kaslr-seed",
3077                                           "Deprecated synonym of dtb-randomness");
3078 
3079     object_class_property_add_str(oc, "x-oem-id",
3080                                   virt_get_oem_id,
3081                                   virt_set_oem_id);
3082     object_class_property_set_description(oc, "x-oem-id",
3083                                           "Override the default value of field OEMID "
3084                                           "in ACPI table header."
3085                                           "The string may be up to 6 bytes in size");
3086 
3087 
3088     object_class_property_add_str(oc, "x-oem-table-id",
3089                                   virt_get_oem_table_id,
3090                                   virt_set_oem_table_id);
3091     object_class_property_set_description(oc, "x-oem-table-id",
3092                                           "Override the default value of field OEM Table ID "
3093                                           "in ACPI table header."
3094                                           "The string may be up to 8 bytes in size");
3095 
3096 }
3097 
3098 static void virt_instance_init(Object *obj)
3099 {
3100     VirtMachineState *vms = VIRT_MACHINE(obj);
3101     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
3102 
3103     /* EL3 is disabled by default on virt: this makes us consistent
3104      * between KVM and TCG for this board, and it also allows us to
3105      * boot UEFI blobs which assume no TrustZone support.
3106      */
3107     vms->secure = false;
3108 
3109     /* EL2 is also disabled by default, for similar reasons */
3110     vms->virt = false;
3111 
3112     /* High memory is enabled by default */
3113     vms->highmem = true;
3114     vms->highmem_compact = !vmc->no_highmem_compact;
3115     vms->gic_version = VIRT_GIC_VERSION_NOSEL;
3116 
3117     vms->highmem_ecam = !vmc->no_highmem_ecam;
3118     vms->highmem_mmio = true;
3119     vms->highmem_redists = true;
3120 
3121     if (vmc->no_its) {
3122         vms->its = false;
3123     } else {
3124         /* Default allows ITS instantiation */
3125         vms->its = true;
3126 
3127         if (vmc->no_tcg_its) {
3128             vms->tcg_its = false;
3129         } else {
3130             vms->tcg_its = true;
3131         }
3132     }
3133 
3134     /* Default disallows iommu instantiation */
3135     vms->iommu = VIRT_IOMMU_NONE;
3136 
3137     /* The default root bus is attached to iommu by default */
3138     vms->default_bus_bypass_iommu = false;
3139 
3140     /* Default disallows RAS instantiation */
3141     vms->ras = false;
3142 
3143     /* MTE is disabled by default.  */
3144     vms->mte = false;
3145 
3146     /* Supply kaslr-seed and rng-seed by default */
3147     vms->dtb_randomness = true;
3148 
3149     vms->irqmap = a15irqmap;
3150 
3151     virt_flash_create(vms);
3152 
3153     vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
3154     vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
3155 }
3156 
3157 static const TypeInfo virt_machine_info = {
3158     .name          = TYPE_VIRT_MACHINE,
3159     .parent        = TYPE_MACHINE,
3160     .abstract      = true,
3161     .instance_size = sizeof(VirtMachineState),
3162     .class_size    = sizeof(VirtMachineClass),
3163     .class_init    = virt_machine_class_init,
3164     .instance_init = virt_instance_init,
3165     .interfaces = (InterfaceInfo[]) {
3166          { TYPE_HOTPLUG_HANDLER },
3167          { }
3168     },
3169 };
3170 
3171 static void machvirt_machine_init(void)
3172 {
3173     type_register_static(&virt_machine_info);
3174 }
3175 type_init(machvirt_machine_init);
3176 
3177 static void virt_machine_8_2_options(MachineClass *mc)
3178 {
3179 }
3180 DEFINE_VIRT_MACHINE_AS_LATEST(8, 2)
3181 
3182 static void virt_machine_8_1_options(MachineClass *mc)
3183 {
3184     virt_machine_8_2_options(mc);
3185     compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len);
3186 }
3187 DEFINE_VIRT_MACHINE(8, 1)
3188 
3189 static void virt_machine_8_0_options(MachineClass *mc)
3190 {
3191     virt_machine_8_1_options(mc);
3192     compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len);
3193 }
3194 DEFINE_VIRT_MACHINE(8, 0)
3195 
3196 static void virt_machine_7_2_options(MachineClass *mc)
3197 {
3198     virt_machine_8_0_options(mc);
3199     compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len);
3200 }
3201 DEFINE_VIRT_MACHINE(7, 2)
3202 
3203 static void virt_machine_7_1_options(MachineClass *mc)
3204 {
3205     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3206 
3207     virt_machine_7_2_options(mc);
3208     compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len);
3209     /* Compact layout for high memory regions was introduced with 7.2 */
3210     vmc->no_highmem_compact = true;
3211 }
3212 DEFINE_VIRT_MACHINE(7, 1)
3213 
3214 static void virt_machine_7_0_options(MachineClass *mc)
3215 {
3216     virt_machine_7_1_options(mc);
3217     compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len);
3218 }
3219 DEFINE_VIRT_MACHINE(7, 0)
3220 
3221 static void virt_machine_6_2_options(MachineClass *mc)
3222 {
3223     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3224 
3225     virt_machine_7_0_options(mc);
3226     compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len);
3227     vmc->no_tcg_lpa2 = true;
3228 }
3229 DEFINE_VIRT_MACHINE(6, 2)
3230 
3231 static void virt_machine_6_1_options(MachineClass *mc)
3232 {
3233     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3234 
3235     virt_machine_6_2_options(mc);
3236     compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len);
3237     mc->smp_props.prefer_sockets = true;
3238     vmc->no_cpu_topology = true;
3239 
3240     /* qemu ITS was introduced with 6.2 */
3241     vmc->no_tcg_its = true;
3242 }
3243 DEFINE_VIRT_MACHINE(6, 1)
3244 
3245 static void virt_machine_6_0_options(MachineClass *mc)
3246 {
3247     virt_machine_6_1_options(mc);
3248     compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len);
3249 }
3250 DEFINE_VIRT_MACHINE(6, 0)
3251 
3252 static void virt_machine_5_2_options(MachineClass *mc)
3253 {
3254     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3255 
3256     virt_machine_6_0_options(mc);
3257     compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len);
3258     vmc->no_secure_gpio = true;
3259 }
3260 DEFINE_VIRT_MACHINE(5, 2)
3261 
3262 static void virt_machine_5_1_options(MachineClass *mc)
3263 {
3264     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3265 
3266     virt_machine_5_2_options(mc);
3267     compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
3268     vmc->no_kvm_steal_time = true;
3269 }
3270 DEFINE_VIRT_MACHINE(5, 1)
3271 
3272 static void virt_machine_5_0_options(MachineClass *mc)
3273 {
3274     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3275 
3276     virt_machine_5_1_options(mc);
3277     compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
3278     mc->numa_mem_supported = true;
3279     vmc->acpi_expose_flash = true;
3280     mc->auto_enable_numa_with_memdev = false;
3281 }
3282 DEFINE_VIRT_MACHINE(5, 0)
3283 
3284 static void virt_machine_4_2_options(MachineClass *mc)
3285 {
3286     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3287 
3288     virt_machine_5_0_options(mc);
3289     compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
3290     vmc->kvm_no_adjvtime = true;
3291 }
3292 DEFINE_VIRT_MACHINE(4, 2)
3293 
3294 static void virt_machine_4_1_options(MachineClass *mc)
3295 {
3296     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3297 
3298     virt_machine_4_2_options(mc);
3299     compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
3300     vmc->no_ged = true;
3301     mc->auto_enable_numa_with_memhp = false;
3302 }
3303 DEFINE_VIRT_MACHINE(4, 1)
3304 
3305 static void virt_machine_4_0_options(MachineClass *mc)
3306 {
3307     virt_machine_4_1_options(mc);
3308     compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
3309 }
3310 DEFINE_VIRT_MACHINE(4, 0)
3311 
3312 static void virt_machine_3_1_options(MachineClass *mc)
3313 {
3314     virt_machine_4_0_options(mc);
3315     compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
3316 }
3317 DEFINE_VIRT_MACHINE(3, 1)
3318 
3319 static void virt_machine_3_0_options(MachineClass *mc)
3320 {
3321     virt_machine_3_1_options(mc);
3322     compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
3323 }
3324 DEFINE_VIRT_MACHINE(3, 0)
3325 
3326 static void virt_machine_2_12_options(MachineClass *mc)
3327 {
3328     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3329 
3330     virt_machine_3_0_options(mc);
3331     compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
3332     vmc->no_highmem_ecam = true;
3333     mc->max_cpus = 255;
3334 }
3335 DEFINE_VIRT_MACHINE(2, 12)
3336 
3337 static void virt_machine_2_11_options(MachineClass *mc)
3338 {
3339     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3340 
3341     virt_machine_2_12_options(mc);
3342     compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
3343     vmc->smbios_old_sys_ver = true;
3344 }
3345 DEFINE_VIRT_MACHINE(2, 11)
3346 
3347 static void virt_machine_2_10_options(MachineClass *mc)
3348 {
3349     virt_machine_2_11_options(mc);
3350     compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
3351     /* before 2.11 we never faulted accesses to bad addresses */
3352     mc->ignore_memory_transaction_failures = true;
3353 }
3354 DEFINE_VIRT_MACHINE(2, 10)
3355 
3356 static void virt_machine_2_9_options(MachineClass *mc)
3357 {
3358     virt_machine_2_10_options(mc);
3359     compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
3360 }
3361 DEFINE_VIRT_MACHINE(2, 9)
3362 
3363 static void virt_machine_2_8_options(MachineClass *mc)
3364 {
3365     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3366 
3367     virt_machine_2_9_options(mc);
3368     compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
3369     /* For 2.8 and earlier we falsely claimed in the DT that
3370      * our timers were edge-triggered, not level-triggered.
3371      */
3372     vmc->claim_edge_triggered_timers = true;
3373 }
3374 DEFINE_VIRT_MACHINE(2, 8)
3375 
3376 static void virt_machine_2_7_options(MachineClass *mc)
3377 {
3378     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3379 
3380     virt_machine_2_8_options(mc);
3381     compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
3382     /* ITS was introduced with 2.8 */
3383     vmc->no_its = true;
3384     /* Stick with 1K pages for migration compatibility */
3385     mc->minimum_page_bits = 0;
3386 }
3387 DEFINE_VIRT_MACHINE(2, 7)
3388 
3389 static void virt_machine_2_6_options(MachineClass *mc)
3390 {
3391     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3392 
3393     virt_machine_2_7_options(mc);
3394     compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
3395     vmc->disallow_affinity_adjustment = true;
3396     /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
3397     vmc->no_pmu = true;
3398 }
3399 DEFINE_VIRT_MACHINE(2, 6)
3400