1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/datadir.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "qapi/error.h" 37 #include "hw/sysbus.h" 38 #include "hw/arm/boot.h" 39 #include "hw/arm/primecell.h" 40 #include "hw/arm/virt.h" 41 #include "hw/block/flash.h" 42 #include "hw/vfio/vfio-calxeda-xgmac.h" 43 #include "hw/vfio/vfio-amd-xgbe.h" 44 #include "hw/display/ramfb.h" 45 #include "net/net.h" 46 #include "sysemu/device_tree.h" 47 #include "sysemu/numa.h" 48 #include "sysemu/runstate.h" 49 #include "sysemu/tpm.h" 50 #include "sysemu/kvm.h" 51 #include "sysemu/hvf.h" 52 #include "hw/loader.h" 53 #include "qapi/error.h" 54 #include "qemu/bitops.h" 55 #include "qemu/error-report.h" 56 #include "qemu/module.h" 57 #include "hw/pci-host/gpex.h" 58 #include "hw/virtio/virtio-pci.h" 59 #include "hw/core/sysbus-fdt.h" 60 #include "hw/platform-bus.h" 61 #include "hw/qdev-properties.h" 62 #include "hw/arm/fdt.h" 63 #include "hw/intc/arm_gic.h" 64 #include "hw/intc/arm_gicv3_common.h" 65 #include "hw/irq.h" 66 #include "kvm_arm.h" 67 #include "hw/firmware/smbios.h" 68 #include "qapi/visitor.h" 69 #include "qapi/qapi-visit-common.h" 70 #include "standard-headers/linux/input.h" 71 #include "hw/arm/smmuv3.h" 72 #include "hw/acpi/acpi.h" 73 #include "target/arm/internals.h" 74 #include "hw/mem/memory-device.h" 75 #include "hw/mem/pc-dimm.h" 76 #include "hw/mem/nvdimm.h" 77 #include "hw/acpi/generic_event_device.h" 78 #include "hw/virtio/virtio-mem-pci.h" 79 #include "hw/virtio/virtio-iommu.h" 80 #include "hw/char/pl011.h" 81 #include "qemu/guest-random.h" 82 83 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 84 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 85 void *data) \ 86 { \ 87 MachineClass *mc = MACHINE_CLASS(oc); \ 88 virt_machine_##major##_##minor##_options(mc); \ 89 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 90 if (latest) { \ 91 mc->alias = "virt"; \ 92 } \ 93 } \ 94 static const TypeInfo machvirt_##major##_##minor##_info = { \ 95 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 96 .parent = TYPE_VIRT_MACHINE, \ 97 .class_init = virt_##major##_##minor##_class_init, \ 98 }; \ 99 static void machvirt_machine_##major##_##minor##_init(void) \ 100 { \ 101 type_register_static(&machvirt_##major##_##minor##_info); \ 102 } \ 103 type_init(machvirt_machine_##major##_##minor##_init); 104 105 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 106 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 107 #define DEFINE_VIRT_MACHINE(major, minor) \ 108 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 109 110 111 /* Number of external interrupt lines to configure the GIC with */ 112 #define NUM_IRQS 256 113 114 #define PLATFORM_BUS_NUM_IRQS 64 115 116 /* Legacy RAM limit in GB (< version 4.0) */ 117 #define LEGACY_RAMLIMIT_GB 255 118 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 119 120 /* Addresses and sizes of our components. 121 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 122 * 128MB..256MB is used for miscellaneous device I/O. 123 * 256MB..1GB is reserved for possible future PCI support (ie where the 124 * PCI memory window will go if we add a PCI host controller). 125 * 1GB and up is RAM (which may happily spill over into the 126 * high memory region beyond 4GB). 127 * This represents a compromise between how much RAM can be given to 128 * a 32 bit VM and leaving space for expansion and in particular for PCI. 129 * Note that devices should generally be placed at multiples of 0x10000, 130 * to accommodate guests using 64K pages. 131 */ 132 static const MemMapEntry base_memmap[] = { 133 /* Space up to 0x8000000 is reserved for a boot ROM */ 134 [VIRT_FLASH] = { 0, 0x08000000 }, 135 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 136 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 137 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 138 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 139 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 140 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 141 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 142 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 143 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 144 /* This redistributor space allows up to 2*64kB*123 CPUs */ 145 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 146 [VIRT_UART] = { 0x09000000, 0x00001000 }, 147 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 148 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 149 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 150 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 151 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 152 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 153 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 154 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 155 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, 156 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, 157 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 158 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 159 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 160 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 161 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 162 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 163 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 164 /* Actual RAM size depends on initial RAM and device memory settings */ 165 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 166 }; 167 168 /* 169 * Highmem IO Regions: This memory map is floating, located after the RAM. 170 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 171 * top of the RAM, so that its base get the same alignment as the size, 172 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 173 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 174 * Note the extended_memmap is sized so that it eventually also includes the 175 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 176 * index of base_memmap). 177 * 178 * The memory map for these Highmem IO Regions can be in legacy or compact 179 * layout, depending on 'compact-highmem' property. With legacy layout, the 180 * PA space for one specific region is always reserved, even if the region 181 * has been disabled or doesn't fit into the PA space. However, the PA space 182 * for the region won't be reserved in these circumstances with compact layout. 183 */ 184 static MemMapEntry extended_memmap[] = { 185 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 186 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 187 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 188 /* Second PCIe window */ 189 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 190 }; 191 192 static const int a15irqmap[] = { 193 [VIRT_UART] = 1, 194 [VIRT_RTC] = 2, 195 [VIRT_PCIE] = 3, /* ... to 6 */ 196 [VIRT_GPIO] = 7, 197 [VIRT_SECURE_UART] = 8, 198 [VIRT_ACPI_GED] = 9, 199 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 200 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 201 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 202 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 203 }; 204 205 static const char *valid_cpus[] = { 206 ARM_CPU_TYPE_NAME("cortex-a7"), 207 ARM_CPU_TYPE_NAME("cortex-a15"), 208 ARM_CPU_TYPE_NAME("cortex-a35"), 209 ARM_CPU_TYPE_NAME("cortex-a53"), 210 ARM_CPU_TYPE_NAME("cortex-a57"), 211 ARM_CPU_TYPE_NAME("cortex-a72"), 212 ARM_CPU_TYPE_NAME("cortex-a76"), 213 ARM_CPU_TYPE_NAME("a64fx"), 214 ARM_CPU_TYPE_NAME("neoverse-n1"), 215 ARM_CPU_TYPE_NAME("host"), 216 ARM_CPU_TYPE_NAME("max"), 217 }; 218 219 static bool cpu_type_valid(const char *cpu) 220 { 221 int i; 222 223 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 224 if (strcmp(cpu, valid_cpus[i]) == 0) { 225 return true; 226 } 227 } 228 return false; 229 } 230 231 static void create_randomness(MachineState *ms, const char *node) 232 { 233 struct { 234 uint64_t kaslr; 235 uint8_t rng[32]; 236 } seed; 237 238 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { 239 return; 240 } 241 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr); 242 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); 243 } 244 245 static void create_fdt(VirtMachineState *vms) 246 { 247 MachineState *ms = MACHINE(vms); 248 int nb_numa_nodes = ms->numa_state->num_nodes; 249 void *fdt = create_device_tree(&vms->fdt_size); 250 251 if (!fdt) { 252 error_report("create_device_tree() failed"); 253 exit(1); 254 } 255 256 ms->fdt = fdt; 257 258 /* Header */ 259 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 260 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 261 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 262 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt"); 263 264 /* /chosen must exist for load_dtb to fill in necessary properties later */ 265 qemu_fdt_add_subnode(fdt, "/chosen"); 266 if (vms->dtb_randomness) { 267 create_randomness(ms, "/chosen"); 268 } 269 270 if (vms->secure) { 271 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 272 if (vms->dtb_randomness) { 273 create_randomness(ms, "/secure-chosen"); 274 } 275 } 276 277 /* Clock node, for the benefit of the UART. The kernel device tree 278 * binding documentation claims the PL011 node clock properties are 279 * optional but in practice if you omit them the kernel refuses to 280 * probe for the device. 281 */ 282 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 283 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 284 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 285 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 286 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 287 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 288 "clk24mhz"); 289 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 290 291 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 292 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 293 uint32_t *matrix = g_malloc0(size); 294 int idx, i, j; 295 296 for (i = 0; i < nb_numa_nodes; i++) { 297 for (j = 0; j < nb_numa_nodes; j++) { 298 idx = (i * nb_numa_nodes + j) * 3; 299 matrix[idx + 0] = cpu_to_be32(i); 300 matrix[idx + 1] = cpu_to_be32(j); 301 matrix[idx + 2] = 302 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 303 } 304 } 305 306 qemu_fdt_add_subnode(fdt, "/distance-map"); 307 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 308 "numa-distance-map-v1"); 309 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 310 matrix, size); 311 g_free(matrix); 312 } 313 } 314 315 static void fdt_add_timer_nodes(const VirtMachineState *vms) 316 { 317 /* On real hardware these interrupts are level-triggered. 318 * On KVM they were edge-triggered before host kernel version 4.4, 319 * and level-triggered afterwards. 320 * On emulated QEMU they are level-triggered. 321 * 322 * Getting the DTB info about them wrong is awkward for some 323 * guest kernels: 324 * pre-4.8 ignore the DT and leave the interrupt configured 325 * with whatever the GIC reset value (or the bootloader) left it at 326 * 4.8 before rc6 honour the incorrect data by programming it back 327 * into the GIC, causing problems 328 * 4.8rc6 and later ignore the DT and always write "level triggered" 329 * into the GIC 330 * 331 * For backwards-compatibility, virt-2.8 and earlier will continue 332 * to say these are edge-triggered, but later machines will report 333 * the correct information. 334 */ 335 ARMCPU *armcpu; 336 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 337 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 338 MachineState *ms = MACHINE(vms); 339 340 if (vmc->claim_edge_triggered_timers) { 341 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 342 } 343 344 if (vms->gic_version == VIRT_GIC_VERSION_2) { 345 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 346 GIC_FDT_IRQ_PPI_CPU_WIDTH, 347 (1 << MACHINE(vms)->smp.cpus) - 1); 348 } 349 350 qemu_fdt_add_subnode(ms->fdt, "/timer"); 351 352 armcpu = ARM_CPU(qemu_get_cpu(0)); 353 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 354 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 355 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", 356 compat, sizeof(compat)); 357 } else { 358 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", 359 "arm,armv7-timer"); 360 } 361 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); 362 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 363 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 364 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 365 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 366 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 367 } 368 369 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 370 { 371 int cpu; 372 int addr_cells = 1; 373 const MachineState *ms = MACHINE(vms); 374 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 375 int smp_cpus = ms->smp.cpus; 376 377 /* 378 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml 379 * On ARM v8 64-bit systems value should be set to 2, 380 * that corresponds to the MPIDR_EL1 register size. 381 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 382 * in the system, #address-cells can be set to 1, since 383 * MPIDR_EL1[63:32] bits are not used for CPUs 384 * identification. 385 * 386 * Here we actually don't know whether our system is 32- or 64-bit one. 387 * The simplest way to go is to examine affinity IDs of all our CPUs. If 388 * at least one of them has Aff3 populated, we set #address-cells to 2. 389 */ 390 for (cpu = 0; cpu < smp_cpus; cpu++) { 391 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 392 393 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 394 addr_cells = 2; 395 break; 396 } 397 } 398 399 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 400 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); 401 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 402 403 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 404 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 405 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 406 CPUState *cs = CPU(armcpu); 407 408 qemu_fdt_add_subnode(ms->fdt, nodename); 409 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 410 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 411 armcpu->dtb_compatible); 412 413 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { 414 qemu_fdt_setprop_string(ms->fdt, nodename, 415 "enable-method", "psci"); 416 } 417 418 if (addr_cells == 2) { 419 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", 420 armcpu->mp_affinity); 421 } else { 422 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", 423 armcpu->mp_affinity); 424 } 425 426 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 427 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 428 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 429 } 430 431 if (!vmc->no_cpu_topology) { 432 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 433 qemu_fdt_alloc_phandle(ms->fdt)); 434 } 435 436 g_free(nodename); 437 } 438 439 if (!vmc->no_cpu_topology) { 440 /* 441 * Add vCPU topology description through fdt node cpu-map. 442 * 443 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt 444 * In a SMP system, the hierarchy of CPUs can be defined through 445 * four entities that are used to describe the layout of CPUs in 446 * the system: socket/cluster/core/thread. 447 * 448 * A socket node represents the boundary of system physical package 449 * and its child nodes must be one or more cluster nodes. A system 450 * can contain several layers of clustering within a single physical 451 * package and cluster nodes can be contained in parent cluster nodes. 452 * 453 * Note: currently we only support one layer of clustering within 454 * each physical package. 455 */ 456 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 457 458 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 459 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); 460 char *map_path; 461 462 if (ms->smp.threads > 1) { 463 map_path = g_strdup_printf( 464 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", 465 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), 466 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, 467 (cpu / ms->smp.threads) % ms->smp.cores, 468 cpu % ms->smp.threads); 469 } else { 470 map_path = g_strdup_printf( 471 "/cpus/cpu-map/socket%d/cluster%d/core%d", 472 cpu / (ms->smp.clusters * ms->smp.cores), 473 (cpu / ms->smp.cores) % ms->smp.clusters, 474 cpu % ms->smp.cores); 475 } 476 qemu_fdt_add_path(ms->fdt, map_path); 477 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 478 479 g_free(map_path); 480 g_free(cpu_path); 481 } 482 } 483 } 484 485 static void fdt_add_its_gic_node(VirtMachineState *vms) 486 { 487 char *nodename; 488 MachineState *ms = MACHINE(vms); 489 490 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 491 nodename = g_strdup_printf("/intc/its@%" PRIx64, 492 vms->memmap[VIRT_GIC_ITS].base); 493 qemu_fdt_add_subnode(ms->fdt, nodename); 494 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 495 "arm,gic-v3-its"); 496 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 497 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1); 498 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 499 2, vms->memmap[VIRT_GIC_ITS].base, 500 2, vms->memmap[VIRT_GIC_ITS].size); 501 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 502 g_free(nodename); 503 } 504 505 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 506 { 507 MachineState *ms = MACHINE(vms); 508 char *nodename; 509 510 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 511 vms->memmap[VIRT_GIC_V2M].base); 512 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 513 qemu_fdt_add_subnode(ms->fdt, nodename); 514 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 515 "arm,gic-v2m-frame"); 516 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 517 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 518 2, vms->memmap[VIRT_GIC_V2M].base, 519 2, vms->memmap[VIRT_GIC_V2M].size); 520 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 521 g_free(nodename); 522 } 523 524 static void fdt_add_gic_node(VirtMachineState *vms) 525 { 526 MachineState *ms = MACHINE(vms); 527 char *nodename; 528 529 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 530 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); 531 532 nodename = g_strdup_printf("/intc@%" PRIx64, 533 vms->memmap[VIRT_GIC_DIST].base); 534 qemu_fdt_add_subnode(ms->fdt, nodename); 535 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 536 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 537 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 538 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 539 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 540 if (vms->gic_version != VIRT_GIC_VERSION_2) { 541 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 542 543 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 544 "arm,gic-v3"); 545 546 qemu_fdt_setprop_cell(ms->fdt, nodename, 547 "#redistributor-regions", nb_redist_regions); 548 549 if (nb_redist_regions == 1) { 550 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 551 2, vms->memmap[VIRT_GIC_DIST].base, 552 2, vms->memmap[VIRT_GIC_DIST].size, 553 2, vms->memmap[VIRT_GIC_REDIST].base, 554 2, vms->memmap[VIRT_GIC_REDIST].size); 555 } else { 556 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 557 2, vms->memmap[VIRT_GIC_DIST].base, 558 2, vms->memmap[VIRT_GIC_DIST].size, 559 2, vms->memmap[VIRT_GIC_REDIST].base, 560 2, vms->memmap[VIRT_GIC_REDIST].size, 561 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 562 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 563 } 564 565 if (vms->virt) { 566 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 567 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 568 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 569 } 570 } else { 571 /* 'cortex-a15-gic' means 'GIC v2' */ 572 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 573 "arm,cortex-a15-gic"); 574 if (!vms->virt) { 575 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 576 2, vms->memmap[VIRT_GIC_DIST].base, 577 2, vms->memmap[VIRT_GIC_DIST].size, 578 2, vms->memmap[VIRT_GIC_CPU].base, 579 2, vms->memmap[VIRT_GIC_CPU].size); 580 } else { 581 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 582 2, vms->memmap[VIRT_GIC_DIST].base, 583 2, vms->memmap[VIRT_GIC_DIST].size, 584 2, vms->memmap[VIRT_GIC_CPU].base, 585 2, vms->memmap[VIRT_GIC_CPU].size, 586 2, vms->memmap[VIRT_GIC_HYP].base, 587 2, vms->memmap[VIRT_GIC_HYP].size, 588 2, vms->memmap[VIRT_GIC_VCPU].base, 589 2, vms->memmap[VIRT_GIC_VCPU].size); 590 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 591 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 592 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 593 } 594 } 595 596 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); 597 g_free(nodename); 598 } 599 600 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 601 { 602 ARMCPU *armcpu = ARM_CPU(first_cpu); 603 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 604 MachineState *ms = MACHINE(vms); 605 606 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 607 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); 608 return; 609 } 610 611 if (vms->gic_version == VIRT_GIC_VERSION_2) { 612 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 613 GIC_FDT_IRQ_PPI_CPU_WIDTH, 614 (1 << MACHINE(vms)->smp.cpus) - 1); 615 } 616 617 qemu_fdt_add_subnode(ms->fdt, "/pmu"); 618 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 619 const char compat[] = "arm,armv8-pmuv3"; 620 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", 621 compat, sizeof(compat)); 622 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", 623 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 624 } 625 } 626 627 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 628 { 629 DeviceState *dev; 630 MachineState *ms = MACHINE(vms); 631 int irq = vms->irqmap[VIRT_ACPI_GED]; 632 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 633 634 if (ms->ram_slots) { 635 event |= ACPI_GED_MEM_HOTPLUG_EVT; 636 } 637 638 if (ms->nvdimms_state->is_enabled) { 639 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 640 } 641 642 dev = qdev_new(TYPE_ACPI_GED); 643 qdev_prop_set_uint32(dev, "ged-event", event); 644 645 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 646 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 647 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 648 649 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 650 651 return dev; 652 } 653 654 static void create_its(VirtMachineState *vms) 655 { 656 const char *itsclass = its_class_name(); 657 DeviceState *dev; 658 659 if (!strcmp(itsclass, "arm-gicv3-its")) { 660 if (!vms->tcg_its) { 661 itsclass = NULL; 662 } 663 } 664 665 if (!itsclass) { 666 /* Do nothing if not supported */ 667 return; 668 } 669 670 dev = qdev_new(itsclass); 671 672 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 673 &error_abort); 674 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 675 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 676 677 fdt_add_its_gic_node(vms); 678 vms->msi_controller = VIRT_MSI_CTRL_ITS; 679 } 680 681 static void create_v2m(VirtMachineState *vms) 682 { 683 int i; 684 int irq = vms->irqmap[VIRT_GIC_V2M]; 685 DeviceState *dev; 686 687 dev = qdev_new("arm-gicv2m"); 688 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 689 qdev_prop_set_uint32(dev, "base-spi", irq); 690 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 691 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 692 693 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 694 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 695 qdev_get_gpio_in(vms->gic, irq + i)); 696 } 697 698 fdt_add_v2m_gic_node(vms); 699 vms->msi_controller = VIRT_MSI_CTRL_GICV2M; 700 } 701 702 static void create_gic(VirtMachineState *vms, MemoryRegion *mem) 703 { 704 MachineState *ms = MACHINE(vms); 705 /* We create a standalone GIC */ 706 SysBusDevice *gicbusdev; 707 const char *gictype; 708 int i; 709 unsigned int smp_cpus = ms->smp.cpus; 710 uint32_t nb_redist_regions = 0; 711 int revision; 712 713 if (vms->gic_version == VIRT_GIC_VERSION_2) { 714 gictype = gic_class_name(); 715 } else { 716 gictype = gicv3_class_name(); 717 } 718 719 switch (vms->gic_version) { 720 case VIRT_GIC_VERSION_2: 721 revision = 2; 722 break; 723 case VIRT_GIC_VERSION_3: 724 revision = 3; 725 break; 726 case VIRT_GIC_VERSION_4: 727 revision = 4; 728 break; 729 default: 730 g_assert_not_reached(); 731 } 732 vms->gic = qdev_new(gictype); 733 qdev_prop_set_uint32(vms->gic, "revision", revision); 734 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 735 /* Note that the num-irq property counts both internal and external 736 * interrupts; there are always 32 of the former (mandated by GIC spec). 737 */ 738 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 739 if (!kvm_irqchip_in_kernel()) { 740 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 741 } 742 743 if (vms->gic_version != VIRT_GIC_VERSION_2) { 744 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); 745 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 746 747 nb_redist_regions = virt_gicv3_redist_region_count(vms); 748 749 qdev_prop_set_uint32(vms->gic, "len-redist-region-count", 750 nb_redist_regions); 751 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count); 752 753 if (!kvm_irqchip_in_kernel()) { 754 if (vms->tcg_its) { 755 object_property_set_link(OBJECT(vms->gic), "sysmem", 756 OBJECT(mem), &error_fatal); 757 qdev_prop_set_bit(vms->gic, "has-lpi", true); 758 } 759 } 760 761 if (nb_redist_regions == 2) { 762 uint32_t redist1_capacity = 763 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 764 765 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", 766 MIN(smp_cpus - redist0_count, redist1_capacity)); 767 } 768 } else { 769 if (!kvm_irqchip_in_kernel()) { 770 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 771 vms->virt); 772 } 773 } 774 gicbusdev = SYS_BUS_DEVICE(vms->gic); 775 sysbus_realize_and_unref(gicbusdev, &error_fatal); 776 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 777 if (vms->gic_version != VIRT_GIC_VERSION_2) { 778 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 779 if (nb_redist_regions == 2) { 780 sysbus_mmio_map(gicbusdev, 2, 781 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 782 } 783 } else { 784 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 785 if (vms->virt) { 786 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 787 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 788 } 789 } 790 791 /* Wire the outputs from each CPU's generic timer and the GICv3 792 * maintenance interrupt signal to the appropriate GIC PPI inputs, 793 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 794 */ 795 for (i = 0; i < smp_cpus; i++) { 796 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 797 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 798 int irq; 799 /* Mapping from the output timer irq lines from the CPU to the 800 * GIC PPI inputs we use for the virt board. 801 */ 802 const int timer_irq[] = { 803 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 804 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 805 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 806 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 807 }; 808 809 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 810 qdev_connect_gpio_out(cpudev, irq, 811 qdev_get_gpio_in(vms->gic, 812 ppibase + timer_irq[irq])); 813 } 814 815 if (vms->gic_version != VIRT_GIC_VERSION_2) { 816 qemu_irq irq = qdev_get_gpio_in(vms->gic, 817 ppibase + ARCH_GIC_MAINT_IRQ); 818 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 819 0, irq); 820 } else if (vms->virt) { 821 qemu_irq irq = qdev_get_gpio_in(vms->gic, 822 ppibase + ARCH_GIC_MAINT_IRQ); 823 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 824 } 825 826 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 827 qdev_get_gpio_in(vms->gic, ppibase 828 + VIRTUAL_PMU_IRQ)); 829 830 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 831 sysbus_connect_irq(gicbusdev, i + smp_cpus, 832 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 833 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 834 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 835 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 836 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 837 } 838 839 fdt_add_gic_node(vms); 840 841 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) { 842 create_its(vms); 843 } else if (vms->gic_version == VIRT_GIC_VERSION_2) { 844 create_v2m(vms); 845 } 846 } 847 848 static void create_uart(const VirtMachineState *vms, int uart, 849 MemoryRegion *mem, Chardev *chr) 850 { 851 char *nodename; 852 hwaddr base = vms->memmap[uart].base; 853 hwaddr size = vms->memmap[uart].size; 854 int irq = vms->irqmap[uart]; 855 const char compat[] = "arm,pl011\0arm,primecell"; 856 const char clocknames[] = "uartclk\0apb_pclk"; 857 DeviceState *dev = qdev_new(TYPE_PL011); 858 SysBusDevice *s = SYS_BUS_DEVICE(dev); 859 MachineState *ms = MACHINE(vms); 860 861 qdev_prop_set_chr(dev, "chardev", chr); 862 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 863 memory_region_add_subregion(mem, base, 864 sysbus_mmio_get_region(s, 0)); 865 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 866 867 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 868 qemu_fdt_add_subnode(ms->fdt, nodename); 869 /* Note that we can't use setprop_string because of the embedded NUL */ 870 qemu_fdt_setprop(ms->fdt, nodename, "compatible", 871 compat, sizeof(compat)); 872 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 873 2, base, 2, size); 874 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 875 GIC_FDT_IRQ_TYPE_SPI, irq, 876 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 877 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", 878 vms->clock_phandle, vms->clock_phandle); 879 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", 880 clocknames, sizeof(clocknames)); 881 882 if (uart == VIRT_UART) { 883 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 884 } else { 885 /* Mark as not usable by the normal world */ 886 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 887 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 888 889 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", 890 nodename); 891 } 892 893 g_free(nodename); 894 } 895 896 static void create_rtc(const VirtMachineState *vms) 897 { 898 char *nodename; 899 hwaddr base = vms->memmap[VIRT_RTC].base; 900 hwaddr size = vms->memmap[VIRT_RTC].size; 901 int irq = vms->irqmap[VIRT_RTC]; 902 const char compat[] = "arm,pl031\0arm,primecell"; 903 MachineState *ms = MACHINE(vms); 904 905 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 906 907 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 908 qemu_fdt_add_subnode(ms->fdt, nodename); 909 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 910 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 911 2, base, 2, size); 912 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 913 GIC_FDT_IRQ_TYPE_SPI, irq, 914 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 915 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 916 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 917 g_free(nodename); 918 } 919 920 static DeviceState *gpio_key_dev; 921 static void virt_powerdown_req(Notifier *n, void *opaque) 922 { 923 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 924 925 if (s->acpi_dev) { 926 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 927 } else { 928 /* use gpio Pin 3 for power button event */ 929 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 930 } 931 } 932 933 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, 934 uint32_t phandle) 935 { 936 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 937 qdev_get_gpio_in(pl061_dev, 3)); 938 939 qemu_fdt_add_subnode(fdt, "/gpio-keys"); 940 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); 941 942 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); 943 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", 944 "label", "GPIO Key Poweroff"); 945 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", 946 KEY_POWER); 947 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", 948 "gpios", phandle, 3, 0); 949 } 950 951 #define SECURE_GPIO_POWEROFF 0 952 #define SECURE_GPIO_RESET 1 953 954 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, 955 uint32_t phandle) 956 { 957 DeviceState *gpio_pwr_dev; 958 959 /* gpio-pwr */ 960 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); 961 962 /* connect secure pl061 to gpio-pwr */ 963 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, 964 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); 965 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, 966 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); 967 968 qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); 969 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", 970 "gpio-poweroff"); 971 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", 972 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); 973 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); 974 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", 975 "okay"); 976 977 qemu_fdt_add_subnode(fdt, "/gpio-restart"); 978 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", 979 "gpio-restart"); 980 qemu_fdt_setprop_cells(fdt, "/gpio-restart", 981 "gpios", phandle, SECURE_GPIO_RESET, 0); 982 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); 983 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", 984 "okay"); 985 } 986 987 static void create_gpio_devices(const VirtMachineState *vms, int gpio, 988 MemoryRegion *mem) 989 { 990 char *nodename; 991 DeviceState *pl061_dev; 992 hwaddr base = vms->memmap[gpio].base; 993 hwaddr size = vms->memmap[gpio].size; 994 int irq = vms->irqmap[gpio]; 995 const char compat[] = "arm,pl061\0arm,primecell"; 996 SysBusDevice *s; 997 MachineState *ms = MACHINE(vms); 998 999 pl061_dev = qdev_new("pl061"); 1000 /* Pull lines down to 0 if not driven by the PL061 */ 1001 qdev_prop_set_uint32(pl061_dev, "pullups", 0); 1002 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); 1003 s = SYS_BUS_DEVICE(pl061_dev); 1004 sysbus_realize_and_unref(s, &error_fatal); 1005 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); 1006 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 1007 1008 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); 1009 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 1010 qemu_fdt_add_subnode(ms->fdt, nodename); 1011 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1012 2, base, 2, size); 1013 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 1014 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); 1015 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); 1016 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1017 GIC_FDT_IRQ_TYPE_SPI, irq, 1018 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1019 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1020 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1021 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); 1022 1023 if (gpio != VIRT_GPIO) { 1024 /* Mark as not usable by the normal world */ 1025 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1026 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1027 } 1028 g_free(nodename); 1029 1030 /* Child gpio devices */ 1031 if (gpio == VIRT_GPIO) { 1032 create_gpio_keys(ms->fdt, pl061_dev, phandle); 1033 } else { 1034 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); 1035 } 1036 } 1037 1038 static void create_virtio_devices(const VirtMachineState *vms) 1039 { 1040 int i; 1041 hwaddr size = vms->memmap[VIRT_MMIO].size; 1042 MachineState *ms = MACHINE(vms); 1043 1044 /* We create the transports in forwards order. Since qbus_realize() 1045 * prepends (not appends) new child buses, the incrementing loop below will 1046 * create a list of virtio-mmio buses with decreasing base addresses. 1047 * 1048 * When a -device option is processed from the command line, 1049 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 1050 * order. The upshot is that -device options in increasing command line 1051 * order are mapped to virtio-mmio buses with decreasing base addresses. 1052 * 1053 * When this code was originally written, that arrangement ensured that the 1054 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 1055 * the first -device on the command line. (The end-to-end order is a 1056 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 1057 * guest kernel's name-to-address assignment strategy.) 1058 * 1059 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 1060 * the message, if not necessarily the code, of commit 70161ff336. 1061 * Therefore the loop now establishes the inverse of the original intent. 1062 * 1063 * Unfortunately, we can't counteract the kernel change by reversing the 1064 * loop; it would break existing command lines. 1065 * 1066 * In any case, the kernel makes no guarantee about the stability of 1067 * enumeration order of virtio devices (as demonstrated by it changing 1068 * between kernel versions). For reliable and stable identification 1069 * of disks users must use UUIDs or similar mechanisms. 1070 */ 1071 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 1072 int irq = vms->irqmap[VIRT_MMIO] + i; 1073 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1074 1075 sysbus_create_simple("virtio-mmio", base, 1076 qdev_get_gpio_in(vms->gic, irq)); 1077 } 1078 1079 /* We add dtb nodes in reverse order so that they appear in the finished 1080 * device tree lowest address first. 1081 * 1082 * Note that this mapping is independent of the loop above. The previous 1083 * loop influences virtio device to virtio transport assignment, whereas 1084 * this loop controls how virtio transports are laid out in the dtb. 1085 */ 1086 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 1087 char *nodename; 1088 int irq = vms->irqmap[VIRT_MMIO] + i; 1089 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1090 1091 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 1092 qemu_fdt_add_subnode(ms->fdt, nodename); 1093 qemu_fdt_setprop_string(ms->fdt, nodename, 1094 "compatible", "virtio,mmio"); 1095 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1096 2, base, 2, size); 1097 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1098 GIC_FDT_IRQ_TYPE_SPI, irq, 1099 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1100 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1101 g_free(nodename); 1102 } 1103 } 1104 1105 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 1106 1107 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 1108 const char *name, 1109 const char *alias_prop_name) 1110 { 1111 /* 1112 * Create a single flash device. We use the same parameters as 1113 * the flash devices on the Versatile Express board. 1114 */ 1115 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 1116 1117 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 1118 qdev_prop_set_uint8(dev, "width", 4); 1119 qdev_prop_set_uint8(dev, "device-width", 2); 1120 qdev_prop_set_bit(dev, "big-endian", false); 1121 qdev_prop_set_uint16(dev, "id0", 0x89); 1122 qdev_prop_set_uint16(dev, "id1", 0x18); 1123 qdev_prop_set_uint16(dev, "id2", 0x00); 1124 qdev_prop_set_uint16(dev, "id3", 0x00); 1125 qdev_prop_set_string(dev, "name", name); 1126 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 1127 object_property_add_alias(OBJECT(vms), alias_prop_name, 1128 OBJECT(dev), "drive"); 1129 return PFLASH_CFI01(dev); 1130 } 1131 1132 static void virt_flash_create(VirtMachineState *vms) 1133 { 1134 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 1135 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 1136 } 1137 1138 static void virt_flash_map1(PFlashCFI01 *flash, 1139 hwaddr base, hwaddr size, 1140 MemoryRegion *sysmem) 1141 { 1142 DeviceState *dev = DEVICE(flash); 1143 1144 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 1145 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 1146 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 1147 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1148 1149 memory_region_add_subregion(sysmem, base, 1150 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1151 0)); 1152 } 1153 1154 static void virt_flash_map(VirtMachineState *vms, 1155 MemoryRegion *sysmem, 1156 MemoryRegion *secure_sysmem) 1157 { 1158 /* 1159 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 1160 * sysmem is the system memory space. secure_sysmem is the secure view 1161 * of the system, and the first flash device should be made visible only 1162 * there. The second flash device is visible to both secure and nonsecure. 1163 * If sysmem == secure_sysmem this means there is no separate Secure 1164 * address space and both flash devices are generally visible. 1165 */ 1166 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1167 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1168 1169 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1170 secure_sysmem); 1171 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1172 sysmem); 1173 } 1174 1175 static void virt_flash_fdt(VirtMachineState *vms, 1176 MemoryRegion *sysmem, 1177 MemoryRegion *secure_sysmem) 1178 { 1179 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1180 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1181 MachineState *ms = MACHINE(vms); 1182 char *nodename; 1183 1184 if (sysmem == secure_sysmem) { 1185 /* Report both flash devices as a single node in the DT */ 1186 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1187 qemu_fdt_add_subnode(ms->fdt, nodename); 1188 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1189 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1190 2, flashbase, 2, flashsize, 1191 2, flashbase + flashsize, 2, flashsize); 1192 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1193 g_free(nodename); 1194 } else { 1195 /* 1196 * Report the devices as separate nodes so we can mark one as 1197 * only visible to the secure world. 1198 */ 1199 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1200 qemu_fdt_add_subnode(ms->fdt, nodename); 1201 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1202 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1203 2, flashbase, 2, flashsize); 1204 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1205 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1206 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1207 g_free(nodename); 1208 1209 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize); 1210 qemu_fdt_add_subnode(ms->fdt, nodename); 1211 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1212 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1213 2, flashbase + flashsize, 2, flashsize); 1214 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1215 g_free(nodename); 1216 } 1217 } 1218 1219 static bool virt_firmware_init(VirtMachineState *vms, 1220 MemoryRegion *sysmem, 1221 MemoryRegion *secure_sysmem) 1222 { 1223 int i; 1224 const char *bios_name; 1225 BlockBackend *pflash_blk0; 1226 1227 /* Map legacy -drive if=pflash to machine properties */ 1228 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1229 pflash_cfi01_legacy_drive(vms->flash[i], 1230 drive_get(IF_PFLASH, 0, i)); 1231 } 1232 1233 virt_flash_map(vms, sysmem, secure_sysmem); 1234 1235 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1236 1237 bios_name = MACHINE(vms)->firmware; 1238 if (bios_name) { 1239 char *fname; 1240 MemoryRegion *mr; 1241 int image_size; 1242 1243 if (pflash_blk0) { 1244 error_report("The contents of the first flash device may be " 1245 "specified with -bios or with -drive if=pflash... " 1246 "but you cannot use both options at once"); 1247 exit(1); 1248 } 1249 1250 /* Fall back to -bios */ 1251 1252 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1253 if (!fname) { 1254 error_report("Could not find ROM image '%s'", bios_name); 1255 exit(1); 1256 } 1257 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1258 image_size = load_image_mr(fname, mr); 1259 g_free(fname); 1260 if (image_size < 0) { 1261 error_report("Could not load ROM image '%s'", bios_name); 1262 exit(1); 1263 } 1264 } 1265 1266 return pflash_blk0 || bios_name; 1267 } 1268 1269 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1270 { 1271 MachineState *ms = MACHINE(vms); 1272 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1273 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1274 FWCfgState *fw_cfg; 1275 char *nodename; 1276 1277 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1278 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1279 1280 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1281 qemu_fdt_add_subnode(ms->fdt, nodename); 1282 qemu_fdt_setprop_string(ms->fdt, nodename, 1283 "compatible", "qemu,fw-cfg-mmio"); 1284 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1285 2, base, 2, size); 1286 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1287 g_free(nodename); 1288 return fw_cfg; 1289 } 1290 1291 static void create_pcie_irq_map(const MachineState *ms, 1292 uint32_t gic_phandle, 1293 int first_irq, const char *nodename) 1294 { 1295 int devfn, pin; 1296 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1297 uint32_t *irq_map = full_irq_map; 1298 1299 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1300 for (pin = 0; pin < 4; pin++) { 1301 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1302 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1303 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1304 int i; 1305 1306 uint32_t map[] = { 1307 devfn << 8, 0, 0, /* devfn */ 1308 pin + 1, /* PCI pin */ 1309 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1310 1311 /* Convert map to big endian */ 1312 for (i = 0; i < 10; i++) { 1313 irq_map[i] = cpu_to_be32(map[i]); 1314 } 1315 irq_map += 10; 1316 } 1317 } 1318 1319 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", 1320 full_irq_map, sizeof(full_irq_map)); 1321 1322 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 1323 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ 1324 0, 0, 1325 0x7 /* PCI irq */); 1326 } 1327 1328 static void create_smmu(const VirtMachineState *vms, 1329 PCIBus *bus) 1330 { 1331 char *node; 1332 const char compat[] = "arm,smmu-v3"; 1333 int irq = vms->irqmap[VIRT_SMMU]; 1334 int i; 1335 hwaddr base = vms->memmap[VIRT_SMMU].base; 1336 hwaddr size = vms->memmap[VIRT_SMMU].size; 1337 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1338 DeviceState *dev; 1339 MachineState *ms = MACHINE(vms); 1340 1341 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1342 return; 1343 } 1344 1345 dev = qdev_new("arm-smmuv3"); 1346 1347 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1348 &error_abort); 1349 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1350 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1351 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1352 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1353 qdev_get_gpio_in(vms->gic, irq + i)); 1354 } 1355 1356 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1357 qemu_fdt_add_subnode(ms->fdt, node); 1358 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1359 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); 1360 1361 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", 1362 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1363 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1364 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1365 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1366 1367 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, 1368 sizeof(irq_names)); 1369 1370 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); 1371 1372 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1373 1374 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1375 g_free(node); 1376 } 1377 1378 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1379 { 1380 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1381 uint16_t bdf = vms->virtio_iommu_bdf; 1382 MachineState *ms = MACHINE(vms); 1383 char *node; 1384 1385 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1386 1387 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename, 1388 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1389 qemu_fdt_add_subnode(ms->fdt, node); 1390 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1391 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 1392 1, bdf << 8, 1, 0, 1, 0, 1393 1, 0, 1, 0); 1394 1395 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1396 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1397 g_free(node); 1398 1399 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", 1400 0x0, vms->iommu_phandle, 0x0, bdf, 1401 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1402 } 1403 1404 static void create_pcie(VirtMachineState *vms) 1405 { 1406 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1407 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1408 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1409 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1410 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1411 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1412 hwaddr base_ecam, size_ecam; 1413 hwaddr base = base_mmio; 1414 int nr_pcie_buses; 1415 int irq = vms->irqmap[VIRT_PCIE]; 1416 MemoryRegion *mmio_alias; 1417 MemoryRegion *mmio_reg; 1418 MemoryRegion *ecam_alias; 1419 MemoryRegion *ecam_reg; 1420 DeviceState *dev; 1421 char *nodename; 1422 int i, ecam_id; 1423 PCIHostState *pci; 1424 MachineState *ms = MACHINE(vms); 1425 1426 dev = qdev_new(TYPE_GPEX_HOST); 1427 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1428 1429 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1430 base_ecam = vms->memmap[ecam_id].base; 1431 size_ecam = vms->memmap[ecam_id].size; 1432 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1433 /* Map only the first size_ecam bytes of ECAM space */ 1434 ecam_alias = g_new0(MemoryRegion, 1); 1435 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1436 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1437 ecam_reg, 0, size_ecam); 1438 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1439 1440 /* Map the MMIO window into system address space so as to expose 1441 * the section of PCI MMIO space which starts at the same base address 1442 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1443 * the window). 1444 */ 1445 mmio_alias = g_new0(MemoryRegion, 1); 1446 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1447 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1448 mmio_reg, base_mmio, size_mmio); 1449 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1450 1451 if (vms->highmem_mmio) { 1452 /* Map high MMIO space */ 1453 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1454 1455 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1456 mmio_reg, base_mmio_high, size_mmio_high); 1457 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1458 high_mmio_alias); 1459 } 1460 1461 /* Map IO port space */ 1462 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1463 1464 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1465 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1466 qdev_get_gpio_in(vms->gic, irq + i)); 1467 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1468 } 1469 1470 pci = PCI_HOST_BRIDGE(dev); 1471 pci->bypass_iommu = vms->default_bus_bypass_iommu; 1472 vms->bus = pci->bus; 1473 if (vms->bus) { 1474 for (i = 0; i < nb_nics; i++) { 1475 NICInfo *nd = &nd_table[i]; 1476 1477 if (!nd->model) { 1478 nd->model = g_strdup("virtio"); 1479 } 1480 1481 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1482 } 1483 } 1484 1485 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1486 qemu_fdt_add_subnode(ms->fdt, nodename); 1487 qemu_fdt_setprop_string(ms->fdt, nodename, 1488 "compatible", "pci-host-ecam-generic"); 1489 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 1490 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 1491 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 1492 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 1493 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 1494 nr_pcie_buses - 1); 1495 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1496 1497 if (vms->msi_phandle) { 1498 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 1499 0, vms->msi_phandle, 0, 0x10000); 1500 } 1501 1502 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1503 2, base_ecam, 2, size_ecam); 1504 1505 if (vms->highmem_mmio) { 1506 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1507 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1508 2, base_pio, 2, size_pio, 1509 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1510 2, base_mmio, 2, size_mmio, 1511 1, FDT_PCI_RANGE_MMIO_64BIT, 1512 2, base_mmio_high, 1513 2, base_mmio_high, 2, size_mmio_high); 1514 } else { 1515 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1516 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1517 2, base_pio, 2, size_pio, 1518 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1519 2, base_mmio, 2, size_mmio); 1520 } 1521 1522 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 1523 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); 1524 1525 if (vms->iommu) { 1526 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1527 1528 switch (vms->iommu) { 1529 case VIRT_IOMMU_SMMUV3: 1530 create_smmu(vms, vms->bus); 1531 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 1532 0x0, vms->iommu_phandle, 0x0, 0x10000); 1533 break; 1534 default: 1535 g_assert_not_reached(); 1536 } 1537 } 1538 } 1539 1540 static void create_platform_bus(VirtMachineState *vms) 1541 { 1542 DeviceState *dev; 1543 SysBusDevice *s; 1544 int i; 1545 MemoryRegion *sysmem = get_system_memory(); 1546 1547 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1548 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1549 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1550 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1551 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1552 vms->platform_bus_dev = dev; 1553 1554 s = SYS_BUS_DEVICE(dev); 1555 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1556 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1557 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1558 } 1559 1560 memory_region_add_subregion(sysmem, 1561 vms->memmap[VIRT_PLATFORM_BUS].base, 1562 sysbus_mmio_get_region(s, 0)); 1563 } 1564 1565 static void create_tag_ram(MemoryRegion *tag_sysmem, 1566 hwaddr base, hwaddr size, 1567 const char *name) 1568 { 1569 MemoryRegion *tagram = g_new(MemoryRegion, 1); 1570 1571 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); 1572 memory_region_add_subregion(tag_sysmem, base / 32, tagram); 1573 } 1574 1575 static void create_secure_ram(VirtMachineState *vms, 1576 MemoryRegion *secure_sysmem, 1577 MemoryRegion *secure_tag_sysmem) 1578 { 1579 MemoryRegion *secram = g_new(MemoryRegion, 1); 1580 char *nodename; 1581 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1582 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1583 MachineState *ms = MACHINE(vms); 1584 1585 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1586 &error_fatal); 1587 memory_region_add_subregion(secure_sysmem, base, secram); 1588 1589 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1590 qemu_fdt_add_subnode(ms->fdt, nodename); 1591 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 1592 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 1593 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1594 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1595 1596 if (secure_tag_sysmem) { 1597 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); 1598 } 1599 1600 g_free(nodename); 1601 } 1602 1603 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1604 { 1605 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1606 bootinfo); 1607 MachineState *ms = MACHINE(board); 1608 1609 1610 *fdt_size = board->fdt_size; 1611 return ms->fdt; 1612 } 1613 1614 static void virt_build_smbios(VirtMachineState *vms) 1615 { 1616 MachineClass *mc = MACHINE_GET_CLASS(vms); 1617 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1618 uint8_t *smbios_tables, *smbios_anchor; 1619 size_t smbios_tables_len, smbios_anchor_len; 1620 const char *product = "QEMU Virtual Machine"; 1621 1622 if (kvm_enabled()) { 1623 product = "KVM Virtual Machine"; 1624 } 1625 1626 smbios_set_defaults("QEMU", product, 1627 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1628 true, SMBIOS_ENTRY_POINT_TYPE_64); 1629 1630 smbios_get_tables(MACHINE(vms), NULL, 0, 1631 &smbios_tables, &smbios_tables_len, 1632 &smbios_anchor, &smbios_anchor_len, 1633 &error_fatal); 1634 1635 if (smbios_anchor) { 1636 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1637 smbios_tables, smbios_tables_len); 1638 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1639 smbios_anchor, smbios_anchor_len); 1640 } 1641 } 1642 1643 static 1644 void virt_machine_done(Notifier *notifier, void *data) 1645 { 1646 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1647 machine_done); 1648 MachineState *ms = MACHINE(vms); 1649 ARMCPU *cpu = ARM_CPU(first_cpu); 1650 struct arm_boot_info *info = &vms->bootinfo; 1651 AddressSpace *as = arm_boot_address_space(cpu, info); 1652 1653 /* 1654 * If the user provided a dtb, we assume the dynamic sysbus nodes 1655 * already are integrated there. This corresponds to a use case where 1656 * the dynamic sysbus nodes are complex and their generation is not yet 1657 * supported. In that case the user can take charge of the guest dt 1658 * while qemu takes charge of the qom stuff. 1659 */ 1660 if (info->dtb_filename == NULL) { 1661 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", 1662 vms->memmap[VIRT_PLATFORM_BUS].base, 1663 vms->memmap[VIRT_PLATFORM_BUS].size, 1664 vms->irqmap[VIRT_PLATFORM_BUS]); 1665 } 1666 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1667 exit(1); 1668 } 1669 1670 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg); 1671 1672 virt_acpi_setup(vms); 1673 virt_build_smbios(vms); 1674 } 1675 1676 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1677 { 1678 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1679 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1680 1681 if (!vmc->disallow_affinity_adjustment) { 1682 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1683 * GIC's target-list limitations. 32-bit KVM hosts currently 1684 * always create clusters of 4 CPUs, but that is expected to 1685 * change when they gain support for gicv3. When KVM is enabled 1686 * it will override the changes we make here, therefore our 1687 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1688 * and to improve SGI efficiency. 1689 */ 1690 if (vms->gic_version == VIRT_GIC_VERSION_2) { 1691 clustersz = GIC_TARGETLIST_BITS; 1692 } else { 1693 clustersz = GICV3_TARGETLIST_BITS; 1694 } 1695 } 1696 return arm_cpu_mp_affinity(idx, clustersz); 1697 } 1698 1699 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, 1700 int index) 1701 { 1702 bool *enabled_array[] = { 1703 &vms->highmem_redists, 1704 &vms->highmem_ecam, 1705 &vms->highmem_mmio, 1706 }; 1707 1708 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST == 1709 ARRAY_SIZE(enabled_array)); 1710 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array)); 1711 1712 return enabled_array[index - VIRT_LOWMEMMAP_LAST]; 1713 } 1714 1715 static void virt_set_high_memmap(VirtMachineState *vms, 1716 hwaddr base, int pa_bits) 1717 { 1718 hwaddr region_base, region_size; 1719 bool *region_enabled, fits; 1720 int i; 1721 1722 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1723 region_enabled = virt_get_high_memmap_enabled(vms, i); 1724 region_base = ROUND_UP(base, extended_memmap[i].size); 1725 region_size = extended_memmap[i].size; 1726 1727 vms->memmap[i].base = region_base; 1728 vms->memmap[i].size = region_size; 1729 1730 /* 1731 * Check each device to see if it fits in the PA space, 1732 * moving highest_gpa as we go. For compatibility, move 1733 * highest_gpa for disabled fitting devices as well, if 1734 * the compact layout has been disabled. 1735 * 1736 * For each device that doesn't fit, disable it. 1737 */ 1738 fits = (region_base + region_size) <= BIT_ULL(pa_bits); 1739 *region_enabled &= fits; 1740 if (vms->highmem_compact && !*region_enabled) { 1741 continue; 1742 } 1743 1744 base = region_base + region_size; 1745 if (fits) { 1746 vms->highest_gpa = base - 1; 1747 } 1748 } 1749 } 1750 1751 static void virt_set_memmap(VirtMachineState *vms, int pa_bits) 1752 { 1753 MachineState *ms = MACHINE(vms); 1754 hwaddr base, device_memory_base, device_memory_size, memtop; 1755 int i; 1756 1757 vms->memmap = extended_memmap; 1758 1759 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1760 vms->memmap[i] = base_memmap[i]; 1761 } 1762 1763 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1764 error_report("unsupported number of memory slots: %"PRIu64, 1765 ms->ram_slots); 1766 exit(EXIT_FAILURE); 1767 } 1768 1769 /* 1770 * !highmem is exactly the same as limiting the PA space to 32bit, 1771 * irrespective of the underlying capabilities of the HW. 1772 */ 1773 if (!vms->highmem) { 1774 pa_bits = 32; 1775 } 1776 1777 /* 1778 * We compute the base of the high IO region depending on the 1779 * amount of initial and device memory. The device memory start/size 1780 * is aligned on 1GiB. We never put the high IO region below 256GiB 1781 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1782 * The device region size assumes 1GiB page max alignment per slot. 1783 */ 1784 device_memory_base = 1785 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1786 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1787 1788 /* Base address of the high IO region */ 1789 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1790 if (memtop > BIT_ULL(pa_bits)) { 1791 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n", 1792 pa_bits, memtop - BIT_ULL(pa_bits)); 1793 exit(EXIT_FAILURE); 1794 } 1795 if (base < device_memory_base) { 1796 error_report("maxmem/slots too huge"); 1797 exit(EXIT_FAILURE); 1798 } 1799 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1800 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1801 } 1802 1803 /* We know for sure that at least the memory fits in the PA space */ 1804 vms->highest_gpa = memtop - 1; 1805 1806 virt_set_high_memmap(vms, base, pa_bits); 1807 1808 if (device_memory_size > 0) { 1809 ms->device_memory = g_malloc0(sizeof(*ms->device_memory)); 1810 ms->device_memory->base = device_memory_base; 1811 memory_region_init(&ms->device_memory->mr, OBJECT(vms), 1812 "device-memory", device_memory_size); 1813 } 1814 } 1815 1816 /* 1817 * finalize_gic_version - Determines the final gic_version 1818 * according to the gic-version property 1819 * 1820 * Default GIC type is v2 1821 */ 1822 static void finalize_gic_version(VirtMachineState *vms) 1823 { 1824 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 1825 1826 if (kvm_enabled()) { 1827 int probe_bitmap; 1828 1829 if (!kvm_irqchip_in_kernel()) { 1830 switch (vms->gic_version) { 1831 case VIRT_GIC_VERSION_HOST: 1832 warn_report( 1833 "gic-version=host not relevant with kernel-irqchip=off " 1834 "as only userspace GICv2 is supported. Using v2 ..."); 1835 return; 1836 case VIRT_GIC_VERSION_MAX: 1837 case VIRT_GIC_VERSION_NOSEL: 1838 vms->gic_version = VIRT_GIC_VERSION_2; 1839 return; 1840 case VIRT_GIC_VERSION_2: 1841 return; 1842 case VIRT_GIC_VERSION_3: 1843 error_report( 1844 "gic-version=3 is not supported with kernel-irqchip=off"); 1845 exit(1); 1846 case VIRT_GIC_VERSION_4: 1847 error_report( 1848 "gic-version=4 is not supported with kernel-irqchip=off"); 1849 exit(1); 1850 } 1851 } 1852 1853 probe_bitmap = kvm_arm_vgic_probe(); 1854 if (!probe_bitmap) { 1855 error_report("Unable to determine GIC version supported by host"); 1856 exit(1); 1857 } 1858 1859 switch (vms->gic_version) { 1860 case VIRT_GIC_VERSION_HOST: 1861 case VIRT_GIC_VERSION_MAX: 1862 if (probe_bitmap & KVM_ARM_VGIC_V3) { 1863 vms->gic_version = VIRT_GIC_VERSION_3; 1864 } else { 1865 vms->gic_version = VIRT_GIC_VERSION_2; 1866 } 1867 return; 1868 case VIRT_GIC_VERSION_NOSEL: 1869 if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) { 1870 vms->gic_version = VIRT_GIC_VERSION_2; 1871 } else if (probe_bitmap & KVM_ARM_VGIC_V3) { 1872 /* 1873 * in case the host does not support v2 in-kernel emulation or 1874 * the end-user requested more than 8 VCPUs we now default 1875 * to v3. In any case defaulting to v2 would be broken. 1876 */ 1877 vms->gic_version = VIRT_GIC_VERSION_3; 1878 } else if (max_cpus > GIC_NCPU) { 1879 error_report("host only supports in-kernel GICv2 emulation " 1880 "but more than 8 vcpus are requested"); 1881 exit(1); 1882 } 1883 break; 1884 case VIRT_GIC_VERSION_2: 1885 case VIRT_GIC_VERSION_3: 1886 break; 1887 case VIRT_GIC_VERSION_4: 1888 error_report("gic-version=4 is not supported with KVM"); 1889 exit(1); 1890 } 1891 1892 /* Check chosen version is effectively supported by the host */ 1893 if (vms->gic_version == VIRT_GIC_VERSION_2 && 1894 !(probe_bitmap & KVM_ARM_VGIC_V2)) { 1895 error_report("host does not support in-kernel GICv2 emulation"); 1896 exit(1); 1897 } else if (vms->gic_version == VIRT_GIC_VERSION_3 && 1898 !(probe_bitmap & KVM_ARM_VGIC_V3)) { 1899 error_report("host does not support in-kernel GICv3 emulation"); 1900 exit(1); 1901 } 1902 return; 1903 } 1904 1905 /* TCG mode */ 1906 switch (vms->gic_version) { 1907 case VIRT_GIC_VERSION_NOSEL: 1908 vms->gic_version = VIRT_GIC_VERSION_2; 1909 break; 1910 case VIRT_GIC_VERSION_MAX: 1911 if (module_object_class_by_name("arm-gicv3")) { 1912 /* CONFIG_ARM_GICV3_TCG was set */ 1913 if (vms->virt) { 1914 /* GICv4 only makes sense if CPU has EL2 */ 1915 vms->gic_version = VIRT_GIC_VERSION_4; 1916 } else { 1917 vms->gic_version = VIRT_GIC_VERSION_3; 1918 } 1919 } else { 1920 vms->gic_version = VIRT_GIC_VERSION_2; 1921 } 1922 break; 1923 case VIRT_GIC_VERSION_HOST: 1924 error_report("gic-version=host requires KVM"); 1925 exit(1); 1926 case VIRT_GIC_VERSION_4: 1927 if (!vms->virt) { 1928 error_report("gic-version=4 requires virtualization enabled"); 1929 exit(1); 1930 } 1931 break; 1932 case VIRT_GIC_VERSION_2: 1933 case VIRT_GIC_VERSION_3: 1934 break; 1935 } 1936 } 1937 1938 /* 1939 * virt_cpu_post_init() must be called after the CPUs have 1940 * been realized and the GIC has been created. 1941 */ 1942 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) 1943 { 1944 int max_cpus = MACHINE(vms)->smp.max_cpus; 1945 bool aarch64, pmu, steal_time; 1946 CPUState *cpu; 1947 1948 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); 1949 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); 1950 steal_time = object_property_get_bool(OBJECT(first_cpu), 1951 "kvm-steal-time", NULL); 1952 1953 if (kvm_enabled()) { 1954 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; 1955 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; 1956 1957 if (steal_time) { 1958 MemoryRegion *pvtime = g_new(MemoryRegion, 1); 1959 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; 1960 1961 /* The memory region size must be a multiple of host page size. */ 1962 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); 1963 1964 if (pvtime_size > pvtime_reg_size) { 1965 error_report("pvtime requires a %" HWADDR_PRId 1966 " byte memory region for %d CPUs," 1967 " but only %" HWADDR_PRId " has been reserved", 1968 pvtime_size, max_cpus, pvtime_reg_size); 1969 exit(1); 1970 } 1971 1972 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); 1973 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); 1974 } 1975 1976 CPU_FOREACH(cpu) { 1977 if (pmu) { 1978 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); 1979 if (kvm_irqchip_in_kernel()) { 1980 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 1981 } 1982 kvm_arm_pmu_init(cpu); 1983 } 1984 if (steal_time) { 1985 kvm_arm_pvtime_init(cpu, pvtime_reg_base + 1986 cpu->cpu_index * PVTIME_SIZE_PER_CPU); 1987 } 1988 } 1989 } else { 1990 if (aarch64 && vms->highmem) { 1991 int requested_pa_size = 64 - clz64(vms->highest_gpa); 1992 int pamax = arm_pamax(ARM_CPU(first_cpu)); 1993 1994 if (pamax < requested_pa_size) { 1995 error_report("VCPU supports less PA bits (%d) than " 1996 "requested by the memory map (%d)", 1997 pamax, requested_pa_size); 1998 exit(1); 1999 } 2000 } 2001 } 2002 } 2003 2004 static void machvirt_init(MachineState *machine) 2005 { 2006 VirtMachineState *vms = VIRT_MACHINE(machine); 2007 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 2008 MachineClass *mc = MACHINE_GET_CLASS(machine); 2009 const CPUArchIdList *possible_cpus; 2010 MemoryRegion *sysmem = get_system_memory(); 2011 MemoryRegion *secure_sysmem = NULL; 2012 MemoryRegion *tag_sysmem = NULL; 2013 MemoryRegion *secure_tag_sysmem = NULL; 2014 int n, virt_max_cpus; 2015 bool firmware_loaded; 2016 bool aarch64 = true; 2017 bool has_ged = !vmc->no_ged; 2018 unsigned int smp_cpus = machine->smp.cpus; 2019 unsigned int max_cpus = machine->smp.max_cpus; 2020 2021 if (!cpu_type_valid(machine->cpu_type)) { 2022 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 2023 exit(1); 2024 } 2025 2026 possible_cpus = mc->possible_cpu_arch_ids(machine); 2027 2028 /* 2029 * In accelerated mode, the memory map is computed earlier in kvm_type() 2030 * to create a VM with the right number of IPA bits. 2031 */ 2032 if (!vms->memmap) { 2033 Object *cpuobj; 2034 ARMCPU *armcpu; 2035 int pa_bits; 2036 2037 /* 2038 * Instanciate a temporary CPU object to find out about what 2039 * we are about to deal with. Once this is done, get rid of 2040 * the object. 2041 */ 2042 cpuobj = object_new(possible_cpus->cpus[0].type); 2043 armcpu = ARM_CPU(cpuobj); 2044 2045 pa_bits = arm_pamax(armcpu); 2046 2047 object_unref(cpuobj); 2048 2049 virt_set_memmap(vms, pa_bits); 2050 } 2051 2052 /* We can probe only here because during property set 2053 * KVM is not available yet 2054 */ 2055 finalize_gic_version(vms); 2056 2057 if (vms->secure) { 2058 /* 2059 * The Secure view of the world is the same as the NonSecure, 2060 * but with a few extra devices. Create it as a container region 2061 * containing the system memory at low priority; any secure-only 2062 * devices go in at higher priority and take precedence. 2063 */ 2064 secure_sysmem = g_new(MemoryRegion, 1); 2065 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 2066 UINT64_MAX); 2067 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 2068 } 2069 2070 firmware_loaded = virt_firmware_init(vms, sysmem, 2071 secure_sysmem ?: sysmem); 2072 2073 /* If we have an EL3 boot ROM then the assumption is that it will 2074 * implement PSCI itself, so disable QEMU's internal implementation 2075 * so it doesn't get in the way. Instead of starting secondary 2076 * CPUs in PSCI powerdown state we will start them all running and 2077 * let the boot ROM sort them out. 2078 * The usual case is that we do use QEMU's PSCI implementation; 2079 * if the guest has EL2 then we will use SMC as the conduit, 2080 * and otherwise we will use HVC (for backwards compatibility and 2081 * because if we're using KVM then we must use HVC). 2082 */ 2083 if (vms->secure && firmware_loaded) { 2084 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 2085 } else if (vms->virt) { 2086 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 2087 } else { 2088 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 2089 } 2090 2091 /* 2092 * The maximum number of CPUs depends on the GIC version, or on how 2093 * many redistributors we can fit into the memory map (which in turn 2094 * depends on whether this is a GICv3 or v4). 2095 */ 2096 if (vms->gic_version == VIRT_GIC_VERSION_2) { 2097 virt_max_cpus = GIC_NCPU; 2098 } else { 2099 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST); 2100 if (vms->highmem_redists) { 2101 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 2102 } 2103 } 2104 2105 if (max_cpus > virt_max_cpus) { 2106 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 2107 "supported by machine 'mach-virt' (%d)", 2108 max_cpus, virt_max_cpus); 2109 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) { 2110 error_printf("Try 'highmem-redists=on' for more CPUs\n"); 2111 } 2112 2113 exit(1); 2114 } 2115 2116 if (vms->secure && (kvm_enabled() || hvf_enabled())) { 2117 error_report("mach-virt: %s does not support providing " 2118 "Security extensions (TrustZone) to the guest CPU", 2119 kvm_enabled() ? "KVM" : "HVF"); 2120 exit(1); 2121 } 2122 2123 if (vms->virt && (kvm_enabled() || hvf_enabled())) { 2124 error_report("mach-virt: %s does not support providing " 2125 "Virtualization extensions to the guest CPU", 2126 kvm_enabled() ? "KVM" : "HVF"); 2127 exit(1); 2128 } 2129 2130 if (vms->mte && (kvm_enabled() || hvf_enabled())) { 2131 error_report("mach-virt: %s does not support providing " 2132 "MTE to the guest CPU", 2133 kvm_enabled() ? "KVM" : "HVF"); 2134 exit(1); 2135 } 2136 2137 create_fdt(vms); 2138 2139 assert(possible_cpus->len == max_cpus); 2140 for (n = 0; n < possible_cpus->len; n++) { 2141 Object *cpuobj; 2142 CPUState *cs; 2143 2144 if (n >= smp_cpus) { 2145 break; 2146 } 2147 2148 cpuobj = object_new(possible_cpus->cpus[n].type); 2149 object_property_set_int(cpuobj, "mp-affinity", 2150 possible_cpus->cpus[n].arch_id, NULL); 2151 2152 cs = CPU(cpuobj); 2153 cs->cpu_index = n; 2154 2155 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 2156 &error_fatal); 2157 2158 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 2159 2160 if (!vms->secure) { 2161 object_property_set_bool(cpuobj, "has_el3", false, NULL); 2162 } 2163 2164 if (!vms->virt && object_property_find(cpuobj, "has_el2")) { 2165 object_property_set_bool(cpuobj, "has_el2", false, NULL); 2166 } 2167 2168 if (vmc->kvm_no_adjvtime && 2169 object_property_find(cpuobj, "kvm-no-adjvtime")) { 2170 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 2171 } 2172 2173 if (vmc->no_kvm_steal_time && 2174 object_property_find(cpuobj, "kvm-steal-time")) { 2175 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); 2176 } 2177 2178 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { 2179 object_property_set_bool(cpuobj, "pmu", false, NULL); 2180 } 2181 2182 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { 2183 object_property_set_bool(cpuobj, "lpa2", false, NULL); 2184 } 2185 2186 if (object_property_find(cpuobj, "reset-cbar")) { 2187 object_property_set_int(cpuobj, "reset-cbar", 2188 vms->memmap[VIRT_CPUPERIPHS].base, 2189 &error_abort); 2190 } 2191 2192 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 2193 &error_abort); 2194 if (vms->secure) { 2195 object_property_set_link(cpuobj, "secure-memory", 2196 OBJECT(secure_sysmem), &error_abort); 2197 } 2198 2199 if (vms->mte) { 2200 /* Create the memory region only once, but link to all cpus. */ 2201 if (!tag_sysmem) { 2202 /* 2203 * The property exists only if MemTag is supported. 2204 * If it is, we must allocate the ram to back that up. 2205 */ 2206 if (!object_property_find(cpuobj, "tag-memory")) { 2207 error_report("MTE requested, but not supported " 2208 "by the guest CPU"); 2209 exit(1); 2210 } 2211 2212 tag_sysmem = g_new(MemoryRegion, 1); 2213 memory_region_init(tag_sysmem, OBJECT(machine), 2214 "tag-memory", UINT64_MAX / 32); 2215 2216 if (vms->secure) { 2217 secure_tag_sysmem = g_new(MemoryRegion, 1); 2218 memory_region_init(secure_tag_sysmem, OBJECT(machine), 2219 "secure-tag-memory", UINT64_MAX / 32); 2220 2221 /* As with ram, secure-tag takes precedence over tag. */ 2222 memory_region_add_subregion_overlap(secure_tag_sysmem, 0, 2223 tag_sysmem, -1); 2224 } 2225 } 2226 2227 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem), 2228 &error_abort); 2229 if (vms->secure) { 2230 object_property_set_link(cpuobj, "secure-tag-memory", 2231 OBJECT(secure_tag_sysmem), 2232 &error_abort); 2233 } 2234 } 2235 2236 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 2237 object_unref(cpuobj); 2238 } 2239 fdt_add_timer_nodes(vms); 2240 fdt_add_cpu_nodes(vms); 2241 2242 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 2243 machine->ram); 2244 if (machine->device_memory) { 2245 memory_region_add_subregion(sysmem, machine->device_memory->base, 2246 &machine->device_memory->mr); 2247 } 2248 2249 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 2250 2251 create_gic(vms, sysmem); 2252 2253 virt_cpu_post_init(vms, sysmem); 2254 2255 fdt_add_pmu_nodes(vms); 2256 2257 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 2258 2259 if (vms->secure) { 2260 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); 2261 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 2262 } 2263 2264 if (tag_sysmem) { 2265 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, 2266 machine->ram_size, "mach-virt.tag"); 2267 } 2268 2269 vms->highmem_ecam &= (!firmware_loaded || aarch64); 2270 2271 create_rtc(vms); 2272 2273 create_pcie(vms); 2274 2275 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 2276 vms->acpi_dev = create_acpi_ged(vms); 2277 } else { 2278 create_gpio_devices(vms, VIRT_GPIO, sysmem); 2279 } 2280 2281 if (vms->secure && !vmc->no_secure_gpio) { 2282 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); 2283 } 2284 2285 /* connect powerdown request */ 2286 vms->powerdown_notifier.notify = virt_powerdown_req; 2287 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 2288 2289 /* Create mmio transports, so the user can create virtio backends 2290 * (which will be automatically plugged in to the transports). If 2291 * no backend is created the transport will just sit harmlessly idle. 2292 */ 2293 create_virtio_devices(vms); 2294 2295 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 2296 rom_set_fw(vms->fw_cfg); 2297 2298 create_platform_bus(vms); 2299 2300 if (machine->nvdimms_state->is_enabled) { 2301 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 2302 .space_id = AML_AS_SYSTEM_MEMORY, 2303 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 2304 .bit_width = NVDIMM_ACPI_IO_LEN << 3 2305 }; 2306 2307 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 2308 arm_virt_nvdimm_acpi_dsmio, 2309 vms->fw_cfg, OBJECT(vms)); 2310 } 2311 2312 vms->bootinfo.ram_size = machine->ram_size; 2313 vms->bootinfo.board_id = -1; 2314 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 2315 vms->bootinfo.get_dtb = machvirt_dtb; 2316 vms->bootinfo.skip_dtb_autoload = true; 2317 vms->bootinfo.firmware_loaded = firmware_loaded; 2318 vms->bootinfo.psci_conduit = vms->psci_conduit; 2319 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 2320 2321 vms->machine_done.notify = virt_machine_done; 2322 qemu_add_machine_init_done_notifier(&vms->machine_done); 2323 } 2324 2325 static bool virt_get_secure(Object *obj, Error **errp) 2326 { 2327 VirtMachineState *vms = VIRT_MACHINE(obj); 2328 2329 return vms->secure; 2330 } 2331 2332 static void virt_set_secure(Object *obj, bool value, Error **errp) 2333 { 2334 VirtMachineState *vms = VIRT_MACHINE(obj); 2335 2336 vms->secure = value; 2337 } 2338 2339 static bool virt_get_virt(Object *obj, Error **errp) 2340 { 2341 VirtMachineState *vms = VIRT_MACHINE(obj); 2342 2343 return vms->virt; 2344 } 2345 2346 static void virt_set_virt(Object *obj, bool value, Error **errp) 2347 { 2348 VirtMachineState *vms = VIRT_MACHINE(obj); 2349 2350 vms->virt = value; 2351 } 2352 2353 static bool virt_get_highmem(Object *obj, Error **errp) 2354 { 2355 VirtMachineState *vms = VIRT_MACHINE(obj); 2356 2357 return vms->highmem; 2358 } 2359 2360 static void virt_set_highmem(Object *obj, bool value, Error **errp) 2361 { 2362 VirtMachineState *vms = VIRT_MACHINE(obj); 2363 2364 vms->highmem = value; 2365 } 2366 2367 static bool virt_get_compact_highmem(Object *obj, Error **errp) 2368 { 2369 VirtMachineState *vms = VIRT_MACHINE(obj); 2370 2371 return vms->highmem_compact; 2372 } 2373 2374 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp) 2375 { 2376 VirtMachineState *vms = VIRT_MACHINE(obj); 2377 2378 vms->highmem_compact = value; 2379 } 2380 2381 static bool virt_get_highmem_redists(Object *obj, Error **errp) 2382 { 2383 VirtMachineState *vms = VIRT_MACHINE(obj); 2384 2385 return vms->highmem_redists; 2386 } 2387 2388 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp) 2389 { 2390 VirtMachineState *vms = VIRT_MACHINE(obj); 2391 2392 vms->highmem_redists = value; 2393 } 2394 2395 static bool virt_get_highmem_ecam(Object *obj, Error **errp) 2396 { 2397 VirtMachineState *vms = VIRT_MACHINE(obj); 2398 2399 return vms->highmem_ecam; 2400 } 2401 2402 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp) 2403 { 2404 VirtMachineState *vms = VIRT_MACHINE(obj); 2405 2406 vms->highmem_ecam = value; 2407 } 2408 2409 static bool virt_get_highmem_mmio(Object *obj, Error **errp) 2410 { 2411 VirtMachineState *vms = VIRT_MACHINE(obj); 2412 2413 return vms->highmem_mmio; 2414 } 2415 2416 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp) 2417 { 2418 VirtMachineState *vms = VIRT_MACHINE(obj); 2419 2420 vms->highmem_mmio = value; 2421 } 2422 2423 2424 static bool virt_get_its(Object *obj, Error **errp) 2425 { 2426 VirtMachineState *vms = VIRT_MACHINE(obj); 2427 2428 return vms->its; 2429 } 2430 2431 static void virt_set_its(Object *obj, bool value, Error **errp) 2432 { 2433 VirtMachineState *vms = VIRT_MACHINE(obj); 2434 2435 vms->its = value; 2436 } 2437 2438 static bool virt_get_dtb_randomness(Object *obj, Error **errp) 2439 { 2440 VirtMachineState *vms = VIRT_MACHINE(obj); 2441 2442 return vms->dtb_randomness; 2443 } 2444 2445 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp) 2446 { 2447 VirtMachineState *vms = VIRT_MACHINE(obj); 2448 2449 vms->dtb_randomness = value; 2450 } 2451 2452 static char *virt_get_oem_id(Object *obj, Error **errp) 2453 { 2454 VirtMachineState *vms = VIRT_MACHINE(obj); 2455 2456 return g_strdup(vms->oem_id); 2457 } 2458 2459 static void virt_set_oem_id(Object *obj, const char *value, Error **errp) 2460 { 2461 VirtMachineState *vms = VIRT_MACHINE(obj); 2462 size_t len = strlen(value); 2463 2464 if (len > 6) { 2465 error_setg(errp, 2466 "User specified oem-id value is bigger than 6 bytes in size"); 2467 return; 2468 } 2469 2470 strncpy(vms->oem_id, value, 6); 2471 } 2472 2473 static char *virt_get_oem_table_id(Object *obj, Error **errp) 2474 { 2475 VirtMachineState *vms = VIRT_MACHINE(obj); 2476 2477 return g_strdup(vms->oem_table_id); 2478 } 2479 2480 static void virt_set_oem_table_id(Object *obj, const char *value, 2481 Error **errp) 2482 { 2483 VirtMachineState *vms = VIRT_MACHINE(obj); 2484 size_t len = strlen(value); 2485 2486 if (len > 8) { 2487 error_setg(errp, 2488 "User specified oem-table-id value is bigger than 8 bytes in size"); 2489 return; 2490 } 2491 strncpy(vms->oem_table_id, value, 8); 2492 } 2493 2494 2495 bool virt_is_acpi_enabled(VirtMachineState *vms) 2496 { 2497 if (vms->acpi == ON_OFF_AUTO_OFF) { 2498 return false; 2499 } 2500 return true; 2501 } 2502 2503 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 2504 void *opaque, Error **errp) 2505 { 2506 VirtMachineState *vms = VIRT_MACHINE(obj); 2507 OnOffAuto acpi = vms->acpi; 2508 2509 visit_type_OnOffAuto(v, name, &acpi, errp); 2510 } 2511 2512 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 2513 void *opaque, Error **errp) 2514 { 2515 VirtMachineState *vms = VIRT_MACHINE(obj); 2516 2517 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 2518 } 2519 2520 static bool virt_get_ras(Object *obj, Error **errp) 2521 { 2522 VirtMachineState *vms = VIRT_MACHINE(obj); 2523 2524 return vms->ras; 2525 } 2526 2527 static void virt_set_ras(Object *obj, bool value, Error **errp) 2528 { 2529 VirtMachineState *vms = VIRT_MACHINE(obj); 2530 2531 vms->ras = value; 2532 } 2533 2534 static bool virt_get_mte(Object *obj, Error **errp) 2535 { 2536 VirtMachineState *vms = VIRT_MACHINE(obj); 2537 2538 return vms->mte; 2539 } 2540 2541 static void virt_set_mte(Object *obj, bool value, Error **errp) 2542 { 2543 VirtMachineState *vms = VIRT_MACHINE(obj); 2544 2545 vms->mte = value; 2546 } 2547 2548 static char *virt_get_gic_version(Object *obj, Error **errp) 2549 { 2550 VirtMachineState *vms = VIRT_MACHINE(obj); 2551 const char *val; 2552 2553 switch (vms->gic_version) { 2554 case VIRT_GIC_VERSION_4: 2555 val = "4"; 2556 break; 2557 case VIRT_GIC_VERSION_3: 2558 val = "3"; 2559 break; 2560 default: 2561 val = "2"; 2562 break; 2563 } 2564 return g_strdup(val); 2565 } 2566 2567 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2568 { 2569 VirtMachineState *vms = VIRT_MACHINE(obj); 2570 2571 if (!strcmp(value, "4")) { 2572 vms->gic_version = VIRT_GIC_VERSION_4; 2573 } else if (!strcmp(value, "3")) { 2574 vms->gic_version = VIRT_GIC_VERSION_3; 2575 } else if (!strcmp(value, "2")) { 2576 vms->gic_version = VIRT_GIC_VERSION_2; 2577 } else if (!strcmp(value, "host")) { 2578 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2579 } else if (!strcmp(value, "max")) { 2580 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2581 } else { 2582 error_setg(errp, "Invalid gic-version value"); 2583 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2584 } 2585 } 2586 2587 static char *virt_get_iommu(Object *obj, Error **errp) 2588 { 2589 VirtMachineState *vms = VIRT_MACHINE(obj); 2590 2591 switch (vms->iommu) { 2592 case VIRT_IOMMU_NONE: 2593 return g_strdup("none"); 2594 case VIRT_IOMMU_SMMUV3: 2595 return g_strdup("smmuv3"); 2596 default: 2597 g_assert_not_reached(); 2598 } 2599 } 2600 2601 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2602 { 2603 VirtMachineState *vms = VIRT_MACHINE(obj); 2604 2605 if (!strcmp(value, "smmuv3")) { 2606 vms->iommu = VIRT_IOMMU_SMMUV3; 2607 } else if (!strcmp(value, "none")) { 2608 vms->iommu = VIRT_IOMMU_NONE; 2609 } else { 2610 error_setg(errp, "Invalid iommu value"); 2611 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2612 } 2613 } 2614 2615 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp) 2616 { 2617 VirtMachineState *vms = VIRT_MACHINE(obj); 2618 2619 return vms->default_bus_bypass_iommu; 2620 } 2621 2622 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value, 2623 Error **errp) 2624 { 2625 VirtMachineState *vms = VIRT_MACHINE(obj); 2626 2627 vms->default_bus_bypass_iommu = value; 2628 } 2629 2630 static CpuInstanceProperties 2631 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2632 { 2633 MachineClass *mc = MACHINE_GET_CLASS(ms); 2634 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2635 2636 assert(cpu_index < possible_cpus->len); 2637 return possible_cpus->cpus[cpu_index].props; 2638 } 2639 2640 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2641 { 2642 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 2643 2644 return socket_id % ms->numa_state->num_nodes; 2645 } 2646 2647 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2648 { 2649 int n; 2650 unsigned int max_cpus = ms->smp.max_cpus; 2651 VirtMachineState *vms = VIRT_MACHINE(ms); 2652 MachineClass *mc = MACHINE_GET_CLASS(vms); 2653 2654 if (ms->possible_cpus) { 2655 assert(ms->possible_cpus->len == max_cpus); 2656 return ms->possible_cpus; 2657 } 2658 2659 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2660 sizeof(CPUArchId) * max_cpus); 2661 ms->possible_cpus->len = max_cpus; 2662 for (n = 0; n < ms->possible_cpus->len; n++) { 2663 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2664 ms->possible_cpus->cpus[n].arch_id = 2665 virt_cpu_mp_affinity(vms, n); 2666 2667 assert(!mc->smp_props.dies_supported); 2668 ms->possible_cpus->cpus[n].props.has_socket_id = true; 2669 ms->possible_cpus->cpus[n].props.socket_id = 2670 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); 2671 ms->possible_cpus->cpus[n].props.has_cluster_id = true; 2672 ms->possible_cpus->cpus[n].props.cluster_id = 2673 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; 2674 ms->possible_cpus->cpus[n].props.has_core_id = true; 2675 ms->possible_cpus->cpus[n].props.core_id = 2676 (n / ms->smp.threads) % ms->smp.cores; 2677 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2678 ms->possible_cpus->cpus[n].props.thread_id = 2679 n % ms->smp.threads; 2680 } 2681 return ms->possible_cpus; 2682 } 2683 2684 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2685 Error **errp) 2686 { 2687 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2688 const MachineState *ms = MACHINE(hotplug_dev); 2689 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2690 2691 if (!vms->acpi_dev) { 2692 error_setg(errp, 2693 "memory hotplug is not enabled: missing acpi-ged device"); 2694 return; 2695 } 2696 2697 if (vms->mte) { 2698 error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); 2699 return; 2700 } 2701 2702 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2703 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2704 return; 2705 } 2706 2707 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 2708 } 2709 2710 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2711 DeviceState *dev, Error **errp) 2712 { 2713 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2714 MachineState *ms = MACHINE(hotplug_dev); 2715 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2716 2717 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); 2718 2719 if (is_nvdimm) { 2720 nvdimm_plug(ms->nvdimms_state); 2721 } 2722 2723 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2724 dev, &error_abort); 2725 } 2726 2727 static void virt_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 2728 DeviceState *dev, Error **errp) 2729 { 2730 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2731 Error *local_err = NULL; 2732 2733 if (!hotplug_dev2 && dev->hotplugged) { 2734 /* 2735 * Without a bus hotplug handler, we cannot control the plug/unplug 2736 * order. We should never reach this point when hotplugging on ARM. 2737 * However, it's nice to add a safety net, similar to what we have 2738 * on x86. 2739 */ 2740 error_setg(errp, "hotplug of virtio based memory devices not supported" 2741 " on this bus."); 2742 return; 2743 } 2744 /* 2745 * First, see if we can plug this memory device at all. If that 2746 * succeeds, branch of to the actual hotplug handler. 2747 */ 2748 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 2749 &local_err); 2750 if (!local_err && hotplug_dev2) { 2751 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 2752 } 2753 error_propagate(errp, local_err); 2754 } 2755 2756 static void virt_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 2757 DeviceState *dev, Error **errp) 2758 { 2759 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2760 Error *local_err = NULL; 2761 2762 /* 2763 * Plug the memory device first and then branch off to the actual 2764 * hotplug handler. If that one fails, we can easily undo the memory 2765 * device bits. 2766 */ 2767 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2768 if (hotplug_dev2) { 2769 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 2770 if (local_err) { 2771 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2772 } 2773 } 2774 error_propagate(errp, local_err); 2775 } 2776 2777 static void virt_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 2778 DeviceState *dev, Error **errp) 2779 { 2780 /* We don't support hot unplug of virtio based memory devices */ 2781 error_setg(errp, "virtio based memory devices cannot be unplugged."); 2782 } 2783 2784 2785 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2786 DeviceState *dev, Error **errp) 2787 { 2788 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2789 2790 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2791 virt_memory_pre_plug(hotplug_dev, dev, errp); 2792 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2793 virt_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 2794 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2795 hwaddr db_start = 0, db_end = 0; 2796 char *resv_prop_str; 2797 2798 if (vms->iommu != VIRT_IOMMU_NONE) { 2799 error_setg(errp, "virt machine does not support multiple IOMMUs"); 2800 return; 2801 } 2802 2803 switch (vms->msi_controller) { 2804 case VIRT_MSI_CTRL_NONE: 2805 return; 2806 case VIRT_MSI_CTRL_ITS: 2807 /* GITS_TRANSLATER page */ 2808 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; 2809 db_end = base_memmap[VIRT_GIC_ITS].base + 2810 base_memmap[VIRT_GIC_ITS].size - 1; 2811 break; 2812 case VIRT_MSI_CTRL_GICV2M: 2813 /* MSI_SETSPI_NS page */ 2814 db_start = base_memmap[VIRT_GIC_V2M].base; 2815 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; 2816 break; 2817 } 2818 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", 2819 db_start, db_end, 2820 VIRTIO_IOMMU_RESV_MEM_T_MSI); 2821 2822 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 2823 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 2824 resv_prop_str, errp); 2825 g_free(resv_prop_str); 2826 } 2827 } 2828 2829 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2830 DeviceState *dev, Error **errp) 2831 { 2832 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2833 2834 if (vms->platform_bus_dev) { 2835 MachineClass *mc = MACHINE_GET_CLASS(vms); 2836 2837 if (device_is_dynamic_sysbus(mc, dev)) { 2838 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2839 SYS_BUS_DEVICE(dev)); 2840 } 2841 } 2842 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2843 virt_memory_plug(hotplug_dev, dev, errp); 2844 } 2845 2846 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2847 virt_virtio_md_pci_plug(hotplug_dev, dev, errp); 2848 } 2849 2850 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2851 PCIDevice *pdev = PCI_DEVICE(dev); 2852 2853 vms->iommu = VIRT_IOMMU_VIRTIO; 2854 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2855 create_virtio_iommu_dt_bindings(vms); 2856 } 2857 } 2858 2859 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, 2860 DeviceState *dev, Error **errp) 2861 { 2862 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2863 Error *local_err = NULL; 2864 2865 if (!vms->acpi_dev) { 2866 error_setg(&local_err, 2867 "memory hotplug is not enabled: missing acpi-ged device"); 2868 goto out; 2869 } 2870 2871 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2872 error_setg(&local_err, 2873 "nvdimm device hot unplug is not supported yet."); 2874 goto out; 2875 } 2876 2877 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, 2878 &local_err); 2879 out: 2880 error_propagate(errp, local_err); 2881 } 2882 2883 static void virt_dimm_unplug(HotplugHandler *hotplug_dev, 2884 DeviceState *dev, Error **errp) 2885 { 2886 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2887 Error *local_err = NULL; 2888 2889 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); 2890 if (local_err) { 2891 goto out; 2892 } 2893 2894 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); 2895 qdev_unrealize(dev); 2896 2897 out: 2898 error_propagate(errp, local_err); 2899 } 2900 2901 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2902 DeviceState *dev, Error **errp) 2903 { 2904 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2905 virt_dimm_unplug_request(hotplug_dev, dev, errp); 2906 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2907 virt_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 2908 } else { 2909 error_setg(errp, "device unplug request for unsupported device" 2910 " type: %s", object_get_typename(OBJECT(dev))); 2911 } 2912 } 2913 2914 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2915 DeviceState *dev, Error **errp) 2916 { 2917 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2918 virt_dimm_unplug(hotplug_dev, dev, errp); 2919 } else { 2920 error_setg(errp, "virt: device unplug for unsupported device" 2921 " type: %s", object_get_typename(OBJECT(dev))); 2922 } 2923 } 2924 2925 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2926 DeviceState *dev) 2927 { 2928 MachineClass *mc = MACHINE_GET_CLASS(machine); 2929 2930 if (device_is_dynamic_sysbus(mc, dev) || 2931 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2932 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 2933 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2934 return HOTPLUG_HANDLER(machine); 2935 } 2936 return NULL; 2937 } 2938 2939 /* 2940 * for arm64 kvm_type [7-0] encodes the requested number of bits 2941 * in the IPA address space 2942 */ 2943 static int virt_kvm_type(MachineState *ms, const char *type_str) 2944 { 2945 VirtMachineState *vms = VIRT_MACHINE(ms); 2946 int max_vm_pa_size, requested_pa_size; 2947 bool fixed_ipa; 2948 2949 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 2950 2951 /* we freeze the memory map to compute the highest gpa */ 2952 virt_set_memmap(vms, max_vm_pa_size); 2953 2954 requested_pa_size = 64 - clz64(vms->highest_gpa); 2955 2956 /* 2957 * KVM requires the IPA size to be at least 32 bits. 2958 */ 2959 if (requested_pa_size < 32) { 2960 requested_pa_size = 32; 2961 } 2962 2963 if (requested_pa_size > max_vm_pa_size) { 2964 error_report("-m and ,maxmem option values " 2965 "require an IPA range (%d bits) larger than " 2966 "the one supported by the host (%d bits)", 2967 requested_pa_size, max_vm_pa_size); 2968 exit(1); 2969 } 2970 /* 2971 * We return the requested PA log size, unless KVM only supports 2972 * the implicit legacy 40b IPA setting, in which case the kvm_type 2973 * must be 0. 2974 */ 2975 return fixed_ipa ? 0 : requested_pa_size; 2976 } 2977 2978 static void virt_machine_class_init(ObjectClass *oc, void *data) 2979 { 2980 MachineClass *mc = MACHINE_CLASS(oc); 2981 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2982 2983 mc->init = machvirt_init; 2984 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 2985 * The value may be reduced later when we have more information about the 2986 * configuration of the particular instance. 2987 */ 2988 mc->max_cpus = 512; 2989 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 2990 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 2991 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 2992 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 2993 #ifdef CONFIG_TPM 2994 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 2995 #endif 2996 mc->block_default_type = IF_VIRTIO; 2997 mc->no_cdrom = 1; 2998 mc->pci_allow_0_address = true; 2999 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 3000 mc->minimum_page_bits = 12; 3001 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 3002 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 3003 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 3004 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 3005 mc->kvm_type = virt_kvm_type; 3006 assert(!mc->get_hotplug_handler); 3007 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 3008 hc->pre_plug = virt_machine_device_pre_plug_cb; 3009 hc->plug = virt_machine_device_plug_cb; 3010 hc->unplug_request = virt_machine_device_unplug_request_cb; 3011 hc->unplug = virt_machine_device_unplug_cb; 3012 mc->nvdimm_supported = true; 3013 mc->smp_props.clusters_supported = true; 3014 mc->auto_enable_numa_with_memhp = true; 3015 mc->auto_enable_numa_with_memdev = true; 3016 mc->default_ram_id = "mach-virt.ram"; 3017 3018 object_class_property_add(oc, "acpi", "OnOffAuto", 3019 virt_get_acpi, virt_set_acpi, 3020 NULL, NULL); 3021 object_class_property_set_description(oc, "acpi", 3022 "Enable ACPI"); 3023 object_class_property_add_bool(oc, "secure", virt_get_secure, 3024 virt_set_secure); 3025 object_class_property_set_description(oc, "secure", 3026 "Set on/off to enable/disable the ARM " 3027 "Security Extensions (TrustZone)"); 3028 3029 object_class_property_add_bool(oc, "virtualization", virt_get_virt, 3030 virt_set_virt); 3031 object_class_property_set_description(oc, "virtualization", 3032 "Set on/off to enable/disable emulating a " 3033 "guest CPU which implements the ARM " 3034 "Virtualization Extensions"); 3035 3036 object_class_property_add_bool(oc, "highmem", virt_get_highmem, 3037 virt_set_highmem); 3038 object_class_property_set_description(oc, "highmem", 3039 "Set on/off to enable/disable using " 3040 "physical address space above 32 bits"); 3041 3042 object_class_property_add_bool(oc, "compact-highmem", 3043 virt_get_compact_highmem, 3044 virt_set_compact_highmem); 3045 object_class_property_set_description(oc, "compact-highmem", 3046 "Set on/off to enable/disable compact " 3047 "layout for high memory regions"); 3048 3049 object_class_property_add_bool(oc, "highmem-redists", 3050 virt_get_highmem_redists, 3051 virt_set_highmem_redists); 3052 object_class_property_set_description(oc, "highmem-redists", 3053 "Set on/off to enable/disable high " 3054 "memory region for GICv3 or GICv4 " 3055 "redistributor"); 3056 3057 object_class_property_add_bool(oc, "highmem-ecam", 3058 virt_get_highmem_ecam, 3059 virt_set_highmem_ecam); 3060 object_class_property_set_description(oc, "highmem-ecam", 3061 "Set on/off to enable/disable high " 3062 "memory region for PCI ECAM"); 3063 3064 object_class_property_add_bool(oc, "highmem-mmio", 3065 virt_get_highmem_mmio, 3066 virt_set_highmem_mmio); 3067 object_class_property_set_description(oc, "highmem-mmio", 3068 "Set on/off to enable/disable high " 3069 "memory region for PCI MMIO"); 3070 3071 object_class_property_add_str(oc, "gic-version", virt_get_gic_version, 3072 virt_set_gic_version); 3073 object_class_property_set_description(oc, "gic-version", 3074 "Set GIC version. " 3075 "Valid values are 2, 3, 4, host and max"); 3076 3077 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); 3078 object_class_property_set_description(oc, "iommu", 3079 "Set the IOMMU type. " 3080 "Valid values are none and smmuv3"); 3081 3082 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 3083 virt_get_default_bus_bypass_iommu, 3084 virt_set_default_bus_bypass_iommu); 3085 object_class_property_set_description(oc, "default-bus-bypass-iommu", 3086 "Set on/off to enable/disable " 3087 "bypass_iommu for default root bus"); 3088 3089 object_class_property_add_bool(oc, "ras", virt_get_ras, 3090 virt_set_ras); 3091 object_class_property_set_description(oc, "ras", 3092 "Set on/off to enable/disable reporting host memory errors " 3093 "to a KVM guest using ACPI and guest external abort exceptions"); 3094 3095 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); 3096 object_class_property_set_description(oc, "mte", 3097 "Set on/off to enable/disable emulating a " 3098 "guest CPU which implements the ARM " 3099 "Memory Tagging Extension"); 3100 3101 object_class_property_add_bool(oc, "its", virt_get_its, 3102 virt_set_its); 3103 object_class_property_set_description(oc, "its", 3104 "Set on/off to enable/disable " 3105 "ITS instantiation"); 3106 3107 object_class_property_add_bool(oc, "dtb-randomness", 3108 virt_get_dtb_randomness, 3109 virt_set_dtb_randomness); 3110 object_class_property_set_description(oc, "dtb-randomness", 3111 "Set off to disable passing random or " 3112 "non-deterministic dtb nodes to guest"); 3113 3114 object_class_property_add_bool(oc, "dtb-kaslr-seed", 3115 virt_get_dtb_randomness, 3116 virt_set_dtb_randomness); 3117 object_class_property_set_description(oc, "dtb-kaslr-seed", 3118 "Deprecated synonym of dtb-randomness"); 3119 3120 object_class_property_add_str(oc, "x-oem-id", 3121 virt_get_oem_id, 3122 virt_set_oem_id); 3123 object_class_property_set_description(oc, "x-oem-id", 3124 "Override the default value of field OEMID " 3125 "in ACPI table header." 3126 "The string may be up to 6 bytes in size"); 3127 3128 3129 object_class_property_add_str(oc, "x-oem-table-id", 3130 virt_get_oem_table_id, 3131 virt_set_oem_table_id); 3132 object_class_property_set_description(oc, "x-oem-table-id", 3133 "Override the default value of field OEM Table ID " 3134 "in ACPI table header." 3135 "The string may be up to 8 bytes in size"); 3136 3137 } 3138 3139 static void virt_instance_init(Object *obj) 3140 { 3141 VirtMachineState *vms = VIRT_MACHINE(obj); 3142 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 3143 3144 /* EL3 is disabled by default on virt: this makes us consistent 3145 * between KVM and TCG for this board, and it also allows us to 3146 * boot UEFI blobs which assume no TrustZone support. 3147 */ 3148 vms->secure = false; 3149 3150 /* EL2 is also disabled by default, for similar reasons */ 3151 vms->virt = false; 3152 3153 /* High memory is enabled by default */ 3154 vms->highmem = true; 3155 vms->highmem_compact = !vmc->no_highmem_compact; 3156 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 3157 3158 vms->highmem_ecam = !vmc->no_highmem_ecam; 3159 vms->highmem_mmio = true; 3160 vms->highmem_redists = true; 3161 3162 if (vmc->no_its) { 3163 vms->its = false; 3164 } else { 3165 /* Default allows ITS instantiation */ 3166 vms->its = true; 3167 3168 if (vmc->no_tcg_its) { 3169 vms->tcg_its = false; 3170 } else { 3171 vms->tcg_its = true; 3172 } 3173 } 3174 3175 /* Default disallows iommu instantiation */ 3176 vms->iommu = VIRT_IOMMU_NONE; 3177 3178 /* The default root bus is attached to iommu by default */ 3179 vms->default_bus_bypass_iommu = false; 3180 3181 /* Default disallows RAS instantiation */ 3182 vms->ras = false; 3183 3184 /* MTE is disabled by default. */ 3185 vms->mte = false; 3186 3187 /* Supply kaslr-seed and rng-seed by default */ 3188 vms->dtb_randomness = true; 3189 3190 vms->irqmap = a15irqmap; 3191 3192 virt_flash_create(vms); 3193 3194 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 3195 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 3196 } 3197 3198 static const TypeInfo virt_machine_info = { 3199 .name = TYPE_VIRT_MACHINE, 3200 .parent = TYPE_MACHINE, 3201 .abstract = true, 3202 .instance_size = sizeof(VirtMachineState), 3203 .class_size = sizeof(VirtMachineClass), 3204 .class_init = virt_machine_class_init, 3205 .instance_init = virt_instance_init, 3206 .interfaces = (InterfaceInfo[]) { 3207 { TYPE_HOTPLUG_HANDLER }, 3208 { } 3209 }, 3210 }; 3211 3212 static void machvirt_machine_init(void) 3213 { 3214 type_register_static(&virt_machine_info); 3215 } 3216 type_init(machvirt_machine_init); 3217 3218 static void virt_machine_7_2_options(MachineClass *mc) 3219 { 3220 } 3221 DEFINE_VIRT_MACHINE_AS_LATEST(7, 2) 3222 3223 static void virt_machine_7_1_options(MachineClass *mc) 3224 { 3225 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3226 3227 virt_machine_7_2_options(mc); 3228 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 3229 /* Compact layout for high memory regions was introduced with 7.2 */ 3230 vmc->no_highmem_compact = true; 3231 } 3232 DEFINE_VIRT_MACHINE(7, 1) 3233 3234 static void virt_machine_7_0_options(MachineClass *mc) 3235 { 3236 virt_machine_7_1_options(mc); 3237 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 3238 } 3239 DEFINE_VIRT_MACHINE(7, 0) 3240 3241 static void virt_machine_6_2_options(MachineClass *mc) 3242 { 3243 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3244 3245 virt_machine_7_0_options(mc); 3246 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 3247 vmc->no_tcg_lpa2 = true; 3248 } 3249 DEFINE_VIRT_MACHINE(6, 2) 3250 3251 static void virt_machine_6_1_options(MachineClass *mc) 3252 { 3253 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3254 3255 virt_machine_6_2_options(mc); 3256 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 3257 mc->smp_props.prefer_sockets = true; 3258 vmc->no_cpu_topology = true; 3259 3260 /* qemu ITS was introduced with 6.2 */ 3261 vmc->no_tcg_its = true; 3262 } 3263 DEFINE_VIRT_MACHINE(6, 1) 3264 3265 static void virt_machine_6_0_options(MachineClass *mc) 3266 { 3267 virt_machine_6_1_options(mc); 3268 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 3269 } 3270 DEFINE_VIRT_MACHINE(6, 0) 3271 3272 static void virt_machine_5_2_options(MachineClass *mc) 3273 { 3274 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3275 3276 virt_machine_6_0_options(mc); 3277 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 3278 vmc->no_secure_gpio = true; 3279 } 3280 DEFINE_VIRT_MACHINE(5, 2) 3281 3282 static void virt_machine_5_1_options(MachineClass *mc) 3283 { 3284 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3285 3286 virt_machine_5_2_options(mc); 3287 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 3288 vmc->no_kvm_steal_time = true; 3289 } 3290 DEFINE_VIRT_MACHINE(5, 1) 3291 3292 static void virt_machine_5_0_options(MachineClass *mc) 3293 { 3294 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3295 3296 virt_machine_5_1_options(mc); 3297 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 3298 mc->numa_mem_supported = true; 3299 vmc->acpi_expose_flash = true; 3300 mc->auto_enable_numa_with_memdev = false; 3301 } 3302 DEFINE_VIRT_MACHINE(5, 0) 3303 3304 static void virt_machine_4_2_options(MachineClass *mc) 3305 { 3306 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3307 3308 virt_machine_5_0_options(mc); 3309 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 3310 vmc->kvm_no_adjvtime = true; 3311 } 3312 DEFINE_VIRT_MACHINE(4, 2) 3313 3314 static void virt_machine_4_1_options(MachineClass *mc) 3315 { 3316 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3317 3318 virt_machine_4_2_options(mc); 3319 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 3320 vmc->no_ged = true; 3321 mc->auto_enable_numa_with_memhp = false; 3322 } 3323 DEFINE_VIRT_MACHINE(4, 1) 3324 3325 static void virt_machine_4_0_options(MachineClass *mc) 3326 { 3327 virt_machine_4_1_options(mc); 3328 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 3329 } 3330 DEFINE_VIRT_MACHINE(4, 0) 3331 3332 static void virt_machine_3_1_options(MachineClass *mc) 3333 { 3334 virt_machine_4_0_options(mc); 3335 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 3336 } 3337 DEFINE_VIRT_MACHINE(3, 1) 3338 3339 static void virt_machine_3_0_options(MachineClass *mc) 3340 { 3341 virt_machine_3_1_options(mc); 3342 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 3343 } 3344 DEFINE_VIRT_MACHINE(3, 0) 3345 3346 static void virt_machine_2_12_options(MachineClass *mc) 3347 { 3348 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3349 3350 virt_machine_3_0_options(mc); 3351 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 3352 vmc->no_highmem_ecam = true; 3353 mc->max_cpus = 255; 3354 } 3355 DEFINE_VIRT_MACHINE(2, 12) 3356 3357 static void virt_machine_2_11_options(MachineClass *mc) 3358 { 3359 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3360 3361 virt_machine_2_12_options(mc); 3362 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 3363 vmc->smbios_old_sys_ver = true; 3364 } 3365 DEFINE_VIRT_MACHINE(2, 11) 3366 3367 static void virt_machine_2_10_options(MachineClass *mc) 3368 { 3369 virt_machine_2_11_options(mc); 3370 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 3371 /* before 2.11 we never faulted accesses to bad addresses */ 3372 mc->ignore_memory_transaction_failures = true; 3373 } 3374 DEFINE_VIRT_MACHINE(2, 10) 3375 3376 static void virt_machine_2_9_options(MachineClass *mc) 3377 { 3378 virt_machine_2_10_options(mc); 3379 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 3380 } 3381 DEFINE_VIRT_MACHINE(2, 9) 3382 3383 static void virt_machine_2_8_options(MachineClass *mc) 3384 { 3385 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3386 3387 virt_machine_2_9_options(mc); 3388 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 3389 /* For 2.8 and earlier we falsely claimed in the DT that 3390 * our timers were edge-triggered, not level-triggered. 3391 */ 3392 vmc->claim_edge_triggered_timers = true; 3393 } 3394 DEFINE_VIRT_MACHINE(2, 8) 3395 3396 static void virt_machine_2_7_options(MachineClass *mc) 3397 { 3398 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3399 3400 virt_machine_2_8_options(mc); 3401 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 3402 /* ITS was introduced with 2.8 */ 3403 vmc->no_its = true; 3404 /* Stick with 1K pages for migration compatibility */ 3405 mc->minimum_page_bits = 0; 3406 } 3407 DEFINE_VIRT_MACHINE(2, 7) 3408 3409 static void virt_machine_2_6_options(MachineClass *mc) 3410 { 3411 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3412 3413 virt_machine_2_7_options(mc); 3414 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 3415 vmc->disallow_affinity_adjustment = true; 3416 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 3417 vmc->no_pmu = true; 3418 } 3419 DEFINE_VIRT_MACHINE(2, 6) 3420