1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/datadir.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "qapi/error.h" 37 #include "hw/sysbus.h" 38 #include "hw/arm/boot.h" 39 #include "hw/arm/primecell.h" 40 #include "hw/arm/virt.h" 41 #include "hw/block/flash.h" 42 #include "hw/vfio/vfio-calxeda-xgmac.h" 43 #include "hw/vfio/vfio-amd-xgbe.h" 44 #include "hw/display/ramfb.h" 45 #include "net/net.h" 46 #include "sysemu/device_tree.h" 47 #include "sysemu/numa.h" 48 #include "sysemu/runstate.h" 49 #include "sysemu/tpm.h" 50 #include "sysemu/tcg.h" 51 #include "sysemu/kvm.h" 52 #include "sysemu/hvf.h" 53 #include "sysemu/qtest.h" 54 #include "hw/loader.h" 55 #include "qapi/error.h" 56 #include "qemu/bitops.h" 57 #include "qemu/error-report.h" 58 #include "qemu/module.h" 59 #include "hw/pci-host/gpex.h" 60 #include "hw/virtio/virtio-pci.h" 61 #include "hw/core/sysbus-fdt.h" 62 #include "hw/platform-bus.h" 63 #include "hw/qdev-properties.h" 64 #include "hw/arm/fdt.h" 65 #include "hw/intc/arm_gic.h" 66 #include "hw/intc/arm_gicv3_common.h" 67 #include "hw/irq.h" 68 #include "kvm_arm.h" 69 #include "hw/firmware/smbios.h" 70 #include "qapi/visitor.h" 71 #include "qapi/qapi-visit-common.h" 72 #include "standard-headers/linux/input.h" 73 #include "hw/arm/smmuv3.h" 74 #include "hw/acpi/acpi.h" 75 #include "target/arm/internals.h" 76 #include "hw/mem/memory-device.h" 77 #include "hw/mem/pc-dimm.h" 78 #include "hw/mem/nvdimm.h" 79 #include "hw/acpi/generic_event_device.h" 80 #include "hw/virtio/virtio-mem-pci.h" 81 #include "hw/virtio/virtio-iommu.h" 82 #include "hw/char/pl011.h" 83 #include "qemu/guest-random.h" 84 85 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 86 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 87 void *data) \ 88 { \ 89 MachineClass *mc = MACHINE_CLASS(oc); \ 90 virt_machine_##major##_##minor##_options(mc); \ 91 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 92 if (latest) { \ 93 mc->alias = "virt"; \ 94 } \ 95 } \ 96 static const TypeInfo machvirt_##major##_##minor##_info = { \ 97 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 98 .parent = TYPE_VIRT_MACHINE, \ 99 .class_init = virt_##major##_##minor##_class_init, \ 100 }; \ 101 static void machvirt_machine_##major##_##minor##_init(void) \ 102 { \ 103 type_register_static(&machvirt_##major##_##minor##_info); \ 104 } \ 105 type_init(machvirt_machine_##major##_##minor##_init); 106 107 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 108 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 109 #define DEFINE_VIRT_MACHINE(major, minor) \ 110 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 111 112 113 /* Number of external interrupt lines to configure the GIC with */ 114 #define NUM_IRQS 256 115 116 #define PLATFORM_BUS_NUM_IRQS 64 117 118 /* Legacy RAM limit in GB (< version 4.0) */ 119 #define LEGACY_RAMLIMIT_GB 255 120 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 121 122 /* Addresses and sizes of our components. 123 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 124 * 128MB..256MB is used for miscellaneous device I/O. 125 * 256MB..1GB is reserved for possible future PCI support (ie where the 126 * PCI memory window will go if we add a PCI host controller). 127 * 1GB and up is RAM (which may happily spill over into the 128 * high memory region beyond 4GB). 129 * This represents a compromise between how much RAM can be given to 130 * a 32 bit VM and leaving space for expansion and in particular for PCI. 131 * Note that devices should generally be placed at multiples of 0x10000, 132 * to accommodate guests using 64K pages. 133 */ 134 static const MemMapEntry base_memmap[] = { 135 /* Space up to 0x8000000 is reserved for a boot ROM */ 136 [VIRT_FLASH] = { 0, 0x08000000 }, 137 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 138 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 139 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 140 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 141 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 142 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 143 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 144 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 145 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 146 /* This redistributor space allows up to 2*64kB*123 CPUs */ 147 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 148 [VIRT_UART] = { 0x09000000, 0x00001000 }, 149 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 150 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 151 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 152 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 153 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 154 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 155 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 156 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 157 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, 158 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, 159 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 160 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 161 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 162 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 163 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 164 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 165 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 166 /* Actual RAM size depends on initial RAM and device memory settings */ 167 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 168 }; 169 170 /* 171 * Highmem IO Regions: This memory map is floating, located after the RAM. 172 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 173 * top of the RAM, so that its base get the same alignment as the size, 174 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 175 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 176 * Note the extended_memmap is sized so that it eventually also includes the 177 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 178 * index of base_memmap). 179 * 180 * The memory map for these Highmem IO Regions can be in legacy or compact 181 * layout, depending on 'compact-highmem' property. With legacy layout, the 182 * PA space for one specific region is always reserved, even if the region 183 * has been disabled or doesn't fit into the PA space. However, the PA space 184 * for the region won't be reserved in these circumstances with compact layout. 185 */ 186 static MemMapEntry extended_memmap[] = { 187 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 188 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 189 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 190 /* Second PCIe window */ 191 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 192 }; 193 194 static const int a15irqmap[] = { 195 [VIRT_UART] = 1, 196 [VIRT_RTC] = 2, 197 [VIRT_PCIE] = 3, /* ... to 6 */ 198 [VIRT_GPIO] = 7, 199 [VIRT_SECURE_UART] = 8, 200 [VIRT_ACPI_GED] = 9, 201 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 202 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 203 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 204 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 205 }; 206 207 static const char *valid_cpus[] = { 208 ARM_CPU_TYPE_NAME("cortex-a7"), 209 ARM_CPU_TYPE_NAME("cortex-a15"), 210 ARM_CPU_TYPE_NAME("cortex-a35"), 211 ARM_CPU_TYPE_NAME("cortex-a53"), 212 ARM_CPU_TYPE_NAME("cortex-a55"), 213 ARM_CPU_TYPE_NAME("cortex-a57"), 214 ARM_CPU_TYPE_NAME("cortex-a72"), 215 ARM_CPU_TYPE_NAME("cortex-a76"), 216 ARM_CPU_TYPE_NAME("a64fx"), 217 ARM_CPU_TYPE_NAME("neoverse-n1"), 218 ARM_CPU_TYPE_NAME("host"), 219 ARM_CPU_TYPE_NAME("max"), 220 }; 221 222 static bool cpu_type_valid(const char *cpu) 223 { 224 int i; 225 226 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 227 if (strcmp(cpu, valid_cpus[i]) == 0) { 228 return true; 229 } 230 } 231 return false; 232 } 233 234 static void create_randomness(MachineState *ms, const char *node) 235 { 236 struct { 237 uint64_t kaslr; 238 uint8_t rng[32]; 239 } seed; 240 241 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { 242 return; 243 } 244 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr); 245 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); 246 } 247 248 static void create_fdt(VirtMachineState *vms) 249 { 250 MachineState *ms = MACHINE(vms); 251 int nb_numa_nodes = ms->numa_state->num_nodes; 252 void *fdt = create_device_tree(&vms->fdt_size); 253 254 if (!fdt) { 255 error_report("create_device_tree() failed"); 256 exit(1); 257 } 258 259 ms->fdt = fdt; 260 261 /* Header */ 262 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 263 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 264 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 265 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt"); 266 267 /* /chosen must exist for load_dtb to fill in necessary properties later */ 268 qemu_fdt_add_subnode(fdt, "/chosen"); 269 if (vms->dtb_randomness) { 270 create_randomness(ms, "/chosen"); 271 } 272 273 if (vms->secure) { 274 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 275 if (vms->dtb_randomness) { 276 create_randomness(ms, "/secure-chosen"); 277 } 278 } 279 280 /* Clock node, for the benefit of the UART. The kernel device tree 281 * binding documentation claims the PL011 node clock properties are 282 * optional but in practice if you omit them the kernel refuses to 283 * probe for the device. 284 */ 285 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 286 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 287 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 288 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 289 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 290 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 291 "clk24mhz"); 292 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 293 294 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 295 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 296 uint32_t *matrix = g_malloc0(size); 297 int idx, i, j; 298 299 for (i = 0; i < nb_numa_nodes; i++) { 300 for (j = 0; j < nb_numa_nodes; j++) { 301 idx = (i * nb_numa_nodes + j) * 3; 302 matrix[idx + 0] = cpu_to_be32(i); 303 matrix[idx + 1] = cpu_to_be32(j); 304 matrix[idx + 2] = 305 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 306 } 307 } 308 309 qemu_fdt_add_subnode(fdt, "/distance-map"); 310 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 311 "numa-distance-map-v1"); 312 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 313 matrix, size); 314 g_free(matrix); 315 } 316 } 317 318 static void fdt_add_timer_nodes(const VirtMachineState *vms) 319 { 320 /* On real hardware these interrupts are level-triggered. 321 * On KVM they were edge-triggered before host kernel version 4.4, 322 * and level-triggered afterwards. 323 * On emulated QEMU they are level-triggered. 324 * 325 * Getting the DTB info about them wrong is awkward for some 326 * guest kernels: 327 * pre-4.8 ignore the DT and leave the interrupt configured 328 * with whatever the GIC reset value (or the bootloader) left it at 329 * 4.8 before rc6 honour the incorrect data by programming it back 330 * into the GIC, causing problems 331 * 4.8rc6 and later ignore the DT and always write "level triggered" 332 * into the GIC 333 * 334 * For backwards-compatibility, virt-2.8 and earlier will continue 335 * to say these are edge-triggered, but later machines will report 336 * the correct information. 337 */ 338 ARMCPU *armcpu; 339 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 340 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 341 MachineState *ms = MACHINE(vms); 342 343 if (vmc->claim_edge_triggered_timers) { 344 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 345 } 346 347 if (vms->gic_version == VIRT_GIC_VERSION_2) { 348 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 349 GIC_FDT_IRQ_PPI_CPU_WIDTH, 350 (1 << MACHINE(vms)->smp.cpus) - 1); 351 } 352 353 qemu_fdt_add_subnode(ms->fdt, "/timer"); 354 355 armcpu = ARM_CPU(qemu_get_cpu(0)); 356 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 357 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 358 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", 359 compat, sizeof(compat)); 360 } else { 361 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", 362 "arm,armv7-timer"); 363 } 364 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); 365 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 366 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 367 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 368 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 369 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 370 } 371 372 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 373 { 374 int cpu; 375 int addr_cells = 1; 376 const MachineState *ms = MACHINE(vms); 377 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 378 int smp_cpus = ms->smp.cpus; 379 380 /* 381 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml 382 * On ARM v8 64-bit systems value should be set to 2, 383 * that corresponds to the MPIDR_EL1 register size. 384 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 385 * in the system, #address-cells can be set to 1, since 386 * MPIDR_EL1[63:32] bits are not used for CPUs 387 * identification. 388 * 389 * Here we actually don't know whether our system is 32- or 64-bit one. 390 * The simplest way to go is to examine affinity IDs of all our CPUs. If 391 * at least one of them has Aff3 populated, we set #address-cells to 2. 392 */ 393 for (cpu = 0; cpu < smp_cpus; cpu++) { 394 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 395 396 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 397 addr_cells = 2; 398 break; 399 } 400 } 401 402 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 403 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); 404 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 405 406 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 407 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 408 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 409 CPUState *cs = CPU(armcpu); 410 411 qemu_fdt_add_subnode(ms->fdt, nodename); 412 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 413 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 414 armcpu->dtb_compatible); 415 416 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { 417 qemu_fdt_setprop_string(ms->fdt, nodename, 418 "enable-method", "psci"); 419 } 420 421 if (addr_cells == 2) { 422 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", 423 armcpu->mp_affinity); 424 } else { 425 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", 426 armcpu->mp_affinity); 427 } 428 429 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 430 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 431 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 432 } 433 434 if (!vmc->no_cpu_topology) { 435 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 436 qemu_fdt_alloc_phandle(ms->fdt)); 437 } 438 439 g_free(nodename); 440 } 441 442 if (!vmc->no_cpu_topology) { 443 /* 444 * Add vCPU topology description through fdt node cpu-map. 445 * 446 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt 447 * In a SMP system, the hierarchy of CPUs can be defined through 448 * four entities that are used to describe the layout of CPUs in 449 * the system: socket/cluster/core/thread. 450 * 451 * A socket node represents the boundary of system physical package 452 * and its child nodes must be one or more cluster nodes. A system 453 * can contain several layers of clustering within a single physical 454 * package and cluster nodes can be contained in parent cluster nodes. 455 * 456 * Note: currently we only support one layer of clustering within 457 * each physical package. 458 */ 459 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 460 461 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 462 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); 463 char *map_path; 464 465 if (ms->smp.threads > 1) { 466 map_path = g_strdup_printf( 467 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", 468 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), 469 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, 470 (cpu / ms->smp.threads) % ms->smp.cores, 471 cpu % ms->smp.threads); 472 } else { 473 map_path = g_strdup_printf( 474 "/cpus/cpu-map/socket%d/cluster%d/core%d", 475 cpu / (ms->smp.clusters * ms->smp.cores), 476 (cpu / ms->smp.cores) % ms->smp.clusters, 477 cpu % ms->smp.cores); 478 } 479 qemu_fdt_add_path(ms->fdt, map_path); 480 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 481 482 g_free(map_path); 483 g_free(cpu_path); 484 } 485 } 486 } 487 488 static void fdt_add_its_gic_node(VirtMachineState *vms) 489 { 490 char *nodename; 491 MachineState *ms = MACHINE(vms); 492 493 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 494 nodename = g_strdup_printf("/intc/its@%" PRIx64, 495 vms->memmap[VIRT_GIC_ITS].base); 496 qemu_fdt_add_subnode(ms->fdt, nodename); 497 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 498 "arm,gic-v3-its"); 499 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 500 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1); 501 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 502 2, vms->memmap[VIRT_GIC_ITS].base, 503 2, vms->memmap[VIRT_GIC_ITS].size); 504 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 505 g_free(nodename); 506 } 507 508 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 509 { 510 MachineState *ms = MACHINE(vms); 511 char *nodename; 512 513 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 514 vms->memmap[VIRT_GIC_V2M].base); 515 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 516 qemu_fdt_add_subnode(ms->fdt, nodename); 517 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 518 "arm,gic-v2m-frame"); 519 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 520 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 521 2, vms->memmap[VIRT_GIC_V2M].base, 522 2, vms->memmap[VIRT_GIC_V2M].size); 523 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 524 g_free(nodename); 525 } 526 527 static void fdt_add_gic_node(VirtMachineState *vms) 528 { 529 MachineState *ms = MACHINE(vms); 530 char *nodename; 531 532 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 533 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); 534 535 nodename = g_strdup_printf("/intc@%" PRIx64, 536 vms->memmap[VIRT_GIC_DIST].base); 537 qemu_fdt_add_subnode(ms->fdt, nodename); 538 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 539 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 540 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 541 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 542 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 543 if (vms->gic_version != VIRT_GIC_VERSION_2) { 544 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 545 546 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 547 "arm,gic-v3"); 548 549 qemu_fdt_setprop_cell(ms->fdt, nodename, 550 "#redistributor-regions", nb_redist_regions); 551 552 if (nb_redist_regions == 1) { 553 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 554 2, vms->memmap[VIRT_GIC_DIST].base, 555 2, vms->memmap[VIRT_GIC_DIST].size, 556 2, vms->memmap[VIRT_GIC_REDIST].base, 557 2, vms->memmap[VIRT_GIC_REDIST].size); 558 } else { 559 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 560 2, vms->memmap[VIRT_GIC_DIST].base, 561 2, vms->memmap[VIRT_GIC_DIST].size, 562 2, vms->memmap[VIRT_GIC_REDIST].base, 563 2, vms->memmap[VIRT_GIC_REDIST].size, 564 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 565 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 566 } 567 568 if (vms->virt) { 569 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 570 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 571 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 572 } 573 } else { 574 /* 'cortex-a15-gic' means 'GIC v2' */ 575 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 576 "arm,cortex-a15-gic"); 577 if (!vms->virt) { 578 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 579 2, vms->memmap[VIRT_GIC_DIST].base, 580 2, vms->memmap[VIRT_GIC_DIST].size, 581 2, vms->memmap[VIRT_GIC_CPU].base, 582 2, vms->memmap[VIRT_GIC_CPU].size); 583 } else { 584 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 585 2, vms->memmap[VIRT_GIC_DIST].base, 586 2, vms->memmap[VIRT_GIC_DIST].size, 587 2, vms->memmap[VIRT_GIC_CPU].base, 588 2, vms->memmap[VIRT_GIC_CPU].size, 589 2, vms->memmap[VIRT_GIC_HYP].base, 590 2, vms->memmap[VIRT_GIC_HYP].size, 591 2, vms->memmap[VIRT_GIC_VCPU].base, 592 2, vms->memmap[VIRT_GIC_VCPU].size); 593 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 594 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 595 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 596 } 597 } 598 599 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); 600 g_free(nodename); 601 } 602 603 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 604 { 605 ARMCPU *armcpu = ARM_CPU(first_cpu); 606 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 607 MachineState *ms = MACHINE(vms); 608 609 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 610 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); 611 return; 612 } 613 614 if (vms->gic_version == VIRT_GIC_VERSION_2) { 615 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 616 GIC_FDT_IRQ_PPI_CPU_WIDTH, 617 (1 << MACHINE(vms)->smp.cpus) - 1); 618 } 619 620 qemu_fdt_add_subnode(ms->fdt, "/pmu"); 621 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 622 const char compat[] = "arm,armv8-pmuv3"; 623 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", 624 compat, sizeof(compat)); 625 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", 626 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 627 } 628 } 629 630 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 631 { 632 DeviceState *dev; 633 MachineState *ms = MACHINE(vms); 634 int irq = vms->irqmap[VIRT_ACPI_GED]; 635 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 636 637 if (ms->ram_slots) { 638 event |= ACPI_GED_MEM_HOTPLUG_EVT; 639 } 640 641 if (ms->nvdimms_state->is_enabled) { 642 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 643 } 644 645 dev = qdev_new(TYPE_ACPI_GED); 646 qdev_prop_set_uint32(dev, "ged-event", event); 647 648 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 649 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 650 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 651 652 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 653 654 return dev; 655 } 656 657 static void create_its(VirtMachineState *vms) 658 { 659 const char *itsclass = its_class_name(); 660 DeviceState *dev; 661 662 if (!strcmp(itsclass, "arm-gicv3-its")) { 663 if (!vms->tcg_its) { 664 itsclass = NULL; 665 } 666 } 667 668 if (!itsclass) { 669 /* Do nothing if not supported */ 670 return; 671 } 672 673 dev = qdev_new(itsclass); 674 675 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 676 &error_abort); 677 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 678 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 679 680 fdt_add_its_gic_node(vms); 681 vms->msi_controller = VIRT_MSI_CTRL_ITS; 682 } 683 684 static void create_v2m(VirtMachineState *vms) 685 { 686 int i; 687 int irq = vms->irqmap[VIRT_GIC_V2M]; 688 DeviceState *dev; 689 690 dev = qdev_new("arm-gicv2m"); 691 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 692 qdev_prop_set_uint32(dev, "base-spi", irq); 693 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 694 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 695 696 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 697 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 698 qdev_get_gpio_in(vms->gic, irq + i)); 699 } 700 701 fdt_add_v2m_gic_node(vms); 702 vms->msi_controller = VIRT_MSI_CTRL_GICV2M; 703 } 704 705 static void create_gic(VirtMachineState *vms, MemoryRegion *mem) 706 { 707 MachineState *ms = MACHINE(vms); 708 /* We create a standalone GIC */ 709 SysBusDevice *gicbusdev; 710 const char *gictype; 711 int i; 712 unsigned int smp_cpus = ms->smp.cpus; 713 uint32_t nb_redist_regions = 0; 714 int revision; 715 716 if (vms->gic_version == VIRT_GIC_VERSION_2) { 717 gictype = gic_class_name(); 718 } else { 719 gictype = gicv3_class_name(); 720 } 721 722 switch (vms->gic_version) { 723 case VIRT_GIC_VERSION_2: 724 revision = 2; 725 break; 726 case VIRT_GIC_VERSION_3: 727 revision = 3; 728 break; 729 case VIRT_GIC_VERSION_4: 730 revision = 4; 731 break; 732 default: 733 g_assert_not_reached(); 734 } 735 vms->gic = qdev_new(gictype); 736 qdev_prop_set_uint32(vms->gic, "revision", revision); 737 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 738 /* Note that the num-irq property counts both internal and external 739 * interrupts; there are always 32 of the former (mandated by GIC spec). 740 */ 741 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 742 if (!kvm_irqchip_in_kernel()) { 743 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 744 } 745 746 if (vms->gic_version != VIRT_GIC_VERSION_2) { 747 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); 748 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 749 750 nb_redist_regions = virt_gicv3_redist_region_count(vms); 751 752 qdev_prop_set_uint32(vms->gic, "len-redist-region-count", 753 nb_redist_regions); 754 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count); 755 756 if (!kvm_irqchip_in_kernel()) { 757 if (vms->tcg_its) { 758 object_property_set_link(OBJECT(vms->gic), "sysmem", 759 OBJECT(mem), &error_fatal); 760 qdev_prop_set_bit(vms->gic, "has-lpi", true); 761 } 762 } 763 764 if (nb_redist_regions == 2) { 765 uint32_t redist1_capacity = 766 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 767 768 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", 769 MIN(smp_cpus - redist0_count, redist1_capacity)); 770 } 771 } else { 772 if (!kvm_irqchip_in_kernel()) { 773 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 774 vms->virt); 775 } 776 } 777 gicbusdev = SYS_BUS_DEVICE(vms->gic); 778 sysbus_realize_and_unref(gicbusdev, &error_fatal); 779 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 780 if (vms->gic_version != VIRT_GIC_VERSION_2) { 781 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 782 if (nb_redist_regions == 2) { 783 sysbus_mmio_map(gicbusdev, 2, 784 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 785 } 786 } else { 787 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 788 if (vms->virt) { 789 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 790 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 791 } 792 } 793 794 /* Wire the outputs from each CPU's generic timer and the GICv3 795 * maintenance interrupt signal to the appropriate GIC PPI inputs, 796 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 797 */ 798 for (i = 0; i < smp_cpus; i++) { 799 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 800 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 801 int irq; 802 /* Mapping from the output timer irq lines from the CPU to the 803 * GIC PPI inputs we use for the virt board. 804 */ 805 const int timer_irq[] = { 806 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 807 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 808 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 809 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 810 }; 811 812 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 813 qdev_connect_gpio_out(cpudev, irq, 814 qdev_get_gpio_in(vms->gic, 815 ppibase + timer_irq[irq])); 816 } 817 818 if (vms->gic_version != VIRT_GIC_VERSION_2) { 819 qemu_irq irq = qdev_get_gpio_in(vms->gic, 820 ppibase + ARCH_GIC_MAINT_IRQ); 821 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 822 0, irq); 823 } else if (vms->virt) { 824 qemu_irq irq = qdev_get_gpio_in(vms->gic, 825 ppibase + ARCH_GIC_MAINT_IRQ); 826 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 827 } 828 829 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 830 qdev_get_gpio_in(vms->gic, ppibase 831 + VIRTUAL_PMU_IRQ)); 832 833 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 834 sysbus_connect_irq(gicbusdev, i + smp_cpus, 835 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 836 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 837 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 838 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 839 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 840 } 841 842 fdt_add_gic_node(vms); 843 844 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) { 845 create_its(vms); 846 } else if (vms->gic_version == VIRT_GIC_VERSION_2) { 847 create_v2m(vms); 848 } 849 } 850 851 static void create_uart(const VirtMachineState *vms, int uart, 852 MemoryRegion *mem, Chardev *chr) 853 { 854 char *nodename; 855 hwaddr base = vms->memmap[uart].base; 856 hwaddr size = vms->memmap[uart].size; 857 int irq = vms->irqmap[uart]; 858 const char compat[] = "arm,pl011\0arm,primecell"; 859 const char clocknames[] = "uartclk\0apb_pclk"; 860 DeviceState *dev = qdev_new(TYPE_PL011); 861 SysBusDevice *s = SYS_BUS_DEVICE(dev); 862 MachineState *ms = MACHINE(vms); 863 864 qdev_prop_set_chr(dev, "chardev", chr); 865 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 866 memory_region_add_subregion(mem, base, 867 sysbus_mmio_get_region(s, 0)); 868 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 869 870 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 871 qemu_fdt_add_subnode(ms->fdt, nodename); 872 /* Note that we can't use setprop_string because of the embedded NUL */ 873 qemu_fdt_setprop(ms->fdt, nodename, "compatible", 874 compat, sizeof(compat)); 875 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 876 2, base, 2, size); 877 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 878 GIC_FDT_IRQ_TYPE_SPI, irq, 879 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 880 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", 881 vms->clock_phandle, vms->clock_phandle); 882 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", 883 clocknames, sizeof(clocknames)); 884 885 if (uart == VIRT_UART) { 886 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 887 } else { 888 /* Mark as not usable by the normal world */ 889 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 890 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 891 892 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", 893 nodename); 894 } 895 896 g_free(nodename); 897 } 898 899 static void create_rtc(const VirtMachineState *vms) 900 { 901 char *nodename; 902 hwaddr base = vms->memmap[VIRT_RTC].base; 903 hwaddr size = vms->memmap[VIRT_RTC].size; 904 int irq = vms->irqmap[VIRT_RTC]; 905 const char compat[] = "arm,pl031\0arm,primecell"; 906 MachineState *ms = MACHINE(vms); 907 908 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 909 910 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 911 qemu_fdt_add_subnode(ms->fdt, nodename); 912 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 913 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 914 2, base, 2, size); 915 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 916 GIC_FDT_IRQ_TYPE_SPI, irq, 917 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 918 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 919 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 920 g_free(nodename); 921 } 922 923 static DeviceState *gpio_key_dev; 924 static void virt_powerdown_req(Notifier *n, void *opaque) 925 { 926 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 927 928 if (s->acpi_dev) { 929 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 930 } else { 931 /* use gpio Pin 3 for power button event */ 932 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 933 } 934 } 935 936 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, 937 uint32_t phandle) 938 { 939 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 940 qdev_get_gpio_in(pl061_dev, 3)); 941 942 qemu_fdt_add_subnode(fdt, "/gpio-keys"); 943 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); 944 945 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); 946 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", 947 "label", "GPIO Key Poweroff"); 948 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", 949 KEY_POWER); 950 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", 951 "gpios", phandle, 3, 0); 952 } 953 954 #define SECURE_GPIO_POWEROFF 0 955 #define SECURE_GPIO_RESET 1 956 957 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, 958 uint32_t phandle) 959 { 960 DeviceState *gpio_pwr_dev; 961 962 /* gpio-pwr */ 963 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); 964 965 /* connect secure pl061 to gpio-pwr */ 966 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, 967 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); 968 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, 969 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); 970 971 qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); 972 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", 973 "gpio-poweroff"); 974 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", 975 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); 976 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); 977 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", 978 "okay"); 979 980 qemu_fdt_add_subnode(fdt, "/gpio-restart"); 981 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", 982 "gpio-restart"); 983 qemu_fdt_setprop_cells(fdt, "/gpio-restart", 984 "gpios", phandle, SECURE_GPIO_RESET, 0); 985 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); 986 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", 987 "okay"); 988 } 989 990 static void create_gpio_devices(const VirtMachineState *vms, int gpio, 991 MemoryRegion *mem) 992 { 993 char *nodename; 994 DeviceState *pl061_dev; 995 hwaddr base = vms->memmap[gpio].base; 996 hwaddr size = vms->memmap[gpio].size; 997 int irq = vms->irqmap[gpio]; 998 const char compat[] = "arm,pl061\0arm,primecell"; 999 SysBusDevice *s; 1000 MachineState *ms = MACHINE(vms); 1001 1002 pl061_dev = qdev_new("pl061"); 1003 /* Pull lines down to 0 if not driven by the PL061 */ 1004 qdev_prop_set_uint32(pl061_dev, "pullups", 0); 1005 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); 1006 s = SYS_BUS_DEVICE(pl061_dev); 1007 sysbus_realize_and_unref(s, &error_fatal); 1008 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); 1009 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 1010 1011 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); 1012 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 1013 qemu_fdt_add_subnode(ms->fdt, nodename); 1014 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1015 2, base, 2, size); 1016 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 1017 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); 1018 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); 1019 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1020 GIC_FDT_IRQ_TYPE_SPI, irq, 1021 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1022 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1023 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1024 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); 1025 1026 if (gpio != VIRT_GPIO) { 1027 /* Mark as not usable by the normal world */ 1028 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1029 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1030 } 1031 g_free(nodename); 1032 1033 /* Child gpio devices */ 1034 if (gpio == VIRT_GPIO) { 1035 create_gpio_keys(ms->fdt, pl061_dev, phandle); 1036 } else { 1037 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); 1038 } 1039 } 1040 1041 static void create_virtio_devices(const VirtMachineState *vms) 1042 { 1043 int i; 1044 hwaddr size = vms->memmap[VIRT_MMIO].size; 1045 MachineState *ms = MACHINE(vms); 1046 1047 /* We create the transports in forwards order. Since qbus_realize() 1048 * prepends (not appends) new child buses, the incrementing loop below will 1049 * create a list of virtio-mmio buses with decreasing base addresses. 1050 * 1051 * When a -device option is processed from the command line, 1052 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 1053 * order. The upshot is that -device options in increasing command line 1054 * order are mapped to virtio-mmio buses with decreasing base addresses. 1055 * 1056 * When this code was originally written, that arrangement ensured that the 1057 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 1058 * the first -device on the command line. (The end-to-end order is a 1059 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 1060 * guest kernel's name-to-address assignment strategy.) 1061 * 1062 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 1063 * the message, if not necessarily the code, of commit 70161ff336. 1064 * Therefore the loop now establishes the inverse of the original intent. 1065 * 1066 * Unfortunately, we can't counteract the kernel change by reversing the 1067 * loop; it would break existing command lines. 1068 * 1069 * In any case, the kernel makes no guarantee about the stability of 1070 * enumeration order of virtio devices (as demonstrated by it changing 1071 * between kernel versions). For reliable and stable identification 1072 * of disks users must use UUIDs or similar mechanisms. 1073 */ 1074 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 1075 int irq = vms->irqmap[VIRT_MMIO] + i; 1076 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1077 1078 sysbus_create_simple("virtio-mmio", base, 1079 qdev_get_gpio_in(vms->gic, irq)); 1080 } 1081 1082 /* We add dtb nodes in reverse order so that they appear in the finished 1083 * device tree lowest address first. 1084 * 1085 * Note that this mapping is independent of the loop above. The previous 1086 * loop influences virtio device to virtio transport assignment, whereas 1087 * this loop controls how virtio transports are laid out in the dtb. 1088 */ 1089 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 1090 char *nodename; 1091 int irq = vms->irqmap[VIRT_MMIO] + i; 1092 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1093 1094 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 1095 qemu_fdt_add_subnode(ms->fdt, nodename); 1096 qemu_fdt_setprop_string(ms->fdt, nodename, 1097 "compatible", "virtio,mmio"); 1098 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1099 2, base, 2, size); 1100 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1101 GIC_FDT_IRQ_TYPE_SPI, irq, 1102 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1103 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1104 g_free(nodename); 1105 } 1106 } 1107 1108 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 1109 1110 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 1111 const char *name, 1112 const char *alias_prop_name) 1113 { 1114 /* 1115 * Create a single flash device. We use the same parameters as 1116 * the flash devices on the Versatile Express board. 1117 */ 1118 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 1119 1120 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 1121 qdev_prop_set_uint8(dev, "width", 4); 1122 qdev_prop_set_uint8(dev, "device-width", 2); 1123 qdev_prop_set_bit(dev, "big-endian", false); 1124 qdev_prop_set_uint16(dev, "id0", 0x89); 1125 qdev_prop_set_uint16(dev, "id1", 0x18); 1126 qdev_prop_set_uint16(dev, "id2", 0x00); 1127 qdev_prop_set_uint16(dev, "id3", 0x00); 1128 qdev_prop_set_string(dev, "name", name); 1129 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 1130 object_property_add_alias(OBJECT(vms), alias_prop_name, 1131 OBJECT(dev), "drive"); 1132 return PFLASH_CFI01(dev); 1133 } 1134 1135 static void virt_flash_create(VirtMachineState *vms) 1136 { 1137 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 1138 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 1139 } 1140 1141 static void virt_flash_map1(PFlashCFI01 *flash, 1142 hwaddr base, hwaddr size, 1143 MemoryRegion *sysmem) 1144 { 1145 DeviceState *dev = DEVICE(flash); 1146 1147 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 1148 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 1149 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 1150 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1151 1152 memory_region_add_subregion(sysmem, base, 1153 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1154 0)); 1155 } 1156 1157 static void virt_flash_map(VirtMachineState *vms, 1158 MemoryRegion *sysmem, 1159 MemoryRegion *secure_sysmem) 1160 { 1161 /* 1162 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 1163 * sysmem is the system memory space. secure_sysmem is the secure view 1164 * of the system, and the first flash device should be made visible only 1165 * there. The second flash device is visible to both secure and nonsecure. 1166 * If sysmem == secure_sysmem this means there is no separate Secure 1167 * address space and both flash devices are generally visible. 1168 */ 1169 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1170 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1171 1172 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1173 secure_sysmem); 1174 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1175 sysmem); 1176 } 1177 1178 static void virt_flash_fdt(VirtMachineState *vms, 1179 MemoryRegion *sysmem, 1180 MemoryRegion *secure_sysmem) 1181 { 1182 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1183 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1184 MachineState *ms = MACHINE(vms); 1185 char *nodename; 1186 1187 if (sysmem == secure_sysmem) { 1188 /* Report both flash devices as a single node in the DT */ 1189 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1190 qemu_fdt_add_subnode(ms->fdt, nodename); 1191 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1192 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1193 2, flashbase, 2, flashsize, 1194 2, flashbase + flashsize, 2, flashsize); 1195 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1196 g_free(nodename); 1197 } else { 1198 /* 1199 * Report the devices as separate nodes so we can mark one as 1200 * only visible to the secure world. 1201 */ 1202 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1203 qemu_fdt_add_subnode(ms->fdt, nodename); 1204 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1205 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1206 2, flashbase, 2, flashsize); 1207 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1208 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1209 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1210 g_free(nodename); 1211 1212 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize); 1213 qemu_fdt_add_subnode(ms->fdt, nodename); 1214 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1215 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1216 2, flashbase + flashsize, 2, flashsize); 1217 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1218 g_free(nodename); 1219 } 1220 } 1221 1222 static bool virt_firmware_init(VirtMachineState *vms, 1223 MemoryRegion *sysmem, 1224 MemoryRegion *secure_sysmem) 1225 { 1226 int i; 1227 const char *bios_name; 1228 BlockBackend *pflash_blk0; 1229 1230 /* Map legacy -drive if=pflash to machine properties */ 1231 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1232 pflash_cfi01_legacy_drive(vms->flash[i], 1233 drive_get(IF_PFLASH, 0, i)); 1234 } 1235 1236 virt_flash_map(vms, sysmem, secure_sysmem); 1237 1238 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1239 1240 bios_name = MACHINE(vms)->firmware; 1241 if (bios_name) { 1242 char *fname; 1243 MemoryRegion *mr; 1244 int image_size; 1245 1246 if (pflash_blk0) { 1247 error_report("The contents of the first flash device may be " 1248 "specified with -bios or with -drive if=pflash... " 1249 "but you cannot use both options at once"); 1250 exit(1); 1251 } 1252 1253 /* Fall back to -bios */ 1254 1255 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1256 if (!fname) { 1257 error_report("Could not find ROM image '%s'", bios_name); 1258 exit(1); 1259 } 1260 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1261 image_size = load_image_mr(fname, mr); 1262 g_free(fname); 1263 if (image_size < 0) { 1264 error_report("Could not load ROM image '%s'", bios_name); 1265 exit(1); 1266 } 1267 } 1268 1269 return pflash_blk0 || bios_name; 1270 } 1271 1272 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1273 { 1274 MachineState *ms = MACHINE(vms); 1275 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1276 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1277 FWCfgState *fw_cfg; 1278 char *nodename; 1279 1280 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1281 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1282 1283 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1284 qemu_fdt_add_subnode(ms->fdt, nodename); 1285 qemu_fdt_setprop_string(ms->fdt, nodename, 1286 "compatible", "qemu,fw-cfg-mmio"); 1287 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1288 2, base, 2, size); 1289 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1290 g_free(nodename); 1291 return fw_cfg; 1292 } 1293 1294 static void create_pcie_irq_map(const MachineState *ms, 1295 uint32_t gic_phandle, 1296 int first_irq, const char *nodename) 1297 { 1298 int devfn, pin; 1299 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1300 uint32_t *irq_map = full_irq_map; 1301 1302 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1303 for (pin = 0; pin < 4; pin++) { 1304 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1305 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1306 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1307 int i; 1308 1309 uint32_t map[] = { 1310 devfn << 8, 0, 0, /* devfn */ 1311 pin + 1, /* PCI pin */ 1312 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1313 1314 /* Convert map to big endian */ 1315 for (i = 0; i < 10; i++) { 1316 irq_map[i] = cpu_to_be32(map[i]); 1317 } 1318 irq_map += 10; 1319 } 1320 } 1321 1322 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", 1323 full_irq_map, sizeof(full_irq_map)); 1324 1325 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 1326 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ 1327 0, 0, 1328 0x7 /* PCI irq */); 1329 } 1330 1331 static void create_smmu(const VirtMachineState *vms, 1332 PCIBus *bus) 1333 { 1334 char *node; 1335 const char compat[] = "arm,smmu-v3"; 1336 int irq = vms->irqmap[VIRT_SMMU]; 1337 int i; 1338 hwaddr base = vms->memmap[VIRT_SMMU].base; 1339 hwaddr size = vms->memmap[VIRT_SMMU].size; 1340 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1341 DeviceState *dev; 1342 MachineState *ms = MACHINE(vms); 1343 1344 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1345 return; 1346 } 1347 1348 dev = qdev_new(TYPE_ARM_SMMUV3); 1349 1350 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1351 &error_abort); 1352 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1353 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1354 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1355 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1356 qdev_get_gpio_in(vms->gic, irq + i)); 1357 } 1358 1359 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1360 qemu_fdt_add_subnode(ms->fdt, node); 1361 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1362 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); 1363 1364 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", 1365 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1366 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1367 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1368 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1369 1370 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, 1371 sizeof(irq_names)); 1372 1373 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); 1374 1375 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1376 1377 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1378 g_free(node); 1379 } 1380 1381 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1382 { 1383 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1384 uint16_t bdf = vms->virtio_iommu_bdf; 1385 MachineState *ms = MACHINE(vms); 1386 char *node; 1387 1388 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1389 1390 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename, 1391 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1392 qemu_fdt_add_subnode(ms->fdt, node); 1393 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1394 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 1395 1, bdf << 8, 1, 0, 1, 0, 1396 1, 0, 1, 0); 1397 1398 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1399 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1400 g_free(node); 1401 1402 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", 1403 0x0, vms->iommu_phandle, 0x0, bdf, 1404 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1405 } 1406 1407 static void create_pcie(VirtMachineState *vms) 1408 { 1409 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1410 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1411 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1412 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1413 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1414 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1415 hwaddr base_ecam, size_ecam; 1416 hwaddr base = base_mmio; 1417 int nr_pcie_buses; 1418 int irq = vms->irqmap[VIRT_PCIE]; 1419 MemoryRegion *mmio_alias; 1420 MemoryRegion *mmio_reg; 1421 MemoryRegion *ecam_alias; 1422 MemoryRegion *ecam_reg; 1423 DeviceState *dev; 1424 char *nodename; 1425 int i, ecam_id; 1426 PCIHostState *pci; 1427 MachineState *ms = MACHINE(vms); 1428 1429 dev = qdev_new(TYPE_GPEX_HOST); 1430 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1431 1432 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1433 base_ecam = vms->memmap[ecam_id].base; 1434 size_ecam = vms->memmap[ecam_id].size; 1435 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1436 /* Map only the first size_ecam bytes of ECAM space */ 1437 ecam_alias = g_new0(MemoryRegion, 1); 1438 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1439 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1440 ecam_reg, 0, size_ecam); 1441 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1442 1443 /* Map the MMIO window into system address space so as to expose 1444 * the section of PCI MMIO space which starts at the same base address 1445 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1446 * the window). 1447 */ 1448 mmio_alias = g_new0(MemoryRegion, 1); 1449 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1450 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1451 mmio_reg, base_mmio, size_mmio); 1452 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1453 1454 if (vms->highmem_mmio) { 1455 /* Map high MMIO space */ 1456 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1457 1458 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1459 mmio_reg, base_mmio_high, size_mmio_high); 1460 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1461 high_mmio_alias); 1462 } 1463 1464 /* Map IO port space */ 1465 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1466 1467 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1468 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1469 qdev_get_gpio_in(vms->gic, irq + i)); 1470 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1471 } 1472 1473 pci = PCI_HOST_BRIDGE(dev); 1474 pci->bypass_iommu = vms->default_bus_bypass_iommu; 1475 vms->bus = pci->bus; 1476 if (vms->bus) { 1477 for (i = 0; i < nb_nics; i++) { 1478 NICInfo *nd = &nd_table[i]; 1479 1480 if (!nd->model) { 1481 nd->model = g_strdup("virtio"); 1482 } 1483 1484 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1485 } 1486 } 1487 1488 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1489 qemu_fdt_add_subnode(ms->fdt, nodename); 1490 qemu_fdt_setprop_string(ms->fdt, nodename, 1491 "compatible", "pci-host-ecam-generic"); 1492 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 1493 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 1494 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 1495 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 1496 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 1497 nr_pcie_buses - 1); 1498 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1499 1500 if (vms->msi_phandle) { 1501 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 1502 0, vms->msi_phandle, 0, 0x10000); 1503 } 1504 1505 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1506 2, base_ecam, 2, size_ecam); 1507 1508 if (vms->highmem_mmio) { 1509 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1510 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1511 2, base_pio, 2, size_pio, 1512 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1513 2, base_mmio, 2, size_mmio, 1514 1, FDT_PCI_RANGE_MMIO_64BIT, 1515 2, base_mmio_high, 1516 2, base_mmio_high, 2, size_mmio_high); 1517 } else { 1518 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1519 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1520 2, base_pio, 2, size_pio, 1521 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1522 2, base_mmio, 2, size_mmio); 1523 } 1524 1525 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 1526 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); 1527 1528 if (vms->iommu) { 1529 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1530 1531 switch (vms->iommu) { 1532 case VIRT_IOMMU_SMMUV3: 1533 create_smmu(vms, vms->bus); 1534 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 1535 0x0, vms->iommu_phandle, 0x0, 0x10000); 1536 break; 1537 default: 1538 g_assert_not_reached(); 1539 } 1540 } 1541 } 1542 1543 static void create_platform_bus(VirtMachineState *vms) 1544 { 1545 DeviceState *dev; 1546 SysBusDevice *s; 1547 int i; 1548 MemoryRegion *sysmem = get_system_memory(); 1549 1550 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1551 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1552 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1553 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1554 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1555 vms->platform_bus_dev = dev; 1556 1557 s = SYS_BUS_DEVICE(dev); 1558 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1559 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1560 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1561 } 1562 1563 memory_region_add_subregion(sysmem, 1564 vms->memmap[VIRT_PLATFORM_BUS].base, 1565 sysbus_mmio_get_region(s, 0)); 1566 } 1567 1568 static void create_tag_ram(MemoryRegion *tag_sysmem, 1569 hwaddr base, hwaddr size, 1570 const char *name) 1571 { 1572 MemoryRegion *tagram = g_new(MemoryRegion, 1); 1573 1574 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); 1575 memory_region_add_subregion(tag_sysmem, base / 32, tagram); 1576 } 1577 1578 static void create_secure_ram(VirtMachineState *vms, 1579 MemoryRegion *secure_sysmem, 1580 MemoryRegion *secure_tag_sysmem) 1581 { 1582 MemoryRegion *secram = g_new(MemoryRegion, 1); 1583 char *nodename; 1584 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1585 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1586 MachineState *ms = MACHINE(vms); 1587 1588 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1589 &error_fatal); 1590 memory_region_add_subregion(secure_sysmem, base, secram); 1591 1592 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1593 qemu_fdt_add_subnode(ms->fdt, nodename); 1594 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 1595 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 1596 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1597 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1598 1599 if (secure_tag_sysmem) { 1600 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); 1601 } 1602 1603 g_free(nodename); 1604 } 1605 1606 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1607 { 1608 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1609 bootinfo); 1610 MachineState *ms = MACHINE(board); 1611 1612 1613 *fdt_size = board->fdt_size; 1614 return ms->fdt; 1615 } 1616 1617 static void virt_build_smbios(VirtMachineState *vms) 1618 { 1619 MachineClass *mc = MACHINE_GET_CLASS(vms); 1620 MachineState *ms = MACHINE(vms); 1621 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1622 uint8_t *smbios_tables, *smbios_anchor; 1623 size_t smbios_tables_len, smbios_anchor_len; 1624 struct smbios_phys_mem_area mem_array; 1625 const char *product = "QEMU Virtual Machine"; 1626 1627 if (kvm_enabled()) { 1628 product = "KVM Virtual Machine"; 1629 } 1630 1631 smbios_set_defaults("QEMU", product, 1632 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1633 true, SMBIOS_ENTRY_POINT_TYPE_64); 1634 1635 /* build the array of physical mem area from base_memmap */ 1636 mem_array.address = vms->memmap[VIRT_MEM].base; 1637 mem_array.length = ms->ram_size; 1638 1639 smbios_get_tables(ms, &mem_array, 1, 1640 &smbios_tables, &smbios_tables_len, 1641 &smbios_anchor, &smbios_anchor_len, 1642 &error_fatal); 1643 1644 if (smbios_anchor) { 1645 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1646 smbios_tables, smbios_tables_len); 1647 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1648 smbios_anchor, smbios_anchor_len); 1649 } 1650 } 1651 1652 static 1653 void virt_machine_done(Notifier *notifier, void *data) 1654 { 1655 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1656 machine_done); 1657 MachineState *ms = MACHINE(vms); 1658 ARMCPU *cpu = ARM_CPU(first_cpu); 1659 struct arm_boot_info *info = &vms->bootinfo; 1660 AddressSpace *as = arm_boot_address_space(cpu, info); 1661 1662 /* 1663 * If the user provided a dtb, we assume the dynamic sysbus nodes 1664 * already are integrated there. This corresponds to a use case where 1665 * the dynamic sysbus nodes are complex and their generation is not yet 1666 * supported. In that case the user can take charge of the guest dt 1667 * while qemu takes charge of the qom stuff. 1668 */ 1669 if (info->dtb_filename == NULL) { 1670 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", 1671 vms->memmap[VIRT_PLATFORM_BUS].base, 1672 vms->memmap[VIRT_PLATFORM_BUS].size, 1673 vms->irqmap[VIRT_PLATFORM_BUS]); 1674 } 1675 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1676 exit(1); 1677 } 1678 1679 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg); 1680 1681 virt_acpi_setup(vms); 1682 virt_build_smbios(vms); 1683 } 1684 1685 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1686 { 1687 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1688 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1689 1690 if (!vmc->disallow_affinity_adjustment) { 1691 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1692 * GIC's target-list limitations. 32-bit KVM hosts currently 1693 * always create clusters of 4 CPUs, but that is expected to 1694 * change when they gain support for gicv3. When KVM is enabled 1695 * it will override the changes we make here, therefore our 1696 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1697 * and to improve SGI efficiency. 1698 */ 1699 if (vms->gic_version == VIRT_GIC_VERSION_2) { 1700 clustersz = GIC_TARGETLIST_BITS; 1701 } else { 1702 clustersz = GICV3_TARGETLIST_BITS; 1703 } 1704 } 1705 return arm_cpu_mp_affinity(idx, clustersz); 1706 } 1707 1708 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, 1709 int index) 1710 { 1711 bool *enabled_array[] = { 1712 &vms->highmem_redists, 1713 &vms->highmem_ecam, 1714 &vms->highmem_mmio, 1715 }; 1716 1717 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST == 1718 ARRAY_SIZE(enabled_array)); 1719 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array)); 1720 1721 return enabled_array[index - VIRT_LOWMEMMAP_LAST]; 1722 } 1723 1724 static void virt_set_high_memmap(VirtMachineState *vms, 1725 hwaddr base, int pa_bits) 1726 { 1727 hwaddr region_base, region_size; 1728 bool *region_enabled, fits; 1729 int i; 1730 1731 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1732 region_enabled = virt_get_high_memmap_enabled(vms, i); 1733 region_base = ROUND_UP(base, extended_memmap[i].size); 1734 region_size = extended_memmap[i].size; 1735 1736 vms->memmap[i].base = region_base; 1737 vms->memmap[i].size = region_size; 1738 1739 /* 1740 * Check each device to see if it fits in the PA space, 1741 * moving highest_gpa as we go. For compatibility, move 1742 * highest_gpa for disabled fitting devices as well, if 1743 * the compact layout has been disabled. 1744 * 1745 * For each device that doesn't fit, disable it. 1746 */ 1747 fits = (region_base + region_size) <= BIT_ULL(pa_bits); 1748 *region_enabled &= fits; 1749 if (vms->highmem_compact && !*region_enabled) { 1750 continue; 1751 } 1752 1753 base = region_base + region_size; 1754 if (fits) { 1755 vms->highest_gpa = base - 1; 1756 } 1757 } 1758 } 1759 1760 static void virt_set_memmap(VirtMachineState *vms, int pa_bits) 1761 { 1762 MachineState *ms = MACHINE(vms); 1763 hwaddr base, device_memory_base, device_memory_size, memtop; 1764 int i; 1765 1766 vms->memmap = extended_memmap; 1767 1768 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1769 vms->memmap[i] = base_memmap[i]; 1770 } 1771 1772 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1773 error_report("unsupported number of memory slots: %"PRIu64, 1774 ms->ram_slots); 1775 exit(EXIT_FAILURE); 1776 } 1777 1778 /* 1779 * !highmem is exactly the same as limiting the PA space to 32bit, 1780 * irrespective of the underlying capabilities of the HW. 1781 */ 1782 if (!vms->highmem) { 1783 pa_bits = 32; 1784 } 1785 1786 /* 1787 * We compute the base of the high IO region depending on the 1788 * amount of initial and device memory. The device memory start/size 1789 * is aligned on 1GiB. We never put the high IO region below 256GiB 1790 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1791 * The device region size assumes 1GiB page max alignment per slot. 1792 */ 1793 device_memory_base = 1794 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1795 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1796 1797 /* Base address of the high IO region */ 1798 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1799 if (memtop > BIT_ULL(pa_bits)) { 1800 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n", 1801 pa_bits, memtop - BIT_ULL(pa_bits)); 1802 exit(EXIT_FAILURE); 1803 } 1804 if (base < device_memory_base) { 1805 error_report("maxmem/slots too huge"); 1806 exit(EXIT_FAILURE); 1807 } 1808 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1809 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1810 } 1811 1812 /* We know for sure that at least the memory fits in the PA space */ 1813 vms->highest_gpa = memtop - 1; 1814 1815 virt_set_high_memmap(vms, base, pa_bits); 1816 1817 if (device_memory_size > 0) { 1818 ms->device_memory = g_malloc0(sizeof(*ms->device_memory)); 1819 ms->device_memory->base = device_memory_base; 1820 memory_region_init(&ms->device_memory->mr, OBJECT(vms), 1821 "device-memory", device_memory_size); 1822 } 1823 } 1824 1825 static VirtGICType finalize_gic_version_do(const char *accel_name, 1826 VirtGICType gic_version, 1827 int gics_supported, 1828 unsigned int max_cpus) 1829 { 1830 /* Convert host/max/nosel to GIC version number */ 1831 switch (gic_version) { 1832 case VIRT_GIC_VERSION_HOST: 1833 if (!kvm_enabled()) { 1834 error_report("gic-version=host requires KVM"); 1835 exit(1); 1836 } 1837 1838 /* For KVM, gic-version=host means gic-version=max */ 1839 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX, 1840 gics_supported, max_cpus); 1841 case VIRT_GIC_VERSION_MAX: 1842 if (gics_supported & VIRT_GIC_VERSION_4_MASK) { 1843 gic_version = VIRT_GIC_VERSION_4; 1844 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1845 gic_version = VIRT_GIC_VERSION_3; 1846 } else { 1847 gic_version = VIRT_GIC_VERSION_2; 1848 } 1849 break; 1850 case VIRT_GIC_VERSION_NOSEL: 1851 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) && 1852 max_cpus <= GIC_NCPU) { 1853 gic_version = VIRT_GIC_VERSION_2; 1854 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1855 /* 1856 * in case the host does not support v2 emulation or 1857 * the end-user requested more than 8 VCPUs we now default 1858 * to v3. In any case defaulting to v2 would be broken. 1859 */ 1860 gic_version = VIRT_GIC_VERSION_3; 1861 } else if (max_cpus > GIC_NCPU) { 1862 error_report("%s only supports GICv2 emulation but more than 8 " 1863 "vcpus are requested", accel_name); 1864 exit(1); 1865 } 1866 break; 1867 case VIRT_GIC_VERSION_2: 1868 case VIRT_GIC_VERSION_3: 1869 case VIRT_GIC_VERSION_4: 1870 break; 1871 } 1872 1873 /* Check chosen version is effectively supported */ 1874 switch (gic_version) { 1875 case VIRT_GIC_VERSION_2: 1876 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) { 1877 error_report("%s does not support GICv2 emulation", accel_name); 1878 exit(1); 1879 } 1880 break; 1881 case VIRT_GIC_VERSION_3: 1882 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) { 1883 error_report("%s does not support GICv3 emulation", accel_name); 1884 exit(1); 1885 } 1886 break; 1887 case VIRT_GIC_VERSION_4: 1888 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) { 1889 error_report("%s does not support GICv4 emulation, is virtualization=on?", 1890 accel_name); 1891 exit(1); 1892 } 1893 break; 1894 default: 1895 error_report("logic error in finalize_gic_version"); 1896 exit(1); 1897 break; 1898 } 1899 1900 return gic_version; 1901 } 1902 1903 /* 1904 * finalize_gic_version - Determines the final gic_version 1905 * according to the gic-version property 1906 * 1907 * Default GIC type is v2 1908 */ 1909 static void finalize_gic_version(VirtMachineState *vms) 1910 { 1911 const char *accel_name = current_accel_name(); 1912 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 1913 int gics_supported = 0; 1914 1915 /* Determine which GIC versions the current environment supports */ 1916 if (kvm_enabled() && kvm_irqchip_in_kernel()) { 1917 int probe_bitmap = kvm_arm_vgic_probe(); 1918 1919 if (!probe_bitmap) { 1920 error_report("Unable to determine GIC version supported by host"); 1921 exit(1); 1922 } 1923 1924 if (probe_bitmap & KVM_ARM_VGIC_V2) { 1925 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1926 } 1927 if (probe_bitmap & KVM_ARM_VGIC_V3) { 1928 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1929 } 1930 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) { 1931 /* KVM w/o kernel irqchip can only deal with GICv2 */ 1932 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1933 accel_name = "KVM with kernel-irqchip=off"; 1934 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { 1935 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1936 if (module_object_class_by_name("arm-gicv3")) { 1937 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1938 if (vms->virt) { 1939 /* GICv4 only makes sense if CPU has EL2 */ 1940 gics_supported |= VIRT_GIC_VERSION_4_MASK; 1941 } 1942 } 1943 } else { 1944 error_report("Unsupported accelerator, can not determine GIC support"); 1945 exit(1); 1946 } 1947 1948 /* 1949 * Then convert helpers like host/max to concrete GIC versions and ensure 1950 * the desired version is supported 1951 */ 1952 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version, 1953 gics_supported, max_cpus); 1954 } 1955 1956 /* 1957 * virt_cpu_post_init() must be called after the CPUs have 1958 * been realized and the GIC has been created. 1959 */ 1960 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) 1961 { 1962 int max_cpus = MACHINE(vms)->smp.max_cpus; 1963 bool aarch64, pmu, steal_time; 1964 CPUState *cpu; 1965 1966 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); 1967 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); 1968 steal_time = object_property_get_bool(OBJECT(first_cpu), 1969 "kvm-steal-time", NULL); 1970 1971 if (kvm_enabled()) { 1972 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; 1973 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; 1974 1975 if (steal_time) { 1976 MemoryRegion *pvtime = g_new(MemoryRegion, 1); 1977 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; 1978 1979 /* The memory region size must be a multiple of host page size. */ 1980 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); 1981 1982 if (pvtime_size > pvtime_reg_size) { 1983 error_report("pvtime requires a %" HWADDR_PRId 1984 " byte memory region for %d CPUs," 1985 " but only %" HWADDR_PRId " has been reserved", 1986 pvtime_size, max_cpus, pvtime_reg_size); 1987 exit(1); 1988 } 1989 1990 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); 1991 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); 1992 } 1993 1994 CPU_FOREACH(cpu) { 1995 if (pmu) { 1996 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); 1997 if (kvm_irqchip_in_kernel()) { 1998 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 1999 } 2000 kvm_arm_pmu_init(cpu); 2001 } 2002 if (steal_time) { 2003 kvm_arm_pvtime_init(cpu, pvtime_reg_base + 2004 cpu->cpu_index * PVTIME_SIZE_PER_CPU); 2005 } 2006 } 2007 } else { 2008 if (aarch64 && vms->highmem) { 2009 int requested_pa_size = 64 - clz64(vms->highest_gpa); 2010 int pamax = arm_pamax(ARM_CPU(first_cpu)); 2011 2012 if (pamax < requested_pa_size) { 2013 error_report("VCPU supports less PA bits (%d) than " 2014 "requested by the memory map (%d)", 2015 pamax, requested_pa_size); 2016 exit(1); 2017 } 2018 } 2019 } 2020 } 2021 2022 static void machvirt_init(MachineState *machine) 2023 { 2024 VirtMachineState *vms = VIRT_MACHINE(machine); 2025 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 2026 MachineClass *mc = MACHINE_GET_CLASS(machine); 2027 const CPUArchIdList *possible_cpus; 2028 MemoryRegion *sysmem = get_system_memory(); 2029 MemoryRegion *secure_sysmem = NULL; 2030 MemoryRegion *tag_sysmem = NULL; 2031 MemoryRegion *secure_tag_sysmem = NULL; 2032 int n, virt_max_cpus; 2033 bool firmware_loaded; 2034 bool aarch64 = true; 2035 bool has_ged = !vmc->no_ged; 2036 unsigned int smp_cpus = machine->smp.cpus; 2037 unsigned int max_cpus = machine->smp.max_cpus; 2038 2039 if (!cpu_type_valid(machine->cpu_type)) { 2040 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 2041 exit(1); 2042 } 2043 2044 possible_cpus = mc->possible_cpu_arch_ids(machine); 2045 2046 /* 2047 * In accelerated mode, the memory map is computed earlier in kvm_type() 2048 * to create a VM with the right number of IPA bits. 2049 */ 2050 if (!vms->memmap) { 2051 Object *cpuobj; 2052 ARMCPU *armcpu; 2053 int pa_bits; 2054 2055 /* 2056 * Instanciate a temporary CPU object to find out about what 2057 * we are about to deal with. Once this is done, get rid of 2058 * the object. 2059 */ 2060 cpuobj = object_new(possible_cpus->cpus[0].type); 2061 armcpu = ARM_CPU(cpuobj); 2062 2063 pa_bits = arm_pamax(armcpu); 2064 2065 object_unref(cpuobj); 2066 2067 virt_set_memmap(vms, pa_bits); 2068 } 2069 2070 /* We can probe only here because during property set 2071 * KVM is not available yet 2072 */ 2073 finalize_gic_version(vms); 2074 2075 if (vms->secure) { 2076 /* 2077 * The Secure view of the world is the same as the NonSecure, 2078 * but with a few extra devices. Create it as a container region 2079 * containing the system memory at low priority; any secure-only 2080 * devices go in at higher priority and take precedence. 2081 */ 2082 secure_sysmem = g_new(MemoryRegion, 1); 2083 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 2084 UINT64_MAX); 2085 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 2086 } 2087 2088 firmware_loaded = virt_firmware_init(vms, sysmem, 2089 secure_sysmem ?: sysmem); 2090 2091 /* If we have an EL3 boot ROM then the assumption is that it will 2092 * implement PSCI itself, so disable QEMU's internal implementation 2093 * so it doesn't get in the way. Instead of starting secondary 2094 * CPUs in PSCI powerdown state we will start them all running and 2095 * let the boot ROM sort them out. 2096 * The usual case is that we do use QEMU's PSCI implementation; 2097 * if the guest has EL2 then we will use SMC as the conduit, 2098 * and otherwise we will use HVC (for backwards compatibility and 2099 * because if we're using KVM then we must use HVC). 2100 */ 2101 if (vms->secure && firmware_loaded) { 2102 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 2103 } else if (vms->virt) { 2104 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 2105 } else { 2106 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 2107 } 2108 2109 /* 2110 * The maximum number of CPUs depends on the GIC version, or on how 2111 * many redistributors we can fit into the memory map (which in turn 2112 * depends on whether this is a GICv3 or v4). 2113 */ 2114 if (vms->gic_version == VIRT_GIC_VERSION_2) { 2115 virt_max_cpus = GIC_NCPU; 2116 } else { 2117 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST); 2118 if (vms->highmem_redists) { 2119 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 2120 } 2121 } 2122 2123 if (max_cpus > virt_max_cpus) { 2124 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 2125 "supported by machine 'mach-virt' (%d)", 2126 max_cpus, virt_max_cpus); 2127 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) { 2128 error_printf("Try 'highmem-redists=on' for more CPUs\n"); 2129 } 2130 2131 exit(1); 2132 } 2133 2134 if (vms->secure && (kvm_enabled() || hvf_enabled())) { 2135 error_report("mach-virt: %s does not support providing " 2136 "Security extensions (TrustZone) to the guest CPU", 2137 kvm_enabled() ? "KVM" : "HVF"); 2138 exit(1); 2139 } 2140 2141 if (vms->virt && (kvm_enabled() || hvf_enabled())) { 2142 error_report("mach-virt: %s does not support providing " 2143 "Virtualization extensions to the guest CPU", 2144 kvm_enabled() ? "KVM" : "HVF"); 2145 exit(1); 2146 } 2147 2148 if (vms->mte && (kvm_enabled() || hvf_enabled())) { 2149 error_report("mach-virt: %s does not support providing " 2150 "MTE to the guest CPU", 2151 kvm_enabled() ? "KVM" : "HVF"); 2152 exit(1); 2153 } 2154 2155 create_fdt(vms); 2156 2157 assert(possible_cpus->len == max_cpus); 2158 for (n = 0; n < possible_cpus->len; n++) { 2159 Object *cpuobj; 2160 CPUState *cs; 2161 2162 if (n >= smp_cpus) { 2163 break; 2164 } 2165 2166 cpuobj = object_new(possible_cpus->cpus[n].type); 2167 object_property_set_int(cpuobj, "mp-affinity", 2168 possible_cpus->cpus[n].arch_id, NULL); 2169 2170 cs = CPU(cpuobj); 2171 cs->cpu_index = n; 2172 2173 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 2174 &error_fatal); 2175 2176 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 2177 2178 if (!vms->secure) { 2179 object_property_set_bool(cpuobj, "has_el3", false, NULL); 2180 } 2181 2182 if (!vms->virt && object_property_find(cpuobj, "has_el2")) { 2183 object_property_set_bool(cpuobj, "has_el2", false, NULL); 2184 } 2185 2186 if (vmc->kvm_no_adjvtime && 2187 object_property_find(cpuobj, "kvm-no-adjvtime")) { 2188 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 2189 } 2190 2191 if (vmc->no_kvm_steal_time && 2192 object_property_find(cpuobj, "kvm-steal-time")) { 2193 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); 2194 } 2195 2196 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { 2197 object_property_set_bool(cpuobj, "pmu", false, NULL); 2198 } 2199 2200 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { 2201 object_property_set_bool(cpuobj, "lpa2", false, NULL); 2202 } 2203 2204 if (object_property_find(cpuobj, "reset-cbar")) { 2205 object_property_set_int(cpuobj, "reset-cbar", 2206 vms->memmap[VIRT_CPUPERIPHS].base, 2207 &error_abort); 2208 } 2209 2210 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 2211 &error_abort); 2212 if (vms->secure) { 2213 object_property_set_link(cpuobj, "secure-memory", 2214 OBJECT(secure_sysmem), &error_abort); 2215 } 2216 2217 if (vms->mte) { 2218 /* Create the memory region only once, but link to all cpus. */ 2219 if (!tag_sysmem) { 2220 /* 2221 * The property exists only if MemTag is supported. 2222 * If it is, we must allocate the ram to back that up. 2223 */ 2224 if (!object_property_find(cpuobj, "tag-memory")) { 2225 error_report("MTE requested, but not supported " 2226 "by the guest CPU"); 2227 exit(1); 2228 } 2229 2230 tag_sysmem = g_new(MemoryRegion, 1); 2231 memory_region_init(tag_sysmem, OBJECT(machine), 2232 "tag-memory", UINT64_MAX / 32); 2233 2234 if (vms->secure) { 2235 secure_tag_sysmem = g_new(MemoryRegion, 1); 2236 memory_region_init(secure_tag_sysmem, OBJECT(machine), 2237 "secure-tag-memory", UINT64_MAX / 32); 2238 2239 /* As with ram, secure-tag takes precedence over tag. */ 2240 memory_region_add_subregion_overlap(secure_tag_sysmem, 0, 2241 tag_sysmem, -1); 2242 } 2243 } 2244 2245 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem), 2246 &error_abort); 2247 if (vms->secure) { 2248 object_property_set_link(cpuobj, "secure-tag-memory", 2249 OBJECT(secure_tag_sysmem), 2250 &error_abort); 2251 } 2252 } 2253 2254 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 2255 object_unref(cpuobj); 2256 } 2257 fdt_add_timer_nodes(vms); 2258 fdt_add_cpu_nodes(vms); 2259 2260 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 2261 machine->ram); 2262 if (machine->device_memory) { 2263 memory_region_add_subregion(sysmem, machine->device_memory->base, 2264 &machine->device_memory->mr); 2265 } 2266 2267 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 2268 2269 create_gic(vms, sysmem); 2270 2271 virt_cpu_post_init(vms, sysmem); 2272 2273 fdt_add_pmu_nodes(vms); 2274 2275 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 2276 2277 if (vms->secure) { 2278 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); 2279 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 2280 } 2281 2282 if (tag_sysmem) { 2283 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, 2284 machine->ram_size, "mach-virt.tag"); 2285 } 2286 2287 vms->highmem_ecam &= (!firmware_loaded || aarch64); 2288 2289 create_rtc(vms); 2290 2291 create_pcie(vms); 2292 2293 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 2294 vms->acpi_dev = create_acpi_ged(vms); 2295 } else { 2296 create_gpio_devices(vms, VIRT_GPIO, sysmem); 2297 } 2298 2299 if (vms->secure && !vmc->no_secure_gpio) { 2300 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); 2301 } 2302 2303 /* connect powerdown request */ 2304 vms->powerdown_notifier.notify = virt_powerdown_req; 2305 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 2306 2307 /* Create mmio transports, so the user can create virtio backends 2308 * (which will be automatically plugged in to the transports). If 2309 * no backend is created the transport will just sit harmlessly idle. 2310 */ 2311 create_virtio_devices(vms); 2312 2313 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 2314 rom_set_fw(vms->fw_cfg); 2315 2316 create_platform_bus(vms); 2317 2318 if (machine->nvdimms_state->is_enabled) { 2319 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 2320 .space_id = AML_AS_SYSTEM_MEMORY, 2321 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 2322 .bit_width = NVDIMM_ACPI_IO_LEN << 3 2323 }; 2324 2325 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 2326 arm_virt_nvdimm_acpi_dsmio, 2327 vms->fw_cfg, OBJECT(vms)); 2328 } 2329 2330 vms->bootinfo.ram_size = machine->ram_size; 2331 vms->bootinfo.board_id = -1; 2332 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 2333 vms->bootinfo.get_dtb = machvirt_dtb; 2334 vms->bootinfo.skip_dtb_autoload = true; 2335 vms->bootinfo.firmware_loaded = firmware_loaded; 2336 vms->bootinfo.psci_conduit = vms->psci_conduit; 2337 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 2338 2339 vms->machine_done.notify = virt_machine_done; 2340 qemu_add_machine_init_done_notifier(&vms->machine_done); 2341 } 2342 2343 static bool virt_get_secure(Object *obj, Error **errp) 2344 { 2345 VirtMachineState *vms = VIRT_MACHINE(obj); 2346 2347 return vms->secure; 2348 } 2349 2350 static void virt_set_secure(Object *obj, bool value, Error **errp) 2351 { 2352 VirtMachineState *vms = VIRT_MACHINE(obj); 2353 2354 vms->secure = value; 2355 } 2356 2357 static bool virt_get_virt(Object *obj, Error **errp) 2358 { 2359 VirtMachineState *vms = VIRT_MACHINE(obj); 2360 2361 return vms->virt; 2362 } 2363 2364 static void virt_set_virt(Object *obj, bool value, Error **errp) 2365 { 2366 VirtMachineState *vms = VIRT_MACHINE(obj); 2367 2368 vms->virt = value; 2369 } 2370 2371 static bool virt_get_highmem(Object *obj, Error **errp) 2372 { 2373 VirtMachineState *vms = VIRT_MACHINE(obj); 2374 2375 return vms->highmem; 2376 } 2377 2378 static void virt_set_highmem(Object *obj, bool value, Error **errp) 2379 { 2380 VirtMachineState *vms = VIRT_MACHINE(obj); 2381 2382 vms->highmem = value; 2383 } 2384 2385 static bool virt_get_compact_highmem(Object *obj, Error **errp) 2386 { 2387 VirtMachineState *vms = VIRT_MACHINE(obj); 2388 2389 return vms->highmem_compact; 2390 } 2391 2392 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp) 2393 { 2394 VirtMachineState *vms = VIRT_MACHINE(obj); 2395 2396 vms->highmem_compact = value; 2397 } 2398 2399 static bool virt_get_highmem_redists(Object *obj, Error **errp) 2400 { 2401 VirtMachineState *vms = VIRT_MACHINE(obj); 2402 2403 return vms->highmem_redists; 2404 } 2405 2406 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp) 2407 { 2408 VirtMachineState *vms = VIRT_MACHINE(obj); 2409 2410 vms->highmem_redists = value; 2411 } 2412 2413 static bool virt_get_highmem_ecam(Object *obj, Error **errp) 2414 { 2415 VirtMachineState *vms = VIRT_MACHINE(obj); 2416 2417 return vms->highmem_ecam; 2418 } 2419 2420 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp) 2421 { 2422 VirtMachineState *vms = VIRT_MACHINE(obj); 2423 2424 vms->highmem_ecam = value; 2425 } 2426 2427 static bool virt_get_highmem_mmio(Object *obj, Error **errp) 2428 { 2429 VirtMachineState *vms = VIRT_MACHINE(obj); 2430 2431 return vms->highmem_mmio; 2432 } 2433 2434 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp) 2435 { 2436 VirtMachineState *vms = VIRT_MACHINE(obj); 2437 2438 vms->highmem_mmio = value; 2439 } 2440 2441 2442 static bool virt_get_its(Object *obj, Error **errp) 2443 { 2444 VirtMachineState *vms = VIRT_MACHINE(obj); 2445 2446 return vms->its; 2447 } 2448 2449 static void virt_set_its(Object *obj, bool value, Error **errp) 2450 { 2451 VirtMachineState *vms = VIRT_MACHINE(obj); 2452 2453 vms->its = value; 2454 } 2455 2456 static bool virt_get_dtb_randomness(Object *obj, Error **errp) 2457 { 2458 VirtMachineState *vms = VIRT_MACHINE(obj); 2459 2460 return vms->dtb_randomness; 2461 } 2462 2463 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp) 2464 { 2465 VirtMachineState *vms = VIRT_MACHINE(obj); 2466 2467 vms->dtb_randomness = value; 2468 } 2469 2470 static char *virt_get_oem_id(Object *obj, Error **errp) 2471 { 2472 VirtMachineState *vms = VIRT_MACHINE(obj); 2473 2474 return g_strdup(vms->oem_id); 2475 } 2476 2477 static void virt_set_oem_id(Object *obj, const char *value, Error **errp) 2478 { 2479 VirtMachineState *vms = VIRT_MACHINE(obj); 2480 size_t len = strlen(value); 2481 2482 if (len > 6) { 2483 error_setg(errp, 2484 "User specified oem-id value is bigger than 6 bytes in size"); 2485 return; 2486 } 2487 2488 strncpy(vms->oem_id, value, 6); 2489 } 2490 2491 static char *virt_get_oem_table_id(Object *obj, Error **errp) 2492 { 2493 VirtMachineState *vms = VIRT_MACHINE(obj); 2494 2495 return g_strdup(vms->oem_table_id); 2496 } 2497 2498 static void virt_set_oem_table_id(Object *obj, const char *value, 2499 Error **errp) 2500 { 2501 VirtMachineState *vms = VIRT_MACHINE(obj); 2502 size_t len = strlen(value); 2503 2504 if (len > 8) { 2505 error_setg(errp, 2506 "User specified oem-table-id value is bigger than 8 bytes in size"); 2507 return; 2508 } 2509 strncpy(vms->oem_table_id, value, 8); 2510 } 2511 2512 2513 bool virt_is_acpi_enabled(VirtMachineState *vms) 2514 { 2515 if (vms->acpi == ON_OFF_AUTO_OFF) { 2516 return false; 2517 } 2518 return true; 2519 } 2520 2521 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 2522 void *opaque, Error **errp) 2523 { 2524 VirtMachineState *vms = VIRT_MACHINE(obj); 2525 OnOffAuto acpi = vms->acpi; 2526 2527 visit_type_OnOffAuto(v, name, &acpi, errp); 2528 } 2529 2530 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 2531 void *opaque, Error **errp) 2532 { 2533 VirtMachineState *vms = VIRT_MACHINE(obj); 2534 2535 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 2536 } 2537 2538 static bool virt_get_ras(Object *obj, Error **errp) 2539 { 2540 VirtMachineState *vms = VIRT_MACHINE(obj); 2541 2542 return vms->ras; 2543 } 2544 2545 static void virt_set_ras(Object *obj, bool value, Error **errp) 2546 { 2547 VirtMachineState *vms = VIRT_MACHINE(obj); 2548 2549 vms->ras = value; 2550 } 2551 2552 static bool virt_get_mte(Object *obj, Error **errp) 2553 { 2554 VirtMachineState *vms = VIRT_MACHINE(obj); 2555 2556 return vms->mte; 2557 } 2558 2559 static void virt_set_mte(Object *obj, bool value, Error **errp) 2560 { 2561 VirtMachineState *vms = VIRT_MACHINE(obj); 2562 2563 vms->mte = value; 2564 } 2565 2566 static char *virt_get_gic_version(Object *obj, Error **errp) 2567 { 2568 VirtMachineState *vms = VIRT_MACHINE(obj); 2569 const char *val; 2570 2571 switch (vms->gic_version) { 2572 case VIRT_GIC_VERSION_4: 2573 val = "4"; 2574 break; 2575 case VIRT_GIC_VERSION_3: 2576 val = "3"; 2577 break; 2578 default: 2579 val = "2"; 2580 break; 2581 } 2582 return g_strdup(val); 2583 } 2584 2585 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2586 { 2587 VirtMachineState *vms = VIRT_MACHINE(obj); 2588 2589 if (!strcmp(value, "4")) { 2590 vms->gic_version = VIRT_GIC_VERSION_4; 2591 } else if (!strcmp(value, "3")) { 2592 vms->gic_version = VIRT_GIC_VERSION_3; 2593 } else if (!strcmp(value, "2")) { 2594 vms->gic_version = VIRT_GIC_VERSION_2; 2595 } else if (!strcmp(value, "host")) { 2596 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2597 } else if (!strcmp(value, "max")) { 2598 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2599 } else { 2600 error_setg(errp, "Invalid gic-version value"); 2601 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2602 } 2603 } 2604 2605 static char *virt_get_iommu(Object *obj, Error **errp) 2606 { 2607 VirtMachineState *vms = VIRT_MACHINE(obj); 2608 2609 switch (vms->iommu) { 2610 case VIRT_IOMMU_NONE: 2611 return g_strdup("none"); 2612 case VIRT_IOMMU_SMMUV3: 2613 return g_strdup("smmuv3"); 2614 default: 2615 g_assert_not_reached(); 2616 } 2617 } 2618 2619 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2620 { 2621 VirtMachineState *vms = VIRT_MACHINE(obj); 2622 2623 if (!strcmp(value, "smmuv3")) { 2624 vms->iommu = VIRT_IOMMU_SMMUV3; 2625 } else if (!strcmp(value, "none")) { 2626 vms->iommu = VIRT_IOMMU_NONE; 2627 } else { 2628 error_setg(errp, "Invalid iommu value"); 2629 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2630 } 2631 } 2632 2633 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp) 2634 { 2635 VirtMachineState *vms = VIRT_MACHINE(obj); 2636 2637 return vms->default_bus_bypass_iommu; 2638 } 2639 2640 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value, 2641 Error **errp) 2642 { 2643 VirtMachineState *vms = VIRT_MACHINE(obj); 2644 2645 vms->default_bus_bypass_iommu = value; 2646 } 2647 2648 static CpuInstanceProperties 2649 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2650 { 2651 MachineClass *mc = MACHINE_GET_CLASS(ms); 2652 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2653 2654 assert(cpu_index < possible_cpus->len); 2655 return possible_cpus->cpus[cpu_index].props; 2656 } 2657 2658 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2659 { 2660 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 2661 2662 return socket_id % ms->numa_state->num_nodes; 2663 } 2664 2665 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2666 { 2667 int n; 2668 unsigned int max_cpus = ms->smp.max_cpus; 2669 VirtMachineState *vms = VIRT_MACHINE(ms); 2670 MachineClass *mc = MACHINE_GET_CLASS(vms); 2671 2672 if (ms->possible_cpus) { 2673 assert(ms->possible_cpus->len == max_cpus); 2674 return ms->possible_cpus; 2675 } 2676 2677 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2678 sizeof(CPUArchId) * max_cpus); 2679 ms->possible_cpus->len = max_cpus; 2680 for (n = 0; n < ms->possible_cpus->len; n++) { 2681 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2682 ms->possible_cpus->cpus[n].arch_id = 2683 virt_cpu_mp_affinity(vms, n); 2684 2685 assert(!mc->smp_props.dies_supported); 2686 ms->possible_cpus->cpus[n].props.has_socket_id = true; 2687 ms->possible_cpus->cpus[n].props.socket_id = 2688 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); 2689 ms->possible_cpus->cpus[n].props.has_cluster_id = true; 2690 ms->possible_cpus->cpus[n].props.cluster_id = 2691 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; 2692 ms->possible_cpus->cpus[n].props.has_core_id = true; 2693 ms->possible_cpus->cpus[n].props.core_id = 2694 (n / ms->smp.threads) % ms->smp.cores; 2695 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2696 ms->possible_cpus->cpus[n].props.thread_id = 2697 n % ms->smp.threads; 2698 } 2699 return ms->possible_cpus; 2700 } 2701 2702 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2703 Error **errp) 2704 { 2705 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2706 const MachineState *ms = MACHINE(hotplug_dev); 2707 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2708 2709 if (!vms->acpi_dev) { 2710 error_setg(errp, 2711 "memory hotplug is not enabled: missing acpi-ged device"); 2712 return; 2713 } 2714 2715 if (vms->mte) { 2716 error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); 2717 return; 2718 } 2719 2720 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2721 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2722 return; 2723 } 2724 2725 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 2726 } 2727 2728 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2729 DeviceState *dev, Error **errp) 2730 { 2731 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2732 MachineState *ms = MACHINE(hotplug_dev); 2733 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2734 2735 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); 2736 2737 if (is_nvdimm) { 2738 nvdimm_plug(ms->nvdimms_state); 2739 } 2740 2741 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2742 dev, &error_abort); 2743 } 2744 2745 static void virt_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 2746 DeviceState *dev, Error **errp) 2747 { 2748 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2749 Error *local_err = NULL; 2750 2751 if (!hotplug_dev2 && dev->hotplugged) { 2752 /* 2753 * Without a bus hotplug handler, we cannot control the plug/unplug 2754 * order. We should never reach this point when hotplugging on ARM. 2755 * However, it's nice to add a safety net, similar to what we have 2756 * on x86. 2757 */ 2758 error_setg(errp, "hotplug of virtio based memory devices not supported" 2759 " on this bus."); 2760 return; 2761 } 2762 /* 2763 * First, see if we can plug this memory device at all. If that 2764 * succeeds, branch of to the actual hotplug handler. 2765 */ 2766 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 2767 &local_err); 2768 if (!local_err && hotplug_dev2) { 2769 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 2770 } 2771 error_propagate(errp, local_err); 2772 } 2773 2774 static void virt_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 2775 DeviceState *dev, Error **errp) 2776 { 2777 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2778 Error *local_err = NULL; 2779 2780 /* 2781 * Plug the memory device first and then branch off to the actual 2782 * hotplug handler. If that one fails, we can easily undo the memory 2783 * device bits. 2784 */ 2785 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2786 if (hotplug_dev2) { 2787 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 2788 if (local_err) { 2789 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2790 } 2791 } 2792 error_propagate(errp, local_err); 2793 } 2794 2795 static void virt_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 2796 DeviceState *dev, Error **errp) 2797 { 2798 /* We don't support hot unplug of virtio based memory devices */ 2799 error_setg(errp, "virtio based memory devices cannot be unplugged."); 2800 } 2801 2802 2803 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2804 DeviceState *dev, Error **errp) 2805 { 2806 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2807 2808 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2809 virt_memory_pre_plug(hotplug_dev, dev, errp); 2810 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2811 virt_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 2812 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2813 hwaddr db_start = 0, db_end = 0; 2814 char *resv_prop_str; 2815 2816 if (vms->iommu != VIRT_IOMMU_NONE) { 2817 error_setg(errp, "virt machine does not support multiple IOMMUs"); 2818 return; 2819 } 2820 2821 switch (vms->msi_controller) { 2822 case VIRT_MSI_CTRL_NONE: 2823 return; 2824 case VIRT_MSI_CTRL_ITS: 2825 /* GITS_TRANSLATER page */ 2826 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; 2827 db_end = base_memmap[VIRT_GIC_ITS].base + 2828 base_memmap[VIRT_GIC_ITS].size - 1; 2829 break; 2830 case VIRT_MSI_CTRL_GICV2M: 2831 /* MSI_SETSPI_NS page */ 2832 db_start = base_memmap[VIRT_GIC_V2M].base; 2833 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; 2834 break; 2835 } 2836 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", 2837 db_start, db_end, 2838 VIRTIO_IOMMU_RESV_MEM_T_MSI); 2839 2840 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 2841 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 2842 resv_prop_str, errp); 2843 g_free(resv_prop_str); 2844 } 2845 } 2846 2847 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2848 DeviceState *dev, Error **errp) 2849 { 2850 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2851 2852 if (vms->platform_bus_dev) { 2853 MachineClass *mc = MACHINE_GET_CLASS(vms); 2854 2855 if (device_is_dynamic_sysbus(mc, dev)) { 2856 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2857 SYS_BUS_DEVICE(dev)); 2858 } 2859 } 2860 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2861 virt_memory_plug(hotplug_dev, dev, errp); 2862 } 2863 2864 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2865 virt_virtio_md_pci_plug(hotplug_dev, dev, errp); 2866 } 2867 2868 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2869 PCIDevice *pdev = PCI_DEVICE(dev); 2870 2871 vms->iommu = VIRT_IOMMU_VIRTIO; 2872 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2873 create_virtio_iommu_dt_bindings(vms); 2874 } 2875 } 2876 2877 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, 2878 DeviceState *dev, Error **errp) 2879 { 2880 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2881 2882 if (!vms->acpi_dev) { 2883 error_setg(errp, 2884 "memory hotplug is not enabled: missing acpi-ged device"); 2885 return; 2886 } 2887 2888 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2889 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 2890 return; 2891 } 2892 2893 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, 2894 errp); 2895 } 2896 2897 static void virt_dimm_unplug(HotplugHandler *hotplug_dev, 2898 DeviceState *dev, Error **errp) 2899 { 2900 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2901 Error *local_err = NULL; 2902 2903 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); 2904 if (local_err) { 2905 goto out; 2906 } 2907 2908 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); 2909 qdev_unrealize(dev); 2910 2911 out: 2912 error_propagate(errp, local_err); 2913 } 2914 2915 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2916 DeviceState *dev, Error **errp) 2917 { 2918 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2919 virt_dimm_unplug_request(hotplug_dev, dev, errp); 2920 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2921 virt_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 2922 } else { 2923 error_setg(errp, "device unplug request for unsupported device" 2924 " type: %s", object_get_typename(OBJECT(dev))); 2925 } 2926 } 2927 2928 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2929 DeviceState *dev, Error **errp) 2930 { 2931 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2932 virt_dimm_unplug(hotplug_dev, dev, errp); 2933 } else { 2934 error_setg(errp, "virt: device unplug for unsupported device" 2935 " type: %s", object_get_typename(OBJECT(dev))); 2936 } 2937 } 2938 2939 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2940 DeviceState *dev) 2941 { 2942 MachineClass *mc = MACHINE_GET_CLASS(machine); 2943 2944 if (device_is_dynamic_sysbus(mc, dev) || 2945 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2946 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 2947 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2948 return HOTPLUG_HANDLER(machine); 2949 } 2950 return NULL; 2951 } 2952 2953 /* 2954 * for arm64 kvm_type [7-0] encodes the requested number of bits 2955 * in the IPA address space 2956 */ 2957 static int virt_kvm_type(MachineState *ms, const char *type_str) 2958 { 2959 VirtMachineState *vms = VIRT_MACHINE(ms); 2960 int max_vm_pa_size, requested_pa_size; 2961 bool fixed_ipa; 2962 2963 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 2964 2965 /* we freeze the memory map to compute the highest gpa */ 2966 virt_set_memmap(vms, max_vm_pa_size); 2967 2968 requested_pa_size = 64 - clz64(vms->highest_gpa); 2969 2970 /* 2971 * KVM requires the IPA size to be at least 32 bits. 2972 */ 2973 if (requested_pa_size < 32) { 2974 requested_pa_size = 32; 2975 } 2976 2977 if (requested_pa_size > max_vm_pa_size) { 2978 error_report("-m and ,maxmem option values " 2979 "require an IPA range (%d bits) larger than " 2980 "the one supported by the host (%d bits)", 2981 requested_pa_size, max_vm_pa_size); 2982 exit(1); 2983 } 2984 /* 2985 * We return the requested PA log size, unless KVM only supports 2986 * the implicit legacy 40b IPA setting, in which case the kvm_type 2987 * must be 0. 2988 */ 2989 return fixed_ipa ? 0 : requested_pa_size; 2990 } 2991 2992 static void virt_machine_class_init(ObjectClass *oc, void *data) 2993 { 2994 MachineClass *mc = MACHINE_CLASS(oc); 2995 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2996 2997 mc->init = machvirt_init; 2998 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 2999 * The value may be reduced later when we have more information about the 3000 * configuration of the particular instance. 3001 */ 3002 mc->max_cpus = 512; 3003 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 3004 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 3005 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 3006 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 3007 #ifdef CONFIG_TPM 3008 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 3009 #endif 3010 mc->block_default_type = IF_VIRTIO; 3011 mc->no_cdrom = 1; 3012 mc->pci_allow_0_address = true; 3013 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 3014 mc->minimum_page_bits = 12; 3015 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 3016 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 3017 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 3018 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 3019 mc->kvm_type = virt_kvm_type; 3020 assert(!mc->get_hotplug_handler); 3021 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 3022 hc->pre_plug = virt_machine_device_pre_plug_cb; 3023 hc->plug = virt_machine_device_plug_cb; 3024 hc->unplug_request = virt_machine_device_unplug_request_cb; 3025 hc->unplug = virt_machine_device_unplug_cb; 3026 mc->nvdimm_supported = true; 3027 mc->smp_props.clusters_supported = true; 3028 mc->auto_enable_numa_with_memhp = true; 3029 mc->auto_enable_numa_with_memdev = true; 3030 mc->default_ram_id = "mach-virt.ram"; 3031 3032 object_class_property_add(oc, "acpi", "OnOffAuto", 3033 virt_get_acpi, virt_set_acpi, 3034 NULL, NULL); 3035 object_class_property_set_description(oc, "acpi", 3036 "Enable ACPI"); 3037 object_class_property_add_bool(oc, "secure", virt_get_secure, 3038 virt_set_secure); 3039 object_class_property_set_description(oc, "secure", 3040 "Set on/off to enable/disable the ARM " 3041 "Security Extensions (TrustZone)"); 3042 3043 object_class_property_add_bool(oc, "virtualization", virt_get_virt, 3044 virt_set_virt); 3045 object_class_property_set_description(oc, "virtualization", 3046 "Set on/off to enable/disable emulating a " 3047 "guest CPU which implements the ARM " 3048 "Virtualization Extensions"); 3049 3050 object_class_property_add_bool(oc, "highmem", virt_get_highmem, 3051 virt_set_highmem); 3052 object_class_property_set_description(oc, "highmem", 3053 "Set on/off to enable/disable using " 3054 "physical address space above 32 bits"); 3055 3056 object_class_property_add_bool(oc, "compact-highmem", 3057 virt_get_compact_highmem, 3058 virt_set_compact_highmem); 3059 object_class_property_set_description(oc, "compact-highmem", 3060 "Set on/off to enable/disable compact " 3061 "layout for high memory regions"); 3062 3063 object_class_property_add_bool(oc, "highmem-redists", 3064 virt_get_highmem_redists, 3065 virt_set_highmem_redists); 3066 object_class_property_set_description(oc, "highmem-redists", 3067 "Set on/off to enable/disable high " 3068 "memory region for GICv3 or GICv4 " 3069 "redistributor"); 3070 3071 object_class_property_add_bool(oc, "highmem-ecam", 3072 virt_get_highmem_ecam, 3073 virt_set_highmem_ecam); 3074 object_class_property_set_description(oc, "highmem-ecam", 3075 "Set on/off to enable/disable high " 3076 "memory region for PCI ECAM"); 3077 3078 object_class_property_add_bool(oc, "highmem-mmio", 3079 virt_get_highmem_mmio, 3080 virt_set_highmem_mmio); 3081 object_class_property_set_description(oc, "highmem-mmio", 3082 "Set on/off to enable/disable high " 3083 "memory region for PCI MMIO"); 3084 3085 object_class_property_add_str(oc, "gic-version", virt_get_gic_version, 3086 virt_set_gic_version); 3087 object_class_property_set_description(oc, "gic-version", 3088 "Set GIC version. " 3089 "Valid values are 2, 3, 4, host and max"); 3090 3091 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); 3092 object_class_property_set_description(oc, "iommu", 3093 "Set the IOMMU type. " 3094 "Valid values are none and smmuv3"); 3095 3096 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 3097 virt_get_default_bus_bypass_iommu, 3098 virt_set_default_bus_bypass_iommu); 3099 object_class_property_set_description(oc, "default-bus-bypass-iommu", 3100 "Set on/off to enable/disable " 3101 "bypass_iommu for default root bus"); 3102 3103 object_class_property_add_bool(oc, "ras", virt_get_ras, 3104 virt_set_ras); 3105 object_class_property_set_description(oc, "ras", 3106 "Set on/off to enable/disable reporting host memory errors " 3107 "to a KVM guest using ACPI and guest external abort exceptions"); 3108 3109 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); 3110 object_class_property_set_description(oc, "mte", 3111 "Set on/off to enable/disable emulating a " 3112 "guest CPU which implements the ARM " 3113 "Memory Tagging Extension"); 3114 3115 object_class_property_add_bool(oc, "its", virt_get_its, 3116 virt_set_its); 3117 object_class_property_set_description(oc, "its", 3118 "Set on/off to enable/disable " 3119 "ITS instantiation"); 3120 3121 object_class_property_add_bool(oc, "dtb-randomness", 3122 virt_get_dtb_randomness, 3123 virt_set_dtb_randomness); 3124 object_class_property_set_description(oc, "dtb-randomness", 3125 "Set off to disable passing random or " 3126 "non-deterministic dtb nodes to guest"); 3127 3128 object_class_property_add_bool(oc, "dtb-kaslr-seed", 3129 virt_get_dtb_randomness, 3130 virt_set_dtb_randomness); 3131 object_class_property_set_description(oc, "dtb-kaslr-seed", 3132 "Deprecated synonym of dtb-randomness"); 3133 3134 object_class_property_add_str(oc, "x-oem-id", 3135 virt_get_oem_id, 3136 virt_set_oem_id); 3137 object_class_property_set_description(oc, "x-oem-id", 3138 "Override the default value of field OEMID " 3139 "in ACPI table header." 3140 "The string may be up to 6 bytes in size"); 3141 3142 3143 object_class_property_add_str(oc, "x-oem-table-id", 3144 virt_get_oem_table_id, 3145 virt_set_oem_table_id); 3146 object_class_property_set_description(oc, "x-oem-table-id", 3147 "Override the default value of field OEM Table ID " 3148 "in ACPI table header." 3149 "The string may be up to 8 bytes in size"); 3150 3151 } 3152 3153 static void virt_instance_init(Object *obj) 3154 { 3155 VirtMachineState *vms = VIRT_MACHINE(obj); 3156 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 3157 3158 /* EL3 is disabled by default on virt: this makes us consistent 3159 * between KVM and TCG for this board, and it also allows us to 3160 * boot UEFI blobs which assume no TrustZone support. 3161 */ 3162 vms->secure = false; 3163 3164 /* EL2 is also disabled by default, for similar reasons */ 3165 vms->virt = false; 3166 3167 /* High memory is enabled by default */ 3168 vms->highmem = true; 3169 vms->highmem_compact = !vmc->no_highmem_compact; 3170 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 3171 3172 vms->highmem_ecam = !vmc->no_highmem_ecam; 3173 vms->highmem_mmio = true; 3174 vms->highmem_redists = true; 3175 3176 if (vmc->no_its) { 3177 vms->its = false; 3178 } else { 3179 /* Default allows ITS instantiation */ 3180 vms->its = true; 3181 3182 if (vmc->no_tcg_its) { 3183 vms->tcg_its = false; 3184 } else { 3185 vms->tcg_its = true; 3186 } 3187 } 3188 3189 /* Default disallows iommu instantiation */ 3190 vms->iommu = VIRT_IOMMU_NONE; 3191 3192 /* The default root bus is attached to iommu by default */ 3193 vms->default_bus_bypass_iommu = false; 3194 3195 /* Default disallows RAS instantiation */ 3196 vms->ras = false; 3197 3198 /* MTE is disabled by default. */ 3199 vms->mte = false; 3200 3201 /* Supply kaslr-seed and rng-seed by default */ 3202 vms->dtb_randomness = true; 3203 3204 vms->irqmap = a15irqmap; 3205 3206 virt_flash_create(vms); 3207 3208 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 3209 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 3210 } 3211 3212 static const TypeInfo virt_machine_info = { 3213 .name = TYPE_VIRT_MACHINE, 3214 .parent = TYPE_MACHINE, 3215 .abstract = true, 3216 .instance_size = sizeof(VirtMachineState), 3217 .class_size = sizeof(VirtMachineClass), 3218 .class_init = virt_machine_class_init, 3219 .instance_init = virt_instance_init, 3220 .interfaces = (InterfaceInfo[]) { 3221 { TYPE_HOTPLUG_HANDLER }, 3222 { } 3223 }, 3224 }; 3225 3226 static void machvirt_machine_init(void) 3227 { 3228 type_register_static(&virt_machine_info); 3229 } 3230 type_init(machvirt_machine_init); 3231 3232 static void virt_machine_8_0_options(MachineClass *mc) 3233 { 3234 } 3235 DEFINE_VIRT_MACHINE_AS_LATEST(8, 0) 3236 3237 static void virt_machine_7_2_options(MachineClass *mc) 3238 { 3239 virt_machine_8_0_options(mc); 3240 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 3241 } 3242 DEFINE_VIRT_MACHINE(7, 2) 3243 3244 static void virt_machine_7_1_options(MachineClass *mc) 3245 { 3246 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3247 3248 virt_machine_7_2_options(mc); 3249 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 3250 /* Compact layout for high memory regions was introduced with 7.2 */ 3251 vmc->no_highmem_compact = true; 3252 } 3253 DEFINE_VIRT_MACHINE(7, 1) 3254 3255 static void virt_machine_7_0_options(MachineClass *mc) 3256 { 3257 virt_machine_7_1_options(mc); 3258 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 3259 } 3260 DEFINE_VIRT_MACHINE(7, 0) 3261 3262 static void virt_machine_6_2_options(MachineClass *mc) 3263 { 3264 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3265 3266 virt_machine_7_0_options(mc); 3267 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 3268 vmc->no_tcg_lpa2 = true; 3269 } 3270 DEFINE_VIRT_MACHINE(6, 2) 3271 3272 static void virt_machine_6_1_options(MachineClass *mc) 3273 { 3274 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3275 3276 virt_machine_6_2_options(mc); 3277 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 3278 mc->smp_props.prefer_sockets = true; 3279 vmc->no_cpu_topology = true; 3280 3281 /* qemu ITS was introduced with 6.2 */ 3282 vmc->no_tcg_its = true; 3283 } 3284 DEFINE_VIRT_MACHINE(6, 1) 3285 3286 static void virt_machine_6_0_options(MachineClass *mc) 3287 { 3288 virt_machine_6_1_options(mc); 3289 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 3290 } 3291 DEFINE_VIRT_MACHINE(6, 0) 3292 3293 static void virt_machine_5_2_options(MachineClass *mc) 3294 { 3295 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3296 3297 virt_machine_6_0_options(mc); 3298 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 3299 vmc->no_secure_gpio = true; 3300 } 3301 DEFINE_VIRT_MACHINE(5, 2) 3302 3303 static void virt_machine_5_1_options(MachineClass *mc) 3304 { 3305 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3306 3307 virt_machine_5_2_options(mc); 3308 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 3309 vmc->no_kvm_steal_time = true; 3310 } 3311 DEFINE_VIRT_MACHINE(5, 1) 3312 3313 static void virt_machine_5_0_options(MachineClass *mc) 3314 { 3315 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3316 3317 virt_machine_5_1_options(mc); 3318 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 3319 mc->numa_mem_supported = true; 3320 vmc->acpi_expose_flash = true; 3321 mc->auto_enable_numa_with_memdev = false; 3322 } 3323 DEFINE_VIRT_MACHINE(5, 0) 3324 3325 static void virt_machine_4_2_options(MachineClass *mc) 3326 { 3327 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3328 3329 virt_machine_5_0_options(mc); 3330 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 3331 vmc->kvm_no_adjvtime = true; 3332 } 3333 DEFINE_VIRT_MACHINE(4, 2) 3334 3335 static void virt_machine_4_1_options(MachineClass *mc) 3336 { 3337 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3338 3339 virt_machine_4_2_options(mc); 3340 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 3341 vmc->no_ged = true; 3342 mc->auto_enable_numa_with_memhp = false; 3343 } 3344 DEFINE_VIRT_MACHINE(4, 1) 3345 3346 static void virt_machine_4_0_options(MachineClass *mc) 3347 { 3348 virt_machine_4_1_options(mc); 3349 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 3350 } 3351 DEFINE_VIRT_MACHINE(4, 0) 3352 3353 static void virt_machine_3_1_options(MachineClass *mc) 3354 { 3355 virt_machine_4_0_options(mc); 3356 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 3357 } 3358 DEFINE_VIRT_MACHINE(3, 1) 3359 3360 static void virt_machine_3_0_options(MachineClass *mc) 3361 { 3362 virt_machine_3_1_options(mc); 3363 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 3364 } 3365 DEFINE_VIRT_MACHINE(3, 0) 3366 3367 static void virt_machine_2_12_options(MachineClass *mc) 3368 { 3369 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3370 3371 virt_machine_3_0_options(mc); 3372 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 3373 vmc->no_highmem_ecam = true; 3374 mc->max_cpus = 255; 3375 } 3376 DEFINE_VIRT_MACHINE(2, 12) 3377 3378 static void virt_machine_2_11_options(MachineClass *mc) 3379 { 3380 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3381 3382 virt_machine_2_12_options(mc); 3383 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 3384 vmc->smbios_old_sys_ver = true; 3385 } 3386 DEFINE_VIRT_MACHINE(2, 11) 3387 3388 static void virt_machine_2_10_options(MachineClass *mc) 3389 { 3390 virt_machine_2_11_options(mc); 3391 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 3392 /* before 2.11 we never faulted accesses to bad addresses */ 3393 mc->ignore_memory_transaction_failures = true; 3394 } 3395 DEFINE_VIRT_MACHINE(2, 10) 3396 3397 static void virt_machine_2_9_options(MachineClass *mc) 3398 { 3399 virt_machine_2_10_options(mc); 3400 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 3401 } 3402 DEFINE_VIRT_MACHINE(2, 9) 3403 3404 static void virt_machine_2_8_options(MachineClass *mc) 3405 { 3406 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3407 3408 virt_machine_2_9_options(mc); 3409 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 3410 /* For 2.8 and earlier we falsely claimed in the DT that 3411 * our timers were edge-triggered, not level-triggered. 3412 */ 3413 vmc->claim_edge_triggered_timers = true; 3414 } 3415 DEFINE_VIRT_MACHINE(2, 8) 3416 3417 static void virt_machine_2_7_options(MachineClass *mc) 3418 { 3419 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3420 3421 virt_machine_2_8_options(mc); 3422 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 3423 /* ITS was introduced with 2.8 */ 3424 vmc->no_its = true; 3425 /* Stick with 1K pages for migration compatibility */ 3426 mc->minimum_page_bits = 0; 3427 } 3428 DEFINE_VIRT_MACHINE(2, 7) 3429 3430 static void virt_machine_2_6_options(MachineClass *mc) 3431 { 3432 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3433 3434 virt_machine_2_7_options(mc); 3435 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 3436 vmc->disallow_affinity_adjustment = true; 3437 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 3438 vmc->no_pmu = true; 3439 } 3440 DEFINE_VIRT_MACHINE(2, 6) 3441