1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/datadir.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "hw/sysbus.h" 37 #include "hw/arm/boot.h" 38 #include "hw/arm/primecell.h" 39 #include "hw/arm/virt.h" 40 #include "hw/block/flash.h" 41 #include "hw/vfio/vfio-calxeda-xgmac.h" 42 #include "hw/vfio/vfio-amd-xgbe.h" 43 #include "hw/display/ramfb.h" 44 #include "net/net.h" 45 #include "system/device_tree.h" 46 #include "system/numa.h" 47 #include "system/runstate.h" 48 #include "system/tpm.h" 49 #include "system/tcg.h" 50 #include "system/kvm.h" 51 #include "system/hvf.h" 52 #include "system/qtest.h" 53 #include "hw/loader.h" 54 #include "qapi/error.h" 55 #include "qemu/bitops.h" 56 #include "qemu/cutils.h" 57 #include "qemu/error-report.h" 58 #include "qemu/module.h" 59 #include "hw/pci-host/gpex.h" 60 #include "hw/pci-bridge/pci_expander_bridge.h" 61 #include "hw/virtio/virtio-pci.h" 62 #include "hw/core/sysbus-fdt.h" 63 #include "hw/platform-bus.h" 64 #include "hw/qdev-properties.h" 65 #include "hw/arm/fdt.h" 66 #include "hw/intc/arm_gic.h" 67 #include "hw/intc/arm_gicv3_common.h" 68 #include "hw/intc/arm_gicv3_its_common.h" 69 #include "hw/irq.h" 70 #include "kvm_arm.h" 71 #include "hvf_arm.h" 72 #include "hw/firmware/smbios.h" 73 #include "qapi/visitor.h" 74 #include "qapi/qapi-visit-common.h" 75 #include "qobject/qlist.h" 76 #include "standard-headers/linux/input.h" 77 #include "hw/arm/smmuv3.h" 78 #include "hw/acpi/acpi.h" 79 #include "target/arm/cpu-qom.h" 80 #include "target/arm/internals.h" 81 #include "target/arm/multiprocessing.h" 82 #include "target/arm/gtimer.h" 83 #include "hw/mem/pc-dimm.h" 84 #include "hw/mem/nvdimm.h" 85 #include "hw/acpi/generic_event_device.h" 86 #include "hw/uefi/var-service-api.h" 87 #include "hw/virtio/virtio-md-pci.h" 88 #include "hw/virtio/virtio-iommu.h" 89 #include "hw/char/pl011.h" 90 #include "hw/cxl/cxl.h" 91 #include "hw/cxl/cxl_host.h" 92 #include "qemu/guest-random.h" 93 94 static GlobalProperty arm_virt_compat[] = { 95 { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "48" }, 96 }; 97 static const size_t arm_virt_compat_len = G_N_ELEMENTS(arm_virt_compat); 98 99 /* 100 * This cannot be called from the virt_machine_class_init() because 101 * TYPE_VIRT_MACHINE is abstract and mc->compat_props g_ptr_array_new() 102 * only is called on virt non abstract class init. 103 */ 104 static void arm_virt_compat_set(MachineClass *mc) 105 { 106 compat_props_add(mc->compat_props, arm_virt_compat, 107 arm_virt_compat_len); 108 } 109 110 #define DEFINE_VIRT_MACHINE_IMPL(latest, ...) \ 111 static void MACHINE_VER_SYM(class_init, virt, __VA_ARGS__)( \ 112 ObjectClass *oc, \ 113 const void *data) \ 114 { \ 115 MachineClass *mc = MACHINE_CLASS(oc); \ 116 arm_virt_compat_set(mc); \ 117 MACHINE_VER_SYM(options, virt, __VA_ARGS__)(mc); \ 118 mc->desc = "QEMU " MACHINE_VER_STR(__VA_ARGS__) " ARM Virtual Machine"; \ 119 MACHINE_VER_DEPRECATION(__VA_ARGS__); \ 120 if (latest) { \ 121 mc->alias = "virt"; \ 122 } \ 123 } \ 124 static const TypeInfo MACHINE_VER_SYM(info, virt, __VA_ARGS__) = \ 125 { \ 126 .name = MACHINE_VER_TYPE_NAME("virt", __VA_ARGS__), \ 127 .parent = TYPE_VIRT_MACHINE, \ 128 .class_init = MACHINE_VER_SYM(class_init, virt, __VA_ARGS__), \ 129 }; \ 130 static void MACHINE_VER_SYM(register, virt, __VA_ARGS__)(void) \ 131 { \ 132 MACHINE_VER_DELETION(__VA_ARGS__); \ 133 type_register_static(&MACHINE_VER_SYM(info, virt, __VA_ARGS__)); \ 134 } \ 135 type_init(MACHINE_VER_SYM(register, virt, __VA_ARGS__)); 136 137 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 138 DEFINE_VIRT_MACHINE_IMPL(true, major, minor) 139 #define DEFINE_VIRT_MACHINE(major, minor) \ 140 DEFINE_VIRT_MACHINE_IMPL(false, major, minor) 141 142 143 /* Number of external interrupt lines to configure the GIC with */ 144 #define NUM_IRQS 256 145 146 #define PLATFORM_BUS_NUM_IRQS 64 147 148 /* Legacy RAM limit in GB (< version 4.0) */ 149 #define LEGACY_RAMLIMIT_GB 255 150 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 151 152 /* Addresses and sizes of our components. 153 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 154 * 128MB..256MB is used for miscellaneous device I/O. 155 * 256MB..1GB is reserved for possible future PCI support (ie where the 156 * PCI memory window will go if we add a PCI host controller). 157 * 1GB and up is RAM (which may happily spill over into the 158 * high memory region beyond 4GB). 159 * This represents a compromise between how much RAM can be given to 160 * a 32 bit VM and leaving space for expansion and in particular for PCI. 161 * Note that devices should generally be placed at multiples of 0x10000, 162 * to accommodate guests using 64K pages. 163 */ 164 static const MemMapEntry base_memmap[] = { 165 /* Space up to 0x8000000 is reserved for a boot ROM */ 166 [VIRT_FLASH] = { 0, 0x08000000 }, 167 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 168 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 169 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 170 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 171 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 172 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 173 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 174 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 175 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 176 /* This redistributor space allows up to 2*64kB*123 CPUs */ 177 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 178 [VIRT_UART0] = { 0x09000000, 0x00001000 }, 179 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 180 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 181 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 182 [VIRT_UART1] = { 0x09040000, 0x00001000 }, 183 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 184 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 185 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 186 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 187 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, 188 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, 189 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 190 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 191 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 192 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 193 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 194 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 195 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 196 /* Actual RAM size depends on initial RAM and device memory settings */ 197 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 198 }; 199 200 /* Update the docs for highmem-mmio-size when changing this default */ 201 #define DEFAULT_HIGH_PCIE_MMIO_SIZE_GB 512 202 #define DEFAULT_HIGH_PCIE_MMIO_SIZE (DEFAULT_HIGH_PCIE_MMIO_SIZE_GB * GiB) 203 204 /* 205 * Highmem IO Regions: This memory map is floating, located after the RAM. 206 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 207 * top of the RAM, so that its base get the same alignment as the size, 208 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 209 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 210 * Note the extended_memmap is sized so that it eventually also includes the 211 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 212 * index of base_memmap). 213 * 214 * The memory map for these Highmem IO Regions can be in legacy or compact 215 * layout, depending on 'compact-highmem' property. With legacy layout, the 216 * PA space for one specific region is always reserved, even if the region 217 * has been disabled or doesn't fit into the PA space. However, the PA space 218 * for the region won't be reserved in these circumstances with compact layout. 219 * 220 * Note that the highmem-mmio-size property will update the high PCIE MMIO size 221 * field in this array. 222 */ 223 static MemMapEntry extended_memmap[] = { 224 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 225 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 226 [VIRT_CXL_HOST] = { 0x0, 64 * KiB * 16 }, /* 16 UID */ 227 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 228 /* Second PCIe window */ 229 [VIRT_HIGH_PCIE_MMIO] = { 0x0, DEFAULT_HIGH_PCIE_MMIO_SIZE }, 230 /* Any CXL Fixed memory windows come here */ 231 }; 232 233 static const int a15irqmap[] = { 234 [VIRT_UART0] = 1, 235 [VIRT_RTC] = 2, 236 [VIRT_PCIE] = 3, /* ... to 6 */ 237 [VIRT_GPIO] = 7, 238 [VIRT_UART1] = 8, 239 [VIRT_ACPI_GED] = 9, 240 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 241 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 242 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 243 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 244 }; 245 246 static void create_randomness(MachineState *ms, const char *node) 247 { 248 struct { 249 uint64_t kaslr; 250 uint8_t rng[32]; 251 } seed; 252 253 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { 254 return; 255 } 256 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr); 257 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); 258 } 259 260 /* 261 * The CPU object always exposes the NS EL2 virt timer IRQ line, 262 * but we don't want to advertise it to the guest in the dtb or ACPI 263 * table unless it's really going to do something. 264 */ 265 static bool ns_el2_virt_timer_present(void) 266 { 267 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0)); 268 CPUARMState *env = &cpu->env; 269 270 return arm_feature(env, ARM_FEATURE_AARCH64) && 271 arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu); 272 } 273 274 static void create_fdt(VirtMachineState *vms) 275 { 276 MachineState *ms = MACHINE(vms); 277 int nb_numa_nodes = ms->numa_state->num_nodes; 278 void *fdt = create_device_tree(&vms->fdt_size); 279 280 if (!fdt) { 281 error_report("create_device_tree() failed"); 282 exit(1); 283 } 284 285 ms->fdt = fdt; 286 287 /* Header */ 288 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 289 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 290 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 291 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt"); 292 293 /* 294 * For QEMU, all DMA is coherent. Advertising this in the root node 295 * has two benefits: 296 * 297 * - It avoids potential bugs where we forget to mark a DMA 298 * capable device as being dma-coherent 299 * - It avoids spurious warnings from the Linux kernel about 300 * devices which can't do DMA at all 301 */ 302 qemu_fdt_setprop(fdt, "/", "dma-coherent", NULL, 0); 303 304 /* /chosen must exist for load_dtb to fill in necessary properties later */ 305 qemu_fdt_add_subnode(fdt, "/chosen"); 306 if (vms->dtb_randomness) { 307 create_randomness(ms, "/chosen"); 308 } 309 310 if (vms->secure) { 311 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 312 if (vms->dtb_randomness) { 313 create_randomness(ms, "/secure-chosen"); 314 } 315 } 316 317 qemu_fdt_add_subnode(fdt, "/aliases"); 318 319 /* Clock node, for the benefit of the UART. The kernel device tree 320 * binding documentation claims the PL011 node clock properties are 321 * optional but in practice if you omit them the kernel refuses to 322 * probe for the device. 323 */ 324 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 325 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 326 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 327 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 328 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 329 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 330 "clk24mhz"); 331 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 332 333 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 334 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 335 uint32_t *matrix = g_malloc0(size); 336 int idx, i, j; 337 338 for (i = 0; i < nb_numa_nodes; i++) { 339 for (j = 0; j < nb_numa_nodes; j++) { 340 idx = (i * nb_numa_nodes + j) * 3; 341 matrix[idx + 0] = cpu_to_be32(i); 342 matrix[idx + 1] = cpu_to_be32(j); 343 matrix[idx + 2] = 344 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 345 } 346 } 347 348 qemu_fdt_add_subnode(fdt, "/distance-map"); 349 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 350 "numa-distance-map-v1"); 351 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 352 matrix, size); 353 g_free(matrix); 354 } 355 } 356 357 static void fdt_add_timer_nodes(const VirtMachineState *vms) 358 { 359 /* On real hardware these interrupts are level-triggered. 360 * On KVM they were edge-triggered before host kernel version 4.4, 361 * and level-triggered afterwards. 362 * On emulated QEMU they are level-triggered. 363 * 364 * Getting the DTB info about them wrong is awkward for some 365 * guest kernels: 366 * pre-4.8 ignore the DT and leave the interrupt configured 367 * with whatever the GIC reset value (or the bootloader) left it at 368 * 4.8 before rc6 honour the incorrect data by programming it back 369 * into the GIC, causing problems 370 * 4.8rc6 and later ignore the DT and always write "level triggered" 371 * into the GIC 372 * 373 * For backwards-compatibility, virt-2.8 and earlier will continue 374 * to say these are edge-triggered, but later machines will report 375 * the correct information. 376 */ 377 ARMCPU *armcpu; 378 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 379 MachineState *ms = MACHINE(vms); 380 381 if (vms->gic_version == VIRT_GIC_VERSION_2) { 382 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 383 GIC_FDT_IRQ_PPI_CPU_WIDTH, 384 (1 << MACHINE(vms)->smp.cpus) - 1); 385 } 386 387 qemu_fdt_add_subnode(ms->fdt, "/timer"); 388 389 armcpu = ARM_CPU(qemu_get_cpu(0)); 390 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 391 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 392 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", 393 compat, sizeof(compat)); 394 } else { 395 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", 396 "arm,armv7-timer"); 397 } 398 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); 399 if (vms->ns_el2_virt_timer_irq) { 400 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 401 GIC_FDT_IRQ_TYPE_PPI, 402 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, 403 GIC_FDT_IRQ_TYPE_PPI, 404 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, 405 GIC_FDT_IRQ_TYPE_PPI, 406 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, 407 GIC_FDT_IRQ_TYPE_PPI, 408 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags, 409 GIC_FDT_IRQ_TYPE_PPI, 410 INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags); 411 } else { 412 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 413 GIC_FDT_IRQ_TYPE_PPI, 414 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, 415 GIC_FDT_IRQ_TYPE_PPI, 416 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, 417 GIC_FDT_IRQ_TYPE_PPI, 418 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, 419 GIC_FDT_IRQ_TYPE_PPI, 420 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags); 421 } 422 } 423 424 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 425 { 426 int cpu; 427 int addr_cells = 1; 428 const MachineState *ms = MACHINE(vms); 429 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 430 int smp_cpus = ms->smp.cpus; 431 432 /* 433 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml 434 * On ARM v8 64-bit systems value should be set to 2, 435 * that corresponds to the MPIDR_EL1 register size. 436 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 437 * in the system, #address-cells can be set to 1, since 438 * MPIDR_EL1[63:32] bits are not used for CPUs 439 * identification. 440 * 441 * Here we actually don't know whether our system is 32- or 64-bit one. 442 * The simplest way to go is to examine affinity IDs of all our CPUs. If 443 * at least one of them has Aff3 populated, we set #address-cells to 2. 444 */ 445 for (cpu = 0; cpu < smp_cpus; cpu++) { 446 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 447 448 if (arm_cpu_mp_affinity(armcpu) & ARM_AFF3_MASK) { 449 addr_cells = 2; 450 break; 451 } 452 } 453 454 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 455 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); 456 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 457 458 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 459 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 460 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 461 CPUState *cs = CPU(armcpu); 462 463 qemu_fdt_add_subnode(ms->fdt, nodename); 464 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 465 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 466 armcpu->dtb_compatible); 467 468 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { 469 qemu_fdt_setprop_string(ms->fdt, nodename, 470 "enable-method", "psci"); 471 } 472 473 if (addr_cells == 2) { 474 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", 475 arm_cpu_mp_affinity(armcpu)); 476 } else { 477 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", 478 arm_cpu_mp_affinity(armcpu)); 479 } 480 481 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 482 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 483 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 484 } 485 486 if (!vmc->no_cpu_topology) { 487 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 488 qemu_fdt_alloc_phandle(ms->fdt)); 489 } 490 491 g_free(nodename); 492 } 493 494 if (!vmc->no_cpu_topology) { 495 /* 496 * Add vCPU topology description through fdt node cpu-map. 497 * 498 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt 499 * In a SMP system, the hierarchy of CPUs can be defined through 500 * four entities that are used to describe the layout of CPUs in 501 * the system: socket/cluster/core/thread. 502 * 503 * A socket node represents the boundary of system physical package 504 * and its child nodes must be one or more cluster nodes. A system 505 * can contain several layers of clustering within a single physical 506 * package and cluster nodes can be contained in parent cluster nodes. 507 * 508 * Note: currently we only support one layer of clustering within 509 * each physical package. 510 */ 511 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 512 513 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 514 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); 515 char *map_path; 516 517 if (ms->smp.threads > 1) { 518 map_path = g_strdup_printf( 519 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", 520 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), 521 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, 522 (cpu / ms->smp.threads) % ms->smp.cores, 523 cpu % ms->smp.threads); 524 } else { 525 map_path = g_strdup_printf( 526 "/cpus/cpu-map/socket%d/cluster%d/core%d", 527 cpu / (ms->smp.clusters * ms->smp.cores), 528 (cpu / ms->smp.cores) % ms->smp.clusters, 529 cpu % ms->smp.cores); 530 } 531 qemu_fdt_add_path(ms->fdt, map_path); 532 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 533 534 g_free(map_path); 535 g_free(cpu_path); 536 } 537 } 538 } 539 540 static void fdt_add_its_gic_node(VirtMachineState *vms) 541 { 542 char *nodename; 543 MachineState *ms = MACHINE(vms); 544 545 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 546 nodename = g_strdup_printf("/intc/its@%" PRIx64, 547 vms->memmap[VIRT_GIC_ITS].base); 548 qemu_fdt_add_subnode(ms->fdt, nodename); 549 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 550 "arm,gic-v3-its"); 551 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 552 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1); 553 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 554 2, vms->memmap[VIRT_GIC_ITS].base, 555 2, vms->memmap[VIRT_GIC_ITS].size); 556 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 557 g_free(nodename); 558 } 559 560 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 561 { 562 MachineState *ms = MACHINE(vms); 563 char *nodename; 564 565 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 566 vms->memmap[VIRT_GIC_V2M].base); 567 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 568 qemu_fdt_add_subnode(ms->fdt, nodename); 569 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 570 "arm,gic-v2m-frame"); 571 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 572 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 573 2, vms->memmap[VIRT_GIC_V2M].base, 574 2, vms->memmap[VIRT_GIC_V2M].size); 575 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 576 g_free(nodename); 577 } 578 579 static void fdt_add_gic_node(VirtMachineState *vms) 580 { 581 MachineState *ms = MACHINE(vms); 582 char *nodename; 583 584 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 585 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); 586 587 nodename = g_strdup_printf("/intc@%" PRIx64, 588 vms->memmap[VIRT_GIC_DIST].base); 589 qemu_fdt_add_subnode(ms->fdt, nodename); 590 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 591 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 592 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 593 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 594 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 595 if (vms->gic_version != VIRT_GIC_VERSION_2) { 596 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 597 598 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 599 "arm,gic-v3"); 600 601 qemu_fdt_setprop_cell(ms->fdt, nodename, 602 "#redistributor-regions", nb_redist_regions); 603 604 if (nb_redist_regions == 1) { 605 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 606 2, vms->memmap[VIRT_GIC_DIST].base, 607 2, vms->memmap[VIRT_GIC_DIST].size, 608 2, vms->memmap[VIRT_GIC_REDIST].base, 609 2, vms->memmap[VIRT_GIC_REDIST].size); 610 } else { 611 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 612 2, vms->memmap[VIRT_GIC_DIST].base, 613 2, vms->memmap[VIRT_GIC_DIST].size, 614 2, vms->memmap[VIRT_GIC_REDIST].base, 615 2, vms->memmap[VIRT_GIC_REDIST].size, 616 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 617 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 618 } 619 620 if (vms->virt) { 621 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 622 GIC_FDT_IRQ_TYPE_PPI, 623 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), 624 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 625 } 626 } else { 627 /* 'cortex-a15-gic' means 'GIC v2' */ 628 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 629 "arm,cortex-a15-gic"); 630 if (!vms->virt) { 631 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 632 2, vms->memmap[VIRT_GIC_DIST].base, 633 2, vms->memmap[VIRT_GIC_DIST].size, 634 2, vms->memmap[VIRT_GIC_CPU].base, 635 2, vms->memmap[VIRT_GIC_CPU].size); 636 } else { 637 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 638 2, vms->memmap[VIRT_GIC_DIST].base, 639 2, vms->memmap[VIRT_GIC_DIST].size, 640 2, vms->memmap[VIRT_GIC_CPU].base, 641 2, vms->memmap[VIRT_GIC_CPU].size, 642 2, vms->memmap[VIRT_GIC_HYP].base, 643 2, vms->memmap[VIRT_GIC_HYP].size, 644 2, vms->memmap[VIRT_GIC_VCPU].base, 645 2, vms->memmap[VIRT_GIC_VCPU].size); 646 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 647 GIC_FDT_IRQ_TYPE_PPI, 648 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), 649 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 650 } 651 } 652 653 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); 654 g_free(nodename); 655 } 656 657 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 658 { 659 ARMCPU *armcpu = ARM_CPU(first_cpu); 660 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 661 MachineState *ms = MACHINE(vms); 662 663 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 664 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); 665 return; 666 } 667 668 if (vms->gic_version == VIRT_GIC_VERSION_2) { 669 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 670 GIC_FDT_IRQ_PPI_CPU_WIDTH, 671 (1 << MACHINE(vms)->smp.cpus) - 1); 672 } 673 674 qemu_fdt_add_subnode(ms->fdt, "/pmu"); 675 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 676 const char compat[] = "arm,armv8-pmuv3"; 677 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", 678 compat, sizeof(compat)); 679 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", 680 GIC_FDT_IRQ_TYPE_PPI, 681 INTID_TO_PPI(VIRTUAL_PMU_IRQ), irqflags); 682 } 683 } 684 685 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 686 { 687 DeviceState *dev; 688 MachineState *ms = MACHINE(vms); 689 int irq = vms->irqmap[VIRT_ACPI_GED]; 690 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 691 692 if (ms->ram_slots) { 693 event |= ACPI_GED_MEM_HOTPLUG_EVT; 694 } 695 696 if (ms->nvdimms_state->is_enabled) { 697 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 698 } 699 700 dev = qdev_new(TYPE_ACPI_GED); 701 qdev_prop_set_uint32(dev, "ged-event", event); 702 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 703 704 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 705 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 706 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 707 708 return dev; 709 } 710 711 static void create_its(VirtMachineState *vms) 712 { 713 DeviceState *dev; 714 715 assert(vms->its); 716 if (!kvm_irqchip_in_kernel() && !vms->tcg_its) { 717 /* 718 * Do nothing if ITS is neither supported by the host nor emulated by 719 * the machine. 720 */ 721 return; 722 } 723 724 dev = qdev_new(its_class_name()); 725 726 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 727 &error_abort); 728 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 729 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 730 731 fdt_add_its_gic_node(vms); 732 vms->msi_controller = VIRT_MSI_CTRL_ITS; 733 } 734 735 static void create_v2m(VirtMachineState *vms) 736 { 737 int i; 738 int irq = vms->irqmap[VIRT_GIC_V2M]; 739 DeviceState *dev; 740 741 dev = qdev_new("arm-gicv2m"); 742 qdev_prop_set_uint32(dev, "base-spi", irq); 743 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 744 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 745 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 746 747 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 748 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 749 qdev_get_gpio_in(vms->gic, irq + i)); 750 } 751 752 fdt_add_v2m_gic_node(vms); 753 vms->msi_controller = VIRT_MSI_CTRL_GICV2M; 754 } 755 756 /* 757 * If the CPU has FEAT_NMI, then turn on the NMI support in the GICv3 too. 758 * It's permitted to have a configuration with NMI in the CPU (and thus the 759 * GICv3 CPU interface) but not in the distributor/redistributors, but it's 760 * not very useful. 761 */ 762 static bool gicv3_nmi_present(VirtMachineState *vms) 763 { 764 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0)); 765 766 return tcg_enabled() && cpu_isar_feature(aa64_nmi, cpu) && 767 (vms->gic_version != VIRT_GIC_VERSION_2); 768 } 769 770 static void create_gic(VirtMachineState *vms, MemoryRegion *mem) 771 { 772 MachineState *ms = MACHINE(vms); 773 /* We create a standalone GIC */ 774 SysBusDevice *gicbusdev; 775 const char *gictype; 776 int i; 777 unsigned int smp_cpus = ms->smp.cpus; 778 uint32_t nb_redist_regions = 0; 779 int revision; 780 781 if (vms->gic_version == VIRT_GIC_VERSION_2) { 782 gictype = gic_class_name(); 783 } else { 784 gictype = gicv3_class_name(); 785 } 786 787 switch (vms->gic_version) { 788 case VIRT_GIC_VERSION_2: 789 revision = 2; 790 break; 791 case VIRT_GIC_VERSION_3: 792 revision = 3; 793 break; 794 case VIRT_GIC_VERSION_4: 795 revision = 4; 796 break; 797 default: 798 g_assert_not_reached(); 799 } 800 vms->gic = qdev_new(gictype); 801 qdev_prop_set_uint32(vms->gic, "revision", revision); 802 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 803 /* Note that the num-irq property counts both internal and external 804 * interrupts; there are always 32 of the former (mandated by GIC spec). 805 */ 806 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 807 if (!kvm_irqchip_in_kernel()) { 808 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 809 } 810 811 if (vms->gic_version != VIRT_GIC_VERSION_2) { 812 QList *redist_region_count; 813 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); 814 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 815 816 nb_redist_regions = virt_gicv3_redist_region_count(vms); 817 818 redist_region_count = qlist_new(); 819 qlist_append_int(redist_region_count, redist0_count); 820 if (nb_redist_regions == 2) { 821 uint32_t redist1_capacity = 822 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 823 824 qlist_append_int(redist_region_count, 825 MIN(smp_cpus - redist0_count, redist1_capacity)); 826 } 827 qdev_prop_set_array(vms->gic, "redist-region-count", 828 redist_region_count); 829 830 if (!kvm_irqchip_in_kernel()) { 831 if (vms->tcg_its) { 832 object_property_set_link(OBJECT(vms->gic), "sysmem", 833 OBJECT(mem), &error_fatal); 834 qdev_prop_set_bit(vms->gic, "has-lpi", true); 835 } 836 } else if (vms->virt) { 837 qdev_prop_set_uint32(vms->gic, "maintenance-interrupt-id", 838 ARCH_GIC_MAINT_IRQ); 839 } 840 } else { 841 if (!kvm_irqchip_in_kernel()) { 842 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 843 vms->virt); 844 } 845 } 846 847 if (gicv3_nmi_present(vms)) { 848 qdev_prop_set_bit(vms->gic, "has-nmi", true); 849 } 850 851 gicbusdev = SYS_BUS_DEVICE(vms->gic); 852 sysbus_realize_and_unref(gicbusdev, &error_fatal); 853 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 854 if (vms->gic_version != VIRT_GIC_VERSION_2) { 855 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 856 if (nb_redist_regions == 2) { 857 sysbus_mmio_map(gicbusdev, 2, 858 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 859 } 860 } else { 861 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 862 if (vms->virt) { 863 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 864 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 865 } 866 } 867 868 /* Wire the outputs from each CPU's generic timer and the GICv3 869 * maintenance interrupt signal to the appropriate GIC PPI inputs, 870 * and the GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to the 871 * CPU's inputs. 872 */ 873 for (i = 0; i < smp_cpus; i++) { 874 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 875 int intidbase = NUM_IRQS + i * GIC_INTERNAL; 876 /* Mapping from the output timer irq lines from the CPU to the 877 * GIC PPI inputs we use for the virt board. 878 */ 879 const int timer_irq[] = { 880 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 881 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 882 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 883 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 884 [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, 885 [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ, 886 [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ, 887 }; 888 889 for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 890 qdev_connect_gpio_out(cpudev, irq, 891 qdev_get_gpio_in(vms->gic, 892 intidbase + timer_irq[irq])); 893 } 894 895 if (vms->gic_version != VIRT_GIC_VERSION_2) { 896 qemu_irq irq = qdev_get_gpio_in(vms->gic, 897 intidbase + ARCH_GIC_MAINT_IRQ); 898 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 899 0, irq); 900 } else if (vms->virt) { 901 qemu_irq irq = qdev_get_gpio_in(vms->gic, 902 intidbase + ARCH_GIC_MAINT_IRQ); 903 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 904 } 905 906 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 907 qdev_get_gpio_in(vms->gic, intidbase 908 + VIRTUAL_PMU_IRQ)); 909 910 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 911 sysbus_connect_irq(gicbusdev, i + smp_cpus, 912 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 913 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 914 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 915 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 916 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 917 918 if (vms->gic_version != VIRT_GIC_VERSION_2) { 919 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, 920 qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); 921 sysbus_connect_irq(gicbusdev, i + 5 * smp_cpus, 922 qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); 923 } 924 } 925 926 fdt_add_gic_node(vms); 927 928 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) { 929 create_its(vms); 930 } else if (vms->gic_version == VIRT_GIC_VERSION_2) { 931 create_v2m(vms); 932 } 933 } 934 935 static void create_uart(const VirtMachineState *vms, int uart, 936 MemoryRegion *mem, Chardev *chr, bool secure) 937 { 938 char *nodename; 939 hwaddr base = vms->memmap[uart].base; 940 hwaddr size = vms->memmap[uart].size; 941 int irq = vms->irqmap[uart]; 942 const char compat[] = "arm,pl011\0arm,primecell"; 943 const char clocknames[] = "uartclk\0apb_pclk"; 944 DeviceState *dev = qdev_new(TYPE_PL011); 945 SysBusDevice *s = SYS_BUS_DEVICE(dev); 946 MachineState *ms = MACHINE(vms); 947 948 qdev_prop_set_chr(dev, "chardev", chr); 949 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 950 memory_region_add_subregion(mem, base, 951 sysbus_mmio_get_region(s, 0)); 952 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 953 954 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 955 qemu_fdt_add_subnode(ms->fdt, nodename); 956 /* Note that we can't use setprop_string because of the embedded NUL */ 957 qemu_fdt_setprop(ms->fdt, nodename, "compatible", 958 compat, sizeof(compat)); 959 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 960 2, base, 2, size); 961 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 962 GIC_FDT_IRQ_TYPE_SPI, irq, 963 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 964 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", 965 vms->clock_phandle, vms->clock_phandle); 966 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", 967 clocknames, sizeof(clocknames)); 968 969 if (uart == VIRT_UART0) { 970 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 971 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", nodename); 972 } else { 973 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial1", nodename); 974 } 975 if (secure) { 976 /* Mark as not usable by the normal world */ 977 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 978 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 979 980 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", 981 nodename); 982 } 983 984 g_free(nodename); 985 } 986 987 static void create_rtc(const VirtMachineState *vms) 988 { 989 char *nodename; 990 hwaddr base = vms->memmap[VIRT_RTC].base; 991 hwaddr size = vms->memmap[VIRT_RTC].size; 992 int irq = vms->irqmap[VIRT_RTC]; 993 const char compat[] = "arm,pl031\0arm,primecell"; 994 MachineState *ms = MACHINE(vms); 995 996 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 997 998 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 999 qemu_fdt_add_subnode(ms->fdt, nodename); 1000 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 1001 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1002 2, base, 2, size); 1003 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1004 GIC_FDT_IRQ_TYPE_SPI, irq, 1005 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1006 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1007 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1008 g_free(nodename); 1009 } 1010 1011 static DeviceState *gpio_key_dev; 1012 static void virt_powerdown_req(Notifier *n, void *opaque) 1013 { 1014 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 1015 1016 if (s->acpi_dev) { 1017 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 1018 } else { 1019 /* use gpio Pin for power button event */ 1020 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 1021 } 1022 } 1023 1024 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, 1025 uint32_t phandle) 1026 { 1027 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 1028 qdev_get_gpio_in(pl061_dev, 1029 GPIO_PIN_POWER_BUTTON)); 1030 1031 qemu_fdt_add_subnode(fdt, "/gpio-keys"); 1032 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); 1033 1034 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); 1035 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", 1036 "label", "GPIO Key Poweroff"); 1037 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", 1038 KEY_POWER); 1039 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", 1040 "gpios", phandle, GPIO_PIN_POWER_BUTTON, 0); 1041 } 1042 1043 #define SECURE_GPIO_POWEROFF 0 1044 #define SECURE_GPIO_RESET 1 1045 1046 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, 1047 uint32_t phandle) 1048 { 1049 DeviceState *gpio_pwr_dev; 1050 1051 /* gpio-pwr */ 1052 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); 1053 1054 /* connect secure pl061 to gpio-pwr */ 1055 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, 1056 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); 1057 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, 1058 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); 1059 1060 qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); 1061 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", 1062 "gpio-poweroff"); 1063 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", 1064 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); 1065 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); 1066 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", 1067 "okay"); 1068 1069 qemu_fdt_add_subnode(fdt, "/gpio-restart"); 1070 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", 1071 "gpio-restart"); 1072 qemu_fdt_setprop_cells(fdt, "/gpio-restart", 1073 "gpios", phandle, SECURE_GPIO_RESET, 0); 1074 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); 1075 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", 1076 "okay"); 1077 } 1078 1079 static void create_gpio_devices(const VirtMachineState *vms, int gpio, 1080 MemoryRegion *mem) 1081 { 1082 char *nodename; 1083 DeviceState *pl061_dev; 1084 hwaddr base = vms->memmap[gpio].base; 1085 hwaddr size = vms->memmap[gpio].size; 1086 int irq = vms->irqmap[gpio]; 1087 const char compat[] = "arm,pl061\0arm,primecell"; 1088 SysBusDevice *s; 1089 MachineState *ms = MACHINE(vms); 1090 1091 pl061_dev = qdev_new("pl061"); 1092 /* Pull lines down to 0 if not driven by the PL061 */ 1093 qdev_prop_set_uint32(pl061_dev, "pullups", 0); 1094 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); 1095 s = SYS_BUS_DEVICE(pl061_dev); 1096 sysbus_realize_and_unref(s, &error_fatal); 1097 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); 1098 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 1099 1100 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); 1101 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 1102 qemu_fdt_add_subnode(ms->fdt, nodename); 1103 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1104 2, base, 2, size); 1105 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 1106 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); 1107 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); 1108 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1109 GIC_FDT_IRQ_TYPE_SPI, irq, 1110 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1111 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1112 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1113 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); 1114 1115 if (gpio != VIRT_GPIO) { 1116 /* Mark as not usable by the normal world */ 1117 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1118 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1119 } 1120 g_free(nodename); 1121 1122 /* Child gpio devices */ 1123 if (gpio == VIRT_GPIO) { 1124 create_gpio_keys(ms->fdt, pl061_dev, phandle); 1125 } else { 1126 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); 1127 } 1128 } 1129 1130 static void create_virtio_devices(const VirtMachineState *vms) 1131 { 1132 int i; 1133 hwaddr size = vms->memmap[VIRT_MMIO].size; 1134 MachineState *ms = MACHINE(vms); 1135 1136 /* We create the transports in forwards order. Since qbus_realize() 1137 * prepends (not appends) new child buses, the incrementing loop below will 1138 * create a list of virtio-mmio buses with decreasing base addresses. 1139 * 1140 * When a -device option is processed from the command line, 1141 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 1142 * order. The upshot is that -device options in increasing command line 1143 * order are mapped to virtio-mmio buses with decreasing base addresses. 1144 * 1145 * When this code was originally written, that arrangement ensured that the 1146 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 1147 * the first -device on the command line. (The end-to-end order is a 1148 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 1149 * guest kernel's name-to-address assignment strategy.) 1150 * 1151 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 1152 * the message, if not necessarily the code, of commit 70161ff336. 1153 * Therefore the loop now establishes the inverse of the original intent. 1154 * 1155 * Unfortunately, we can't counteract the kernel change by reversing the 1156 * loop; it would break existing command lines. 1157 * 1158 * In any case, the kernel makes no guarantee about the stability of 1159 * enumeration order of virtio devices (as demonstrated by it changing 1160 * between kernel versions). For reliable and stable identification 1161 * of disks users must use UUIDs or similar mechanisms. 1162 */ 1163 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 1164 int irq = vms->irqmap[VIRT_MMIO] + i; 1165 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1166 1167 sysbus_create_simple("virtio-mmio", base, 1168 qdev_get_gpio_in(vms->gic, irq)); 1169 } 1170 1171 /* We add dtb nodes in reverse order so that they appear in the finished 1172 * device tree lowest address first. 1173 * 1174 * Note that this mapping is independent of the loop above. The previous 1175 * loop influences virtio device to virtio transport assignment, whereas 1176 * this loop controls how virtio transports are laid out in the dtb. 1177 */ 1178 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 1179 char *nodename; 1180 int irq = vms->irqmap[VIRT_MMIO] + i; 1181 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1182 1183 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 1184 qemu_fdt_add_subnode(ms->fdt, nodename); 1185 qemu_fdt_setprop_string(ms->fdt, nodename, 1186 "compatible", "virtio,mmio"); 1187 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1188 2, base, 2, size); 1189 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1190 GIC_FDT_IRQ_TYPE_SPI, irq, 1191 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1192 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1193 g_free(nodename); 1194 } 1195 } 1196 1197 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 1198 1199 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 1200 const char *name, 1201 const char *alias_prop_name) 1202 { 1203 /* 1204 * Create a single flash device. We use the same parameters as 1205 * the flash devices on the Versatile Express board. 1206 */ 1207 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 1208 1209 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 1210 qdev_prop_set_uint8(dev, "width", 4); 1211 qdev_prop_set_uint8(dev, "device-width", 2); 1212 qdev_prop_set_bit(dev, "big-endian", false); 1213 qdev_prop_set_uint16(dev, "id0", 0x89); 1214 qdev_prop_set_uint16(dev, "id1", 0x18); 1215 qdev_prop_set_uint16(dev, "id2", 0x00); 1216 qdev_prop_set_uint16(dev, "id3", 0x00); 1217 qdev_prop_set_string(dev, "name", name); 1218 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 1219 object_property_add_alias(OBJECT(vms), alias_prop_name, 1220 OBJECT(dev), "drive"); 1221 return PFLASH_CFI01(dev); 1222 } 1223 1224 static void virt_flash_create(VirtMachineState *vms) 1225 { 1226 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 1227 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 1228 } 1229 1230 static void virt_flash_map1(PFlashCFI01 *flash, 1231 hwaddr base, hwaddr size, 1232 MemoryRegion *sysmem) 1233 { 1234 DeviceState *dev = DEVICE(flash); 1235 1236 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 1237 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 1238 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 1239 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1240 1241 memory_region_add_subregion(sysmem, base, 1242 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1243 0)); 1244 } 1245 1246 static void virt_flash_map(VirtMachineState *vms, 1247 MemoryRegion *sysmem, 1248 MemoryRegion *secure_sysmem) 1249 { 1250 /* 1251 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 1252 * sysmem is the system memory space. secure_sysmem is the secure view 1253 * of the system, and the first flash device should be made visible only 1254 * there. The second flash device is visible to both secure and nonsecure. 1255 * If sysmem == secure_sysmem this means there is no separate Secure 1256 * address space and both flash devices are generally visible. 1257 */ 1258 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1259 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1260 1261 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1262 secure_sysmem); 1263 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1264 sysmem); 1265 } 1266 1267 static void virt_flash_fdt(VirtMachineState *vms, 1268 MemoryRegion *sysmem, 1269 MemoryRegion *secure_sysmem) 1270 { 1271 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1272 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1273 MachineState *ms = MACHINE(vms); 1274 char *nodename; 1275 1276 if (sysmem == secure_sysmem) { 1277 /* Report both flash devices as a single node in the DT */ 1278 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1279 qemu_fdt_add_subnode(ms->fdt, nodename); 1280 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1281 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1282 2, flashbase, 2, flashsize, 1283 2, flashbase + flashsize, 2, flashsize); 1284 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1285 g_free(nodename); 1286 } else { 1287 /* 1288 * Report the devices as separate nodes so we can mark one as 1289 * only visible to the secure world. 1290 */ 1291 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1292 qemu_fdt_add_subnode(ms->fdt, nodename); 1293 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1294 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1295 2, flashbase, 2, flashsize); 1296 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1297 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1298 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1299 g_free(nodename); 1300 1301 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize); 1302 qemu_fdt_add_subnode(ms->fdt, nodename); 1303 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1304 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1305 2, flashbase + flashsize, 2, flashsize); 1306 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1307 g_free(nodename); 1308 } 1309 } 1310 1311 static bool virt_firmware_init(VirtMachineState *vms, 1312 MemoryRegion *sysmem, 1313 MemoryRegion *secure_sysmem) 1314 { 1315 int i; 1316 const char *bios_name; 1317 BlockBackend *pflash_blk0; 1318 1319 /* Map legacy -drive if=pflash to machine properties */ 1320 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1321 pflash_cfi01_legacy_drive(vms->flash[i], 1322 drive_get(IF_PFLASH, 0, i)); 1323 } 1324 1325 virt_flash_map(vms, sysmem, secure_sysmem); 1326 1327 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1328 1329 bios_name = MACHINE(vms)->firmware; 1330 if (bios_name) { 1331 char *fname; 1332 MemoryRegion *mr; 1333 int image_size; 1334 1335 if (pflash_blk0) { 1336 error_report("The contents of the first flash device may be " 1337 "specified with -bios or with -drive if=pflash... " 1338 "but you cannot use both options at once"); 1339 exit(1); 1340 } 1341 1342 /* Fall back to -bios */ 1343 1344 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1345 if (!fname) { 1346 error_report("Could not find ROM image '%s'", bios_name); 1347 exit(1); 1348 } 1349 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1350 image_size = load_image_mr(fname, mr); 1351 g_free(fname); 1352 if (image_size < 0) { 1353 error_report("Could not load ROM image '%s'", bios_name); 1354 exit(1); 1355 } 1356 } 1357 1358 return pflash_blk0 || bios_name; 1359 } 1360 1361 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1362 { 1363 MachineState *ms = MACHINE(vms); 1364 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1365 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1366 FWCfgState *fw_cfg; 1367 char *nodename; 1368 1369 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1370 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1371 1372 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1373 qemu_fdt_add_subnode(ms->fdt, nodename); 1374 qemu_fdt_setprop_string(ms->fdt, nodename, 1375 "compatible", "qemu,fw-cfg-mmio"); 1376 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1377 2, base, 2, size); 1378 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1379 g_free(nodename); 1380 return fw_cfg; 1381 } 1382 1383 static void create_pcie_irq_map(const MachineState *ms, 1384 uint32_t gic_phandle, 1385 int first_irq, const char *nodename) 1386 { 1387 int devfn, pin; 1388 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1389 uint32_t *irq_map = full_irq_map; 1390 1391 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1392 for (pin = 0; pin < 4; pin++) { 1393 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1394 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1395 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1396 int i; 1397 1398 uint32_t map[] = { 1399 devfn << 8, 0, 0, /* devfn */ 1400 pin + 1, /* PCI pin */ 1401 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1402 1403 /* Convert map to big endian */ 1404 for (i = 0; i < 10; i++) { 1405 irq_map[i] = cpu_to_be32(map[i]); 1406 } 1407 irq_map += 10; 1408 } 1409 } 1410 1411 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", 1412 full_irq_map, sizeof(full_irq_map)); 1413 1414 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 1415 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ 1416 0, 0, 1417 0x7 /* PCI irq */); 1418 } 1419 1420 static void create_smmu(const VirtMachineState *vms, 1421 PCIBus *bus) 1422 { 1423 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1424 char *node; 1425 const char compat[] = "arm,smmu-v3"; 1426 int irq = vms->irqmap[VIRT_SMMU]; 1427 int i; 1428 hwaddr base = vms->memmap[VIRT_SMMU].base; 1429 hwaddr size = vms->memmap[VIRT_SMMU].size; 1430 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1431 DeviceState *dev; 1432 MachineState *ms = MACHINE(vms); 1433 1434 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1435 return; 1436 } 1437 1438 dev = qdev_new(TYPE_ARM_SMMUV3); 1439 1440 if (!vmc->no_nested_smmu) { 1441 object_property_set_str(OBJECT(dev), "stage", "nested", &error_fatal); 1442 } 1443 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1444 &error_abort); 1445 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1446 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1447 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1448 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1449 qdev_get_gpio_in(vms->gic, irq + i)); 1450 } 1451 1452 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1453 qemu_fdt_add_subnode(ms->fdt, node); 1454 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1455 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); 1456 1457 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", 1458 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1459 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1460 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1461 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1462 1463 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, 1464 sizeof(irq_names)); 1465 1466 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); 1467 1468 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1469 1470 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1471 g_free(node); 1472 } 1473 1474 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1475 { 1476 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1477 uint16_t bdf = vms->virtio_iommu_bdf; 1478 MachineState *ms = MACHINE(vms); 1479 char *node; 1480 1481 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1482 1483 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename, 1484 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1485 qemu_fdt_add_subnode(ms->fdt, node); 1486 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1487 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 1488 1, bdf << 8, 1, 0, 1, 0, 1489 1, 0, 1, 0); 1490 1491 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1492 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1493 g_free(node); 1494 1495 if (!vms->default_bus_bypass_iommu) { 1496 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", 1497 0x0, vms->iommu_phandle, 0x0, bdf, 1498 bdf + 1, vms->iommu_phandle, bdf + 1, 1499 0xffff - bdf); 1500 } 1501 } 1502 1503 static void create_pcie(VirtMachineState *vms) 1504 { 1505 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1506 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1507 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1508 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1509 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1510 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1511 hwaddr base_ecam, size_ecam; 1512 hwaddr base = base_mmio; 1513 int nr_pcie_buses; 1514 int irq = vms->irqmap[VIRT_PCIE]; 1515 MemoryRegion *mmio_alias; 1516 MemoryRegion *mmio_reg; 1517 MemoryRegion *ecam_alias; 1518 MemoryRegion *ecam_reg; 1519 DeviceState *dev; 1520 char *nodename; 1521 int i, ecam_id; 1522 PCIHostState *pci; 1523 MachineState *ms = MACHINE(vms); 1524 MachineClass *mc = MACHINE_GET_CLASS(ms); 1525 1526 dev = qdev_new(TYPE_GPEX_HOST); 1527 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1528 1529 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1530 base_ecam = vms->memmap[ecam_id].base; 1531 size_ecam = vms->memmap[ecam_id].size; 1532 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1533 /* Map only the first size_ecam bytes of ECAM space */ 1534 ecam_alias = g_new0(MemoryRegion, 1); 1535 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1536 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1537 ecam_reg, 0, size_ecam); 1538 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1539 1540 /* Map the MMIO window into system address space so as to expose 1541 * the section of PCI MMIO space which starts at the same base address 1542 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1543 * the window). 1544 */ 1545 mmio_alias = g_new0(MemoryRegion, 1); 1546 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1547 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1548 mmio_reg, base_mmio, size_mmio); 1549 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1550 1551 if (vms->highmem_mmio) { 1552 /* Map high MMIO space */ 1553 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1554 1555 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1556 mmio_reg, base_mmio_high, size_mmio_high); 1557 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1558 high_mmio_alias); 1559 } 1560 1561 /* Map IO port space */ 1562 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1563 1564 for (i = 0; i < PCI_NUM_PINS; i++) { 1565 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1566 qdev_get_gpio_in(vms->gic, irq + i)); 1567 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1568 } 1569 1570 pci = PCI_HOST_BRIDGE(dev); 1571 pci->bypass_iommu = vms->default_bus_bypass_iommu; 1572 vms->bus = pci->bus; 1573 if (vms->bus) { 1574 pci_init_nic_devices(pci->bus, mc->default_nic); 1575 } 1576 1577 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1578 qemu_fdt_add_subnode(ms->fdt, nodename); 1579 qemu_fdt_setprop_string(ms->fdt, nodename, 1580 "compatible", "pci-host-ecam-generic"); 1581 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 1582 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 1583 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 1584 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 1585 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 1586 nr_pcie_buses - 1); 1587 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1588 1589 if (vms->msi_phandle) { 1590 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 1591 0, vms->msi_phandle, 0, 0x10000); 1592 } 1593 1594 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1595 2, base_ecam, 2, size_ecam); 1596 1597 if (vms->highmem_mmio) { 1598 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1599 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1600 2, base_pio, 2, size_pio, 1601 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1602 2, base_mmio, 2, size_mmio, 1603 1, FDT_PCI_RANGE_MMIO_64BIT, 1604 2, base_mmio_high, 1605 2, base_mmio_high, 2, size_mmio_high); 1606 } else { 1607 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1608 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1609 2, base_pio, 2, size_pio, 1610 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1611 2, base_mmio, 2, size_mmio); 1612 } 1613 1614 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 1615 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); 1616 1617 if (vms->iommu) { 1618 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1619 1620 switch (vms->iommu) { 1621 case VIRT_IOMMU_SMMUV3: 1622 create_smmu(vms, vms->bus); 1623 if (!vms->default_bus_bypass_iommu) { 1624 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 1625 0x0, vms->iommu_phandle, 0x0, 0x10000); 1626 } 1627 break; 1628 default: 1629 g_assert_not_reached(); 1630 } 1631 } 1632 } 1633 1634 static void create_cxl_host_reg_region(VirtMachineState *vms) 1635 { 1636 MemoryRegion *sysmem = get_system_memory(); 1637 MemoryRegion *mr = &vms->cxl_devices_state.host_mr; 1638 1639 memory_region_init(mr, OBJECT(vms), "cxl_host_reg", 1640 vms->memmap[VIRT_CXL_HOST].size); 1641 memory_region_add_subregion(sysmem, vms->memmap[VIRT_CXL_HOST].base, mr); 1642 vms->highmem_cxl = true; 1643 } 1644 1645 static void create_platform_bus(VirtMachineState *vms) 1646 { 1647 DeviceState *dev; 1648 SysBusDevice *s; 1649 int i; 1650 MemoryRegion *sysmem = get_system_memory(); 1651 1652 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1653 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1654 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1655 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1656 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1657 vms->platform_bus_dev = dev; 1658 1659 s = SYS_BUS_DEVICE(dev); 1660 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1661 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1662 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1663 } 1664 1665 memory_region_add_subregion(sysmem, 1666 vms->memmap[VIRT_PLATFORM_BUS].base, 1667 sysbus_mmio_get_region(s, 0)); 1668 } 1669 1670 static void create_tag_ram(MemoryRegion *tag_sysmem, 1671 hwaddr base, hwaddr size, 1672 const char *name) 1673 { 1674 MemoryRegion *tagram = g_new(MemoryRegion, 1); 1675 1676 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); 1677 memory_region_add_subregion(tag_sysmem, base / 32, tagram); 1678 } 1679 1680 static void create_secure_ram(VirtMachineState *vms, 1681 MemoryRegion *secure_sysmem, 1682 MemoryRegion *secure_tag_sysmem) 1683 { 1684 MemoryRegion *secram = g_new(MemoryRegion, 1); 1685 char *nodename; 1686 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1687 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1688 MachineState *ms = MACHINE(vms); 1689 1690 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1691 &error_fatal); 1692 memory_region_add_subregion(secure_sysmem, base, secram); 1693 1694 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1695 qemu_fdt_add_subnode(ms->fdt, nodename); 1696 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 1697 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 1698 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1699 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1700 1701 if (secure_tag_sysmem) { 1702 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); 1703 } 1704 1705 g_free(nodename); 1706 } 1707 1708 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1709 { 1710 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1711 bootinfo); 1712 MachineState *ms = MACHINE(board); 1713 1714 1715 *fdt_size = board->fdt_size; 1716 return ms->fdt; 1717 } 1718 1719 static void virt_build_smbios(VirtMachineState *vms) 1720 { 1721 MachineClass *mc = MACHINE_GET_CLASS(vms); 1722 MachineState *ms = MACHINE(vms); 1723 uint8_t *smbios_tables, *smbios_anchor; 1724 size_t smbios_tables_len, smbios_anchor_len; 1725 struct smbios_phys_mem_area mem_array; 1726 const char *product = "QEMU Virtual Machine"; 1727 1728 if (kvm_enabled()) { 1729 product = "KVM Virtual Machine"; 1730 } 1731 1732 smbios_set_defaults("QEMU", product, mc->name); 1733 1734 /* build the array of physical mem area from base_memmap */ 1735 mem_array.address = vms->memmap[VIRT_MEM].base; 1736 mem_array.length = ms->ram_size; 1737 1738 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, &mem_array, 1, 1739 &smbios_tables, &smbios_tables_len, 1740 &smbios_anchor, &smbios_anchor_len, 1741 &error_fatal); 1742 1743 if (smbios_anchor) { 1744 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1745 smbios_tables, smbios_tables_len); 1746 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1747 smbios_anchor, smbios_anchor_len); 1748 } 1749 } 1750 1751 static 1752 void virt_machine_done(Notifier *notifier, void *data) 1753 { 1754 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1755 machine_done); 1756 MachineState *ms = MACHINE(vms); 1757 ARMCPU *cpu = ARM_CPU(first_cpu); 1758 struct arm_boot_info *info = &vms->bootinfo; 1759 AddressSpace *as = arm_boot_address_space(cpu, info); 1760 1761 cxl_hook_up_pxb_registers(vms->bus, &vms->cxl_devices_state, 1762 &error_fatal); 1763 1764 if (vms->cxl_devices_state.is_enabled) { 1765 cxl_fmws_link_targets(&error_fatal); 1766 } 1767 /* 1768 * If the user provided a dtb, we assume the dynamic sysbus nodes 1769 * already are integrated there. This corresponds to a use case where 1770 * the dynamic sysbus nodes are complex and their generation is not yet 1771 * supported. In that case the user can take charge of the guest dt 1772 * while qemu takes charge of the qom stuff. 1773 */ 1774 if (info->dtb_filename == NULL) { 1775 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", 1776 vms->memmap[VIRT_PLATFORM_BUS].base, 1777 vms->memmap[VIRT_PLATFORM_BUS].size, 1778 vms->irqmap[VIRT_PLATFORM_BUS]); 1779 } 1780 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms, cpu) < 0) { 1781 exit(1); 1782 } 1783 1784 pci_bus_add_fw_cfg_extra_pci_roots(vms->fw_cfg, vms->bus, 1785 &error_abort); 1786 1787 virt_acpi_setup(vms); 1788 virt_build_smbios(vms); 1789 } 1790 1791 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1792 { 1793 uint8_t clustersz; 1794 1795 /* 1796 * Adjust MPIDR to make TCG consistent (with 64-bit KVM hosts) 1797 * and to improve SGI efficiency. 1798 */ 1799 if (vms->gic_version == VIRT_GIC_VERSION_2) { 1800 clustersz = GIC_TARGETLIST_BITS; 1801 } else { 1802 clustersz = GICV3_TARGETLIST_BITS; 1803 } 1804 1805 return arm_build_mp_affinity(idx, clustersz); 1806 } 1807 1808 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, 1809 int index) 1810 { 1811 bool *enabled_array[] = { 1812 &vms->highmem_redists, 1813 &vms->highmem_cxl, 1814 &vms->highmem_ecam, 1815 &vms->highmem_mmio, 1816 }; 1817 1818 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST == 1819 ARRAY_SIZE(enabled_array)); 1820 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array)); 1821 1822 return enabled_array[index - VIRT_LOWMEMMAP_LAST]; 1823 } 1824 1825 static void virt_set_high_memmap(VirtMachineState *vms, 1826 hwaddr base, int pa_bits) 1827 { 1828 hwaddr region_base, region_size; 1829 bool *region_enabled, fits; 1830 int i; 1831 1832 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1833 region_enabled = virt_get_high_memmap_enabled(vms, i); 1834 region_base = ROUND_UP(base, extended_memmap[i].size); 1835 region_size = extended_memmap[i].size; 1836 1837 vms->memmap[i].base = region_base; 1838 vms->memmap[i].size = region_size; 1839 1840 /* 1841 * Check each device to see if it fits in the PA space, 1842 * moving highest_gpa as we go. For compatibility, move 1843 * highest_gpa for disabled fitting devices as well, if 1844 * the compact layout has been disabled. 1845 * 1846 * For each device that doesn't fit, disable it. 1847 */ 1848 fits = (region_base + region_size) <= BIT_ULL(pa_bits); 1849 *region_enabled &= fits; 1850 if (vms->highmem_compact && !*region_enabled) { 1851 continue; 1852 } 1853 1854 base = region_base + region_size; 1855 if (fits) { 1856 vms->highest_gpa = base - 1; 1857 } 1858 } 1859 } 1860 1861 static void virt_set_memmap(VirtMachineState *vms, int pa_bits) 1862 { 1863 MachineState *ms = MACHINE(vms); 1864 hwaddr base, device_memory_base, device_memory_size, memtop; 1865 int i; 1866 1867 vms->memmap = extended_memmap; 1868 1869 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1870 vms->memmap[i] = base_memmap[i]; 1871 } 1872 1873 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1874 error_report("unsupported number of memory slots: %"PRIu64, 1875 ms->ram_slots); 1876 exit(EXIT_FAILURE); 1877 } 1878 1879 /* 1880 * !highmem is exactly the same as limiting the PA space to 32bit, 1881 * irrespective of the underlying capabilities of the HW. 1882 */ 1883 if (!vms->highmem) { 1884 pa_bits = 32; 1885 } 1886 1887 /* 1888 * We compute the base of the high IO region depending on the 1889 * amount of initial and device memory. The device memory start/size 1890 * is aligned on 1GiB. We never put the high IO region below 256GiB 1891 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1892 * The device region size assumes 1GiB page max alignment per slot. 1893 */ 1894 device_memory_base = 1895 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1896 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1897 1898 /* Base address of the high IO region */ 1899 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1900 if (memtop > BIT_ULL(pa_bits)) { 1901 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes", 1902 pa_bits, memtop - BIT_ULL(pa_bits)); 1903 exit(EXIT_FAILURE); 1904 } 1905 if (base < device_memory_base) { 1906 error_report("maxmem/slots too huge"); 1907 exit(EXIT_FAILURE); 1908 } 1909 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1910 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1911 } 1912 1913 /* We know for sure that at least the memory fits in the PA space */ 1914 vms->highest_gpa = memtop - 1; 1915 1916 virt_set_high_memmap(vms, base, pa_bits); 1917 1918 if (device_memory_size > 0) { 1919 machine_memory_devices_init(ms, device_memory_base, device_memory_size); 1920 } 1921 vms->highest_gpa = cxl_fmws_set_memmap(ROUND_UP(vms->highest_gpa + 1, 1922 256 * MiB), 1923 BIT_ULL(pa_bits)) - 1; 1924 } 1925 1926 static VirtGICType finalize_gic_version_do(const char *accel_name, 1927 VirtGICType gic_version, 1928 int gics_supported, 1929 unsigned int max_cpus) 1930 { 1931 /* Convert host/max/nosel to GIC version number */ 1932 switch (gic_version) { 1933 case VIRT_GIC_VERSION_HOST: 1934 if (!kvm_enabled()) { 1935 error_report("gic-version=host requires KVM"); 1936 exit(1); 1937 } 1938 1939 /* For KVM, gic-version=host means gic-version=max */ 1940 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX, 1941 gics_supported, max_cpus); 1942 case VIRT_GIC_VERSION_MAX: 1943 if (gics_supported & VIRT_GIC_VERSION_4_MASK) { 1944 gic_version = VIRT_GIC_VERSION_4; 1945 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1946 gic_version = VIRT_GIC_VERSION_3; 1947 } else { 1948 gic_version = VIRT_GIC_VERSION_2; 1949 } 1950 break; 1951 case VIRT_GIC_VERSION_NOSEL: 1952 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) && 1953 max_cpus <= GIC_NCPU) { 1954 gic_version = VIRT_GIC_VERSION_2; 1955 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1956 /* 1957 * in case the host does not support v2 emulation or 1958 * the end-user requested more than 8 VCPUs we now default 1959 * to v3. In any case defaulting to v2 would be broken. 1960 */ 1961 gic_version = VIRT_GIC_VERSION_3; 1962 } else if (max_cpus > GIC_NCPU) { 1963 error_report("%s only supports GICv2 emulation but more than 8 " 1964 "vcpus are requested", accel_name); 1965 exit(1); 1966 } 1967 break; 1968 case VIRT_GIC_VERSION_2: 1969 case VIRT_GIC_VERSION_3: 1970 case VIRT_GIC_VERSION_4: 1971 break; 1972 } 1973 1974 /* Check chosen version is effectively supported */ 1975 switch (gic_version) { 1976 case VIRT_GIC_VERSION_2: 1977 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) { 1978 error_report("%s does not support GICv2 emulation", accel_name); 1979 exit(1); 1980 } 1981 break; 1982 case VIRT_GIC_VERSION_3: 1983 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) { 1984 error_report("%s does not support GICv3 emulation", accel_name); 1985 exit(1); 1986 } 1987 break; 1988 case VIRT_GIC_VERSION_4: 1989 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) { 1990 error_report("%s does not support GICv4 emulation, is virtualization=on?", 1991 accel_name); 1992 exit(1); 1993 } 1994 break; 1995 default: 1996 error_report("logic error in finalize_gic_version"); 1997 exit(1); 1998 break; 1999 } 2000 2001 return gic_version; 2002 } 2003 2004 /* 2005 * finalize_gic_version - Determines the final gic_version 2006 * according to the gic-version property 2007 * 2008 * Default GIC type is v2 2009 */ 2010 static void finalize_gic_version(VirtMachineState *vms) 2011 { 2012 const char *accel_name = current_accel_name(); 2013 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 2014 int gics_supported = 0; 2015 2016 /* Determine which GIC versions the current environment supports */ 2017 if (kvm_enabled() && kvm_irqchip_in_kernel()) { 2018 int probe_bitmap = kvm_arm_vgic_probe(); 2019 2020 if (!probe_bitmap) { 2021 error_report("Unable to determine GIC version supported by host"); 2022 exit(1); 2023 } 2024 2025 if (probe_bitmap & KVM_ARM_VGIC_V2) { 2026 gics_supported |= VIRT_GIC_VERSION_2_MASK; 2027 } 2028 if (probe_bitmap & KVM_ARM_VGIC_V3) { 2029 gics_supported |= VIRT_GIC_VERSION_3_MASK; 2030 } 2031 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) { 2032 /* KVM w/o kernel irqchip can only deal with GICv2 */ 2033 gics_supported |= VIRT_GIC_VERSION_2_MASK; 2034 accel_name = "KVM with kernel-irqchip=off"; 2035 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { 2036 gics_supported |= VIRT_GIC_VERSION_2_MASK; 2037 if (module_object_class_by_name("arm-gicv3")) { 2038 gics_supported |= VIRT_GIC_VERSION_3_MASK; 2039 if (vms->virt) { 2040 /* GICv4 only makes sense if CPU has EL2 */ 2041 gics_supported |= VIRT_GIC_VERSION_4_MASK; 2042 } 2043 } 2044 } else { 2045 error_report("Unsupported accelerator, can not determine GIC support"); 2046 exit(1); 2047 } 2048 2049 /* 2050 * Then convert helpers like host/max to concrete GIC versions and ensure 2051 * the desired version is supported 2052 */ 2053 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version, 2054 gics_supported, max_cpus); 2055 } 2056 2057 /* 2058 * virt_post_cpus_gic_realized() must be called after the CPUs and 2059 * the GIC have both been realized. 2060 */ 2061 static void virt_post_cpus_gic_realized(VirtMachineState *vms, 2062 MemoryRegion *sysmem) 2063 { 2064 int max_cpus = MACHINE(vms)->smp.max_cpus; 2065 bool aarch64, pmu, steal_time; 2066 CPUState *cpu; 2067 2068 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); 2069 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); 2070 steal_time = object_property_get_bool(OBJECT(first_cpu), 2071 "kvm-steal-time", NULL); 2072 2073 if (kvm_enabled()) { 2074 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; 2075 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; 2076 2077 if (steal_time) { 2078 MemoryRegion *pvtime = g_new(MemoryRegion, 1); 2079 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; 2080 2081 /* The memory region size must be a multiple of host page size. */ 2082 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); 2083 2084 if (pvtime_size > pvtime_reg_size) { 2085 error_report("pvtime requires a %" HWADDR_PRId 2086 " byte memory region for %d CPUs," 2087 " but only %" HWADDR_PRId " has been reserved", 2088 pvtime_size, max_cpus, pvtime_reg_size); 2089 exit(1); 2090 } 2091 2092 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); 2093 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); 2094 } 2095 2096 CPU_FOREACH(cpu) { 2097 if (pmu) { 2098 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); 2099 if (kvm_irqchip_in_kernel()) { 2100 kvm_arm_pmu_set_irq(ARM_CPU(cpu), VIRTUAL_PMU_IRQ); 2101 } 2102 kvm_arm_pmu_init(ARM_CPU(cpu)); 2103 } 2104 if (steal_time) { 2105 kvm_arm_pvtime_init(ARM_CPU(cpu), pvtime_reg_base 2106 + cpu->cpu_index 2107 * PVTIME_SIZE_PER_CPU); 2108 } 2109 } 2110 } else { 2111 if (aarch64 && vms->highmem) { 2112 int requested_pa_size = 64 - clz64(vms->highest_gpa); 2113 int pamax = arm_pamax(ARM_CPU(first_cpu)); 2114 2115 if (pamax < requested_pa_size) { 2116 error_report("VCPU supports less PA bits (%d) than " 2117 "requested by the memory map (%d)", 2118 pamax, requested_pa_size); 2119 exit(1); 2120 } 2121 } 2122 } 2123 } 2124 2125 static void machvirt_init(MachineState *machine) 2126 { 2127 VirtMachineState *vms = VIRT_MACHINE(machine); 2128 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 2129 MachineClass *mc = MACHINE_GET_CLASS(machine); 2130 const CPUArchIdList *possible_cpus; 2131 MemoryRegion *sysmem = get_system_memory(); 2132 MemoryRegion *secure_sysmem = NULL; 2133 MemoryRegion *tag_sysmem = NULL; 2134 MemoryRegion *secure_tag_sysmem = NULL; 2135 int n, virt_max_cpus; 2136 bool firmware_loaded; 2137 bool aarch64 = true; 2138 bool has_ged = !vmc->no_ged; 2139 unsigned int smp_cpus = machine->smp.cpus; 2140 unsigned int max_cpus = machine->smp.max_cpus; 2141 2142 possible_cpus = mc->possible_cpu_arch_ids(machine); 2143 2144 /* 2145 * In accelerated mode, the memory map is computed earlier in kvm_type() 2146 * for Linux, or hvf_get_physical_address_range() for macOS to create a 2147 * VM with the right number of IPA bits. 2148 */ 2149 if (!vms->memmap) { 2150 Object *cpuobj; 2151 ARMCPU *armcpu; 2152 int pa_bits; 2153 2154 /* 2155 * Instantiate a temporary CPU object to find out about what 2156 * we are about to deal with. Once this is done, get rid of 2157 * the object. 2158 */ 2159 cpuobj = object_new(possible_cpus->cpus[0].type); 2160 armcpu = ARM_CPU(cpuobj); 2161 2162 pa_bits = arm_pamax(armcpu); 2163 2164 object_unref(cpuobj); 2165 2166 virt_set_memmap(vms, pa_bits); 2167 } 2168 2169 /* We can probe only here because during property set 2170 * KVM is not available yet 2171 */ 2172 finalize_gic_version(vms); 2173 2174 if (vms->secure) { 2175 /* 2176 * The Secure view of the world is the same as the NonSecure, 2177 * but with a few extra devices. Create it as a container region 2178 * containing the system memory at low priority; any secure-only 2179 * devices go in at higher priority and take precedence. 2180 */ 2181 secure_sysmem = g_new(MemoryRegion, 1); 2182 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 2183 UINT64_MAX); 2184 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 2185 } 2186 2187 firmware_loaded = virt_firmware_init(vms, sysmem, 2188 secure_sysmem ?: sysmem); 2189 2190 /* If we have an EL3 boot ROM then the assumption is that it will 2191 * implement PSCI itself, so disable QEMU's internal implementation 2192 * so it doesn't get in the way. Instead of starting secondary 2193 * CPUs in PSCI powerdown state we will start them all running and 2194 * let the boot ROM sort them out. 2195 * The usual case is that we do use QEMU's PSCI implementation; 2196 * if the guest has EL2 then we will use SMC as the conduit, 2197 * and otherwise we will use HVC (for backwards compatibility and 2198 * because if we're using KVM then we must use HVC). 2199 */ 2200 if (vms->secure && firmware_loaded) { 2201 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 2202 } else if (vms->virt) { 2203 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 2204 } else { 2205 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 2206 } 2207 2208 /* 2209 * The maximum number of CPUs depends on the GIC version, or on how 2210 * many redistributors we can fit into the memory map (which in turn 2211 * depends on whether this is a GICv3 or v4). 2212 */ 2213 if (vms->gic_version == VIRT_GIC_VERSION_2) { 2214 virt_max_cpus = GIC_NCPU; 2215 } else { 2216 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST); 2217 if (vms->highmem_redists) { 2218 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 2219 } 2220 } 2221 2222 if (max_cpus > virt_max_cpus) { 2223 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 2224 "supported by machine 'mach-virt' (%d)", 2225 max_cpus, virt_max_cpus); 2226 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) { 2227 error_printf("Try 'highmem-redists=on' for more CPUs\n"); 2228 } 2229 2230 exit(1); 2231 } 2232 2233 if (vms->secure && !tcg_enabled() && !qtest_enabled()) { 2234 error_report("mach-virt: %s does not support providing " 2235 "Security extensions (TrustZone) to the guest CPU", 2236 current_accel_name()); 2237 exit(1); 2238 } 2239 2240 if (vms->virt && !tcg_enabled() && !qtest_enabled()) { 2241 error_report("mach-virt: %s does not support providing " 2242 "Virtualization extensions to the guest CPU", 2243 current_accel_name()); 2244 exit(1); 2245 } 2246 2247 if (vms->mte && hvf_enabled()) { 2248 error_report("mach-virt: %s does not support providing " 2249 "MTE to the guest CPU", 2250 current_accel_name()); 2251 exit(1); 2252 } 2253 2254 create_fdt(vms); 2255 2256 assert(possible_cpus->len == max_cpus); 2257 for (n = 0; n < possible_cpus->len; n++) { 2258 Object *cpuobj; 2259 CPUState *cs; 2260 2261 if (n >= smp_cpus) { 2262 break; 2263 } 2264 2265 cpuobj = object_new(possible_cpus->cpus[n].type); 2266 object_property_set_int(cpuobj, "mp-affinity", 2267 possible_cpus->cpus[n].arch_id, NULL); 2268 2269 cs = CPU(cpuobj); 2270 cs->cpu_index = n; 2271 2272 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 2273 &error_fatal); 2274 2275 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 2276 2277 if (!vms->secure) { 2278 object_property_set_bool(cpuobj, "has_el3", false, NULL); 2279 } 2280 2281 if (!vms->virt && object_property_find(cpuobj, "has_el2")) { 2282 object_property_set_bool(cpuobj, "has_el2", false, NULL); 2283 } 2284 2285 if (vmc->kvm_no_adjvtime && 2286 object_property_find(cpuobj, "kvm-no-adjvtime")) { 2287 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 2288 } 2289 2290 if (vmc->no_kvm_steal_time && 2291 object_property_find(cpuobj, "kvm-steal-time")) { 2292 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); 2293 } 2294 2295 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { 2296 object_property_set_bool(cpuobj, "lpa2", false, NULL); 2297 } 2298 2299 if (object_property_find(cpuobj, "reset-cbar")) { 2300 object_property_set_int(cpuobj, "reset-cbar", 2301 vms->memmap[VIRT_CPUPERIPHS].base, 2302 &error_abort); 2303 } 2304 2305 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 2306 &error_abort); 2307 if (vms->secure) { 2308 object_property_set_link(cpuobj, "secure-memory", 2309 OBJECT(secure_sysmem), &error_abort); 2310 } 2311 2312 if (vms->mte) { 2313 if (tcg_enabled()) { 2314 /* Create the memory region only once, but link to all cpus. */ 2315 if (!tag_sysmem) { 2316 /* 2317 * The property exists only if MemTag is supported. 2318 * If it is, we must allocate the ram to back that up. 2319 */ 2320 if (!object_property_find(cpuobj, "tag-memory")) { 2321 error_report("MTE requested, but not supported " 2322 "by the guest CPU"); 2323 exit(1); 2324 } 2325 2326 tag_sysmem = g_new(MemoryRegion, 1); 2327 memory_region_init(tag_sysmem, OBJECT(machine), 2328 "tag-memory", UINT64_MAX / 32); 2329 2330 if (vms->secure) { 2331 secure_tag_sysmem = g_new(MemoryRegion, 1); 2332 memory_region_init(secure_tag_sysmem, OBJECT(machine), 2333 "secure-tag-memory", 2334 UINT64_MAX / 32); 2335 2336 /* As with ram, secure-tag takes precedence over tag. */ 2337 memory_region_add_subregion_overlap(secure_tag_sysmem, 2338 0, tag_sysmem, -1); 2339 } 2340 } 2341 2342 object_property_set_link(cpuobj, "tag-memory", 2343 OBJECT(tag_sysmem), &error_abort); 2344 if (vms->secure) { 2345 object_property_set_link(cpuobj, "secure-tag-memory", 2346 OBJECT(secure_tag_sysmem), 2347 &error_abort); 2348 } 2349 } else if (kvm_enabled()) { 2350 if (!kvm_arm_mte_supported()) { 2351 error_report("MTE requested, but not supported by KVM"); 2352 exit(1); 2353 } 2354 kvm_arm_enable_mte(cpuobj, &error_abort); 2355 } else { 2356 error_report("MTE requested, but not supported "); 2357 exit(1); 2358 } 2359 } 2360 2361 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 2362 object_unref(cpuobj); 2363 } 2364 2365 /* Now we've created the CPUs we can see if they have the hypvirt timer */ 2366 vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() && 2367 !vmc->no_ns_el2_virt_timer_irq; 2368 2369 fdt_add_timer_nodes(vms); 2370 fdt_add_cpu_nodes(vms); 2371 2372 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 2373 machine->ram); 2374 2375 cxl_fmws_update_mmio(); 2376 2377 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 2378 2379 create_gic(vms, sysmem); 2380 2381 virt_post_cpus_gic_realized(vms, sysmem); 2382 2383 fdt_add_pmu_nodes(vms); 2384 2385 /* 2386 * The first UART always exists. If the security extensions are 2387 * enabled, the second UART also always exists. Otherwise, it only exists 2388 * if a backend is configured explicitly via '-serial <backend>'. 2389 * This avoids potentially breaking existing user setups that expect 2390 * only one NonSecure UART to be present (for instance, older EDK2 2391 * binaries). 2392 * 2393 * The nodes end up in the DTB in reverse order of creation, so we must 2394 * create UART0 last to ensure it appears as the first node in the DTB, 2395 * for compatibility with guest software that just iterates through the 2396 * DTB to find the first UART, as older versions of EDK2 do. 2397 * DTB readers that follow the spec, as Linux does, should honour the 2398 * aliases node information and /chosen/stdout-path regardless of 2399 * the order that nodes appear in the DTB. 2400 * 2401 * For similar back-compatibility reasons, if UART1 is the secure UART 2402 * we create it second (and so it appears first in the DTB), because 2403 * that's what QEMU has always done. 2404 */ 2405 if (!vms->secure) { 2406 Chardev *serial1 = serial_hd(1); 2407 2408 if (serial1) { 2409 vms->second_ns_uart_present = true; 2410 create_uart(vms, VIRT_UART1, sysmem, serial1, false); 2411 } 2412 } 2413 create_uart(vms, VIRT_UART0, sysmem, serial_hd(0), false); 2414 if (vms->secure) { 2415 create_uart(vms, VIRT_UART1, secure_sysmem, serial_hd(1), true); 2416 } 2417 2418 if (vms->secure) { 2419 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); 2420 } 2421 2422 if (tag_sysmem) { 2423 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, 2424 machine->ram_size, "mach-virt.tag"); 2425 } 2426 2427 vms->highmem_ecam &= (!firmware_loaded || aarch64); 2428 2429 create_rtc(vms); 2430 2431 create_pcie(vms); 2432 create_cxl_host_reg_region(vms); 2433 2434 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 2435 vms->acpi_dev = create_acpi_ged(vms); 2436 } else { 2437 create_gpio_devices(vms, VIRT_GPIO, sysmem); 2438 } 2439 2440 if (vms->secure && !vmc->no_secure_gpio) { 2441 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); 2442 } 2443 2444 /* connect powerdown request */ 2445 vms->powerdown_notifier.notify = virt_powerdown_req; 2446 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 2447 2448 /* Create mmio transports, so the user can create virtio backends 2449 * (which will be automatically plugged in to the transports). If 2450 * no backend is created the transport will just sit harmlessly idle. 2451 */ 2452 create_virtio_devices(vms); 2453 2454 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 2455 rom_set_fw(vms->fw_cfg); 2456 2457 create_platform_bus(vms); 2458 2459 if (machine->nvdimms_state->is_enabled) { 2460 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 2461 .space_id = AML_AS_SYSTEM_MEMORY, 2462 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 2463 .bit_width = NVDIMM_ACPI_IO_LEN << 3 2464 }; 2465 2466 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 2467 arm_virt_nvdimm_acpi_dsmio, 2468 vms->fw_cfg, OBJECT(vms)); 2469 } 2470 2471 vms->bootinfo.ram_size = machine->ram_size; 2472 vms->bootinfo.board_id = -1; 2473 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 2474 vms->bootinfo.get_dtb = machvirt_dtb; 2475 vms->bootinfo.skip_dtb_autoload = true; 2476 vms->bootinfo.firmware_loaded = firmware_loaded; 2477 vms->bootinfo.psci_conduit = vms->psci_conduit; 2478 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 2479 2480 vms->machine_done.notify = virt_machine_done; 2481 qemu_add_machine_init_done_notifier(&vms->machine_done); 2482 } 2483 2484 static bool virt_get_secure(Object *obj, Error **errp) 2485 { 2486 VirtMachineState *vms = VIRT_MACHINE(obj); 2487 2488 return vms->secure; 2489 } 2490 2491 static void virt_set_secure(Object *obj, bool value, Error **errp) 2492 { 2493 VirtMachineState *vms = VIRT_MACHINE(obj); 2494 2495 vms->secure = value; 2496 } 2497 2498 static bool virt_get_virt(Object *obj, Error **errp) 2499 { 2500 VirtMachineState *vms = VIRT_MACHINE(obj); 2501 2502 return vms->virt; 2503 } 2504 2505 static void virt_set_virt(Object *obj, bool value, Error **errp) 2506 { 2507 VirtMachineState *vms = VIRT_MACHINE(obj); 2508 2509 vms->virt = value; 2510 } 2511 2512 static bool virt_get_highmem(Object *obj, Error **errp) 2513 { 2514 VirtMachineState *vms = VIRT_MACHINE(obj); 2515 2516 return vms->highmem; 2517 } 2518 2519 static void virt_set_highmem(Object *obj, bool value, Error **errp) 2520 { 2521 VirtMachineState *vms = VIRT_MACHINE(obj); 2522 2523 vms->highmem = value; 2524 } 2525 2526 static bool virt_get_compact_highmem(Object *obj, Error **errp) 2527 { 2528 VirtMachineState *vms = VIRT_MACHINE(obj); 2529 2530 return vms->highmem_compact; 2531 } 2532 2533 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp) 2534 { 2535 VirtMachineState *vms = VIRT_MACHINE(obj); 2536 2537 vms->highmem_compact = value; 2538 } 2539 2540 static bool virt_get_highmem_redists(Object *obj, Error **errp) 2541 { 2542 VirtMachineState *vms = VIRT_MACHINE(obj); 2543 2544 return vms->highmem_redists; 2545 } 2546 2547 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp) 2548 { 2549 VirtMachineState *vms = VIRT_MACHINE(obj); 2550 2551 vms->highmem_redists = value; 2552 } 2553 2554 static bool virt_get_highmem_ecam(Object *obj, Error **errp) 2555 { 2556 VirtMachineState *vms = VIRT_MACHINE(obj); 2557 2558 return vms->highmem_ecam; 2559 } 2560 2561 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp) 2562 { 2563 VirtMachineState *vms = VIRT_MACHINE(obj); 2564 2565 vms->highmem_ecam = value; 2566 } 2567 2568 static bool virt_get_highmem_mmio(Object *obj, Error **errp) 2569 { 2570 VirtMachineState *vms = VIRT_MACHINE(obj); 2571 2572 return vms->highmem_mmio; 2573 } 2574 2575 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp) 2576 { 2577 VirtMachineState *vms = VIRT_MACHINE(obj); 2578 2579 vms->highmem_mmio = value; 2580 } 2581 2582 static void virt_get_highmem_mmio_size(Object *obj, Visitor *v, 2583 const char *name, void *opaque, 2584 Error **errp) 2585 { 2586 uint64_t size = extended_memmap[VIRT_HIGH_PCIE_MMIO].size; 2587 2588 visit_type_size(v, name, &size, errp); 2589 } 2590 2591 static void virt_set_highmem_mmio_size(Object *obj, Visitor *v, 2592 const char *name, void *opaque, 2593 Error **errp) 2594 { 2595 uint64_t size; 2596 2597 if (!visit_type_size(v, name, &size, errp)) { 2598 return; 2599 } 2600 2601 if (!is_power_of_2(size)) { 2602 error_setg(errp, "highmem-mmio-size is not a power of 2"); 2603 return; 2604 } 2605 2606 if (size < DEFAULT_HIGH_PCIE_MMIO_SIZE) { 2607 char *sz = size_to_str(DEFAULT_HIGH_PCIE_MMIO_SIZE); 2608 error_setg(errp, "highmem-mmio-size cannot be set to a lower value " 2609 "than the default (%s)", sz); 2610 g_free(sz); 2611 return; 2612 } 2613 2614 extended_memmap[VIRT_HIGH_PCIE_MMIO].size = size; 2615 } 2616 2617 static bool virt_get_its(Object *obj, Error **errp) 2618 { 2619 VirtMachineState *vms = VIRT_MACHINE(obj); 2620 2621 return vms->its; 2622 } 2623 2624 static void virt_set_its(Object *obj, bool value, Error **errp) 2625 { 2626 VirtMachineState *vms = VIRT_MACHINE(obj); 2627 2628 vms->its = value; 2629 } 2630 2631 static bool virt_get_dtb_randomness(Object *obj, Error **errp) 2632 { 2633 VirtMachineState *vms = VIRT_MACHINE(obj); 2634 2635 return vms->dtb_randomness; 2636 } 2637 2638 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp) 2639 { 2640 VirtMachineState *vms = VIRT_MACHINE(obj); 2641 2642 vms->dtb_randomness = value; 2643 } 2644 2645 static char *virt_get_oem_id(Object *obj, Error **errp) 2646 { 2647 VirtMachineState *vms = VIRT_MACHINE(obj); 2648 2649 return g_strdup(vms->oem_id); 2650 } 2651 2652 static void virt_set_oem_id(Object *obj, const char *value, Error **errp) 2653 { 2654 VirtMachineState *vms = VIRT_MACHINE(obj); 2655 size_t len = strlen(value); 2656 2657 if (len > 6) { 2658 error_setg(errp, 2659 "User specified oem-id value is bigger than 6 bytes in size"); 2660 return; 2661 } 2662 2663 strncpy(vms->oem_id, value, 6); 2664 } 2665 2666 static char *virt_get_oem_table_id(Object *obj, Error **errp) 2667 { 2668 VirtMachineState *vms = VIRT_MACHINE(obj); 2669 2670 return g_strdup(vms->oem_table_id); 2671 } 2672 2673 static void virt_set_oem_table_id(Object *obj, const char *value, 2674 Error **errp) 2675 { 2676 VirtMachineState *vms = VIRT_MACHINE(obj); 2677 size_t len = strlen(value); 2678 2679 if (len > 8) { 2680 error_setg(errp, 2681 "User specified oem-table-id value is bigger than 8 bytes in size"); 2682 return; 2683 } 2684 strncpy(vms->oem_table_id, value, 8); 2685 } 2686 2687 2688 bool virt_is_acpi_enabled(VirtMachineState *vms) 2689 { 2690 if (vms->acpi == ON_OFF_AUTO_OFF) { 2691 return false; 2692 } 2693 return true; 2694 } 2695 2696 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 2697 void *opaque, Error **errp) 2698 { 2699 VirtMachineState *vms = VIRT_MACHINE(obj); 2700 OnOffAuto acpi = vms->acpi; 2701 2702 visit_type_OnOffAuto(v, name, &acpi, errp); 2703 } 2704 2705 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 2706 void *opaque, Error **errp) 2707 { 2708 VirtMachineState *vms = VIRT_MACHINE(obj); 2709 2710 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 2711 } 2712 2713 static bool virt_get_ras(Object *obj, Error **errp) 2714 { 2715 VirtMachineState *vms = VIRT_MACHINE(obj); 2716 2717 return vms->ras; 2718 } 2719 2720 static void virt_set_ras(Object *obj, bool value, Error **errp) 2721 { 2722 VirtMachineState *vms = VIRT_MACHINE(obj); 2723 2724 vms->ras = value; 2725 } 2726 2727 static bool virt_get_mte(Object *obj, Error **errp) 2728 { 2729 VirtMachineState *vms = VIRT_MACHINE(obj); 2730 2731 return vms->mte; 2732 } 2733 2734 static void virt_set_mte(Object *obj, bool value, Error **errp) 2735 { 2736 VirtMachineState *vms = VIRT_MACHINE(obj); 2737 2738 vms->mte = value; 2739 } 2740 2741 static char *virt_get_gic_version(Object *obj, Error **errp) 2742 { 2743 VirtMachineState *vms = VIRT_MACHINE(obj); 2744 const char *val; 2745 2746 switch (vms->gic_version) { 2747 case VIRT_GIC_VERSION_4: 2748 val = "4"; 2749 break; 2750 case VIRT_GIC_VERSION_3: 2751 val = "3"; 2752 break; 2753 default: 2754 val = "2"; 2755 break; 2756 } 2757 return g_strdup(val); 2758 } 2759 2760 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2761 { 2762 VirtMachineState *vms = VIRT_MACHINE(obj); 2763 2764 if (!strcmp(value, "4")) { 2765 vms->gic_version = VIRT_GIC_VERSION_4; 2766 } else if (!strcmp(value, "3")) { 2767 vms->gic_version = VIRT_GIC_VERSION_3; 2768 } else if (!strcmp(value, "2")) { 2769 vms->gic_version = VIRT_GIC_VERSION_2; 2770 } else if (!strcmp(value, "host")) { 2771 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2772 } else if (!strcmp(value, "max")) { 2773 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2774 } else { 2775 error_setg(errp, "Invalid gic-version value"); 2776 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2777 } 2778 } 2779 2780 static char *virt_get_iommu(Object *obj, Error **errp) 2781 { 2782 VirtMachineState *vms = VIRT_MACHINE(obj); 2783 2784 switch (vms->iommu) { 2785 case VIRT_IOMMU_NONE: 2786 return g_strdup("none"); 2787 case VIRT_IOMMU_SMMUV3: 2788 return g_strdup("smmuv3"); 2789 default: 2790 g_assert_not_reached(); 2791 } 2792 } 2793 2794 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2795 { 2796 VirtMachineState *vms = VIRT_MACHINE(obj); 2797 2798 if (!strcmp(value, "smmuv3")) { 2799 vms->iommu = VIRT_IOMMU_SMMUV3; 2800 } else if (!strcmp(value, "none")) { 2801 vms->iommu = VIRT_IOMMU_NONE; 2802 } else { 2803 error_setg(errp, "Invalid iommu value"); 2804 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2805 } 2806 } 2807 2808 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp) 2809 { 2810 VirtMachineState *vms = VIRT_MACHINE(obj); 2811 2812 return vms->default_bus_bypass_iommu; 2813 } 2814 2815 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value, 2816 Error **errp) 2817 { 2818 VirtMachineState *vms = VIRT_MACHINE(obj); 2819 2820 vms->default_bus_bypass_iommu = value; 2821 } 2822 2823 static CpuInstanceProperties 2824 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2825 { 2826 MachineClass *mc = MACHINE_GET_CLASS(ms); 2827 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2828 2829 assert(cpu_index < possible_cpus->len); 2830 return possible_cpus->cpus[cpu_index].props; 2831 } 2832 2833 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2834 { 2835 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 2836 2837 return socket_id % ms->numa_state->num_nodes; 2838 } 2839 2840 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2841 { 2842 int n; 2843 unsigned int max_cpus = ms->smp.max_cpus; 2844 VirtMachineState *vms = VIRT_MACHINE(ms); 2845 MachineClass *mc = MACHINE_GET_CLASS(vms); 2846 2847 if (ms->possible_cpus) { 2848 assert(ms->possible_cpus->len == max_cpus); 2849 return ms->possible_cpus; 2850 } 2851 2852 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2853 sizeof(CPUArchId) * max_cpus); 2854 ms->possible_cpus->len = max_cpus; 2855 for (n = 0; n < ms->possible_cpus->len; n++) { 2856 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2857 ms->possible_cpus->cpus[n].arch_id = 2858 virt_cpu_mp_affinity(vms, n); 2859 2860 assert(!mc->smp_props.dies_supported); 2861 ms->possible_cpus->cpus[n].props.has_socket_id = true; 2862 ms->possible_cpus->cpus[n].props.socket_id = 2863 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); 2864 ms->possible_cpus->cpus[n].props.has_cluster_id = true; 2865 ms->possible_cpus->cpus[n].props.cluster_id = 2866 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; 2867 ms->possible_cpus->cpus[n].props.has_core_id = true; 2868 ms->possible_cpus->cpus[n].props.core_id = 2869 (n / ms->smp.threads) % ms->smp.cores; 2870 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2871 ms->possible_cpus->cpus[n].props.thread_id = 2872 n % ms->smp.threads; 2873 } 2874 return ms->possible_cpus; 2875 } 2876 2877 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2878 Error **errp) 2879 { 2880 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2881 const MachineState *ms = MACHINE(hotplug_dev); 2882 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2883 2884 if (!vms->acpi_dev) { 2885 error_setg(errp, 2886 "memory hotplug is not enabled: missing acpi-ged device"); 2887 return; 2888 } 2889 2890 if (vms->mte) { 2891 error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); 2892 return; 2893 } 2894 2895 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2896 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2897 return; 2898 } 2899 2900 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp); 2901 } 2902 2903 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2904 DeviceState *dev, Error **errp) 2905 { 2906 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2907 MachineState *ms = MACHINE(hotplug_dev); 2908 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2909 2910 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); 2911 2912 if (is_nvdimm) { 2913 nvdimm_plug(ms->nvdimms_state); 2914 } 2915 2916 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2917 dev, &error_abort); 2918 } 2919 2920 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2921 DeviceState *dev, Error **errp) 2922 { 2923 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2924 2925 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2926 virt_memory_pre_plug(hotplug_dev, dev, errp); 2927 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2928 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2929 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2930 hwaddr db_start = 0, db_end = 0; 2931 QList *reserved_regions; 2932 char *resv_prop_str; 2933 2934 if (vms->iommu != VIRT_IOMMU_NONE) { 2935 error_setg(errp, "virt machine does not support multiple IOMMUs"); 2936 return; 2937 } 2938 2939 switch (vms->msi_controller) { 2940 case VIRT_MSI_CTRL_NONE: 2941 return; 2942 case VIRT_MSI_CTRL_ITS: 2943 /* GITS_TRANSLATER page */ 2944 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; 2945 db_end = base_memmap[VIRT_GIC_ITS].base + 2946 base_memmap[VIRT_GIC_ITS].size - 1; 2947 break; 2948 case VIRT_MSI_CTRL_GICV2M: 2949 /* MSI_SETSPI_NS page */ 2950 db_start = base_memmap[VIRT_GIC_V2M].base; 2951 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; 2952 break; 2953 } 2954 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", 2955 db_start, db_end, 2956 VIRTIO_IOMMU_RESV_MEM_T_MSI); 2957 2958 reserved_regions = qlist_new(); 2959 qlist_append_str(reserved_regions, resv_prop_str); 2960 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 2961 g_free(resv_prop_str); 2962 } 2963 } 2964 2965 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2966 DeviceState *dev, Error **errp) 2967 { 2968 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2969 2970 if (vms->platform_bus_dev) { 2971 MachineClass *mc = MACHINE_GET_CLASS(vms); 2972 2973 if (device_is_dynamic_sysbus(mc, dev)) { 2974 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2975 SYS_BUS_DEVICE(dev)); 2976 } 2977 } 2978 2979 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2980 virt_memory_plug(hotplug_dev, dev, errp); 2981 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2982 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2983 } 2984 2985 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2986 PCIDevice *pdev = PCI_DEVICE(dev); 2987 2988 vms->iommu = VIRT_IOMMU_VIRTIO; 2989 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2990 create_virtio_iommu_dt_bindings(vms); 2991 } 2992 } 2993 2994 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, 2995 DeviceState *dev, Error **errp) 2996 { 2997 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2998 2999 if (!vms->acpi_dev) { 3000 error_setg(errp, 3001 "memory hotplug is not enabled: missing acpi-ged device"); 3002 return; 3003 } 3004 3005 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3006 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3007 return; 3008 } 3009 3010 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, 3011 errp); 3012 } 3013 3014 static void virt_dimm_unplug(HotplugHandler *hotplug_dev, 3015 DeviceState *dev, Error **errp) 3016 { 3017 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 3018 Error *local_err = NULL; 3019 3020 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); 3021 if (local_err) { 3022 goto out; 3023 } 3024 3025 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); 3026 qdev_unrealize(dev); 3027 3028 out: 3029 error_propagate(errp, local_err); 3030 } 3031 3032 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 3033 DeviceState *dev, Error **errp) 3034 { 3035 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3036 virt_dimm_unplug_request(hotplug_dev, dev, errp); 3037 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 3038 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 3039 errp); 3040 } else { 3041 error_setg(errp, "device unplug request for unsupported device" 3042 " type: %s", object_get_typename(OBJECT(dev))); 3043 } 3044 } 3045 3046 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 3047 DeviceState *dev, Error **errp) 3048 { 3049 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3050 virt_dimm_unplug(hotplug_dev, dev, errp); 3051 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 3052 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 3053 } else { 3054 error_setg(errp, "virt: device unplug for unsupported device" 3055 " type: %s", object_get_typename(OBJECT(dev))); 3056 } 3057 } 3058 3059 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 3060 DeviceState *dev) 3061 { 3062 MachineClass *mc = MACHINE_GET_CLASS(machine); 3063 3064 if (device_is_dynamic_sysbus(mc, dev) || 3065 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3066 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 3067 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 3068 return HOTPLUG_HANDLER(machine); 3069 } 3070 return NULL; 3071 } 3072 3073 /* 3074 * for arm64 kvm_type [7-0] encodes the requested number of bits 3075 * in the IPA address space 3076 */ 3077 static int virt_kvm_type(MachineState *ms, const char *type_str) 3078 { 3079 VirtMachineState *vms = VIRT_MACHINE(ms); 3080 int max_vm_pa_size, requested_pa_size; 3081 bool fixed_ipa; 3082 3083 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 3084 3085 /* we freeze the memory map to compute the highest gpa */ 3086 virt_set_memmap(vms, max_vm_pa_size); 3087 3088 requested_pa_size = 64 - clz64(vms->highest_gpa); 3089 3090 /* 3091 * KVM requires the IPA size to be at least 32 bits. 3092 */ 3093 if (requested_pa_size < 32) { 3094 requested_pa_size = 32; 3095 } 3096 3097 if (requested_pa_size > max_vm_pa_size) { 3098 error_report("-m and ,maxmem option values " 3099 "require an IPA range (%d bits) larger than " 3100 "the one supported by the host (%d bits)", 3101 requested_pa_size, max_vm_pa_size); 3102 return -1; 3103 } 3104 /* 3105 * We return the requested PA log size, unless KVM only supports 3106 * the implicit legacy 40b IPA setting, in which case the kvm_type 3107 * must be 0. 3108 */ 3109 return fixed_ipa ? 0 : requested_pa_size; 3110 } 3111 3112 static int virt_hvf_get_physical_address_range(MachineState *ms) 3113 { 3114 VirtMachineState *vms = VIRT_MACHINE(ms); 3115 3116 int default_ipa_size = hvf_arm_get_default_ipa_bit_size(); 3117 int max_ipa_size = hvf_arm_get_max_ipa_bit_size(); 3118 3119 /* We freeze the memory map to compute the highest gpa */ 3120 virt_set_memmap(vms, max_ipa_size); 3121 3122 int requested_ipa_size = 64 - clz64(vms->highest_gpa); 3123 3124 /* 3125 * If we're <= the default IPA size just use the default. 3126 * If we're above the default but below the maximum, round up to 3127 * the maximum. hvf_arm_get_max_ipa_bit_size() conveniently only 3128 * returns values that are valid ARM PARange values. 3129 */ 3130 if (requested_ipa_size <= default_ipa_size) { 3131 requested_ipa_size = default_ipa_size; 3132 } else if (requested_ipa_size <= max_ipa_size) { 3133 requested_ipa_size = max_ipa_size; 3134 } else { 3135 error_report("-m and ,maxmem option values " 3136 "require an IPA range (%d bits) larger than " 3137 "the one supported by the host (%d bits)", 3138 requested_ipa_size, max_ipa_size); 3139 return -1; 3140 } 3141 3142 return requested_ipa_size; 3143 } 3144 3145 static void virt_machine_class_init(ObjectClass *oc, const void *data) 3146 { 3147 MachineClass *mc = MACHINE_CLASS(oc); 3148 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3149 static const char * const valid_cpu_types[] = { 3150 #ifdef CONFIG_TCG 3151 ARM_CPU_TYPE_NAME("cortex-a7"), 3152 ARM_CPU_TYPE_NAME("cortex-a15"), 3153 #ifdef TARGET_AARCH64 3154 ARM_CPU_TYPE_NAME("cortex-a35"), 3155 ARM_CPU_TYPE_NAME("cortex-a55"), 3156 ARM_CPU_TYPE_NAME("cortex-a72"), 3157 ARM_CPU_TYPE_NAME("cortex-a76"), 3158 ARM_CPU_TYPE_NAME("cortex-a710"), 3159 ARM_CPU_TYPE_NAME("a64fx"), 3160 ARM_CPU_TYPE_NAME("neoverse-n1"), 3161 ARM_CPU_TYPE_NAME("neoverse-v1"), 3162 ARM_CPU_TYPE_NAME("neoverse-n2"), 3163 #endif /* TARGET_AARCH64 */ 3164 #endif /* CONFIG_TCG */ 3165 #ifdef TARGET_AARCH64 3166 ARM_CPU_TYPE_NAME("cortex-a53"), 3167 ARM_CPU_TYPE_NAME("cortex-a57"), 3168 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 3169 ARM_CPU_TYPE_NAME("host"), 3170 #endif /* CONFIG_KVM || CONFIG_HVF */ 3171 #endif /* TARGET_AARCH64 */ 3172 ARM_CPU_TYPE_NAME("max"), 3173 NULL 3174 }; 3175 3176 mc->init = machvirt_init; 3177 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 3178 * The value may be reduced later when we have more information about the 3179 * configuration of the particular instance. 3180 */ 3181 mc->max_cpus = 512; 3182 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 3183 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 3184 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 3185 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 3186 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS); 3187 #ifdef CONFIG_TPM 3188 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 3189 #endif 3190 mc->block_default_type = IF_VIRTIO; 3191 mc->no_cdrom = 1; 3192 mc->pci_allow_0_address = true; 3193 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 3194 mc->minimum_page_bits = 12; 3195 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 3196 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 3197 #ifdef CONFIG_TCG 3198 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 3199 #else 3200 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); 3201 #endif 3202 mc->valid_cpu_types = valid_cpu_types; 3203 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 3204 mc->kvm_type = virt_kvm_type; 3205 mc->hvf_get_physical_address_range = virt_hvf_get_physical_address_range; 3206 assert(!mc->get_hotplug_handler); 3207 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 3208 hc->pre_plug = virt_machine_device_pre_plug_cb; 3209 hc->plug = virt_machine_device_plug_cb; 3210 hc->unplug_request = virt_machine_device_unplug_request_cb; 3211 hc->unplug = virt_machine_device_unplug_cb; 3212 mc->nvdimm_supported = true; 3213 mc->smp_props.clusters_supported = true; 3214 mc->auto_enable_numa_with_memhp = true; 3215 mc->auto_enable_numa_with_memdev = true; 3216 /* platform instead of architectural choice */ 3217 mc->cpu_cluster_has_numa_boundary = true; 3218 mc->default_ram_id = "mach-virt.ram"; 3219 mc->default_nic = "virtio-net-pci"; 3220 3221 object_class_property_add(oc, "acpi", "OnOffAuto", 3222 virt_get_acpi, virt_set_acpi, 3223 NULL, NULL); 3224 object_class_property_set_description(oc, "acpi", 3225 "Enable ACPI"); 3226 object_class_property_add_bool(oc, "secure", virt_get_secure, 3227 virt_set_secure); 3228 object_class_property_set_description(oc, "secure", 3229 "Set on/off to enable/disable the ARM " 3230 "Security Extensions (TrustZone)"); 3231 3232 object_class_property_add_bool(oc, "virtualization", virt_get_virt, 3233 virt_set_virt); 3234 object_class_property_set_description(oc, "virtualization", 3235 "Set on/off to enable/disable emulating a " 3236 "guest CPU which implements the ARM " 3237 "Virtualization Extensions"); 3238 3239 object_class_property_add_bool(oc, "highmem", virt_get_highmem, 3240 virt_set_highmem); 3241 object_class_property_set_description(oc, "highmem", 3242 "Set on/off to enable/disable using " 3243 "physical address space above 32 bits"); 3244 3245 object_class_property_add_bool(oc, "compact-highmem", 3246 virt_get_compact_highmem, 3247 virt_set_compact_highmem); 3248 object_class_property_set_description(oc, "compact-highmem", 3249 "Set on/off to enable/disable compact " 3250 "layout for high memory regions"); 3251 3252 object_class_property_add_bool(oc, "highmem-redists", 3253 virt_get_highmem_redists, 3254 virt_set_highmem_redists); 3255 object_class_property_set_description(oc, "highmem-redists", 3256 "Set on/off to enable/disable high " 3257 "memory region for GICv3 or GICv4 " 3258 "redistributor"); 3259 3260 object_class_property_add_bool(oc, "highmem-ecam", 3261 virt_get_highmem_ecam, 3262 virt_set_highmem_ecam); 3263 object_class_property_set_description(oc, "highmem-ecam", 3264 "Set on/off to enable/disable high " 3265 "memory region for PCI ECAM"); 3266 3267 object_class_property_add_bool(oc, "highmem-mmio", 3268 virt_get_highmem_mmio, 3269 virt_set_highmem_mmio); 3270 object_class_property_set_description(oc, "highmem-mmio", 3271 "Set on/off to enable/disable high " 3272 "memory region for PCI MMIO"); 3273 3274 object_class_property_add(oc, "highmem-mmio-size", "size", 3275 virt_get_highmem_mmio_size, 3276 virt_set_highmem_mmio_size, 3277 NULL, NULL); 3278 object_class_property_set_description(oc, "highmem-mmio-size", 3279 "Set the high memory region size " 3280 "for PCI MMIO"); 3281 3282 object_class_property_add_str(oc, "gic-version", virt_get_gic_version, 3283 virt_set_gic_version); 3284 object_class_property_set_description(oc, "gic-version", 3285 "Set GIC version. " 3286 "Valid values are 2, 3, 4, host and max"); 3287 3288 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); 3289 object_class_property_set_description(oc, "iommu", 3290 "Set the IOMMU type. " 3291 "Valid values are none and smmuv3"); 3292 3293 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 3294 virt_get_default_bus_bypass_iommu, 3295 virt_set_default_bus_bypass_iommu); 3296 object_class_property_set_description(oc, "default-bus-bypass-iommu", 3297 "Set on/off to enable/disable " 3298 "bypass_iommu for default root bus"); 3299 3300 object_class_property_add_bool(oc, "ras", virt_get_ras, 3301 virt_set_ras); 3302 object_class_property_set_description(oc, "ras", 3303 "Set on/off to enable/disable reporting host memory errors " 3304 "to a KVM guest using ACPI and guest external abort exceptions"); 3305 3306 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); 3307 object_class_property_set_description(oc, "mte", 3308 "Set on/off to enable/disable emulating a " 3309 "guest CPU which implements the ARM " 3310 "Memory Tagging Extension"); 3311 3312 object_class_property_add_bool(oc, "its", virt_get_its, 3313 virt_set_its); 3314 object_class_property_set_description(oc, "its", 3315 "Set on/off to enable/disable " 3316 "ITS instantiation"); 3317 3318 object_class_property_add_bool(oc, "dtb-randomness", 3319 virt_get_dtb_randomness, 3320 virt_set_dtb_randomness); 3321 object_class_property_set_description(oc, "dtb-randomness", 3322 "Set off to disable passing random or " 3323 "non-deterministic dtb nodes to guest"); 3324 3325 object_class_property_add_bool(oc, "dtb-kaslr-seed", 3326 virt_get_dtb_randomness, 3327 virt_set_dtb_randomness); 3328 object_class_property_set_description(oc, "dtb-kaslr-seed", 3329 "Deprecated synonym of dtb-randomness"); 3330 3331 object_class_property_add_str(oc, "x-oem-id", 3332 virt_get_oem_id, 3333 virt_set_oem_id); 3334 object_class_property_set_description(oc, "x-oem-id", 3335 "Override the default value of field OEMID " 3336 "in ACPI table header." 3337 "The string may be up to 6 bytes in size"); 3338 3339 3340 object_class_property_add_str(oc, "x-oem-table-id", 3341 virt_get_oem_table_id, 3342 virt_set_oem_table_id); 3343 object_class_property_set_description(oc, "x-oem-table-id", 3344 "Override the default value of field OEM Table ID " 3345 "in ACPI table header." 3346 "The string may be up to 8 bytes in size"); 3347 3348 } 3349 3350 static void virt_instance_init(Object *obj) 3351 { 3352 VirtMachineState *vms = VIRT_MACHINE(obj); 3353 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 3354 3355 /* EL3 is disabled by default on virt: this makes us consistent 3356 * between KVM and TCG for this board, and it also allows us to 3357 * boot UEFI blobs which assume no TrustZone support. 3358 */ 3359 vms->secure = false; 3360 3361 /* EL2 is also disabled by default, for similar reasons */ 3362 vms->virt = false; 3363 3364 /* High memory is enabled by default */ 3365 vms->highmem = true; 3366 vms->highmem_compact = !vmc->no_highmem_compact; 3367 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 3368 3369 vms->highmem_ecam = true; 3370 vms->highmem_mmio = true; 3371 vms->highmem_redists = true; 3372 3373 /* Default allows ITS instantiation */ 3374 vms->its = true; 3375 /* Allow ITS emulation if the machine version supports it */ 3376 vms->tcg_its = !vmc->no_tcg_its; 3377 3378 /* Default disallows iommu instantiation */ 3379 vms->iommu = VIRT_IOMMU_NONE; 3380 3381 /* The default root bus is attached to iommu by default */ 3382 vms->default_bus_bypass_iommu = false; 3383 3384 /* Default disallows RAS instantiation */ 3385 vms->ras = false; 3386 3387 /* MTE is disabled by default. */ 3388 vms->mte = false; 3389 3390 /* Supply kaslr-seed and rng-seed by default */ 3391 vms->dtb_randomness = true; 3392 3393 vms->irqmap = a15irqmap; 3394 3395 virt_flash_create(vms); 3396 3397 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 3398 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 3399 cxl_machine_init(obj, &vms->cxl_devices_state); 3400 } 3401 3402 static const TypeInfo virt_machine_info = { 3403 .name = TYPE_VIRT_MACHINE, 3404 .parent = TYPE_MACHINE, 3405 .abstract = true, 3406 .instance_size = sizeof(VirtMachineState), 3407 .class_size = sizeof(VirtMachineClass), 3408 .class_init = virt_machine_class_init, 3409 .instance_init = virt_instance_init, 3410 .interfaces = (const InterfaceInfo[]) { 3411 { TYPE_HOTPLUG_HANDLER }, 3412 { } 3413 }, 3414 }; 3415 3416 static void machvirt_machine_init(void) 3417 { 3418 type_register_static(&virt_machine_info); 3419 } 3420 type_init(machvirt_machine_init); 3421 3422 static void virt_machine_10_1_options(MachineClass *mc) 3423 { 3424 } 3425 DEFINE_VIRT_MACHINE_AS_LATEST(10, 1) 3426 3427 static void virt_machine_10_0_options(MachineClass *mc) 3428 { 3429 virt_machine_10_1_options(mc); 3430 compat_props_add(mc->compat_props, hw_compat_10_0, hw_compat_10_0_len); 3431 } 3432 DEFINE_VIRT_MACHINE(10, 0) 3433 3434 static void virt_machine_9_2_options(MachineClass *mc) 3435 { 3436 virt_machine_10_0_options(mc); 3437 compat_props_add(mc->compat_props, hw_compat_9_2, hw_compat_9_2_len); 3438 } 3439 DEFINE_VIRT_MACHINE(9, 2) 3440 3441 static void virt_machine_9_1_options(MachineClass *mc) 3442 { 3443 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3444 3445 virt_machine_9_2_options(mc); 3446 compat_props_add(mc->compat_props, hw_compat_9_1, hw_compat_9_1_len); 3447 /* 9.1 and earlier have only a stage-1 SMMU, not a nested s1+2 one */ 3448 vmc->no_nested_smmu = true; 3449 } 3450 DEFINE_VIRT_MACHINE(9, 1) 3451 3452 static void virt_machine_9_0_options(MachineClass *mc) 3453 { 3454 virt_machine_9_1_options(mc); 3455 mc->smbios_memory_device_size = 16 * GiB; 3456 compat_props_add(mc->compat_props, hw_compat_9_0, hw_compat_9_0_len); 3457 } 3458 DEFINE_VIRT_MACHINE(9, 0) 3459 3460 static void virt_machine_8_2_options(MachineClass *mc) 3461 { 3462 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3463 3464 virt_machine_9_0_options(mc); 3465 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len); 3466 /* 3467 * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and 3468 * earlier machines. (Exposing it tickles a bug in older EDK2 3469 * guest BIOS binaries.) 3470 */ 3471 vmc->no_ns_el2_virt_timer_irq = true; 3472 } 3473 DEFINE_VIRT_MACHINE(8, 2) 3474 3475 static void virt_machine_8_1_options(MachineClass *mc) 3476 { 3477 virt_machine_8_2_options(mc); 3478 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len); 3479 } 3480 DEFINE_VIRT_MACHINE(8, 1) 3481 3482 static void virt_machine_8_0_options(MachineClass *mc) 3483 { 3484 virt_machine_8_1_options(mc); 3485 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 3486 } 3487 DEFINE_VIRT_MACHINE(8, 0) 3488 3489 static void virt_machine_7_2_options(MachineClass *mc) 3490 { 3491 virt_machine_8_0_options(mc); 3492 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 3493 } 3494 DEFINE_VIRT_MACHINE(7, 2) 3495 3496 static void virt_machine_7_1_options(MachineClass *mc) 3497 { 3498 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3499 3500 virt_machine_7_2_options(mc); 3501 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 3502 /* Compact layout for high memory regions was introduced with 7.2 */ 3503 vmc->no_highmem_compact = true; 3504 } 3505 DEFINE_VIRT_MACHINE(7, 1) 3506 3507 static void virt_machine_7_0_options(MachineClass *mc) 3508 { 3509 virt_machine_7_1_options(mc); 3510 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 3511 } 3512 DEFINE_VIRT_MACHINE(7, 0) 3513 3514 static void virt_machine_6_2_options(MachineClass *mc) 3515 { 3516 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3517 3518 virt_machine_7_0_options(mc); 3519 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 3520 vmc->no_tcg_lpa2 = true; 3521 } 3522 DEFINE_VIRT_MACHINE(6, 2) 3523 3524 static void virt_machine_6_1_options(MachineClass *mc) 3525 { 3526 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3527 3528 virt_machine_6_2_options(mc); 3529 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 3530 mc->smp_props.prefer_sockets = true; 3531 vmc->no_cpu_topology = true; 3532 3533 /* qemu ITS was introduced with 6.2 */ 3534 vmc->no_tcg_its = true; 3535 } 3536 DEFINE_VIRT_MACHINE(6, 1) 3537 3538 static void virt_machine_6_0_options(MachineClass *mc) 3539 { 3540 virt_machine_6_1_options(mc); 3541 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 3542 } 3543 DEFINE_VIRT_MACHINE(6, 0) 3544 3545 static void virt_machine_5_2_options(MachineClass *mc) 3546 { 3547 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3548 3549 virt_machine_6_0_options(mc); 3550 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 3551 vmc->no_secure_gpio = true; 3552 } 3553 DEFINE_VIRT_MACHINE(5, 2) 3554 3555 static void virt_machine_5_1_options(MachineClass *mc) 3556 { 3557 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3558 3559 virt_machine_5_2_options(mc); 3560 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 3561 vmc->no_kvm_steal_time = true; 3562 } 3563 DEFINE_VIRT_MACHINE(5, 1) 3564 3565 static void virt_machine_5_0_options(MachineClass *mc) 3566 { 3567 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3568 3569 virt_machine_5_1_options(mc); 3570 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 3571 mc->numa_mem_supported = true; 3572 vmc->acpi_expose_flash = true; 3573 mc->auto_enable_numa_with_memdev = false; 3574 } 3575 DEFINE_VIRT_MACHINE(5, 0) 3576 3577 static void virt_machine_4_2_options(MachineClass *mc) 3578 { 3579 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3580 3581 virt_machine_5_0_options(mc); 3582 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 3583 vmc->kvm_no_adjvtime = true; 3584 } 3585 DEFINE_VIRT_MACHINE(4, 2) 3586 3587 static void virt_machine_4_1_options(MachineClass *mc) 3588 { 3589 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3590 3591 virt_machine_4_2_options(mc); 3592 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 3593 vmc->no_ged = true; 3594 mc->auto_enable_numa_with_memhp = false; 3595 } 3596 DEFINE_VIRT_MACHINE(4, 1) 3597