1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/datadir.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "hw/sysbus.h" 37 #include "hw/arm/boot.h" 38 #include "hw/arm/primecell.h" 39 #include "hw/arm/virt.h" 40 #include "hw/block/flash.h" 41 #include "hw/vfio/vfio-calxeda-xgmac.h" 42 #include "hw/vfio/vfio-amd-xgbe.h" 43 #include "hw/display/ramfb.h" 44 #include "net/net.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/numa.h" 47 #include "sysemu/runstate.h" 48 #include "sysemu/tpm.h" 49 #include "sysemu/tcg.h" 50 #include "sysemu/kvm.h" 51 #include "sysemu/hvf.h" 52 #include "sysemu/qtest.h" 53 #include "hw/loader.h" 54 #include "qapi/error.h" 55 #include "qemu/bitops.h" 56 #include "qemu/error-report.h" 57 #include "qemu/module.h" 58 #include "hw/pci-host/gpex.h" 59 #include "hw/virtio/virtio-pci.h" 60 #include "hw/core/sysbus-fdt.h" 61 #include "hw/platform-bus.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/arm/fdt.h" 64 #include "hw/intc/arm_gic.h" 65 #include "hw/intc/arm_gicv3_common.h" 66 #include "hw/intc/arm_gicv3_its_common.h" 67 #include "hw/irq.h" 68 #include "kvm_arm.h" 69 #include "hw/firmware/smbios.h" 70 #include "qapi/visitor.h" 71 #include "qapi/qapi-visit-common.h" 72 #include "standard-headers/linux/input.h" 73 #include "hw/arm/smmuv3.h" 74 #include "hw/acpi/acpi.h" 75 #include "target/arm/internals.h" 76 #include "hw/mem/memory-device.h" 77 #include "hw/mem/pc-dimm.h" 78 #include "hw/mem/nvdimm.h" 79 #include "hw/acpi/generic_event_device.h" 80 #include "hw/virtio/virtio-mem-pci.h" 81 #include "hw/virtio/virtio-iommu.h" 82 #include "hw/char/pl011.h" 83 #include "qemu/guest-random.h" 84 85 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 86 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 87 void *data) \ 88 { \ 89 MachineClass *mc = MACHINE_CLASS(oc); \ 90 virt_machine_##major##_##minor##_options(mc); \ 91 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 92 if (latest) { \ 93 mc->alias = "virt"; \ 94 } \ 95 } \ 96 static const TypeInfo machvirt_##major##_##minor##_info = { \ 97 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 98 .parent = TYPE_VIRT_MACHINE, \ 99 .class_init = virt_##major##_##minor##_class_init, \ 100 }; \ 101 static void machvirt_machine_##major##_##minor##_init(void) \ 102 { \ 103 type_register_static(&machvirt_##major##_##minor##_info); \ 104 } \ 105 type_init(machvirt_machine_##major##_##minor##_init); 106 107 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 108 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 109 #define DEFINE_VIRT_MACHINE(major, minor) \ 110 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 111 112 113 /* Number of external interrupt lines to configure the GIC with */ 114 #define NUM_IRQS 256 115 116 #define PLATFORM_BUS_NUM_IRQS 64 117 118 /* Legacy RAM limit in GB (< version 4.0) */ 119 #define LEGACY_RAMLIMIT_GB 255 120 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 121 122 /* Addresses and sizes of our components. 123 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 124 * 128MB..256MB is used for miscellaneous device I/O. 125 * 256MB..1GB is reserved for possible future PCI support (ie where the 126 * PCI memory window will go if we add a PCI host controller). 127 * 1GB and up is RAM (which may happily spill over into the 128 * high memory region beyond 4GB). 129 * This represents a compromise between how much RAM can be given to 130 * a 32 bit VM and leaving space for expansion and in particular for PCI. 131 * Note that devices should generally be placed at multiples of 0x10000, 132 * to accommodate guests using 64K pages. 133 */ 134 static const MemMapEntry base_memmap[] = { 135 /* Space up to 0x8000000 is reserved for a boot ROM */ 136 [VIRT_FLASH] = { 0, 0x08000000 }, 137 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 138 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 139 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 140 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 141 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 142 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 143 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 144 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 145 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 146 /* This redistributor space allows up to 2*64kB*123 CPUs */ 147 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 148 [VIRT_UART] = { 0x09000000, 0x00001000 }, 149 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 150 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 151 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 152 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 153 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 154 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 155 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 156 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 157 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, 158 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, 159 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 160 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 161 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 162 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 163 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 164 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 165 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 166 /* Actual RAM size depends on initial RAM and device memory settings */ 167 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 168 }; 169 170 /* 171 * Highmem IO Regions: This memory map is floating, located after the RAM. 172 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 173 * top of the RAM, so that its base get the same alignment as the size, 174 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 175 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 176 * Note the extended_memmap is sized so that it eventually also includes the 177 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 178 * index of base_memmap). 179 * 180 * The memory map for these Highmem IO Regions can be in legacy or compact 181 * layout, depending on 'compact-highmem' property. With legacy layout, the 182 * PA space for one specific region is always reserved, even if the region 183 * has been disabled or doesn't fit into the PA space. However, the PA space 184 * for the region won't be reserved in these circumstances with compact layout. 185 */ 186 static MemMapEntry extended_memmap[] = { 187 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 188 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 189 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 190 /* Second PCIe window */ 191 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 192 }; 193 194 static const int a15irqmap[] = { 195 [VIRT_UART] = 1, 196 [VIRT_RTC] = 2, 197 [VIRT_PCIE] = 3, /* ... to 6 */ 198 [VIRT_GPIO] = 7, 199 [VIRT_SECURE_UART] = 8, 200 [VIRT_ACPI_GED] = 9, 201 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 202 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 203 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 204 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 205 }; 206 207 static const char *valid_cpus[] = { 208 #ifdef CONFIG_TCG 209 ARM_CPU_TYPE_NAME("cortex-a7"), 210 ARM_CPU_TYPE_NAME("cortex-a15"), 211 ARM_CPU_TYPE_NAME("cortex-a35"), 212 ARM_CPU_TYPE_NAME("cortex-a55"), 213 ARM_CPU_TYPE_NAME("cortex-a72"), 214 ARM_CPU_TYPE_NAME("cortex-a76"), 215 ARM_CPU_TYPE_NAME("a64fx"), 216 ARM_CPU_TYPE_NAME("neoverse-n1"), 217 #endif 218 ARM_CPU_TYPE_NAME("cortex-a53"), 219 ARM_CPU_TYPE_NAME("cortex-a57"), 220 ARM_CPU_TYPE_NAME("host"), 221 ARM_CPU_TYPE_NAME("max"), 222 }; 223 224 static bool cpu_type_valid(const char *cpu) 225 { 226 int i; 227 228 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 229 if (strcmp(cpu, valid_cpus[i]) == 0) { 230 return true; 231 } 232 } 233 return false; 234 } 235 236 static void create_randomness(MachineState *ms, const char *node) 237 { 238 struct { 239 uint64_t kaslr; 240 uint8_t rng[32]; 241 } seed; 242 243 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { 244 return; 245 } 246 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr); 247 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); 248 } 249 250 static void create_fdt(VirtMachineState *vms) 251 { 252 MachineState *ms = MACHINE(vms); 253 int nb_numa_nodes = ms->numa_state->num_nodes; 254 void *fdt = create_device_tree(&vms->fdt_size); 255 256 if (!fdt) { 257 error_report("create_device_tree() failed"); 258 exit(1); 259 } 260 261 ms->fdt = fdt; 262 263 /* Header */ 264 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 265 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 266 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 267 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt"); 268 269 /* /chosen must exist for load_dtb to fill in necessary properties later */ 270 qemu_fdt_add_subnode(fdt, "/chosen"); 271 if (vms->dtb_randomness) { 272 create_randomness(ms, "/chosen"); 273 } 274 275 if (vms->secure) { 276 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 277 if (vms->dtb_randomness) { 278 create_randomness(ms, "/secure-chosen"); 279 } 280 } 281 282 /* Clock node, for the benefit of the UART. The kernel device tree 283 * binding documentation claims the PL011 node clock properties are 284 * optional but in practice if you omit them the kernel refuses to 285 * probe for the device. 286 */ 287 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 288 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 289 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 290 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 291 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 292 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 293 "clk24mhz"); 294 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 295 296 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 297 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 298 uint32_t *matrix = g_malloc0(size); 299 int idx, i, j; 300 301 for (i = 0; i < nb_numa_nodes; i++) { 302 for (j = 0; j < nb_numa_nodes; j++) { 303 idx = (i * nb_numa_nodes + j) * 3; 304 matrix[idx + 0] = cpu_to_be32(i); 305 matrix[idx + 1] = cpu_to_be32(j); 306 matrix[idx + 2] = 307 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 308 } 309 } 310 311 qemu_fdt_add_subnode(fdt, "/distance-map"); 312 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 313 "numa-distance-map-v1"); 314 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 315 matrix, size); 316 g_free(matrix); 317 } 318 } 319 320 static void fdt_add_timer_nodes(const VirtMachineState *vms) 321 { 322 /* On real hardware these interrupts are level-triggered. 323 * On KVM they were edge-triggered before host kernel version 4.4, 324 * and level-triggered afterwards. 325 * On emulated QEMU they are level-triggered. 326 * 327 * Getting the DTB info about them wrong is awkward for some 328 * guest kernels: 329 * pre-4.8 ignore the DT and leave the interrupt configured 330 * with whatever the GIC reset value (or the bootloader) left it at 331 * 4.8 before rc6 honour the incorrect data by programming it back 332 * into the GIC, causing problems 333 * 4.8rc6 and later ignore the DT and always write "level triggered" 334 * into the GIC 335 * 336 * For backwards-compatibility, virt-2.8 and earlier will continue 337 * to say these are edge-triggered, but later machines will report 338 * the correct information. 339 */ 340 ARMCPU *armcpu; 341 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 342 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 343 MachineState *ms = MACHINE(vms); 344 345 if (vmc->claim_edge_triggered_timers) { 346 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 347 } 348 349 if (vms->gic_version == VIRT_GIC_VERSION_2) { 350 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 351 GIC_FDT_IRQ_PPI_CPU_WIDTH, 352 (1 << MACHINE(vms)->smp.cpus) - 1); 353 } 354 355 qemu_fdt_add_subnode(ms->fdt, "/timer"); 356 357 armcpu = ARM_CPU(qemu_get_cpu(0)); 358 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 359 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 360 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", 361 compat, sizeof(compat)); 362 } else { 363 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", 364 "arm,armv7-timer"); 365 } 366 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); 367 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 368 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 369 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 370 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 371 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 372 } 373 374 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 375 { 376 int cpu; 377 int addr_cells = 1; 378 const MachineState *ms = MACHINE(vms); 379 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 380 int smp_cpus = ms->smp.cpus; 381 382 /* 383 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml 384 * On ARM v8 64-bit systems value should be set to 2, 385 * that corresponds to the MPIDR_EL1 register size. 386 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 387 * in the system, #address-cells can be set to 1, since 388 * MPIDR_EL1[63:32] bits are not used for CPUs 389 * identification. 390 * 391 * Here we actually don't know whether our system is 32- or 64-bit one. 392 * The simplest way to go is to examine affinity IDs of all our CPUs. If 393 * at least one of them has Aff3 populated, we set #address-cells to 2. 394 */ 395 for (cpu = 0; cpu < smp_cpus; cpu++) { 396 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 397 398 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 399 addr_cells = 2; 400 break; 401 } 402 } 403 404 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 405 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); 406 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 407 408 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 409 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 410 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 411 CPUState *cs = CPU(armcpu); 412 413 qemu_fdt_add_subnode(ms->fdt, nodename); 414 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 415 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 416 armcpu->dtb_compatible); 417 418 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { 419 qemu_fdt_setprop_string(ms->fdt, nodename, 420 "enable-method", "psci"); 421 } 422 423 if (addr_cells == 2) { 424 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", 425 armcpu->mp_affinity); 426 } else { 427 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", 428 armcpu->mp_affinity); 429 } 430 431 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 432 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 433 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 434 } 435 436 if (!vmc->no_cpu_topology) { 437 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 438 qemu_fdt_alloc_phandle(ms->fdt)); 439 } 440 441 g_free(nodename); 442 } 443 444 if (!vmc->no_cpu_topology) { 445 /* 446 * Add vCPU topology description through fdt node cpu-map. 447 * 448 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt 449 * In a SMP system, the hierarchy of CPUs can be defined through 450 * four entities that are used to describe the layout of CPUs in 451 * the system: socket/cluster/core/thread. 452 * 453 * A socket node represents the boundary of system physical package 454 * and its child nodes must be one or more cluster nodes. A system 455 * can contain several layers of clustering within a single physical 456 * package and cluster nodes can be contained in parent cluster nodes. 457 * 458 * Note: currently we only support one layer of clustering within 459 * each physical package. 460 */ 461 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 462 463 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 464 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); 465 char *map_path; 466 467 if (ms->smp.threads > 1) { 468 map_path = g_strdup_printf( 469 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", 470 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), 471 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, 472 (cpu / ms->smp.threads) % ms->smp.cores, 473 cpu % ms->smp.threads); 474 } else { 475 map_path = g_strdup_printf( 476 "/cpus/cpu-map/socket%d/cluster%d/core%d", 477 cpu / (ms->smp.clusters * ms->smp.cores), 478 (cpu / ms->smp.cores) % ms->smp.clusters, 479 cpu % ms->smp.cores); 480 } 481 qemu_fdt_add_path(ms->fdt, map_path); 482 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 483 484 g_free(map_path); 485 g_free(cpu_path); 486 } 487 } 488 } 489 490 static void fdt_add_its_gic_node(VirtMachineState *vms) 491 { 492 char *nodename; 493 MachineState *ms = MACHINE(vms); 494 495 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 496 nodename = g_strdup_printf("/intc/its@%" PRIx64, 497 vms->memmap[VIRT_GIC_ITS].base); 498 qemu_fdt_add_subnode(ms->fdt, nodename); 499 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 500 "arm,gic-v3-its"); 501 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 502 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1); 503 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 504 2, vms->memmap[VIRT_GIC_ITS].base, 505 2, vms->memmap[VIRT_GIC_ITS].size); 506 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 507 g_free(nodename); 508 } 509 510 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 511 { 512 MachineState *ms = MACHINE(vms); 513 char *nodename; 514 515 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 516 vms->memmap[VIRT_GIC_V2M].base); 517 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 518 qemu_fdt_add_subnode(ms->fdt, nodename); 519 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 520 "arm,gic-v2m-frame"); 521 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 522 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 523 2, vms->memmap[VIRT_GIC_V2M].base, 524 2, vms->memmap[VIRT_GIC_V2M].size); 525 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 526 g_free(nodename); 527 } 528 529 static void fdt_add_gic_node(VirtMachineState *vms) 530 { 531 MachineState *ms = MACHINE(vms); 532 char *nodename; 533 534 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 535 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); 536 537 nodename = g_strdup_printf("/intc@%" PRIx64, 538 vms->memmap[VIRT_GIC_DIST].base); 539 qemu_fdt_add_subnode(ms->fdt, nodename); 540 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 541 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 542 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 543 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 544 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 545 if (vms->gic_version != VIRT_GIC_VERSION_2) { 546 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 547 548 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 549 "arm,gic-v3"); 550 551 qemu_fdt_setprop_cell(ms->fdt, nodename, 552 "#redistributor-regions", nb_redist_regions); 553 554 if (nb_redist_regions == 1) { 555 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 556 2, vms->memmap[VIRT_GIC_DIST].base, 557 2, vms->memmap[VIRT_GIC_DIST].size, 558 2, vms->memmap[VIRT_GIC_REDIST].base, 559 2, vms->memmap[VIRT_GIC_REDIST].size); 560 } else { 561 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 562 2, vms->memmap[VIRT_GIC_DIST].base, 563 2, vms->memmap[VIRT_GIC_DIST].size, 564 2, vms->memmap[VIRT_GIC_REDIST].base, 565 2, vms->memmap[VIRT_GIC_REDIST].size, 566 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 567 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 568 } 569 570 if (vms->virt) { 571 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 572 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 573 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 574 } 575 } else { 576 /* 'cortex-a15-gic' means 'GIC v2' */ 577 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 578 "arm,cortex-a15-gic"); 579 if (!vms->virt) { 580 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 581 2, vms->memmap[VIRT_GIC_DIST].base, 582 2, vms->memmap[VIRT_GIC_DIST].size, 583 2, vms->memmap[VIRT_GIC_CPU].base, 584 2, vms->memmap[VIRT_GIC_CPU].size); 585 } else { 586 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 587 2, vms->memmap[VIRT_GIC_DIST].base, 588 2, vms->memmap[VIRT_GIC_DIST].size, 589 2, vms->memmap[VIRT_GIC_CPU].base, 590 2, vms->memmap[VIRT_GIC_CPU].size, 591 2, vms->memmap[VIRT_GIC_HYP].base, 592 2, vms->memmap[VIRT_GIC_HYP].size, 593 2, vms->memmap[VIRT_GIC_VCPU].base, 594 2, vms->memmap[VIRT_GIC_VCPU].size); 595 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 596 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 597 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 598 } 599 } 600 601 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); 602 g_free(nodename); 603 } 604 605 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 606 { 607 ARMCPU *armcpu = ARM_CPU(first_cpu); 608 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 609 MachineState *ms = MACHINE(vms); 610 611 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 612 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); 613 return; 614 } 615 616 if (vms->gic_version == VIRT_GIC_VERSION_2) { 617 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 618 GIC_FDT_IRQ_PPI_CPU_WIDTH, 619 (1 << MACHINE(vms)->smp.cpus) - 1); 620 } 621 622 qemu_fdt_add_subnode(ms->fdt, "/pmu"); 623 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 624 const char compat[] = "arm,armv8-pmuv3"; 625 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", 626 compat, sizeof(compat)); 627 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", 628 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 629 } 630 } 631 632 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 633 { 634 DeviceState *dev; 635 MachineState *ms = MACHINE(vms); 636 int irq = vms->irqmap[VIRT_ACPI_GED]; 637 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 638 639 if (ms->ram_slots) { 640 event |= ACPI_GED_MEM_HOTPLUG_EVT; 641 } 642 643 if (ms->nvdimms_state->is_enabled) { 644 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 645 } 646 647 dev = qdev_new(TYPE_ACPI_GED); 648 qdev_prop_set_uint32(dev, "ged-event", event); 649 650 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 651 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 652 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 653 654 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 655 656 return dev; 657 } 658 659 static void create_its(VirtMachineState *vms) 660 { 661 const char *itsclass = its_class_name(); 662 DeviceState *dev; 663 664 if (!strcmp(itsclass, "arm-gicv3-its")) { 665 if (!vms->tcg_its) { 666 itsclass = NULL; 667 } 668 } 669 670 if (!itsclass) { 671 /* Do nothing if not supported */ 672 return; 673 } 674 675 dev = qdev_new(itsclass); 676 677 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 678 &error_abort); 679 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 680 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 681 682 fdt_add_its_gic_node(vms); 683 vms->msi_controller = VIRT_MSI_CTRL_ITS; 684 } 685 686 static void create_v2m(VirtMachineState *vms) 687 { 688 int i; 689 int irq = vms->irqmap[VIRT_GIC_V2M]; 690 DeviceState *dev; 691 692 dev = qdev_new("arm-gicv2m"); 693 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 694 qdev_prop_set_uint32(dev, "base-spi", irq); 695 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 696 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 697 698 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 699 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 700 qdev_get_gpio_in(vms->gic, irq + i)); 701 } 702 703 fdt_add_v2m_gic_node(vms); 704 vms->msi_controller = VIRT_MSI_CTRL_GICV2M; 705 } 706 707 static void create_gic(VirtMachineState *vms, MemoryRegion *mem) 708 { 709 MachineState *ms = MACHINE(vms); 710 /* We create a standalone GIC */ 711 SysBusDevice *gicbusdev; 712 const char *gictype; 713 int i; 714 unsigned int smp_cpus = ms->smp.cpus; 715 uint32_t nb_redist_regions = 0; 716 int revision; 717 718 if (vms->gic_version == VIRT_GIC_VERSION_2) { 719 gictype = gic_class_name(); 720 } else { 721 gictype = gicv3_class_name(); 722 } 723 724 switch (vms->gic_version) { 725 case VIRT_GIC_VERSION_2: 726 revision = 2; 727 break; 728 case VIRT_GIC_VERSION_3: 729 revision = 3; 730 break; 731 case VIRT_GIC_VERSION_4: 732 revision = 4; 733 break; 734 default: 735 g_assert_not_reached(); 736 } 737 vms->gic = qdev_new(gictype); 738 qdev_prop_set_uint32(vms->gic, "revision", revision); 739 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 740 /* Note that the num-irq property counts both internal and external 741 * interrupts; there are always 32 of the former (mandated by GIC spec). 742 */ 743 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 744 if (!kvm_irqchip_in_kernel()) { 745 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 746 } 747 748 if (vms->gic_version != VIRT_GIC_VERSION_2) { 749 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); 750 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 751 752 nb_redist_regions = virt_gicv3_redist_region_count(vms); 753 754 qdev_prop_set_uint32(vms->gic, "len-redist-region-count", 755 nb_redist_regions); 756 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count); 757 758 if (!kvm_irqchip_in_kernel()) { 759 if (vms->tcg_its) { 760 object_property_set_link(OBJECT(vms->gic), "sysmem", 761 OBJECT(mem), &error_fatal); 762 qdev_prop_set_bit(vms->gic, "has-lpi", true); 763 } 764 } 765 766 if (nb_redist_regions == 2) { 767 uint32_t redist1_capacity = 768 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 769 770 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", 771 MIN(smp_cpus - redist0_count, redist1_capacity)); 772 } 773 } else { 774 if (!kvm_irqchip_in_kernel()) { 775 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 776 vms->virt); 777 } 778 } 779 gicbusdev = SYS_BUS_DEVICE(vms->gic); 780 sysbus_realize_and_unref(gicbusdev, &error_fatal); 781 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 782 if (vms->gic_version != VIRT_GIC_VERSION_2) { 783 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 784 if (nb_redist_regions == 2) { 785 sysbus_mmio_map(gicbusdev, 2, 786 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 787 } 788 } else { 789 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 790 if (vms->virt) { 791 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 792 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 793 } 794 } 795 796 /* Wire the outputs from each CPU's generic timer and the GICv3 797 * maintenance interrupt signal to the appropriate GIC PPI inputs, 798 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 799 */ 800 for (i = 0; i < smp_cpus; i++) { 801 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 802 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 803 int irq; 804 /* Mapping from the output timer irq lines from the CPU to the 805 * GIC PPI inputs we use for the virt board. 806 */ 807 const int timer_irq[] = { 808 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 809 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 810 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 811 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 812 }; 813 814 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 815 qdev_connect_gpio_out(cpudev, irq, 816 qdev_get_gpio_in(vms->gic, 817 ppibase + timer_irq[irq])); 818 } 819 820 if (vms->gic_version != VIRT_GIC_VERSION_2) { 821 qemu_irq irq = qdev_get_gpio_in(vms->gic, 822 ppibase + ARCH_GIC_MAINT_IRQ); 823 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 824 0, irq); 825 } else if (vms->virt) { 826 qemu_irq irq = qdev_get_gpio_in(vms->gic, 827 ppibase + ARCH_GIC_MAINT_IRQ); 828 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 829 } 830 831 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 832 qdev_get_gpio_in(vms->gic, ppibase 833 + VIRTUAL_PMU_IRQ)); 834 835 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 836 sysbus_connect_irq(gicbusdev, i + smp_cpus, 837 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 838 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 839 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 840 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 841 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 842 } 843 844 fdt_add_gic_node(vms); 845 846 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) { 847 create_its(vms); 848 } else if (vms->gic_version == VIRT_GIC_VERSION_2) { 849 create_v2m(vms); 850 } 851 } 852 853 static void create_uart(const VirtMachineState *vms, int uart, 854 MemoryRegion *mem, Chardev *chr) 855 { 856 char *nodename; 857 hwaddr base = vms->memmap[uart].base; 858 hwaddr size = vms->memmap[uart].size; 859 int irq = vms->irqmap[uart]; 860 const char compat[] = "arm,pl011\0arm,primecell"; 861 const char clocknames[] = "uartclk\0apb_pclk"; 862 DeviceState *dev = qdev_new(TYPE_PL011); 863 SysBusDevice *s = SYS_BUS_DEVICE(dev); 864 MachineState *ms = MACHINE(vms); 865 866 qdev_prop_set_chr(dev, "chardev", chr); 867 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 868 memory_region_add_subregion(mem, base, 869 sysbus_mmio_get_region(s, 0)); 870 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 871 872 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 873 qemu_fdt_add_subnode(ms->fdt, nodename); 874 /* Note that we can't use setprop_string because of the embedded NUL */ 875 qemu_fdt_setprop(ms->fdt, nodename, "compatible", 876 compat, sizeof(compat)); 877 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 878 2, base, 2, size); 879 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 880 GIC_FDT_IRQ_TYPE_SPI, irq, 881 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 882 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", 883 vms->clock_phandle, vms->clock_phandle); 884 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", 885 clocknames, sizeof(clocknames)); 886 887 if (uart == VIRT_UART) { 888 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 889 } else { 890 /* Mark as not usable by the normal world */ 891 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 892 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 893 894 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", 895 nodename); 896 } 897 898 g_free(nodename); 899 } 900 901 static void create_rtc(const VirtMachineState *vms) 902 { 903 char *nodename; 904 hwaddr base = vms->memmap[VIRT_RTC].base; 905 hwaddr size = vms->memmap[VIRT_RTC].size; 906 int irq = vms->irqmap[VIRT_RTC]; 907 const char compat[] = "arm,pl031\0arm,primecell"; 908 MachineState *ms = MACHINE(vms); 909 910 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 911 912 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 913 qemu_fdt_add_subnode(ms->fdt, nodename); 914 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 915 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 916 2, base, 2, size); 917 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 918 GIC_FDT_IRQ_TYPE_SPI, irq, 919 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 920 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 921 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 922 g_free(nodename); 923 } 924 925 static DeviceState *gpio_key_dev; 926 static void virt_powerdown_req(Notifier *n, void *opaque) 927 { 928 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 929 930 if (s->acpi_dev) { 931 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 932 } else { 933 /* use gpio Pin 3 for power button event */ 934 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 935 } 936 } 937 938 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, 939 uint32_t phandle) 940 { 941 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 942 qdev_get_gpio_in(pl061_dev, 3)); 943 944 qemu_fdt_add_subnode(fdt, "/gpio-keys"); 945 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); 946 947 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); 948 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", 949 "label", "GPIO Key Poweroff"); 950 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", 951 KEY_POWER); 952 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", 953 "gpios", phandle, 3, 0); 954 } 955 956 #define SECURE_GPIO_POWEROFF 0 957 #define SECURE_GPIO_RESET 1 958 959 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, 960 uint32_t phandle) 961 { 962 DeviceState *gpio_pwr_dev; 963 964 /* gpio-pwr */ 965 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); 966 967 /* connect secure pl061 to gpio-pwr */ 968 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, 969 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); 970 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, 971 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); 972 973 qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); 974 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", 975 "gpio-poweroff"); 976 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", 977 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); 978 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); 979 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", 980 "okay"); 981 982 qemu_fdt_add_subnode(fdt, "/gpio-restart"); 983 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", 984 "gpio-restart"); 985 qemu_fdt_setprop_cells(fdt, "/gpio-restart", 986 "gpios", phandle, SECURE_GPIO_RESET, 0); 987 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); 988 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", 989 "okay"); 990 } 991 992 static void create_gpio_devices(const VirtMachineState *vms, int gpio, 993 MemoryRegion *mem) 994 { 995 char *nodename; 996 DeviceState *pl061_dev; 997 hwaddr base = vms->memmap[gpio].base; 998 hwaddr size = vms->memmap[gpio].size; 999 int irq = vms->irqmap[gpio]; 1000 const char compat[] = "arm,pl061\0arm,primecell"; 1001 SysBusDevice *s; 1002 MachineState *ms = MACHINE(vms); 1003 1004 pl061_dev = qdev_new("pl061"); 1005 /* Pull lines down to 0 if not driven by the PL061 */ 1006 qdev_prop_set_uint32(pl061_dev, "pullups", 0); 1007 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); 1008 s = SYS_BUS_DEVICE(pl061_dev); 1009 sysbus_realize_and_unref(s, &error_fatal); 1010 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); 1011 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 1012 1013 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); 1014 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 1015 qemu_fdt_add_subnode(ms->fdt, nodename); 1016 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1017 2, base, 2, size); 1018 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 1019 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); 1020 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); 1021 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1022 GIC_FDT_IRQ_TYPE_SPI, irq, 1023 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1024 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1025 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1026 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); 1027 1028 if (gpio != VIRT_GPIO) { 1029 /* Mark as not usable by the normal world */ 1030 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1031 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1032 } 1033 g_free(nodename); 1034 1035 /* Child gpio devices */ 1036 if (gpio == VIRT_GPIO) { 1037 create_gpio_keys(ms->fdt, pl061_dev, phandle); 1038 } else { 1039 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); 1040 } 1041 } 1042 1043 static void create_virtio_devices(const VirtMachineState *vms) 1044 { 1045 int i; 1046 hwaddr size = vms->memmap[VIRT_MMIO].size; 1047 MachineState *ms = MACHINE(vms); 1048 1049 /* We create the transports in forwards order. Since qbus_realize() 1050 * prepends (not appends) new child buses, the incrementing loop below will 1051 * create a list of virtio-mmio buses with decreasing base addresses. 1052 * 1053 * When a -device option is processed from the command line, 1054 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 1055 * order. The upshot is that -device options in increasing command line 1056 * order are mapped to virtio-mmio buses with decreasing base addresses. 1057 * 1058 * When this code was originally written, that arrangement ensured that the 1059 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 1060 * the first -device on the command line. (The end-to-end order is a 1061 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 1062 * guest kernel's name-to-address assignment strategy.) 1063 * 1064 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 1065 * the message, if not necessarily the code, of commit 70161ff336. 1066 * Therefore the loop now establishes the inverse of the original intent. 1067 * 1068 * Unfortunately, we can't counteract the kernel change by reversing the 1069 * loop; it would break existing command lines. 1070 * 1071 * In any case, the kernel makes no guarantee about the stability of 1072 * enumeration order of virtio devices (as demonstrated by it changing 1073 * between kernel versions). For reliable and stable identification 1074 * of disks users must use UUIDs or similar mechanisms. 1075 */ 1076 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 1077 int irq = vms->irqmap[VIRT_MMIO] + i; 1078 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1079 1080 sysbus_create_simple("virtio-mmio", base, 1081 qdev_get_gpio_in(vms->gic, irq)); 1082 } 1083 1084 /* We add dtb nodes in reverse order so that they appear in the finished 1085 * device tree lowest address first. 1086 * 1087 * Note that this mapping is independent of the loop above. The previous 1088 * loop influences virtio device to virtio transport assignment, whereas 1089 * this loop controls how virtio transports are laid out in the dtb. 1090 */ 1091 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 1092 char *nodename; 1093 int irq = vms->irqmap[VIRT_MMIO] + i; 1094 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1095 1096 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 1097 qemu_fdt_add_subnode(ms->fdt, nodename); 1098 qemu_fdt_setprop_string(ms->fdt, nodename, 1099 "compatible", "virtio,mmio"); 1100 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1101 2, base, 2, size); 1102 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1103 GIC_FDT_IRQ_TYPE_SPI, irq, 1104 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1105 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1106 g_free(nodename); 1107 } 1108 } 1109 1110 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 1111 1112 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 1113 const char *name, 1114 const char *alias_prop_name) 1115 { 1116 /* 1117 * Create a single flash device. We use the same parameters as 1118 * the flash devices on the Versatile Express board. 1119 */ 1120 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 1121 1122 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 1123 qdev_prop_set_uint8(dev, "width", 4); 1124 qdev_prop_set_uint8(dev, "device-width", 2); 1125 qdev_prop_set_bit(dev, "big-endian", false); 1126 qdev_prop_set_uint16(dev, "id0", 0x89); 1127 qdev_prop_set_uint16(dev, "id1", 0x18); 1128 qdev_prop_set_uint16(dev, "id2", 0x00); 1129 qdev_prop_set_uint16(dev, "id3", 0x00); 1130 qdev_prop_set_string(dev, "name", name); 1131 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 1132 object_property_add_alias(OBJECT(vms), alias_prop_name, 1133 OBJECT(dev), "drive"); 1134 return PFLASH_CFI01(dev); 1135 } 1136 1137 static void virt_flash_create(VirtMachineState *vms) 1138 { 1139 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 1140 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 1141 } 1142 1143 static void virt_flash_map1(PFlashCFI01 *flash, 1144 hwaddr base, hwaddr size, 1145 MemoryRegion *sysmem) 1146 { 1147 DeviceState *dev = DEVICE(flash); 1148 1149 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 1150 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 1151 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 1152 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1153 1154 memory_region_add_subregion(sysmem, base, 1155 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1156 0)); 1157 } 1158 1159 static void virt_flash_map(VirtMachineState *vms, 1160 MemoryRegion *sysmem, 1161 MemoryRegion *secure_sysmem) 1162 { 1163 /* 1164 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 1165 * sysmem is the system memory space. secure_sysmem is the secure view 1166 * of the system, and the first flash device should be made visible only 1167 * there. The second flash device is visible to both secure and nonsecure. 1168 * If sysmem == secure_sysmem this means there is no separate Secure 1169 * address space and both flash devices are generally visible. 1170 */ 1171 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1172 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1173 1174 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1175 secure_sysmem); 1176 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1177 sysmem); 1178 } 1179 1180 static void virt_flash_fdt(VirtMachineState *vms, 1181 MemoryRegion *sysmem, 1182 MemoryRegion *secure_sysmem) 1183 { 1184 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1185 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1186 MachineState *ms = MACHINE(vms); 1187 char *nodename; 1188 1189 if (sysmem == secure_sysmem) { 1190 /* Report both flash devices as a single node in the DT */ 1191 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1192 qemu_fdt_add_subnode(ms->fdt, nodename); 1193 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1194 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1195 2, flashbase, 2, flashsize, 1196 2, flashbase + flashsize, 2, flashsize); 1197 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1198 g_free(nodename); 1199 } else { 1200 /* 1201 * Report the devices as separate nodes so we can mark one as 1202 * only visible to the secure world. 1203 */ 1204 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1205 qemu_fdt_add_subnode(ms->fdt, nodename); 1206 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1207 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1208 2, flashbase, 2, flashsize); 1209 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1210 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1211 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1212 g_free(nodename); 1213 1214 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize); 1215 qemu_fdt_add_subnode(ms->fdt, nodename); 1216 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1217 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1218 2, flashbase + flashsize, 2, flashsize); 1219 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1220 g_free(nodename); 1221 } 1222 } 1223 1224 static bool virt_firmware_init(VirtMachineState *vms, 1225 MemoryRegion *sysmem, 1226 MemoryRegion *secure_sysmem) 1227 { 1228 int i; 1229 const char *bios_name; 1230 BlockBackend *pflash_blk0; 1231 1232 /* Map legacy -drive if=pflash to machine properties */ 1233 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1234 pflash_cfi01_legacy_drive(vms->flash[i], 1235 drive_get(IF_PFLASH, 0, i)); 1236 } 1237 1238 virt_flash_map(vms, sysmem, secure_sysmem); 1239 1240 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1241 1242 bios_name = MACHINE(vms)->firmware; 1243 if (bios_name) { 1244 char *fname; 1245 MemoryRegion *mr; 1246 int image_size; 1247 1248 if (pflash_blk0) { 1249 error_report("The contents of the first flash device may be " 1250 "specified with -bios or with -drive if=pflash... " 1251 "but you cannot use both options at once"); 1252 exit(1); 1253 } 1254 1255 /* Fall back to -bios */ 1256 1257 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1258 if (!fname) { 1259 error_report("Could not find ROM image '%s'", bios_name); 1260 exit(1); 1261 } 1262 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1263 image_size = load_image_mr(fname, mr); 1264 g_free(fname); 1265 if (image_size < 0) { 1266 error_report("Could not load ROM image '%s'", bios_name); 1267 exit(1); 1268 } 1269 } 1270 1271 return pflash_blk0 || bios_name; 1272 } 1273 1274 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1275 { 1276 MachineState *ms = MACHINE(vms); 1277 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1278 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1279 FWCfgState *fw_cfg; 1280 char *nodename; 1281 1282 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1283 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1284 1285 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1286 qemu_fdt_add_subnode(ms->fdt, nodename); 1287 qemu_fdt_setprop_string(ms->fdt, nodename, 1288 "compatible", "qemu,fw-cfg-mmio"); 1289 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1290 2, base, 2, size); 1291 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1292 g_free(nodename); 1293 return fw_cfg; 1294 } 1295 1296 static void create_pcie_irq_map(const MachineState *ms, 1297 uint32_t gic_phandle, 1298 int first_irq, const char *nodename) 1299 { 1300 int devfn, pin; 1301 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1302 uint32_t *irq_map = full_irq_map; 1303 1304 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1305 for (pin = 0; pin < 4; pin++) { 1306 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1307 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1308 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1309 int i; 1310 1311 uint32_t map[] = { 1312 devfn << 8, 0, 0, /* devfn */ 1313 pin + 1, /* PCI pin */ 1314 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1315 1316 /* Convert map to big endian */ 1317 for (i = 0; i < 10; i++) { 1318 irq_map[i] = cpu_to_be32(map[i]); 1319 } 1320 irq_map += 10; 1321 } 1322 } 1323 1324 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", 1325 full_irq_map, sizeof(full_irq_map)); 1326 1327 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 1328 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ 1329 0, 0, 1330 0x7 /* PCI irq */); 1331 } 1332 1333 static void create_smmu(const VirtMachineState *vms, 1334 PCIBus *bus) 1335 { 1336 char *node; 1337 const char compat[] = "arm,smmu-v3"; 1338 int irq = vms->irqmap[VIRT_SMMU]; 1339 int i; 1340 hwaddr base = vms->memmap[VIRT_SMMU].base; 1341 hwaddr size = vms->memmap[VIRT_SMMU].size; 1342 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1343 DeviceState *dev; 1344 MachineState *ms = MACHINE(vms); 1345 1346 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1347 return; 1348 } 1349 1350 dev = qdev_new(TYPE_ARM_SMMUV3); 1351 1352 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1353 &error_abort); 1354 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1355 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1356 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1357 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1358 qdev_get_gpio_in(vms->gic, irq + i)); 1359 } 1360 1361 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1362 qemu_fdt_add_subnode(ms->fdt, node); 1363 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1364 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); 1365 1366 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", 1367 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1368 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1369 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1370 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1371 1372 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, 1373 sizeof(irq_names)); 1374 1375 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); 1376 1377 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1378 1379 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1380 g_free(node); 1381 } 1382 1383 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1384 { 1385 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1386 uint16_t bdf = vms->virtio_iommu_bdf; 1387 MachineState *ms = MACHINE(vms); 1388 char *node; 1389 1390 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1391 1392 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename, 1393 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1394 qemu_fdt_add_subnode(ms->fdt, node); 1395 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1396 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 1397 1, bdf << 8, 1, 0, 1, 0, 1398 1, 0, 1, 0); 1399 1400 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1401 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1402 g_free(node); 1403 1404 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", 1405 0x0, vms->iommu_phandle, 0x0, bdf, 1406 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1407 } 1408 1409 static void create_pcie(VirtMachineState *vms) 1410 { 1411 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1412 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1413 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1414 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1415 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1416 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1417 hwaddr base_ecam, size_ecam; 1418 hwaddr base = base_mmio; 1419 int nr_pcie_buses; 1420 int irq = vms->irqmap[VIRT_PCIE]; 1421 MemoryRegion *mmio_alias; 1422 MemoryRegion *mmio_reg; 1423 MemoryRegion *ecam_alias; 1424 MemoryRegion *ecam_reg; 1425 DeviceState *dev; 1426 char *nodename; 1427 int i, ecam_id; 1428 PCIHostState *pci; 1429 MachineState *ms = MACHINE(vms); 1430 MachineClass *mc = MACHINE_GET_CLASS(ms); 1431 1432 dev = qdev_new(TYPE_GPEX_HOST); 1433 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1434 1435 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1436 base_ecam = vms->memmap[ecam_id].base; 1437 size_ecam = vms->memmap[ecam_id].size; 1438 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1439 /* Map only the first size_ecam bytes of ECAM space */ 1440 ecam_alias = g_new0(MemoryRegion, 1); 1441 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1442 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1443 ecam_reg, 0, size_ecam); 1444 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1445 1446 /* Map the MMIO window into system address space so as to expose 1447 * the section of PCI MMIO space which starts at the same base address 1448 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1449 * the window). 1450 */ 1451 mmio_alias = g_new0(MemoryRegion, 1); 1452 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1453 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1454 mmio_reg, base_mmio, size_mmio); 1455 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1456 1457 if (vms->highmem_mmio) { 1458 /* Map high MMIO space */ 1459 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1460 1461 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1462 mmio_reg, base_mmio_high, size_mmio_high); 1463 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1464 high_mmio_alias); 1465 } 1466 1467 /* Map IO port space */ 1468 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1469 1470 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1471 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1472 qdev_get_gpio_in(vms->gic, irq + i)); 1473 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1474 } 1475 1476 pci = PCI_HOST_BRIDGE(dev); 1477 pci->bypass_iommu = vms->default_bus_bypass_iommu; 1478 vms->bus = pci->bus; 1479 if (vms->bus) { 1480 for (i = 0; i < nb_nics; i++) { 1481 NICInfo *nd = &nd_table[i]; 1482 1483 if (!nd->model) { 1484 nd->model = g_strdup(mc->default_nic); 1485 } 1486 1487 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1488 } 1489 } 1490 1491 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1492 qemu_fdt_add_subnode(ms->fdt, nodename); 1493 qemu_fdt_setprop_string(ms->fdt, nodename, 1494 "compatible", "pci-host-ecam-generic"); 1495 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 1496 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 1497 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 1498 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 1499 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 1500 nr_pcie_buses - 1); 1501 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1502 1503 if (vms->msi_phandle) { 1504 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 1505 0, vms->msi_phandle, 0, 0x10000); 1506 } 1507 1508 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1509 2, base_ecam, 2, size_ecam); 1510 1511 if (vms->highmem_mmio) { 1512 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1513 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1514 2, base_pio, 2, size_pio, 1515 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1516 2, base_mmio, 2, size_mmio, 1517 1, FDT_PCI_RANGE_MMIO_64BIT, 1518 2, base_mmio_high, 1519 2, base_mmio_high, 2, size_mmio_high); 1520 } else { 1521 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1522 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1523 2, base_pio, 2, size_pio, 1524 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1525 2, base_mmio, 2, size_mmio); 1526 } 1527 1528 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 1529 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); 1530 1531 if (vms->iommu) { 1532 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1533 1534 switch (vms->iommu) { 1535 case VIRT_IOMMU_SMMUV3: 1536 create_smmu(vms, vms->bus); 1537 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 1538 0x0, vms->iommu_phandle, 0x0, 0x10000); 1539 break; 1540 default: 1541 g_assert_not_reached(); 1542 } 1543 } 1544 } 1545 1546 static void create_platform_bus(VirtMachineState *vms) 1547 { 1548 DeviceState *dev; 1549 SysBusDevice *s; 1550 int i; 1551 MemoryRegion *sysmem = get_system_memory(); 1552 1553 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1554 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1555 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1556 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1557 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1558 vms->platform_bus_dev = dev; 1559 1560 s = SYS_BUS_DEVICE(dev); 1561 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1562 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1563 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1564 } 1565 1566 memory_region_add_subregion(sysmem, 1567 vms->memmap[VIRT_PLATFORM_BUS].base, 1568 sysbus_mmio_get_region(s, 0)); 1569 } 1570 1571 static void create_tag_ram(MemoryRegion *tag_sysmem, 1572 hwaddr base, hwaddr size, 1573 const char *name) 1574 { 1575 MemoryRegion *tagram = g_new(MemoryRegion, 1); 1576 1577 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); 1578 memory_region_add_subregion(tag_sysmem, base / 32, tagram); 1579 } 1580 1581 static void create_secure_ram(VirtMachineState *vms, 1582 MemoryRegion *secure_sysmem, 1583 MemoryRegion *secure_tag_sysmem) 1584 { 1585 MemoryRegion *secram = g_new(MemoryRegion, 1); 1586 char *nodename; 1587 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1588 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1589 MachineState *ms = MACHINE(vms); 1590 1591 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1592 &error_fatal); 1593 memory_region_add_subregion(secure_sysmem, base, secram); 1594 1595 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1596 qemu_fdt_add_subnode(ms->fdt, nodename); 1597 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 1598 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 1599 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1600 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1601 1602 if (secure_tag_sysmem) { 1603 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); 1604 } 1605 1606 g_free(nodename); 1607 } 1608 1609 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1610 { 1611 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1612 bootinfo); 1613 MachineState *ms = MACHINE(board); 1614 1615 1616 *fdt_size = board->fdt_size; 1617 return ms->fdt; 1618 } 1619 1620 static void virt_build_smbios(VirtMachineState *vms) 1621 { 1622 MachineClass *mc = MACHINE_GET_CLASS(vms); 1623 MachineState *ms = MACHINE(vms); 1624 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1625 uint8_t *smbios_tables, *smbios_anchor; 1626 size_t smbios_tables_len, smbios_anchor_len; 1627 struct smbios_phys_mem_area mem_array; 1628 const char *product = "QEMU Virtual Machine"; 1629 1630 if (kvm_enabled()) { 1631 product = "KVM Virtual Machine"; 1632 } 1633 1634 smbios_set_defaults("QEMU", product, 1635 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1636 true, SMBIOS_ENTRY_POINT_TYPE_64); 1637 1638 /* build the array of physical mem area from base_memmap */ 1639 mem_array.address = vms->memmap[VIRT_MEM].base; 1640 mem_array.length = ms->ram_size; 1641 1642 smbios_get_tables(ms, &mem_array, 1, 1643 &smbios_tables, &smbios_tables_len, 1644 &smbios_anchor, &smbios_anchor_len, 1645 &error_fatal); 1646 1647 if (smbios_anchor) { 1648 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1649 smbios_tables, smbios_tables_len); 1650 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1651 smbios_anchor, smbios_anchor_len); 1652 } 1653 } 1654 1655 static 1656 void virt_machine_done(Notifier *notifier, void *data) 1657 { 1658 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1659 machine_done); 1660 MachineState *ms = MACHINE(vms); 1661 ARMCPU *cpu = ARM_CPU(first_cpu); 1662 struct arm_boot_info *info = &vms->bootinfo; 1663 AddressSpace *as = arm_boot_address_space(cpu, info); 1664 1665 /* 1666 * If the user provided a dtb, we assume the dynamic sysbus nodes 1667 * already are integrated there. This corresponds to a use case where 1668 * the dynamic sysbus nodes are complex and their generation is not yet 1669 * supported. In that case the user can take charge of the guest dt 1670 * while qemu takes charge of the qom stuff. 1671 */ 1672 if (info->dtb_filename == NULL) { 1673 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", 1674 vms->memmap[VIRT_PLATFORM_BUS].base, 1675 vms->memmap[VIRT_PLATFORM_BUS].size, 1676 vms->irqmap[VIRT_PLATFORM_BUS]); 1677 } 1678 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1679 exit(1); 1680 } 1681 1682 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg); 1683 1684 virt_acpi_setup(vms); 1685 virt_build_smbios(vms); 1686 } 1687 1688 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1689 { 1690 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1691 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1692 1693 if (!vmc->disallow_affinity_adjustment) { 1694 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1695 * GIC's target-list limitations. 32-bit KVM hosts currently 1696 * always create clusters of 4 CPUs, but that is expected to 1697 * change when they gain support for gicv3. When KVM is enabled 1698 * it will override the changes we make here, therefore our 1699 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1700 * and to improve SGI efficiency. 1701 */ 1702 if (vms->gic_version == VIRT_GIC_VERSION_2) { 1703 clustersz = GIC_TARGETLIST_BITS; 1704 } else { 1705 clustersz = GICV3_TARGETLIST_BITS; 1706 } 1707 } 1708 return arm_cpu_mp_affinity(idx, clustersz); 1709 } 1710 1711 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, 1712 int index) 1713 { 1714 bool *enabled_array[] = { 1715 &vms->highmem_redists, 1716 &vms->highmem_ecam, 1717 &vms->highmem_mmio, 1718 }; 1719 1720 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST == 1721 ARRAY_SIZE(enabled_array)); 1722 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array)); 1723 1724 return enabled_array[index - VIRT_LOWMEMMAP_LAST]; 1725 } 1726 1727 static void virt_set_high_memmap(VirtMachineState *vms, 1728 hwaddr base, int pa_bits) 1729 { 1730 hwaddr region_base, region_size; 1731 bool *region_enabled, fits; 1732 int i; 1733 1734 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1735 region_enabled = virt_get_high_memmap_enabled(vms, i); 1736 region_base = ROUND_UP(base, extended_memmap[i].size); 1737 region_size = extended_memmap[i].size; 1738 1739 vms->memmap[i].base = region_base; 1740 vms->memmap[i].size = region_size; 1741 1742 /* 1743 * Check each device to see if it fits in the PA space, 1744 * moving highest_gpa as we go. For compatibility, move 1745 * highest_gpa for disabled fitting devices as well, if 1746 * the compact layout has been disabled. 1747 * 1748 * For each device that doesn't fit, disable it. 1749 */ 1750 fits = (region_base + region_size) <= BIT_ULL(pa_bits); 1751 *region_enabled &= fits; 1752 if (vms->highmem_compact && !*region_enabled) { 1753 continue; 1754 } 1755 1756 base = region_base + region_size; 1757 if (fits) { 1758 vms->highest_gpa = base - 1; 1759 } 1760 } 1761 } 1762 1763 static void virt_set_memmap(VirtMachineState *vms, int pa_bits) 1764 { 1765 MachineState *ms = MACHINE(vms); 1766 hwaddr base, device_memory_base, device_memory_size, memtop; 1767 int i; 1768 1769 vms->memmap = extended_memmap; 1770 1771 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1772 vms->memmap[i] = base_memmap[i]; 1773 } 1774 1775 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1776 error_report("unsupported number of memory slots: %"PRIu64, 1777 ms->ram_slots); 1778 exit(EXIT_FAILURE); 1779 } 1780 1781 /* 1782 * !highmem is exactly the same as limiting the PA space to 32bit, 1783 * irrespective of the underlying capabilities of the HW. 1784 */ 1785 if (!vms->highmem) { 1786 pa_bits = 32; 1787 } 1788 1789 /* 1790 * We compute the base of the high IO region depending on the 1791 * amount of initial and device memory. The device memory start/size 1792 * is aligned on 1GiB. We never put the high IO region below 256GiB 1793 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1794 * The device region size assumes 1GiB page max alignment per slot. 1795 */ 1796 device_memory_base = 1797 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1798 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1799 1800 /* Base address of the high IO region */ 1801 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1802 if (memtop > BIT_ULL(pa_bits)) { 1803 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n", 1804 pa_bits, memtop - BIT_ULL(pa_bits)); 1805 exit(EXIT_FAILURE); 1806 } 1807 if (base < device_memory_base) { 1808 error_report("maxmem/slots too huge"); 1809 exit(EXIT_FAILURE); 1810 } 1811 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1812 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1813 } 1814 1815 /* We know for sure that at least the memory fits in the PA space */ 1816 vms->highest_gpa = memtop - 1; 1817 1818 virt_set_high_memmap(vms, base, pa_bits); 1819 1820 if (device_memory_size > 0) { 1821 ms->device_memory = g_malloc0(sizeof(*ms->device_memory)); 1822 ms->device_memory->base = device_memory_base; 1823 memory_region_init(&ms->device_memory->mr, OBJECT(vms), 1824 "device-memory", device_memory_size); 1825 } 1826 } 1827 1828 static VirtGICType finalize_gic_version_do(const char *accel_name, 1829 VirtGICType gic_version, 1830 int gics_supported, 1831 unsigned int max_cpus) 1832 { 1833 /* Convert host/max/nosel to GIC version number */ 1834 switch (gic_version) { 1835 case VIRT_GIC_VERSION_HOST: 1836 if (!kvm_enabled()) { 1837 error_report("gic-version=host requires KVM"); 1838 exit(1); 1839 } 1840 1841 /* For KVM, gic-version=host means gic-version=max */ 1842 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX, 1843 gics_supported, max_cpus); 1844 case VIRT_GIC_VERSION_MAX: 1845 if (gics_supported & VIRT_GIC_VERSION_4_MASK) { 1846 gic_version = VIRT_GIC_VERSION_4; 1847 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1848 gic_version = VIRT_GIC_VERSION_3; 1849 } else { 1850 gic_version = VIRT_GIC_VERSION_2; 1851 } 1852 break; 1853 case VIRT_GIC_VERSION_NOSEL: 1854 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) && 1855 max_cpus <= GIC_NCPU) { 1856 gic_version = VIRT_GIC_VERSION_2; 1857 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1858 /* 1859 * in case the host does not support v2 emulation or 1860 * the end-user requested more than 8 VCPUs we now default 1861 * to v3. In any case defaulting to v2 would be broken. 1862 */ 1863 gic_version = VIRT_GIC_VERSION_3; 1864 } else if (max_cpus > GIC_NCPU) { 1865 error_report("%s only supports GICv2 emulation but more than 8 " 1866 "vcpus are requested", accel_name); 1867 exit(1); 1868 } 1869 break; 1870 case VIRT_GIC_VERSION_2: 1871 case VIRT_GIC_VERSION_3: 1872 case VIRT_GIC_VERSION_4: 1873 break; 1874 } 1875 1876 /* Check chosen version is effectively supported */ 1877 switch (gic_version) { 1878 case VIRT_GIC_VERSION_2: 1879 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) { 1880 error_report("%s does not support GICv2 emulation", accel_name); 1881 exit(1); 1882 } 1883 break; 1884 case VIRT_GIC_VERSION_3: 1885 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) { 1886 error_report("%s does not support GICv3 emulation", accel_name); 1887 exit(1); 1888 } 1889 break; 1890 case VIRT_GIC_VERSION_4: 1891 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) { 1892 error_report("%s does not support GICv4 emulation, is virtualization=on?", 1893 accel_name); 1894 exit(1); 1895 } 1896 break; 1897 default: 1898 error_report("logic error in finalize_gic_version"); 1899 exit(1); 1900 break; 1901 } 1902 1903 return gic_version; 1904 } 1905 1906 /* 1907 * finalize_gic_version - Determines the final gic_version 1908 * according to the gic-version property 1909 * 1910 * Default GIC type is v2 1911 */ 1912 static void finalize_gic_version(VirtMachineState *vms) 1913 { 1914 const char *accel_name = current_accel_name(); 1915 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 1916 int gics_supported = 0; 1917 1918 /* Determine which GIC versions the current environment supports */ 1919 if (kvm_enabled() && kvm_irqchip_in_kernel()) { 1920 int probe_bitmap = kvm_arm_vgic_probe(); 1921 1922 if (!probe_bitmap) { 1923 error_report("Unable to determine GIC version supported by host"); 1924 exit(1); 1925 } 1926 1927 if (probe_bitmap & KVM_ARM_VGIC_V2) { 1928 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1929 } 1930 if (probe_bitmap & KVM_ARM_VGIC_V3) { 1931 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1932 } 1933 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) { 1934 /* KVM w/o kernel irqchip can only deal with GICv2 */ 1935 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1936 accel_name = "KVM with kernel-irqchip=off"; 1937 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { 1938 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1939 if (module_object_class_by_name("arm-gicv3")) { 1940 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1941 if (vms->virt) { 1942 /* GICv4 only makes sense if CPU has EL2 */ 1943 gics_supported |= VIRT_GIC_VERSION_4_MASK; 1944 } 1945 } 1946 } else { 1947 error_report("Unsupported accelerator, can not determine GIC support"); 1948 exit(1); 1949 } 1950 1951 /* 1952 * Then convert helpers like host/max to concrete GIC versions and ensure 1953 * the desired version is supported 1954 */ 1955 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version, 1956 gics_supported, max_cpus); 1957 } 1958 1959 /* 1960 * virt_cpu_post_init() must be called after the CPUs have 1961 * been realized and the GIC has been created. 1962 */ 1963 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) 1964 { 1965 int max_cpus = MACHINE(vms)->smp.max_cpus; 1966 bool aarch64, pmu, steal_time; 1967 CPUState *cpu; 1968 1969 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); 1970 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); 1971 steal_time = object_property_get_bool(OBJECT(first_cpu), 1972 "kvm-steal-time", NULL); 1973 1974 if (kvm_enabled()) { 1975 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; 1976 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; 1977 1978 if (steal_time) { 1979 MemoryRegion *pvtime = g_new(MemoryRegion, 1); 1980 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; 1981 1982 /* The memory region size must be a multiple of host page size. */ 1983 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); 1984 1985 if (pvtime_size > pvtime_reg_size) { 1986 error_report("pvtime requires a %" HWADDR_PRId 1987 " byte memory region for %d CPUs," 1988 " but only %" HWADDR_PRId " has been reserved", 1989 pvtime_size, max_cpus, pvtime_reg_size); 1990 exit(1); 1991 } 1992 1993 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); 1994 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); 1995 } 1996 1997 CPU_FOREACH(cpu) { 1998 if (pmu) { 1999 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); 2000 if (kvm_irqchip_in_kernel()) { 2001 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 2002 } 2003 kvm_arm_pmu_init(cpu); 2004 } 2005 if (steal_time) { 2006 kvm_arm_pvtime_init(cpu, pvtime_reg_base + 2007 cpu->cpu_index * PVTIME_SIZE_PER_CPU); 2008 } 2009 } 2010 } else { 2011 if (aarch64 && vms->highmem) { 2012 int requested_pa_size = 64 - clz64(vms->highest_gpa); 2013 int pamax = arm_pamax(ARM_CPU(first_cpu)); 2014 2015 if (pamax < requested_pa_size) { 2016 error_report("VCPU supports less PA bits (%d) than " 2017 "requested by the memory map (%d)", 2018 pamax, requested_pa_size); 2019 exit(1); 2020 } 2021 } 2022 } 2023 } 2024 2025 static void machvirt_init(MachineState *machine) 2026 { 2027 VirtMachineState *vms = VIRT_MACHINE(machine); 2028 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 2029 MachineClass *mc = MACHINE_GET_CLASS(machine); 2030 const CPUArchIdList *possible_cpus; 2031 MemoryRegion *sysmem = get_system_memory(); 2032 MemoryRegion *secure_sysmem = NULL; 2033 MemoryRegion *tag_sysmem = NULL; 2034 MemoryRegion *secure_tag_sysmem = NULL; 2035 int n, virt_max_cpus; 2036 bool firmware_loaded; 2037 bool aarch64 = true; 2038 bool has_ged = !vmc->no_ged; 2039 unsigned int smp_cpus = machine->smp.cpus; 2040 unsigned int max_cpus = machine->smp.max_cpus; 2041 2042 if (!cpu_type_valid(machine->cpu_type)) { 2043 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 2044 exit(1); 2045 } 2046 2047 possible_cpus = mc->possible_cpu_arch_ids(machine); 2048 2049 /* 2050 * In accelerated mode, the memory map is computed earlier in kvm_type() 2051 * to create a VM with the right number of IPA bits. 2052 */ 2053 if (!vms->memmap) { 2054 Object *cpuobj; 2055 ARMCPU *armcpu; 2056 int pa_bits; 2057 2058 /* 2059 * Instantiate a temporary CPU object to find out about what 2060 * we are about to deal with. Once this is done, get rid of 2061 * the object. 2062 */ 2063 cpuobj = object_new(possible_cpus->cpus[0].type); 2064 armcpu = ARM_CPU(cpuobj); 2065 2066 pa_bits = arm_pamax(armcpu); 2067 2068 object_unref(cpuobj); 2069 2070 virt_set_memmap(vms, pa_bits); 2071 } 2072 2073 /* We can probe only here because during property set 2074 * KVM is not available yet 2075 */ 2076 finalize_gic_version(vms); 2077 2078 if (vms->secure) { 2079 /* 2080 * The Secure view of the world is the same as the NonSecure, 2081 * but with a few extra devices. Create it as a container region 2082 * containing the system memory at low priority; any secure-only 2083 * devices go in at higher priority and take precedence. 2084 */ 2085 secure_sysmem = g_new(MemoryRegion, 1); 2086 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 2087 UINT64_MAX); 2088 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 2089 } 2090 2091 firmware_loaded = virt_firmware_init(vms, sysmem, 2092 secure_sysmem ?: sysmem); 2093 2094 /* If we have an EL3 boot ROM then the assumption is that it will 2095 * implement PSCI itself, so disable QEMU's internal implementation 2096 * so it doesn't get in the way. Instead of starting secondary 2097 * CPUs in PSCI powerdown state we will start them all running and 2098 * let the boot ROM sort them out. 2099 * The usual case is that we do use QEMU's PSCI implementation; 2100 * if the guest has EL2 then we will use SMC as the conduit, 2101 * and otherwise we will use HVC (for backwards compatibility and 2102 * because if we're using KVM then we must use HVC). 2103 */ 2104 if (vms->secure && firmware_loaded) { 2105 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 2106 } else if (vms->virt) { 2107 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 2108 } else { 2109 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 2110 } 2111 2112 /* 2113 * The maximum number of CPUs depends on the GIC version, or on how 2114 * many redistributors we can fit into the memory map (which in turn 2115 * depends on whether this is a GICv3 or v4). 2116 */ 2117 if (vms->gic_version == VIRT_GIC_VERSION_2) { 2118 virt_max_cpus = GIC_NCPU; 2119 } else { 2120 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST); 2121 if (vms->highmem_redists) { 2122 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 2123 } 2124 } 2125 2126 if (max_cpus > virt_max_cpus) { 2127 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 2128 "supported by machine 'mach-virt' (%d)", 2129 max_cpus, virt_max_cpus); 2130 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) { 2131 error_printf("Try 'highmem-redists=on' for more CPUs\n"); 2132 } 2133 2134 exit(1); 2135 } 2136 2137 if (vms->secure && (kvm_enabled() || hvf_enabled())) { 2138 error_report("mach-virt: %s does not support providing " 2139 "Security extensions (TrustZone) to the guest CPU", 2140 current_accel_name()); 2141 exit(1); 2142 } 2143 2144 if (vms->virt && (kvm_enabled() || hvf_enabled())) { 2145 error_report("mach-virt: %s does not support providing " 2146 "Virtualization extensions to the guest CPU", 2147 current_accel_name()); 2148 exit(1); 2149 } 2150 2151 if (vms->mte && (kvm_enabled() || hvf_enabled())) { 2152 error_report("mach-virt: %s does not support providing " 2153 "MTE to the guest CPU", 2154 current_accel_name()); 2155 exit(1); 2156 } 2157 2158 create_fdt(vms); 2159 2160 assert(possible_cpus->len == max_cpus); 2161 for (n = 0; n < possible_cpus->len; n++) { 2162 Object *cpuobj; 2163 CPUState *cs; 2164 2165 if (n >= smp_cpus) { 2166 break; 2167 } 2168 2169 cpuobj = object_new(possible_cpus->cpus[n].type); 2170 object_property_set_int(cpuobj, "mp-affinity", 2171 possible_cpus->cpus[n].arch_id, NULL); 2172 2173 cs = CPU(cpuobj); 2174 cs->cpu_index = n; 2175 2176 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 2177 &error_fatal); 2178 2179 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 2180 2181 if (!vms->secure) { 2182 object_property_set_bool(cpuobj, "has_el3", false, NULL); 2183 } 2184 2185 if (!vms->virt && object_property_find(cpuobj, "has_el2")) { 2186 object_property_set_bool(cpuobj, "has_el2", false, NULL); 2187 } 2188 2189 if (vmc->kvm_no_adjvtime && 2190 object_property_find(cpuobj, "kvm-no-adjvtime")) { 2191 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 2192 } 2193 2194 if (vmc->no_kvm_steal_time && 2195 object_property_find(cpuobj, "kvm-steal-time")) { 2196 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); 2197 } 2198 2199 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { 2200 object_property_set_bool(cpuobj, "pmu", false, NULL); 2201 } 2202 2203 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { 2204 object_property_set_bool(cpuobj, "lpa2", false, NULL); 2205 } 2206 2207 if (object_property_find(cpuobj, "reset-cbar")) { 2208 object_property_set_int(cpuobj, "reset-cbar", 2209 vms->memmap[VIRT_CPUPERIPHS].base, 2210 &error_abort); 2211 } 2212 2213 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 2214 &error_abort); 2215 if (vms->secure) { 2216 object_property_set_link(cpuobj, "secure-memory", 2217 OBJECT(secure_sysmem), &error_abort); 2218 } 2219 2220 if (vms->mte) { 2221 /* Create the memory region only once, but link to all cpus. */ 2222 if (!tag_sysmem) { 2223 /* 2224 * The property exists only if MemTag is supported. 2225 * If it is, we must allocate the ram to back that up. 2226 */ 2227 if (!object_property_find(cpuobj, "tag-memory")) { 2228 error_report("MTE requested, but not supported " 2229 "by the guest CPU"); 2230 exit(1); 2231 } 2232 2233 tag_sysmem = g_new(MemoryRegion, 1); 2234 memory_region_init(tag_sysmem, OBJECT(machine), 2235 "tag-memory", UINT64_MAX / 32); 2236 2237 if (vms->secure) { 2238 secure_tag_sysmem = g_new(MemoryRegion, 1); 2239 memory_region_init(secure_tag_sysmem, OBJECT(machine), 2240 "secure-tag-memory", UINT64_MAX / 32); 2241 2242 /* As with ram, secure-tag takes precedence over tag. */ 2243 memory_region_add_subregion_overlap(secure_tag_sysmem, 0, 2244 tag_sysmem, -1); 2245 } 2246 } 2247 2248 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem), 2249 &error_abort); 2250 if (vms->secure) { 2251 object_property_set_link(cpuobj, "secure-tag-memory", 2252 OBJECT(secure_tag_sysmem), 2253 &error_abort); 2254 } 2255 } 2256 2257 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 2258 object_unref(cpuobj); 2259 } 2260 fdt_add_timer_nodes(vms); 2261 fdt_add_cpu_nodes(vms); 2262 2263 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 2264 machine->ram); 2265 if (machine->device_memory) { 2266 memory_region_add_subregion(sysmem, machine->device_memory->base, 2267 &machine->device_memory->mr); 2268 } 2269 2270 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 2271 2272 create_gic(vms, sysmem); 2273 2274 virt_cpu_post_init(vms, sysmem); 2275 2276 fdt_add_pmu_nodes(vms); 2277 2278 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 2279 2280 if (vms->secure) { 2281 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); 2282 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 2283 } 2284 2285 if (tag_sysmem) { 2286 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, 2287 machine->ram_size, "mach-virt.tag"); 2288 } 2289 2290 vms->highmem_ecam &= (!firmware_loaded || aarch64); 2291 2292 create_rtc(vms); 2293 2294 create_pcie(vms); 2295 2296 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 2297 vms->acpi_dev = create_acpi_ged(vms); 2298 } else { 2299 create_gpio_devices(vms, VIRT_GPIO, sysmem); 2300 } 2301 2302 if (vms->secure && !vmc->no_secure_gpio) { 2303 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); 2304 } 2305 2306 /* connect powerdown request */ 2307 vms->powerdown_notifier.notify = virt_powerdown_req; 2308 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 2309 2310 /* Create mmio transports, so the user can create virtio backends 2311 * (which will be automatically plugged in to the transports). If 2312 * no backend is created the transport will just sit harmlessly idle. 2313 */ 2314 create_virtio_devices(vms); 2315 2316 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 2317 rom_set_fw(vms->fw_cfg); 2318 2319 create_platform_bus(vms); 2320 2321 if (machine->nvdimms_state->is_enabled) { 2322 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 2323 .space_id = AML_AS_SYSTEM_MEMORY, 2324 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 2325 .bit_width = NVDIMM_ACPI_IO_LEN << 3 2326 }; 2327 2328 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 2329 arm_virt_nvdimm_acpi_dsmio, 2330 vms->fw_cfg, OBJECT(vms)); 2331 } 2332 2333 vms->bootinfo.ram_size = machine->ram_size; 2334 vms->bootinfo.board_id = -1; 2335 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 2336 vms->bootinfo.get_dtb = machvirt_dtb; 2337 vms->bootinfo.skip_dtb_autoload = true; 2338 vms->bootinfo.firmware_loaded = firmware_loaded; 2339 vms->bootinfo.psci_conduit = vms->psci_conduit; 2340 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 2341 2342 vms->machine_done.notify = virt_machine_done; 2343 qemu_add_machine_init_done_notifier(&vms->machine_done); 2344 } 2345 2346 static bool virt_get_secure(Object *obj, Error **errp) 2347 { 2348 VirtMachineState *vms = VIRT_MACHINE(obj); 2349 2350 return vms->secure; 2351 } 2352 2353 static void virt_set_secure(Object *obj, bool value, Error **errp) 2354 { 2355 VirtMachineState *vms = VIRT_MACHINE(obj); 2356 2357 vms->secure = value; 2358 } 2359 2360 static bool virt_get_virt(Object *obj, Error **errp) 2361 { 2362 VirtMachineState *vms = VIRT_MACHINE(obj); 2363 2364 return vms->virt; 2365 } 2366 2367 static void virt_set_virt(Object *obj, bool value, Error **errp) 2368 { 2369 VirtMachineState *vms = VIRT_MACHINE(obj); 2370 2371 vms->virt = value; 2372 } 2373 2374 static bool virt_get_highmem(Object *obj, Error **errp) 2375 { 2376 VirtMachineState *vms = VIRT_MACHINE(obj); 2377 2378 return vms->highmem; 2379 } 2380 2381 static void virt_set_highmem(Object *obj, bool value, Error **errp) 2382 { 2383 VirtMachineState *vms = VIRT_MACHINE(obj); 2384 2385 vms->highmem = value; 2386 } 2387 2388 static bool virt_get_compact_highmem(Object *obj, Error **errp) 2389 { 2390 VirtMachineState *vms = VIRT_MACHINE(obj); 2391 2392 return vms->highmem_compact; 2393 } 2394 2395 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp) 2396 { 2397 VirtMachineState *vms = VIRT_MACHINE(obj); 2398 2399 vms->highmem_compact = value; 2400 } 2401 2402 static bool virt_get_highmem_redists(Object *obj, Error **errp) 2403 { 2404 VirtMachineState *vms = VIRT_MACHINE(obj); 2405 2406 return vms->highmem_redists; 2407 } 2408 2409 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp) 2410 { 2411 VirtMachineState *vms = VIRT_MACHINE(obj); 2412 2413 vms->highmem_redists = value; 2414 } 2415 2416 static bool virt_get_highmem_ecam(Object *obj, Error **errp) 2417 { 2418 VirtMachineState *vms = VIRT_MACHINE(obj); 2419 2420 return vms->highmem_ecam; 2421 } 2422 2423 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp) 2424 { 2425 VirtMachineState *vms = VIRT_MACHINE(obj); 2426 2427 vms->highmem_ecam = value; 2428 } 2429 2430 static bool virt_get_highmem_mmio(Object *obj, Error **errp) 2431 { 2432 VirtMachineState *vms = VIRT_MACHINE(obj); 2433 2434 return vms->highmem_mmio; 2435 } 2436 2437 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp) 2438 { 2439 VirtMachineState *vms = VIRT_MACHINE(obj); 2440 2441 vms->highmem_mmio = value; 2442 } 2443 2444 2445 static bool virt_get_its(Object *obj, Error **errp) 2446 { 2447 VirtMachineState *vms = VIRT_MACHINE(obj); 2448 2449 return vms->its; 2450 } 2451 2452 static void virt_set_its(Object *obj, bool value, Error **errp) 2453 { 2454 VirtMachineState *vms = VIRT_MACHINE(obj); 2455 2456 vms->its = value; 2457 } 2458 2459 static bool virt_get_dtb_randomness(Object *obj, Error **errp) 2460 { 2461 VirtMachineState *vms = VIRT_MACHINE(obj); 2462 2463 return vms->dtb_randomness; 2464 } 2465 2466 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp) 2467 { 2468 VirtMachineState *vms = VIRT_MACHINE(obj); 2469 2470 vms->dtb_randomness = value; 2471 } 2472 2473 static char *virt_get_oem_id(Object *obj, Error **errp) 2474 { 2475 VirtMachineState *vms = VIRT_MACHINE(obj); 2476 2477 return g_strdup(vms->oem_id); 2478 } 2479 2480 static void virt_set_oem_id(Object *obj, const char *value, Error **errp) 2481 { 2482 VirtMachineState *vms = VIRT_MACHINE(obj); 2483 size_t len = strlen(value); 2484 2485 if (len > 6) { 2486 error_setg(errp, 2487 "User specified oem-id value is bigger than 6 bytes in size"); 2488 return; 2489 } 2490 2491 strncpy(vms->oem_id, value, 6); 2492 } 2493 2494 static char *virt_get_oem_table_id(Object *obj, Error **errp) 2495 { 2496 VirtMachineState *vms = VIRT_MACHINE(obj); 2497 2498 return g_strdup(vms->oem_table_id); 2499 } 2500 2501 static void virt_set_oem_table_id(Object *obj, const char *value, 2502 Error **errp) 2503 { 2504 VirtMachineState *vms = VIRT_MACHINE(obj); 2505 size_t len = strlen(value); 2506 2507 if (len > 8) { 2508 error_setg(errp, 2509 "User specified oem-table-id value is bigger than 8 bytes in size"); 2510 return; 2511 } 2512 strncpy(vms->oem_table_id, value, 8); 2513 } 2514 2515 2516 bool virt_is_acpi_enabled(VirtMachineState *vms) 2517 { 2518 if (vms->acpi == ON_OFF_AUTO_OFF) { 2519 return false; 2520 } 2521 return true; 2522 } 2523 2524 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 2525 void *opaque, Error **errp) 2526 { 2527 VirtMachineState *vms = VIRT_MACHINE(obj); 2528 OnOffAuto acpi = vms->acpi; 2529 2530 visit_type_OnOffAuto(v, name, &acpi, errp); 2531 } 2532 2533 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 2534 void *opaque, Error **errp) 2535 { 2536 VirtMachineState *vms = VIRT_MACHINE(obj); 2537 2538 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 2539 } 2540 2541 static bool virt_get_ras(Object *obj, Error **errp) 2542 { 2543 VirtMachineState *vms = VIRT_MACHINE(obj); 2544 2545 return vms->ras; 2546 } 2547 2548 static void virt_set_ras(Object *obj, bool value, Error **errp) 2549 { 2550 VirtMachineState *vms = VIRT_MACHINE(obj); 2551 2552 vms->ras = value; 2553 } 2554 2555 static bool virt_get_mte(Object *obj, Error **errp) 2556 { 2557 VirtMachineState *vms = VIRT_MACHINE(obj); 2558 2559 return vms->mte; 2560 } 2561 2562 static void virt_set_mte(Object *obj, bool value, Error **errp) 2563 { 2564 VirtMachineState *vms = VIRT_MACHINE(obj); 2565 2566 vms->mte = value; 2567 } 2568 2569 static char *virt_get_gic_version(Object *obj, Error **errp) 2570 { 2571 VirtMachineState *vms = VIRT_MACHINE(obj); 2572 const char *val; 2573 2574 switch (vms->gic_version) { 2575 case VIRT_GIC_VERSION_4: 2576 val = "4"; 2577 break; 2578 case VIRT_GIC_VERSION_3: 2579 val = "3"; 2580 break; 2581 default: 2582 val = "2"; 2583 break; 2584 } 2585 return g_strdup(val); 2586 } 2587 2588 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2589 { 2590 VirtMachineState *vms = VIRT_MACHINE(obj); 2591 2592 if (!strcmp(value, "4")) { 2593 vms->gic_version = VIRT_GIC_VERSION_4; 2594 } else if (!strcmp(value, "3")) { 2595 vms->gic_version = VIRT_GIC_VERSION_3; 2596 } else if (!strcmp(value, "2")) { 2597 vms->gic_version = VIRT_GIC_VERSION_2; 2598 } else if (!strcmp(value, "host")) { 2599 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2600 } else if (!strcmp(value, "max")) { 2601 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2602 } else { 2603 error_setg(errp, "Invalid gic-version value"); 2604 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2605 } 2606 } 2607 2608 static char *virt_get_iommu(Object *obj, Error **errp) 2609 { 2610 VirtMachineState *vms = VIRT_MACHINE(obj); 2611 2612 switch (vms->iommu) { 2613 case VIRT_IOMMU_NONE: 2614 return g_strdup("none"); 2615 case VIRT_IOMMU_SMMUV3: 2616 return g_strdup("smmuv3"); 2617 default: 2618 g_assert_not_reached(); 2619 } 2620 } 2621 2622 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2623 { 2624 VirtMachineState *vms = VIRT_MACHINE(obj); 2625 2626 if (!strcmp(value, "smmuv3")) { 2627 vms->iommu = VIRT_IOMMU_SMMUV3; 2628 } else if (!strcmp(value, "none")) { 2629 vms->iommu = VIRT_IOMMU_NONE; 2630 } else { 2631 error_setg(errp, "Invalid iommu value"); 2632 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2633 } 2634 } 2635 2636 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp) 2637 { 2638 VirtMachineState *vms = VIRT_MACHINE(obj); 2639 2640 return vms->default_bus_bypass_iommu; 2641 } 2642 2643 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value, 2644 Error **errp) 2645 { 2646 VirtMachineState *vms = VIRT_MACHINE(obj); 2647 2648 vms->default_bus_bypass_iommu = value; 2649 } 2650 2651 static CpuInstanceProperties 2652 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2653 { 2654 MachineClass *mc = MACHINE_GET_CLASS(ms); 2655 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2656 2657 assert(cpu_index < possible_cpus->len); 2658 return possible_cpus->cpus[cpu_index].props; 2659 } 2660 2661 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2662 { 2663 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 2664 2665 return socket_id % ms->numa_state->num_nodes; 2666 } 2667 2668 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2669 { 2670 int n; 2671 unsigned int max_cpus = ms->smp.max_cpus; 2672 VirtMachineState *vms = VIRT_MACHINE(ms); 2673 MachineClass *mc = MACHINE_GET_CLASS(vms); 2674 2675 if (ms->possible_cpus) { 2676 assert(ms->possible_cpus->len == max_cpus); 2677 return ms->possible_cpus; 2678 } 2679 2680 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2681 sizeof(CPUArchId) * max_cpus); 2682 ms->possible_cpus->len = max_cpus; 2683 for (n = 0; n < ms->possible_cpus->len; n++) { 2684 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2685 ms->possible_cpus->cpus[n].arch_id = 2686 virt_cpu_mp_affinity(vms, n); 2687 2688 assert(!mc->smp_props.dies_supported); 2689 ms->possible_cpus->cpus[n].props.has_socket_id = true; 2690 ms->possible_cpus->cpus[n].props.socket_id = 2691 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); 2692 ms->possible_cpus->cpus[n].props.has_cluster_id = true; 2693 ms->possible_cpus->cpus[n].props.cluster_id = 2694 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; 2695 ms->possible_cpus->cpus[n].props.has_core_id = true; 2696 ms->possible_cpus->cpus[n].props.core_id = 2697 (n / ms->smp.threads) % ms->smp.cores; 2698 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2699 ms->possible_cpus->cpus[n].props.thread_id = 2700 n % ms->smp.threads; 2701 } 2702 return ms->possible_cpus; 2703 } 2704 2705 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2706 Error **errp) 2707 { 2708 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2709 const MachineState *ms = MACHINE(hotplug_dev); 2710 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2711 2712 if (!vms->acpi_dev) { 2713 error_setg(errp, 2714 "memory hotplug is not enabled: missing acpi-ged device"); 2715 return; 2716 } 2717 2718 if (vms->mte) { 2719 error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); 2720 return; 2721 } 2722 2723 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2724 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2725 return; 2726 } 2727 2728 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 2729 } 2730 2731 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2732 DeviceState *dev, Error **errp) 2733 { 2734 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2735 MachineState *ms = MACHINE(hotplug_dev); 2736 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2737 2738 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); 2739 2740 if (is_nvdimm) { 2741 nvdimm_plug(ms->nvdimms_state); 2742 } 2743 2744 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2745 dev, &error_abort); 2746 } 2747 2748 static void virt_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 2749 DeviceState *dev, Error **errp) 2750 { 2751 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2752 Error *local_err = NULL; 2753 2754 if (!hotplug_dev2 && dev->hotplugged) { 2755 /* 2756 * Without a bus hotplug handler, we cannot control the plug/unplug 2757 * order. We should never reach this point when hotplugging on ARM. 2758 * However, it's nice to add a safety net, similar to what we have 2759 * on x86. 2760 */ 2761 error_setg(errp, "hotplug of virtio based memory devices not supported" 2762 " on this bus."); 2763 return; 2764 } 2765 /* 2766 * First, see if we can plug this memory device at all. If that 2767 * succeeds, branch of to the actual hotplug handler. 2768 */ 2769 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 2770 &local_err); 2771 if (!local_err && hotplug_dev2) { 2772 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 2773 } 2774 error_propagate(errp, local_err); 2775 } 2776 2777 static void virt_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 2778 DeviceState *dev, Error **errp) 2779 { 2780 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2781 Error *local_err = NULL; 2782 2783 /* 2784 * Plug the memory device first and then branch off to the actual 2785 * hotplug handler. If that one fails, we can easily undo the memory 2786 * device bits. 2787 */ 2788 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2789 if (hotplug_dev2) { 2790 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 2791 if (local_err) { 2792 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2793 } 2794 } 2795 error_propagate(errp, local_err); 2796 } 2797 2798 static void virt_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 2799 DeviceState *dev, Error **errp) 2800 { 2801 /* We don't support hot unplug of virtio based memory devices */ 2802 error_setg(errp, "virtio based memory devices cannot be unplugged."); 2803 } 2804 2805 2806 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2807 DeviceState *dev, Error **errp) 2808 { 2809 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2810 2811 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2812 virt_memory_pre_plug(hotplug_dev, dev, errp); 2813 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2814 virt_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 2815 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2816 hwaddr db_start = 0, db_end = 0; 2817 char *resv_prop_str; 2818 2819 if (vms->iommu != VIRT_IOMMU_NONE) { 2820 error_setg(errp, "virt machine does not support multiple IOMMUs"); 2821 return; 2822 } 2823 2824 switch (vms->msi_controller) { 2825 case VIRT_MSI_CTRL_NONE: 2826 return; 2827 case VIRT_MSI_CTRL_ITS: 2828 /* GITS_TRANSLATER page */ 2829 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; 2830 db_end = base_memmap[VIRT_GIC_ITS].base + 2831 base_memmap[VIRT_GIC_ITS].size - 1; 2832 break; 2833 case VIRT_MSI_CTRL_GICV2M: 2834 /* MSI_SETSPI_NS page */ 2835 db_start = base_memmap[VIRT_GIC_V2M].base; 2836 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; 2837 break; 2838 } 2839 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", 2840 db_start, db_end, 2841 VIRTIO_IOMMU_RESV_MEM_T_MSI); 2842 2843 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 2844 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 2845 resv_prop_str, errp); 2846 g_free(resv_prop_str); 2847 } 2848 } 2849 2850 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2851 DeviceState *dev, Error **errp) 2852 { 2853 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2854 2855 if (vms->platform_bus_dev) { 2856 MachineClass *mc = MACHINE_GET_CLASS(vms); 2857 2858 if (device_is_dynamic_sysbus(mc, dev)) { 2859 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2860 SYS_BUS_DEVICE(dev)); 2861 } 2862 } 2863 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2864 virt_memory_plug(hotplug_dev, dev, errp); 2865 } 2866 2867 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2868 virt_virtio_md_pci_plug(hotplug_dev, dev, errp); 2869 } 2870 2871 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2872 PCIDevice *pdev = PCI_DEVICE(dev); 2873 2874 vms->iommu = VIRT_IOMMU_VIRTIO; 2875 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2876 create_virtio_iommu_dt_bindings(vms); 2877 } 2878 } 2879 2880 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, 2881 DeviceState *dev, Error **errp) 2882 { 2883 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2884 2885 if (!vms->acpi_dev) { 2886 error_setg(errp, 2887 "memory hotplug is not enabled: missing acpi-ged device"); 2888 return; 2889 } 2890 2891 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2892 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 2893 return; 2894 } 2895 2896 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, 2897 errp); 2898 } 2899 2900 static void virt_dimm_unplug(HotplugHandler *hotplug_dev, 2901 DeviceState *dev, Error **errp) 2902 { 2903 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2904 Error *local_err = NULL; 2905 2906 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); 2907 if (local_err) { 2908 goto out; 2909 } 2910 2911 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); 2912 qdev_unrealize(dev); 2913 2914 out: 2915 error_propagate(errp, local_err); 2916 } 2917 2918 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2919 DeviceState *dev, Error **errp) 2920 { 2921 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2922 virt_dimm_unplug_request(hotplug_dev, dev, errp); 2923 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 2924 virt_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 2925 } else { 2926 error_setg(errp, "device unplug request for unsupported device" 2927 " type: %s", object_get_typename(OBJECT(dev))); 2928 } 2929 } 2930 2931 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2932 DeviceState *dev, Error **errp) 2933 { 2934 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2935 virt_dimm_unplug(hotplug_dev, dev, errp); 2936 } else { 2937 error_setg(errp, "virt: device unplug for unsupported device" 2938 " type: %s", object_get_typename(OBJECT(dev))); 2939 } 2940 } 2941 2942 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2943 DeviceState *dev) 2944 { 2945 MachineClass *mc = MACHINE_GET_CLASS(machine); 2946 2947 if (device_is_dynamic_sysbus(mc, dev) || 2948 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2949 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 2950 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2951 return HOTPLUG_HANDLER(machine); 2952 } 2953 return NULL; 2954 } 2955 2956 /* 2957 * for arm64 kvm_type [7-0] encodes the requested number of bits 2958 * in the IPA address space 2959 */ 2960 static int virt_kvm_type(MachineState *ms, const char *type_str) 2961 { 2962 VirtMachineState *vms = VIRT_MACHINE(ms); 2963 int max_vm_pa_size, requested_pa_size; 2964 bool fixed_ipa; 2965 2966 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 2967 2968 /* we freeze the memory map to compute the highest gpa */ 2969 virt_set_memmap(vms, max_vm_pa_size); 2970 2971 requested_pa_size = 64 - clz64(vms->highest_gpa); 2972 2973 /* 2974 * KVM requires the IPA size to be at least 32 bits. 2975 */ 2976 if (requested_pa_size < 32) { 2977 requested_pa_size = 32; 2978 } 2979 2980 if (requested_pa_size > max_vm_pa_size) { 2981 error_report("-m and ,maxmem option values " 2982 "require an IPA range (%d bits) larger than " 2983 "the one supported by the host (%d bits)", 2984 requested_pa_size, max_vm_pa_size); 2985 exit(1); 2986 } 2987 /* 2988 * We return the requested PA log size, unless KVM only supports 2989 * the implicit legacy 40b IPA setting, in which case the kvm_type 2990 * must be 0. 2991 */ 2992 return fixed_ipa ? 0 : requested_pa_size; 2993 } 2994 2995 static void virt_machine_class_init(ObjectClass *oc, void *data) 2996 { 2997 MachineClass *mc = MACHINE_CLASS(oc); 2998 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2999 3000 mc->init = machvirt_init; 3001 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 3002 * The value may be reduced later when we have more information about the 3003 * configuration of the particular instance. 3004 */ 3005 mc->max_cpus = 512; 3006 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 3007 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 3008 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 3009 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 3010 #ifdef CONFIG_TPM 3011 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 3012 #endif 3013 mc->block_default_type = IF_VIRTIO; 3014 mc->no_cdrom = 1; 3015 mc->pci_allow_0_address = true; 3016 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 3017 mc->minimum_page_bits = 12; 3018 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 3019 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 3020 #ifdef CONFIG_TCG 3021 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 3022 #else 3023 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); 3024 #endif 3025 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 3026 mc->kvm_type = virt_kvm_type; 3027 assert(!mc->get_hotplug_handler); 3028 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 3029 hc->pre_plug = virt_machine_device_pre_plug_cb; 3030 hc->plug = virt_machine_device_plug_cb; 3031 hc->unplug_request = virt_machine_device_unplug_request_cb; 3032 hc->unplug = virt_machine_device_unplug_cb; 3033 mc->nvdimm_supported = true; 3034 mc->smp_props.clusters_supported = true; 3035 mc->auto_enable_numa_with_memhp = true; 3036 mc->auto_enable_numa_with_memdev = true; 3037 /* platform instead of architectural choice */ 3038 mc->cpu_cluster_has_numa_boundary = true; 3039 mc->default_ram_id = "mach-virt.ram"; 3040 mc->default_nic = "virtio-net-pci"; 3041 3042 object_class_property_add(oc, "acpi", "OnOffAuto", 3043 virt_get_acpi, virt_set_acpi, 3044 NULL, NULL); 3045 object_class_property_set_description(oc, "acpi", 3046 "Enable ACPI"); 3047 object_class_property_add_bool(oc, "secure", virt_get_secure, 3048 virt_set_secure); 3049 object_class_property_set_description(oc, "secure", 3050 "Set on/off to enable/disable the ARM " 3051 "Security Extensions (TrustZone)"); 3052 3053 object_class_property_add_bool(oc, "virtualization", virt_get_virt, 3054 virt_set_virt); 3055 object_class_property_set_description(oc, "virtualization", 3056 "Set on/off to enable/disable emulating a " 3057 "guest CPU which implements the ARM " 3058 "Virtualization Extensions"); 3059 3060 object_class_property_add_bool(oc, "highmem", virt_get_highmem, 3061 virt_set_highmem); 3062 object_class_property_set_description(oc, "highmem", 3063 "Set on/off to enable/disable using " 3064 "physical address space above 32 bits"); 3065 3066 object_class_property_add_bool(oc, "compact-highmem", 3067 virt_get_compact_highmem, 3068 virt_set_compact_highmem); 3069 object_class_property_set_description(oc, "compact-highmem", 3070 "Set on/off to enable/disable compact " 3071 "layout for high memory regions"); 3072 3073 object_class_property_add_bool(oc, "highmem-redists", 3074 virt_get_highmem_redists, 3075 virt_set_highmem_redists); 3076 object_class_property_set_description(oc, "highmem-redists", 3077 "Set on/off to enable/disable high " 3078 "memory region for GICv3 or GICv4 " 3079 "redistributor"); 3080 3081 object_class_property_add_bool(oc, "highmem-ecam", 3082 virt_get_highmem_ecam, 3083 virt_set_highmem_ecam); 3084 object_class_property_set_description(oc, "highmem-ecam", 3085 "Set on/off to enable/disable high " 3086 "memory region for PCI ECAM"); 3087 3088 object_class_property_add_bool(oc, "highmem-mmio", 3089 virt_get_highmem_mmio, 3090 virt_set_highmem_mmio); 3091 object_class_property_set_description(oc, "highmem-mmio", 3092 "Set on/off to enable/disable high " 3093 "memory region for PCI MMIO"); 3094 3095 object_class_property_add_str(oc, "gic-version", virt_get_gic_version, 3096 virt_set_gic_version); 3097 object_class_property_set_description(oc, "gic-version", 3098 "Set GIC version. " 3099 "Valid values are 2, 3, 4, host and max"); 3100 3101 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); 3102 object_class_property_set_description(oc, "iommu", 3103 "Set the IOMMU type. " 3104 "Valid values are none and smmuv3"); 3105 3106 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 3107 virt_get_default_bus_bypass_iommu, 3108 virt_set_default_bus_bypass_iommu); 3109 object_class_property_set_description(oc, "default-bus-bypass-iommu", 3110 "Set on/off to enable/disable " 3111 "bypass_iommu for default root bus"); 3112 3113 object_class_property_add_bool(oc, "ras", virt_get_ras, 3114 virt_set_ras); 3115 object_class_property_set_description(oc, "ras", 3116 "Set on/off to enable/disable reporting host memory errors " 3117 "to a KVM guest using ACPI and guest external abort exceptions"); 3118 3119 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); 3120 object_class_property_set_description(oc, "mte", 3121 "Set on/off to enable/disable emulating a " 3122 "guest CPU which implements the ARM " 3123 "Memory Tagging Extension"); 3124 3125 object_class_property_add_bool(oc, "its", virt_get_its, 3126 virt_set_its); 3127 object_class_property_set_description(oc, "its", 3128 "Set on/off to enable/disable " 3129 "ITS instantiation"); 3130 3131 object_class_property_add_bool(oc, "dtb-randomness", 3132 virt_get_dtb_randomness, 3133 virt_set_dtb_randomness); 3134 object_class_property_set_description(oc, "dtb-randomness", 3135 "Set off to disable passing random or " 3136 "non-deterministic dtb nodes to guest"); 3137 3138 object_class_property_add_bool(oc, "dtb-kaslr-seed", 3139 virt_get_dtb_randomness, 3140 virt_set_dtb_randomness); 3141 object_class_property_set_description(oc, "dtb-kaslr-seed", 3142 "Deprecated synonym of dtb-randomness"); 3143 3144 object_class_property_add_str(oc, "x-oem-id", 3145 virt_get_oem_id, 3146 virt_set_oem_id); 3147 object_class_property_set_description(oc, "x-oem-id", 3148 "Override the default value of field OEMID " 3149 "in ACPI table header." 3150 "The string may be up to 6 bytes in size"); 3151 3152 3153 object_class_property_add_str(oc, "x-oem-table-id", 3154 virt_get_oem_table_id, 3155 virt_set_oem_table_id); 3156 object_class_property_set_description(oc, "x-oem-table-id", 3157 "Override the default value of field OEM Table ID " 3158 "in ACPI table header." 3159 "The string may be up to 8 bytes in size"); 3160 3161 } 3162 3163 static void virt_instance_init(Object *obj) 3164 { 3165 VirtMachineState *vms = VIRT_MACHINE(obj); 3166 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 3167 3168 /* EL3 is disabled by default on virt: this makes us consistent 3169 * between KVM and TCG for this board, and it also allows us to 3170 * boot UEFI blobs which assume no TrustZone support. 3171 */ 3172 vms->secure = false; 3173 3174 /* EL2 is also disabled by default, for similar reasons */ 3175 vms->virt = false; 3176 3177 /* High memory is enabled by default */ 3178 vms->highmem = true; 3179 vms->highmem_compact = !vmc->no_highmem_compact; 3180 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 3181 3182 vms->highmem_ecam = !vmc->no_highmem_ecam; 3183 vms->highmem_mmio = true; 3184 vms->highmem_redists = true; 3185 3186 if (vmc->no_its) { 3187 vms->its = false; 3188 } else { 3189 /* Default allows ITS instantiation */ 3190 vms->its = true; 3191 3192 if (vmc->no_tcg_its) { 3193 vms->tcg_its = false; 3194 } else { 3195 vms->tcg_its = true; 3196 } 3197 } 3198 3199 /* Default disallows iommu instantiation */ 3200 vms->iommu = VIRT_IOMMU_NONE; 3201 3202 /* The default root bus is attached to iommu by default */ 3203 vms->default_bus_bypass_iommu = false; 3204 3205 /* Default disallows RAS instantiation */ 3206 vms->ras = false; 3207 3208 /* MTE is disabled by default. */ 3209 vms->mte = false; 3210 3211 /* Supply kaslr-seed and rng-seed by default */ 3212 vms->dtb_randomness = true; 3213 3214 vms->irqmap = a15irqmap; 3215 3216 virt_flash_create(vms); 3217 3218 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 3219 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 3220 } 3221 3222 static const TypeInfo virt_machine_info = { 3223 .name = TYPE_VIRT_MACHINE, 3224 .parent = TYPE_MACHINE, 3225 .abstract = true, 3226 .instance_size = sizeof(VirtMachineState), 3227 .class_size = sizeof(VirtMachineClass), 3228 .class_init = virt_machine_class_init, 3229 .instance_init = virt_instance_init, 3230 .interfaces = (InterfaceInfo[]) { 3231 { TYPE_HOTPLUG_HANDLER }, 3232 { } 3233 }, 3234 }; 3235 3236 static void machvirt_machine_init(void) 3237 { 3238 type_register_static(&virt_machine_info); 3239 } 3240 type_init(machvirt_machine_init); 3241 3242 static void virt_machine_8_1_options(MachineClass *mc) 3243 { 3244 } 3245 DEFINE_VIRT_MACHINE_AS_LATEST(8, 1) 3246 3247 static void virt_machine_8_0_options(MachineClass *mc) 3248 { 3249 virt_machine_8_1_options(mc); 3250 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 3251 } 3252 DEFINE_VIRT_MACHINE(8, 0) 3253 3254 static void virt_machine_7_2_options(MachineClass *mc) 3255 { 3256 virt_machine_8_0_options(mc); 3257 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 3258 } 3259 DEFINE_VIRT_MACHINE(7, 2) 3260 3261 static void virt_machine_7_1_options(MachineClass *mc) 3262 { 3263 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3264 3265 virt_machine_7_2_options(mc); 3266 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 3267 /* Compact layout for high memory regions was introduced with 7.2 */ 3268 vmc->no_highmem_compact = true; 3269 } 3270 DEFINE_VIRT_MACHINE(7, 1) 3271 3272 static void virt_machine_7_0_options(MachineClass *mc) 3273 { 3274 virt_machine_7_1_options(mc); 3275 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 3276 } 3277 DEFINE_VIRT_MACHINE(7, 0) 3278 3279 static void virt_machine_6_2_options(MachineClass *mc) 3280 { 3281 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3282 3283 virt_machine_7_0_options(mc); 3284 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 3285 vmc->no_tcg_lpa2 = true; 3286 } 3287 DEFINE_VIRT_MACHINE(6, 2) 3288 3289 static void virt_machine_6_1_options(MachineClass *mc) 3290 { 3291 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3292 3293 virt_machine_6_2_options(mc); 3294 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 3295 mc->smp_props.prefer_sockets = true; 3296 vmc->no_cpu_topology = true; 3297 3298 /* qemu ITS was introduced with 6.2 */ 3299 vmc->no_tcg_its = true; 3300 } 3301 DEFINE_VIRT_MACHINE(6, 1) 3302 3303 static void virt_machine_6_0_options(MachineClass *mc) 3304 { 3305 virt_machine_6_1_options(mc); 3306 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 3307 } 3308 DEFINE_VIRT_MACHINE(6, 0) 3309 3310 static void virt_machine_5_2_options(MachineClass *mc) 3311 { 3312 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3313 3314 virt_machine_6_0_options(mc); 3315 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 3316 vmc->no_secure_gpio = true; 3317 } 3318 DEFINE_VIRT_MACHINE(5, 2) 3319 3320 static void virt_machine_5_1_options(MachineClass *mc) 3321 { 3322 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3323 3324 virt_machine_5_2_options(mc); 3325 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 3326 vmc->no_kvm_steal_time = true; 3327 } 3328 DEFINE_VIRT_MACHINE(5, 1) 3329 3330 static void virt_machine_5_0_options(MachineClass *mc) 3331 { 3332 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3333 3334 virt_machine_5_1_options(mc); 3335 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 3336 mc->numa_mem_supported = true; 3337 vmc->acpi_expose_flash = true; 3338 mc->auto_enable_numa_with_memdev = false; 3339 } 3340 DEFINE_VIRT_MACHINE(5, 0) 3341 3342 static void virt_machine_4_2_options(MachineClass *mc) 3343 { 3344 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3345 3346 virt_machine_5_0_options(mc); 3347 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 3348 vmc->kvm_no_adjvtime = true; 3349 } 3350 DEFINE_VIRT_MACHINE(4, 2) 3351 3352 static void virt_machine_4_1_options(MachineClass *mc) 3353 { 3354 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3355 3356 virt_machine_4_2_options(mc); 3357 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 3358 vmc->no_ged = true; 3359 mc->auto_enable_numa_with_memhp = false; 3360 } 3361 DEFINE_VIRT_MACHINE(4, 1) 3362 3363 static void virt_machine_4_0_options(MachineClass *mc) 3364 { 3365 virt_machine_4_1_options(mc); 3366 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 3367 } 3368 DEFINE_VIRT_MACHINE(4, 0) 3369 3370 static void virt_machine_3_1_options(MachineClass *mc) 3371 { 3372 virt_machine_4_0_options(mc); 3373 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 3374 } 3375 DEFINE_VIRT_MACHINE(3, 1) 3376 3377 static void virt_machine_3_0_options(MachineClass *mc) 3378 { 3379 virt_machine_3_1_options(mc); 3380 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 3381 } 3382 DEFINE_VIRT_MACHINE(3, 0) 3383 3384 static void virt_machine_2_12_options(MachineClass *mc) 3385 { 3386 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3387 3388 virt_machine_3_0_options(mc); 3389 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 3390 vmc->no_highmem_ecam = true; 3391 mc->max_cpus = 255; 3392 } 3393 DEFINE_VIRT_MACHINE(2, 12) 3394 3395 static void virt_machine_2_11_options(MachineClass *mc) 3396 { 3397 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3398 3399 virt_machine_2_12_options(mc); 3400 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 3401 vmc->smbios_old_sys_ver = true; 3402 } 3403 DEFINE_VIRT_MACHINE(2, 11) 3404 3405 static void virt_machine_2_10_options(MachineClass *mc) 3406 { 3407 virt_machine_2_11_options(mc); 3408 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 3409 /* before 2.11 we never faulted accesses to bad addresses */ 3410 mc->ignore_memory_transaction_failures = true; 3411 } 3412 DEFINE_VIRT_MACHINE(2, 10) 3413 3414 static void virt_machine_2_9_options(MachineClass *mc) 3415 { 3416 virt_machine_2_10_options(mc); 3417 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 3418 } 3419 DEFINE_VIRT_MACHINE(2, 9) 3420 3421 static void virt_machine_2_8_options(MachineClass *mc) 3422 { 3423 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3424 3425 virt_machine_2_9_options(mc); 3426 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 3427 /* For 2.8 and earlier we falsely claimed in the DT that 3428 * our timers were edge-triggered, not level-triggered. 3429 */ 3430 vmc->claim_edge_triggered_timers = true; 3431 } 3432 DEFINE_VIRT_MACHINE(2, 8) 3433 3434 static void virt_machine_2_7_options(MachineClass *mc) 3435 { 3436 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3437 3438 virt_machine_2_8_options(mc); 3439 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 3440 /* ITS was introduced with 2.8 */ 3441 vmc->no_its = true; 3442 /* Stick with 1K pages for migration compatibility */ 3443 mc->minimum_page_bits = 0; 3444 } 3445 DEFINE_VIRT_MACHINE(2, 7) 3446 3447 static void virt_machine_2_6_options(MachineClass *mc) 3448 { 3449 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3450 3451 virt_machine_2_7_options(mc); 3452 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 3453 vmc->disallow_affinity_adjustment = true; 3454 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 3455 vmc->no_pmu = true; 3456 } 3457 DEFINE_VIRT_MACHINE(2, 6) 3458