xref: /openbmc/qemu/hw/arm/virt.c (revision 64552b6b)
1 /*
2  * ARM mach-virt emulation
3  *
4  * Copyright (c) 2013 Linaro Limited
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2 or later, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program.  If not, see <http://www.gnu.org/licenses/>.
17  *
18  * Emulate a virtual board which works by passing Linux all the information
19  * it needs about what devices are present via the device tree.
20  * There are some restrictions about what we can do here:
21  *  + we can only present devices whose Linux drivers will work based
22  *    purely on the device tree with no platform data at all
23  *  + we want to present a very stripped-down minimalist platform,
24  *    both because this reduces the security attack surface from the guest
25  *    and also because it reduces our exposure to being broken when
26  *    the kernel updates its device tree bindings and requires further
27  *    information in a device binding that we aren't providing.
28  * This is essentially the same approach kvmtool uses.
29  */
30 
31 #include "qemu/osdep.h"
32 #include "qemu-common.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "qapi/error.h"
36 #include "hw/sysbus.h"
37 #include "hw/arm/boot.h"
38 #include "hw/arm/primecell.h"
39 #include "hw/arm/virt.h"
40 #include "hw/block/flash.h"
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
43 #include "hw/display/ramfb.h"
44 #include "net/net.h"
45 #include "sysemu/device_tree.h"
46 #include "sysemu/numa.h"
47 #include "sysemu/sysemu.h"
48 #include "sysemu/kvm.h"
49 #include "hw/loader.h"
50 #include "exec/address-spaces.h"
51 #include "qemu/bitops.h"
52 #include "qemu/error-report.h"
53 #include "qemu/module.h"
54 #include "hw/pci-host/gpex.h"
55 #include "hw/arm/sysbus-fdt.h"
56 #include "hw/platform-bus.h"
57 #include "hw/arm/fdt.h"
58 #include "hw/intc/arm_gic.h"
59 #include "hw/intc/arm_gicv3_common.h"
60 #include "hw/irq.h"
61 #include "kvm_arm.h"
62 #include "hw/firmware/smbios.h"
63 #include "qapi/visitor.h"
64 #include "standard-headers/linux/input.h"
65 #include "hw/arm/smmuv3.h"
66 #include "hw/acpi/acpi.h"
67 #include "target/arm/internals.h"
68 
69 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
70     static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
71                                                     void *data) \
72     { \
73         MachineClass *mc = MACHINE_CLASS(oc); \
74         virt_machine_##major##_##minor##_options(mc); \
75         mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
76         if (latest) { \
77             mc->alias = "virt"; \
78         } \
79     } \
80     static const TypeInfo machvirt_##major##_##minor##_info = { \
81         .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
82         .parent = TYPE_VIRT_MACHINE, \
83         .class_init = virt_##major##_##minor##_class_init, \
84     }; \
85     static void machvirt_machine_##major##_##minor##_init(void) \
86     { \
87         type_register_static(&machvirt_##major##_##minor##_info); \
88     } \
89     type_init(machvirt_machine_##major##_##minor##_init);
90 
91 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
92     DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
93 #define DEFINE_VIRT_MACHINE(major, minor) \
94     DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
95 
96 
97 /* Number of external interrupt lines to configure the GIC with */
98 #define NUM_IRQS 256
99 
100 #define PLATFORM_BUS_NUM_IRQS 64
101 
102 /* Legacy RAM limit in GB (< version 4.0) */
103 #define LEGACY_RAMLIMIT_GB 255
104 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
105 
106 /* Addresses and sizes of our components.
107  * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
108  * 128MB..256MB is used for miscellaneous device I/O.
109  * 256MB..1GB is reserved for possible future PCI support (ie where the
110  * PCI memory window will go if we add a PCI host controller).
111  * 1GB and up is RAM (which may happily spill over into the
112  * high memory region beyond 4GB).
113  * This represents a compromise between how much RAM can be given to
114  * a 32 bit VM and leaving space for expansion and in particular for PCI.
115  * Note that devices should generally be placed at multiples of 0x10000,
116  * to accommodate guests using 64K pages.
117  */
118 static const MemMapEntry base_memmap[] = {
119     /* Space up to 0x8000000 is reserved for a boot ROM */
120     [VIRT_FLASH] =              {          0, 0x08000000 },
121     [VIRT_CPUPERIPHS] =         { 0x08000000, 0x00020000 },
122     /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
123     [VIRT_GIC_DIST] =           { 0x08000000, 0x00010000 },
124     [VIRT_GIC_CPU] =            { 0x08010000, 0x00010000 },
125     [VIRT_GIC_V2M] =            { 0x08020000, 0x00001000 },
126     [VIRT_GIC_HYP] =            { 0x08030000, 0x00010000 },
127     [VIRT_GIC_VCPU] =           { 0x08040000, 0x00010000 },
128     /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
129     [VIRT_GIC_ITS] =            { 0x08080000, 0x00020000 },
130     /* This redistributor space allows up to 2*64kB*123 CPUs */
131     [VIRT_GIC_REDIST] =         { 0x080A0000, 0x00F60000 },
132     [VIRT_UART] =               { 0x09000000, 0x00001000 },
133     [VIRT_RTC] =                { 0x09010000, 0x00001000 },
134     [VIRT_FW_CFG] =             { 0x09020000, 0x00000018 },
135     [VIRT_GPIO] =               { 0x09030000, 0x00001000 },
136     [VIRT_SECURE_UART] =        { 0x09040000, 0x00001000 },
137     [VIRT_SMMU] =               { 0x09050000, 0x00020000 },
138     [VIRT_MMIO] =               { 0x0a000000, 0x00000200 },
139     /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
140     [VIRT_PLATFORM_BUS] =       { 0x0c000000, 0x02000000 },
141     [VIRT_SECURE_MEM] =         { 0x0e000000, 0x01000000 },
142     [VIRT_PCIE_MMIO] =          { 0x10000000, 0x2eff0000 },
143     [VIRT_PCIE_PIO] =           { 0x3eff0000, 0x00010000 },
144     [VIRT_PCIE_ECAM] =          { 0x3f000000, 0x01000000 },
145     /* Actual RAM size depends on initial RAM and device memory settings */
146     [VIRT_MEM] =                { GiB, LEGACY_RAMLIMIT_BYTES },
147 };
148 
149 /*
150  * Highmem IO Regions: This memory map is floating, located after the RAM.
151  * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
152  * top of the RAM, so that its base get the same alignment as the size,
153  * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
154  * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
155  * Note the extended_memmap is sized so that it eventually also includes the
156  * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
157  * index of base_memmap).
158  */
159 static MemMapEntry extended_memmap[] = {
160     /* Additional 64 MB redist region (can contain up to 512 redistributors) */
161     [VIRT_HIGH_GIC_REDIST2] =   { 0x0, 64 * MiB },
162     [VIRT_HIGH_PCIE_ECAM] =     { 0x0, 256 * MiB },
163     /* Second PCIe window */
164     [VIRT_HIGH_PCIE_MMIO] =     { 0x0, 512 * GiB },
165 };
166 
167 static const int a15irqmap[] = {
168     [VIRT_UART] = 1,
169     [VIRT_RTC] = 2,
170     [VIRT_PCIE] = 3, /* ... to 6 */
171     [VIRT_GPIO] = 7,
172     [VIRT_SECURE_UART] = 8,
173     [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
174     [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
175     [VIRT_SMMU] = 74,    /* ...to 74 + NUM_SMMU_IRQS - 1 */
176     [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
177 };
178 
179 static const char *valid_cpus[] = {
180     ARM_CPU_TYPE_NAME("cortex-a7"),
181     ARM_CPU_TYPE_NAME("cortex-a15"),
182     ARM_CPU_TYPE_NAME("cortex-a53"),
183     ARM_CPU_TYPE_NAME("cortex-a57"),
184     ARM_CPU_TYPE_NAME("cortex-a72"),
185     ARM_CPU_TYPE_NAME("host"),
186     ARM_CPU_TYPE_NAME("max"),
187 };
188 
189 static bool cpu_type_valid(const char *cpu)
190 {
191     int i;
192 
193     for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
194         if (strcmp(cpu, valid_cpus[i]) == 0) {
195             return true;
196         }
197     }
198     return false;
199 }
200 
201 static void create_fdt(VirtMachineState *vms)
202 {
203     void *fdt = create_device_tree(&vms->fdt_size);
204 
205     if (!fdt) {
206         error_report("create_device_tree() failed");
207         exit(1);
208     }
209 
210     vms->fdt = fdt;
211 
212     /* Header */
213     qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
214     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
215     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
216 
217     /* /chosen must exist for load_dtb to fill in necessary properties later */
218     qemu_fdt_add_subnode(fdt, "/chosen");
219 
220     /* Clock node, for the benefit of the UART. The kernel device tree
221      * binding documentation claims the PL011 node clock properties are
222      * optional but in practice if you omit them the kernel refuses to
223      * probe for the device.
224      */
225     vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
226     qemu_fdt_add_subnode(fdt, "/apb-pclk");
227     qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
228     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
229     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
230     qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
231                                 "clk24mhz");
232     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
233 
234     if (have_numa_distance) {
235         int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
236         uint32_t *matrix = g_malloc0(size);
237         int idx, i, j;
238 
239         for (i = 0; i < nb_numa_nodes; i++) {
240             for (j = 0; j < nb_numa_nodes; j++) {
241                 idx = (i * nb_numa_nodes + j) * 3;
242                 matrix[idx + 0] = cpu_to_be32(i);
243                 matrix[idx + 1] = cpu_to_be32(j);
244                 matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]);
245             }
246         }
247 
248         qemu_fdt_add_subnode(fdt, "/distance-map");
249         qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
250                                 "numa-distance-map-v1");
251         qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
252                          matrix, size);
253         g_free(matrix);
254     }
255 }
256 
257 static void fdt_add_timer_nodes(const VirtMachineState *vms)
258 {
259     /* On real hardware these interrupts are level-triggered.
260      * On KVM they were edge-triggered before host kernel version 4.4,
261      * and level-triggered afterwards.
262      * On emulated QEMU they are level-triggered.
263      *
264      * Getting the DTB info about them wrong is awkward for some
265      * guest kernels:
266      *  pre-4.8 ignore the DT and leave the interrupt configured
267      *   with whatever the GIC reset value (or the bootloader) left it at
268      *  4.8 before rc6 honour the incorrect data by programming it back
269      *   into the GIC, causing problems
270      *  4.8rc6 and later ignore the DT and always write "level triggered"
271      *   into the GIC
272      *
273      * For backwards-compatibility, virt-2.8 and earlier will continue
274      * to say these are edge-triggered, but later machines will report
275      * the correct information.
276      */
277     ARMCPU *armcpu;
278     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
279     uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
280 
281     if (vmc->claim_edge_triggered_timers) {
282         irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
283     }
284 
285     if (vms->gic_version == 2) {
286         irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
287                              GIC_FDT_IRQ_PPI_CPU_WIDTH,
288                              (1 << vms->smp_cpus) - 1);
289     }
290 
291     qemu_fdt_add_subnode(vms->fdt, "/timer");
292 
293     armcpu = ARM_CPU(qemu_get_cpu(0));
294     if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
295         const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
296         qemu_fdt_setprop(vms->fdt, "/timer", "compatible",
297                          compat, sizeof(compat));
298     } else {
299         qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible",
300                                 "arm,armv7-timer");
301     }
302     qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0);
303     qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts",
304                        GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
305                        GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
306                        GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
307                        GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
308 }
309 
310 static void fdt_add_cpu_nodes(const VirtMachineState *vms)
311 {
312     int cpu;
313     int addr_cells = 1;
314     const MachineState *ms = MACHINE(vms);
315 
316     /*
317      * From Documentation/devicetree/bindings/arm/cpus.txt
318      *  On ARM v8 64-bit systems value should be set to 2,
319      *  that corresponds to the MPIDR_EL1 register size.
320      *  If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
321      *  in the system, #address-cells can be set to 1, since
322      *  MPIDR_EL1[63:32] bits are not used for CPUs
323      *  identification.
324      *
325      *  Here we actually don't know whether our system is 32- or 64-bit one.
326      *  The simplest way to go is to examine affinity IDs of all our CPUs. If
327      *  at least one of them has Aff3 populated, we set #address-cells to 2.
328      */
329     for (cpu = 0; cpu < vms->smp_cpus; cpu++) {
330         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
331 
332         if (armcpu->mp_affinity & ARM_AFF3_MASK) {
333             addr_cells = 2;
334             break;
335         }
336     }
337 
338     qemu_fdt_add_subnode(vms->fdt, "/cpus");
339     qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells);
340     qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0);
341 
342     for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) {
343         char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
344         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
345         CPUState *cs = CPU(armcpu);
346 
347         qemu_fdt_add_subnode(vms->fdt, nodename);
348         qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu");
349         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
350                                     armcpu->dtb_compatible);
351 
352         if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED
353             && vms->smp_cpus > 1) {
354             qemu_fdt_setprop_string(vms->fdt, nodename,
355                                         "enable-method", "psci");
356         }
357 
358         if (addr_cells == 2) {
359             qemu_fdt_setprop_u64(vms->fdt, nodename, "reg",
360                                  armcpu->mp_affinity);
361         } else {
362             qemu_fdt_setprop_cell(vms->fdt, nodename, "reg",
363                                   armcpu->mp_affinity);
364         }
365 
366         if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
367             qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id",
368                 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
369         }
370 
371         g_free(nodename);
372     }
373 }
374 
375 static void fdt_add_its_gic_node(VirtMachineState *vms)
376 {
377     char *nodename;
378 
379     vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
380     nodename = g_strdup_printf("/intc/its@%" PRIx64,
381                                vms->memmap[VIRT_GIC_ITS].base);
382     qemu_fdt_add_subnode(vms->fdt, nodename);
383     qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
384                             "arm,gic-v3-its");
385     qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0);
386     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
387                                  2, vms->memmap[VIRT_GIC_ITS].base,
388                                  2, vms->memmap[VIRT_GIC_ITS].size);
389     qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle);
390     g_free(nodename);
391 }
392 
393 static void fdt_add_v2m_gic_node(VirtMachineState *vms)
394 {
395     char *nodename;
396 
397     nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
398                                vms->memmap[VIRT_GIC_V2M].base);
399     vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
400     qemu_fdt_add_subnode(vms->fdt, nodename);
401     qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
402                             "arm,gic-v2m-frame");
403     qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0);
404     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
405                                  2, vms->memmap[VIRT_GIC_V2M].base,
406                                  2, vms->memmap[VIRT_GIC_V2M].size);
407     qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle);
408     g_free(nodename);
409 }
410 
411 static void fdt_add_gic_node(VirtMachineState *vms)
412 {
413     char *nodename;
414 
415     vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt);
416     qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle);
417 
418     nodename = g_strdup_printf("/intc@%" PRIx64,
419                                vms->memmap[VIRT_GIC_DIST].base);
420     qemu_fdt_add_subnode(vms->fdt, nodename);
421     qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 3);
422     qemu_fdt_setprop(vms->fdt, nodename, "interrupt-controller", NULL, 0);
423     qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2);
424     qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2);
425     qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0);
426     if (vms->gic_version == 3) {
427         int nb_redist_regions = virt_gicv3_redist_region_count(vms);
428 
429         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
430                                 "arm,gic-v3");
431 
432         qemu_fdt_setprop_cell(vms->fdt, nodename,
433                               "#redistributor-regions", nb_redist_regions);
434 
435         if (nb_redist_regions == 1) {
436             qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
437                                          2, vms->memmap[VIRT_GIC_DIST].base,
438                                          2, vms->memmap[VIRT_GIC_DIST].size,
439                                          2, vms->memmap[VIRT_GIC_REDIST].base,
440                                          2, vms->memmap[VIRT_GIC_REDIST].size);
441         } else {
442             qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
443                                  2, vms->memmap[VIRT_GIC_DIST].base,
444                                  2, vms->memmap[VIRT_GIC_DIST].size,
445                                  2, vms->memmap[VIRT_GIC_REDIST].base,
446                                  2, vms->memmap[VIRT_GIC_REDIST].size,
447                                  2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
448                                  2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
449         }
450 
451         if (vms->virt) {
452             qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
453                                    GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
454                                    GIC_FDT_IRQ_FLAGS_LEVEL_HI);
455         }
456     } else {
457         /* 'cortex-a15-gic' means 'GIC v2' */
458         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
459                                 "arm,cortex-a15-gic");
460         if (!vms->virt) {
461             qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
462                                          2, vms->memmap[VIRT_GIC_DIST].base,
463                                          2, vms->memmap[VIRT_GIC_DIST].size,
464                                          2, vms->memmap[VIRT_GIC_CPU].base,
465                                          2, vms->memmap[VIRT_GIC_CPU].size);
466         } else {
467             qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
468                                          2, vms->memmap[VIRT_GIC_DIST].base,
469                                          2, vms->memmap[VIRT_GIC_DIST].size,
470                                          2, vms->memmap[VIRT_GIC_CPU].base,
471                                          2, vms->memmap[VIRT_GIC_CPU].size,
472                                          2, vms->memmap[VIRT_GIC_HYP].base,
473                                          2, vms->memmap[VIRT_GIC_HYP].size,
474                                          2, vms->memmap[VIRT_GIC_VCPU].base,
475                                          2, vms->memmap[VIRT_GIC_VCPU].size);
476             qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
477                                    GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
478                                    GIC_FDT_IRQ_FLAGS_LEVEL_HI);
479         }
480     }
481 
482     qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle);
483     g_free(nodename);
484 }
485 
486 static void fdt_add_pmu_nodes(const VirtMachineState *vms)
487 {
488     CPUState *cpu;
489     ARMCPU *armcpu;
490     uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
491 
492     CPU_FOREACH(cpu) {
493         armcpu = ARM_CPU(cpu);
494         if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
495             return;
496         }
497         if (kvm_enabled()) {
498             if (kvm_irqchip_in_kernel()) {
499                 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
500             }
501             kvm_arm_pmu_init(cpu);
502         }
503     }
504 
505     if (vms->gic_version == 2) {
506         irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
507                              GIC_FDT_IRQ_PPI_CPU_WIDTH,
508                              (1 << vms->smp_cpus) - 1);
509     }
510 
511     armcpu = ARM_CPU(qemu_get_cpu(0));
512     qemu_fdt_add_subnode(vms->fdt, "/pmu");
513     if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
514         const char compat[] = "arm,armv8-pmuv3";
515         qemu_fdt_setprop(vms->fdt, "/pmu", "compatible",
516                          compat, sizeof(compat));
517         qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts",
518                                GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
519     }
520 }
521 
522 static void create_its(VirtMachineState *vms, DeviceState *gicdev)
523 {
524     const char *itsclass = its_class_name();
525     DeviceState *dev;
526 
527     if (!itsclass) {
528         /* Do nothing if not supported */
529         return;
530     }
531 
532     dev = qdev_create(NULL, itsclass);
533 
534     object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3",
535                              &error_abort);
536     qdev_init_nofail(dev);
537     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
538 
539     fdt_add_its_gic_node(vms);
540 }
541 
542 static void create_v2m(VirtMachineState *vms, qemu_irq *pic)
543 {
544     int i;
545     int irq = vms->irqmap[VIRT_GIC_V2M];
546     DeviceState *dev;
547 
548     dev = qdev_create(NULL, "arm-gicv2m");
549     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
550     qdev_prop_set_uint32(dev, "base-spi", irq);
551     qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
552     qdev_init_nofail(dev);
553 
554     for (i = 0; i < NUM_GICV2M_SPIS; i++) {
555         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
556     }
557 
558     fdt_add_v2m_gic_node(vms);
559 }
560 
561 static void create_gic(VirtMachineState *vms, qemu_irq *pic)
562 {
563     MachineState *ms = MACHINE(vms);
564     /* We create a standalone GIC */
565     DeviceState *gicdev;
566     SysBusDevice *gicbusdev;
567     const char *gictype;
568     int type = vms->gic_version, i;
569     unsigned int smp_cpus = ms->smp.cpus;
570     uint32_t nb_redist_regions = 0;
571 
572     gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
573 
574     gicdev = qdev_create(NULL, gictype);
575     qdev_prop_set_uint32(gicdev, "revision", type);
576     qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus);
577     /* Note that the num-irq property counts both internal and external
578      * interrupts; there are always 32 of the former (mandated by GIC spec).
579      */
580     qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32);
581     if (!kvm_irqchip_in_kernel()) {
582         qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure);
583     }
584 
585     if (type == 3) {
586         uint32_t redist0_capacity =
587                     vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
588         uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
589 
590         nb_redist_regions = virt_gicv3_redist_region_count(vms);
591 
592         qdev_prop_set_uint32(gicdev, "len-redist-region-count",
593                              nb_redist_regions);
594         qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count);
595 
596         if (nb_redist_regions == 2) {
597             uint32_t redist1_capacity =
598                     vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
599 
600             qdev_prop_set_uint32(gicdev, "redist-region-count[1]",
601                 MIN(smp_cpus - redist0_count, redist1_capacity));
602         }
603     } else {
604         if (!kvm_irqchip_in_kernel()) {
605             qdev_prop_set_bit(gicdev, "has-virtualization-extensions",
606                               vms->virt);
607         }
608     }
609     qdev_init_nofail(gicdev);
610     gicbusdev = SYS_BUS_DEVICE(gicdev);
611     sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
612     if (type == 3) {
613         sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
614         if (nb_redist_regions == 2) {
615             sysbus_mmio_map(gicbusdev, 2,
616                             vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
617         }
618     } else {
619         sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
620         if (vms->virt) {
621             sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
622             sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
623         }
624     }
625 
626     /* Wire the outputs from each CPU's generic timer and the GICv3
627      * maintenance interrupt signal to the appropriate GIC PPI inputs,
628      * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
629      */
630     for (i = 0; i < smp_cpus; i++) {
631         DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
632         int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
633         int irq;
634         /* Mapping from the output timer irq lines from the CPU to the
635          * GIC PPI inputs we use for the virt board.
636          */
637         const int timer_irq[] = {
638             [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
639             [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
640             [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
641             [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,
642         };
643 
644         for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
645             qdev_connect_gpio_out(cpudev, irq,
646                                   qdev_get_gpio_in(gicdev,
647                                                    ppibase + timer_irq[irq]));
648         }
649 
650         if (type == 3) {
651             qemu_irq irq = qdev_get_gpio_in(gicdev,
652                                             ppibase + ARCH_GIC_MAINT_IRQ);
653             qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
654                                         0, irq);
655         } else if (vms->virt) {
656             qemu_irq irq = qdev_get_gpio_in(gicdev,
657                                             ppibase + ARCH_GIC_MAINT_IRQ);
658             sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
659         }
660 
661         qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
662                                     qdev_get_gpio_in(gicdev, ppibase
663                                                      + VIRTUAL_PMU_IRQ));
664 
665         sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
666         sysbus_connect_irq(gicbusdev, i + smp_cpus,
667                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
668         sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
669                            qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
670         sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
671                            qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
672     }
673 
674     for (i = 0; i < NUM_IRQS; i++) {
675         pic[i] = qdev_get_gpio_in(gicdev, i);
676     }
677 
678     fdt_add_gic_node(vms);
679 
680     if (type == 3 && vms->its) {
681         create_its(vms, gicdev);
682     } else if (type == 2) {
683         create_v2m(vms, pic);
684     }
685 }
686 
687 static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart,
688                         MemoryRegion *mem, Chardev *chr)
689 {
690     char *nodename;
691     hwaddr base = vms->memmap[uart].base;
692     hwaddr size = vms->memmap[uart].size;
693     int irq = vms->irqmap[uart];
694     const char compat[] = "arm,pl011\0arm,primecell";
695     const char clocknames[] = "uartclk\0apb_pclk";
696     DeviceState *dev = qdev_create(NULL, "pl011");
697     SysBusDevice *s = SYS_BUS_DEVICE(dev);
698 
699     qdev_prop_set_chr(dev, "chardev", chr);
700     qdev_init_nofail(dev);
701     memory_region_add_subregion(mem, base,
702                                 sysbus_mmio_get_region(s, 0));
703     sysbus_connect_irq(s, 0, pic[irq]);
704 
705     nodename = g_strdup_printf("/pl011@%" PRIx64, base);
706     qemu_fdt_add_subnode(vms->fdt, nodename);
707     /* Note that we can't use setprop_string because of the embedded NUL */
708     qemu_fdt_setprop(vms->fdt, nodename, "compatible",
709                          compat, sizeof(compat));
710     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
711                                      2, base, 2, size);
712     qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
713                                GIC_FDT_IRQ_TYPE_SPI, irq,
714                                GIC_FDT_IRQ_FLAGS_LEVEL_HI);
715     qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks",
716                                vms->clock_phandle, vms->clock_phandle);
717     qemu_fdt_setprop(vms->fdt, nodename, "clock-names",
718                          clocknames, sizeof(clocknames));
719 
720     if (uart == VIRT_UART) {
721         qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename);
722     } else {
723         /* Mark as not usable by the normal world */
724         qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
725         qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
726 
727         qemu_fdt_add_subnode(vms->fdt, "/secure-chosen");
728         qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path",
729                                 nodename);
730     }
731 
732     g_free(nodename);
733 }
734 
735 static void create_rtc(const VirtMachineState *vms, qemu_irq *pic)
736 {
737     char *nodename;
738     hwaddr base = vms->memmap[VIRT_RTC].base;
739     hwaddr size = vms->memmap[VIRT_RTC].size;
740     int irq = vms->irqmap[VIRT_RTC];
741     const char compat[] = "arm,pl031\0arm,primecell";
742 
743     sysbus_create_simple("pl031", base, pic[irq]);
744 
745     nodename = g_strdup_printf("/pl031@%" PRIx64, base);
746     qemu_fdt_add_subnode(vms->fdt, nodename);
747     qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
748     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
749                                  2, base, 2, size);
750     qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
751                            GIC_FDT_IRQ_TYPE_SPI, irq,
752                            GIC_FDT_IRQ_FLAGS_LEVEL_HI);
753     qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
754     qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
755     g_free(nodename);
756 }
757 
758 static DeviceState *gpio_key_dev;
759 static void virt_powerdown_req(Notifier *n, void *opaque)
760 {
761     /* use gpio Pin 3 for power button event */
762     qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
763 }
764 
765 static Notifier virt_system_powerdown_notifier = {
766     .notify = virt_powerdown_req
767 };
768 
769 static void create_gpio(const VirtMachineState *vms, qemu_irq *pic)
770 {
771     char *nodename;
772     DeviceState *pl061_dev;
773     hwaddr base = vms->memmap[VIRT_GPIO].base;
774     hwaddr size = vms->memmap[VIRT_GPIO].size;
775     int irq = vms->irqmap[VIRT_GPIO];
776     const char compat[] = "arm,pl061\0arm,primecell";
777 
778     pl061_dev = sysbus_create_simple("pl061", base, pic[irq]);
779 
780     uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt);
781     nodename = g_strdup_printf("/pl061@%" PRIx64, base);
782     qemu_fdt_add_subnode(vms->fdt, nodename);
783     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
784                                  2, base, 2, size);
785     qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
786     qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2);
787     qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0);
788     qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
789                            GIC_FDT_IRQ_TYPE_SPI, irq,
790                            GIC_FDT_IRQ_FLAGS_LEVEL_HI);
791     qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
792     qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
793     qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle);
794 
795     gpio_key_dev = sysbus_create_simple("gpio-key", -1,
796                                         qdev_get_gpio_in(pl061_dev, 3));
797     qemu_fdt_add_subnode(vms->fdt, "/gpio-keys");
798     qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys");
799     qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0);
800     qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1);
801 
802     qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff");
803     qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff",
804                             "label", "GPIO Key Poweroff");
805     qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code",
806                           KEY_POWER);
807     qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff",
808                            "gpios", phandle, 3, 0);
809 
810     /* connect powerdown request */
811     qemu_register_powerdown_notifier(&virt_system_powerdown_notifier);
812 
813     g_free(nodename);
814 }
815 
816 static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic)
817 {
818     int i;
819     hwaddr size = vms->memmap[VIRT_MMIO].size;
820 
821     /* We create the transports in forwards order. Since qbus_realize()
822      * prepends (not appends) new child buses, the incrementing loop below will
823      * create a list of virtio-mmio buses with decreasing base addresses.
824      *
825      * When a -device option is processed from the command line,
826      * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
827      * order. The upshot is that -device options in increasing command line
828      * order are mapped to virtio-mmio buses with decreasing base addresses.
829      *
830      * When this code was originally written, that arrangement ensured that the
831      * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
832      * the first -device on the command line. (The end-to-end order is a
833      * function of this loop, qbus_realize(), qbus_find_recursive(), and the
834      * guest kernel's name-to-address assignment strategy.)
835      *
836      * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
837      * the message, if not necessarily the code, of commit 70161ff336.
838      * Therefore the loop now establishes the inverse of the original intent.
839      *
840      * Unfortunately, we can't counteract the kernel change by reversing the
841      * loop; it would break existing command lines.
842      *
843      * In any case, the kernel makes no guarantee about the stability of
844      * enumeration order of virtio devices (as demonstrated by it changing
845      * between kernel versions). For reliable and stable identification
846      * of disks users must use UUIDs or similar mechanisms.
847      */
848     for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
849         int irq = vms->irqmap[VIRT_MMIO] + i;
850         hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
851 
852         sysbus_create_simple("virtio-mmio", base, pic[irq]);
853     }
854 
855     /* We add dtb nodes in reverse order so that they appear in the finished
856      * device tree lowest address first.
857      *
858      * Note that this mapping is independent of the loop above. The previous
859      * loop influences virtio device to virtio transport assignment, whereas
860      * this loop controls how virtio transports are laid out in the dtb.
861      */
862     for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
863         char *nodename;
864         int irq = vms->irqmap[VIRT_MMIO] + i;
865         hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
866 
867         nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
868         qemu_fdt_add_subnode(vms->fdt, nodename);
869         qemu_fdt_setprop_string(vms->fdt, nodename,
870                                 "compatible", "virtio,mmio");
871         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
872                                      2, base, 2, size);
873         qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
874                                GIC_FDT_IRQ_TYPE_SPI, irq,
875                                GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
876         qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
877         g_free(nodename);
878     }
879 }
880 
881 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
882 
883 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
884                                         const char *name,
885                                         const char *alias_prop_name)
886 {
887     /*
888      * Create a single flash device.  We use the same parameters as
889      * the flash devices on the Versatile Express board.
890      */
891     DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
892 
893     qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
894     qdev_prop_set_uint8(dev, "width", 4);
895     qdev_prop_set_uint8(dev, "device-width", 2);
896     qdev_prop_set_bit(dev, "big-endian", false);
897     qdev_prop_set_uint16(dev, "id0", 0x89);
898     qdev_prop_set_uint16(dev, "id1", 0x18);
899     qdev_prop_set_uint16(dev, "id2", 0x00);
900     qdev_prop_set_uint16(dev, "id3", 0x00);
901     qdev_prop_set_string(dev, "name", name);
902     object_property_add_child(OBJECT(vms), name, OBJECT(dev),
903                               &error_abort);
904     object_property_add_alias(OBJECT(vms), alias_prop_name,
905                               OBJECT(dev), "drive", &error_abort);
906     return PFLASH_CFI01(dev);
907 }
908 
909 static void virt_flash_create(VirtMachineState *vms)
910 {
911     vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
912     vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
913 }
914 
915 static void virt_flash_map1(PFlashCFI01 *flash,
916                             hwaddr base, hwaddr size,
917                             MemoryRegion *sysmem)
918 {
919     DeviceState *dev = DEVICE(flash);
920 
921     assert(size % VIRT_FLASH_SECTOR_SIZE == 0);
922     assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
923     qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
924     qdev_init_nofail(dev);
925 
926     memory_region_add_subregion(sysmem, base,
927                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
928                                                        0));
929 }
930 
931 static void virt_flash_map(VirtMachineState *vms,
932                            MemoryRegion *sysmem,
933                            MemoryRegion *secure_sysmem)
934 {
935     /*
936      * Map two flash devices to fill the VIRT_FLASH space in the memmap.
937      * sysmem is the system memory space. secure_sysmem is the secure view
938      * of the system, and the first flash device should be made visible only
939      * there. The second flash device is visible to both secure and nonsecure.
940      * If sysmem == secure_sysmem this means there is no separate Secure
941      * address space and both flash devices are generally visible.
942      */
943     hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
944     hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
945 
946     virt_flash_map1(vms->flash[0], flashbase, flashsize,
947                     secure_sysmem);
948     virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
949                     sysmem);
950 }
951 
952 static void virt_flash_fdt(VirtMachineState *vms,
953                            MemoryRegion *sysmem,
954                            MemoryRegion *secure_sysmem)
955 {
956     hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
957     hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
958     char *nodename;
959 
960     if (sysmem == secure_sysmem) {
961         /* Report both flash devices as a single node in the DT */
962         nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
963         qemu_fdt_add_subnode(vms->fdt, nodename);
964         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
965         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
966                                      2, flashbase, 2, flashsize,
967                                      2, flashbase + flashsize, 2, flashsize);
968         qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
969         g_free(nodename);
970     } else {
971         /*
972          * Report the devices as separate nodes so we can mark one as
973          * only visible to the secure world.
974          */
975         nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
976         qemu_fdt_add_subnode(vms->fdt, nodename);
977         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
978         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
979                                      2, flashbase, 2, flashsize);
980         qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
981         qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
982         qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
983         g_free(nodename);
984 
985         nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
986         qemu_fdt_add_subnode(vms->fdt, nodename);
987         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
988         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
989                                      2, flashbase + flashsize, 2, flashsize);
990         qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
991         g_free(nodename);
992     }
993 }
994 
995 static bool virt_firmware_init(VirtMachineState *vms,
996                                MemoryRegion *sysmem,
997                                MemoryRegion *secure_sysmem)
998 {
999     int i;
1000     BlockBackend *pflash_blk0;
1001 
1002     /* Map legacy -drive if=pflash to machine properties */
1003     for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1004         pflash_cfi01_legacy_drive(vms->flash[i],
1005                                   drive_get(IF_PFLASH, 0, i));
1006     }
1007 
1008     virt_flash_map(vms, sysmem, secure_sysmem);
1009 
1010     pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1011 
1012     if (bios_name) {
1013         char *fname;
1014         MemoryRegion *mr;
1015         int image_size;
1016 
1017         if (pflash_blk0) {
1018             error_report("The contents of the first flash device may be "
1019                          "specified with -bios or with -drive if=pflash... "
1020                          "but you cannot use both options at once");
1021             exit(1);
1022         }
1023 
1024         /* Fall back to -bios */
1025 
1026         fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1027         if (!fname) {
1028             error_report("Could not find ROM image '%s'", bios_name);
1029             exit(1);
1030         }
1031         mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1032         image_size = load_image_mr(fname, mr);
1033         g_free(fname);
1034         if (image_size < 0) {
1035             error_report("Could not load ROM image '%s'", bios_name);
1036             exit(1);
1037         }
1038     }
1039 
1040     return pflash_blk0 || bios_name;
1041 }
1042 
1043 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
1044 {
1045     MachineState *ms = MACHINE(vms);
1046     hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1047     hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1048     FWCfgState *fw_cfg;
1049     char *nodename;
1050 
1051     fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
1052     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1053 
1054     nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1055     qemu_fdt_add_subnode(vms->fdt, nodename);
1056     qemu_fdt_setprop_string(vms->fdt, nodename,
1057                             "compatible", "qemu,fw-cfg-mmio");
1058     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
1059                                  2, base, 2, size);
1060     qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
1061     g_free(nodename);
1062     return fw_cfg;
1063 }
1064 
1065 static void create_pcie_irq_map(const VirtMachineState *vms,
1066                                 uint32_t gic_phandle,
1067                                 int first_irq, const char *nodename)
1068 {
1069     int devfn, pin;
1070     uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1071     uint32_t *irq_map = full_irq_map;
1072 
1073     for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1074         for (pin = 0; pin < 4; pin++) {
1075             int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1076             int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1077             int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1078             int i;
1079 
1080             uint32_t map[] = {
1081                 devfn << 8, 0, 0,                           /* devfn */
1082                 pin + 1,                                    /* PCI pin */
1083                 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */
1084 
1085             /* Convert map to big endian */
1086             for (i = 0; i < 10; i++) {
1087                 irq_map[i] = cpu_to_be32(map[i]);
1088             }
1089             irq_map += 10;
1090         }
1091     }
1092 
1093     qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map",
1094                      full_irq_map, sizeof(full_irq_map));
1095 
1096     qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask",
1097                            0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
1098                            0x7           /* PCI irq */);
1099 }
1100 
1101 static void create_smmu(const VirtMachineState *vms, qemu_irq *pic,
1102                         PCIBus *bus)
1103 {
1104     char *node;
1105     const char compat[] = "arm,smmu-v3";
1106     int irq =  vms->irqmap[VIRT_SMMU];
1107     int i;
1108     hwaddr base = vms->memmap[VIRT_SMMU].base;
1109     hwaddr size = vms->memmap[VIRT_SMMU].size;
1110     const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1111     DeviceState *dev;
1112 
1113     if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1114         return;
1115     }
1116 
1117     dev = qdev_create(NULL, "arm-smmuv3");
1118 
1119     object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
1120                              &error_abort);
1121     qdev_init_nofail(dev);
1122     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1123     for (i = 0; i < NUM_SMMU_IRQS; i++) {
1124         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
1125     }
1126 
1127     node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1128     qemu_fdt_add_subnode(vms->fdt, node);
1129     qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat));
1130     qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size);
1131 
1132     qemu_fdt_setprop_cells(vms->fdt, node, "interrupts",
1133             GIC_FDT_IRQ_TYPE_SPI, irq    , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1134             GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1135             GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1136             GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1137 
1138     qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names,
1139                      sizeof(irq_names));
1140 
1141     qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle);
1142     qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk");
1143     qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0);
1144 
1145     qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1);
1146 
1147     qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle);
1148     g_free(node);
1149 }
1150 
1151 static void create_pcie(VirtMachineState *vms, qemu_irq *pic)
1152 {
1153     hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1154     hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1155     hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1156     hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1157     hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1158     hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1159     hwaddr base_ecam, size_ecam;
1160     hwaddr base = base_mmio;
1161     int nr_pcie_buses;
1162     int irq = vms->irqmap[VIRT_PCIE];
1163     MemoryRegion *mmio_alias;
1164     MemoryRegion *mmio_reg;
1165     MemoryRegion *ecam_alias;
1166     MemoryRegion *ecam_reg;
1167     DeviceState *dev;
1168     char *nodename;
1169     int i, ecam_id;
1170     PCIHostState *pci;
1171 
1172     dev = qdev_create(NULL, TYPE_GPEX_HOST);
1173     qdev_init_nofail(dev);
1174 
1175     ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1176     base_ecam = vms->memmap[ecam_id].base;
1177     size_ecam = vms->memmap[ecam_id].size;
1178     nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1179     /* Map only the first size_ecam bytes of ECAM space */
1180     ecam_alias = g_new0(MemoryRegion, 1);
1181     ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1182     memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1183                              ecam_reg, 0, size_ecam);
1184     memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1185 
1186     /* Map the MMIO window into system address space so as to expose
1187      * the section of PCI MMIO space which starts at the same base address
1188      * (ie 1:1 mapping for that part of PCI MMIO space visible through
1189      * the window).
1190      */
1191     mmio_alias = g_new0(MemoryRegion, 1);
1192     mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1193     memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1194                              mmio_reg, base_mmio, size_mmio);
1195     memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1196 
1197     if (vms->highmem) {
1198         /* Map high MMIO space */
1199         MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1200 
1201         memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1202                                  mmio_reg, base_mmio_high, size_mmio_high);
1203         memory_region_add_subregion(get_system_memory(), base_mmio_high,
1204                                     high_mmio_alias);
1205     }
1206 
1207     /* Map IO port space */
1208     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1209 
1210     for (i = 0; i < GPEX_NUM_IRQS; i++) {
1211         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
1212         gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1213     }
1214 
1215     pci = PCI_HOST_BRIDGE(dev);
1216     if (pci->bus) {
1217         for (i = 0; i < nb_nics; i++) {
1218             NICInfo *nd = &nd_table[i];
1219 
1220             if (!nd->model) {
1221                 nd->model = g_strdup("virtio");
1222             }
1223 
1224             pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
1225         }
1226     }
1227 
1228     nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1229     qemu_fdt_add_subnode(vms->fdt, nodename);
1230     qemu_fdt_setprop_string(vms->fdt, nodename,
1231                             "compatible", "pci-host-ecam-generic");
1232     qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci");
1233     qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3);
1234     qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2);
1235     qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0);
1236     qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0,
1237                            nr_pcie_buses - 1);
1238     qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
1239 
1240     if (vms->msi_phandle) {
1241         qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent",
1242                                vms->msi_phandle);
1243     }
1244 
1245     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
1246                                  2, base_ecam, 2, size_ecam);
1247 
1248     if (vms->highmem) {
1249         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
1250                                      1, FDT_PCI_RANGE_IOPORT, 2, 0,
1251                                      2, base_pio, 2, size_pio,
1252                                      1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1253                                      2, base_mmio, 2, size_mmio,
1254                                      1, FDT_PCI_RANGE_MMIO_64BIT,
1255                                      2, base_mmio_high,
1256                                      2, base_mmio_high, 2, size_mmio_high);
1257     } else {
1258         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
1259                                      1, FDT_PCI_RANGE_IOPORT, 2, 0,
1260                                      2, base_pio, 2, size_pio,
1261                                      1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1262                                      2, base_mmio, 2, size_mmio);
1263     }
1264 
1265     qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1);
1266     create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename);
1267 
1268     if (vms->iommu) {
1269         vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt);
1270 
1271         create_smmu(vms, pic, pci->bus);
1272 
1273         qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map",
1274                                0x0, vms->iommu_phandle, 0x0, 0x10000);
1275     }
1276 
1277     g_free(nodename);
1278 }
1279 
1280 static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic)
1281 {
1282     DeviceState *dev;
1283     SysBusDevice *s;
1284     int i;
1285     MemoryRegion *sysmem = get_system_memory();
1286 
1287     dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
1288     dev->id = TYPE_PLATFORM_BUS_DEVICE;
1289     qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1290     qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1291     qdev_init_nofail(dev);
1292     vms->platform_bus_dev = dev;
1293 
1294     s = SYS_BUS_DEVICE(dev);
1295     for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1296         int irqn = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1297         sysbus_connect_irq(s, i, pic[irqn]);
1298     }
1299 
1300     memory_region_add_subregion(sysmem,
1301                                 vms->memmap[VIRT_PLATFORM_BUS].base,
1302                                 sysbus_mmio_get_region(s, 0));
1303 }
1304 
1305 static void create_secure_ram(VirtMachineState *vms,
1306                               MemoryRegion *secure_sysmem)
1307 {
1308     MemoryRegion *secram = g_new(MemoryRegion, 1);
1309     char *nodename;
1310     hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1311     hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1312 
1313     memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1314                            &error_fatal);
1315     memory_region_add_subregion(secure_sysmem, base, secram);
1316 
1317     nodename = g_strdup_printf("/secram@%" PRIx64, base);
1318     qemu_fdt_add_subnode(vms->fdt, nodename);
1319     qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory");
1320     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size);
1321     qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
1322     qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
1323 
1324     g_free(nodename);
1325 }
1326 
1327 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1328 {
1329     const VirtMachineState *board = container_of(binfo, VirtMachineState,
1330                                                  bootinfo);
1331 
1332     *fdt_size = board->fdt_size;
1333     return board->fdt;
1334 }
1335 
1336 static void virt_build_smbios(VirtMachineState *vms)
1337 {
1338     MachineClass *mc = MACHINE_GET_CLASS(vms);
1339     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1340     uint8_t *smbios_tables, *smbios_anchor;
1341     size_t smbios_tables_len, smbios_anchor_len;
1342     const char *product = "QEMU Virtual Machine";
1343 
1344     if (kvm_enabled()) {
1345         product = "KVM Virtual Machine";
1346     }
1347 
1348     smbios_set_defaults("QEMU", product,
1349                         vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
1350                         true, SMBIOS_ENTRY_POINT_30);
1351 
1352     smbios_get_tables(MACHINE(vms), NULL, 0, &smbios_tables, &smbios_tables_len,
1353                       &smbios_anchor, &smbios_anchor_len);
1354 
1355     if (smbios_anchor) {
1356         fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1357                         smbios_tables, smbios_tables_len);
1358         fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1359                         smbios_anchor, smbios_anchor_len);
1360     }
1361 }
1362 
1363 static
1364 void virt_machine_done(Notifier *notifier, void *data)
1365 {
1366     VirtMachineState *vms = container_of(notifier, VirtMachineState,
1367                                          machine_done);
1368     ARMCPU *cpu = ARM_CPU(first_cpu);
1369     struct arm_boot_info *info = &vms->bootinfo;
1370     AddressSpace *as = arm_boot_address_space(cpu, info);
1371 
1372     /*
1373      * If the user provided a dtb, we assume the dynamic sysbus nodes
1374      * already are integrated there. This corresponds to a use case where
1375      * the dynamic sysbus nodes are complex and their generation is not yet
1376      * supported. In that case the user can take charge of the guest dt
1377      * while qemu takes charge of the qom stuff.
1378      */
1379     if (info->dtb_filename == NULL) {
1380         platform_bus_add_all_fdt_nodes(vms->fdt, "/intc",
1381                                        vms->memmap[VIRT_PLATFORM_BUS].base,
1382                                        vms->memmap[VIRT_PLATFORM_BUS].size,
1383                                        vms->irqmap[VIRT_PLATFORM_BUS]);
1384     }
1385     if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
1386         exit(1);
1387     }
1388 
1389     virt_acpi_setup(vms);
1390     virt_build_smbios(vms);
1391 }
1392 
1393 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1394 {
1395     uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1396     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1397 
1398     if (!vmc->disallow_affinity_adjustment) {
1399         /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1400          * GIC's target-list limitations. 32-bit KVM hosts currently
1401          * always create clusters of 4 CPUs, but that is expected to
1402          * change when they gain support for gicv3. When KVM is enabled
1403          * it will override the changes we make here, therefore our
1404          * purposes are to make TCG consistent (with 64-bit KVM hosts)
1405          * and to improve SGI efficiency.
1406          */
1407         if (vms->gic_version == 3) {
1408             clustersz = GICV3_TARGETLIST_BITS;
1409         } else {
1410             clustersz = GIC_TARGETLIST_BITS;
1411         }
1412     }
1413     return arm_cpu_mp_affinity(idx, clustersz);
1414 }
1415 
1416 static void virt_set_memmap(VirtMachineState *vms)
1417 {
1418     MachineState *ms = MACHINE(vms);
1419     hwaddr base, device_memory_base, device_memory_size;
1420     int i;
1421 
1422     vms->memmap = extended_memmap;
1423 
1424     for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1425         vms->memmap[i] = base_memmap[i];
1426     }
1427 
1428     if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1429         error_report("unsupported number of memory slots: %"PRIu64,
1430                      ms->ram_slots);
1431         exit(EXIT_FAILURE);
1432     }
1433 
1434     /*
1435      * We compute the base of the high IO region depending on the
1436      * amount of initial and device memory. The device memory start/size
1437      * is aligned on 1GiB. We never put the high IO region below 256GiB
1438      * so that if maxram_size is < 255GiB we keep the legacy memory map.
1439      * The device region size assumes 1GiB page max alignment per slot.
1440      */
1441     device_memory_base =
1442         ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1443     device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1444 
1445     /* Base address of the high IO region */
1446     base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1447     if (base < device_memory_base) {
1448         error_report("maxmem/slots too huge");
1449         exit(EXIT_FAILURE);
1450     }
1451     if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1452         base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1453     }
1454 
1455     for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1456         hwaddr size = extended_memmap[i].size;
1457 
1458         base = ROUND_UP(base, size);
1459         vms->memmap[i].base = base;
1460         vms->memmap[i].size = size;
1461         base += size;
1462     }
1463     vms->highest_gpa = base - 1;
1464     if (device_memory_size > 0) {
1465         ms->device_memory = g_malloc0(sizeof(*ms->device_memory));
1466         ms->device_memory->base = device_memory_base;
1467         memory_region_init(&ms->device_memory->mr, OBJECT(vms),
1468                            "device-memory", device_memory_size);
1469     }
1470 }
1471 
1472 static void machvirt_init(MachineState *machine)
1473 {
1474     VirtMachineState *vms = VIRT_MACHINE(machine);
1475     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
1476     MachineClass *mc = MACHINE_GET_CLASS(machine);
1477     const CPUArchIdList *possible_cpus;
1478     qemu_irq pic[NUM_IRQS];
1479     MemoryRegion *sysmem = get_system_memory();
1480     MemoryRegion *secure_sysmem = NULL;
1481     int n, virt_max_cpus;
1482     MemoryRegion *ram = g_new(MemoryRegion, 1);
1483     bool firmware_loaded;
1484     bool aarch64 = true;
1485     unsigned int smp_cpus = machine->smp.cpus;
1486     unsigned int max_cpus = machine->smp.max_cpus;
1487 
1488     /*
1489      * In accelerated mode, the memory map is computed earlier in kvm_type()
1490      * to create a VM with the right number of IPA bits.
1491      */
1492     if (!vms->memmap) {
1493         virt_set_memmap(vms);
1494     }
1495 
1496     /* We can probe only here because during property set
1497      * KVM is not available yet
1498      */
1499     if (vms->gic_version <= 0) {
1500         /* "host" or "max" */
1501         if (!kvm_enabled()) {
1502             if (vms->gic_version == 0) {
1503                 error_report("gic-version=host requires KVM");
1504                 exit(1);
1505             } else {
1506                 /* "max": currently means 3 for TCG */
1507                 vms->gic_version = 3;
1508             }
1509         } else {
1510             vms->gic_version = kvm_arm_vgic_probe();
1511             if (!vms->gic_version) {
1512                 error_report(
1513                     "Unable to determine GIC version supported by host");
1514                 exit(1);
1515             }
1516         }
1517     }
1518 
1519     if (!cpu_type_valid(machine->cpu_type)) {
1520         error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
1521         exit(1);
1522     }
1523 
1524     if (vms->secure) {
1525         if (kvm_enabled()) {
1526             error_report("mach-virt: KVM does not support Security extensions");
1527             exit(1);
1528         }
1529 
1530         /*
1531          * The Secure view of the world is the same as the NonSecure,
1532          * but with a few extra devices. Create it as a container region
1533          * containing the system memory at low priority; any secure-only
1534          * devices go in at higher priority and take precedence.
1535          */
1536         secure_sysmem = g_new(MemoryRegion, 1);
1537         memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
1538                            UINT64_MAX);
1539         memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
1540     }
1541 
1542     firmware_loaded = virt_firmware_init(vms, sysmem,
1543                                          secure_sysmem ?: sysmem);
1544 
1545     /* If we have an EL3 boot ROM then the assumption is that it will
1546      * implement PSCI itself, so disable QEMU's internal implementation
1547      * so it doesn't get in the way. Instead of starting secondary
1548      * CPUs in PSCI powerdown state we will start them all running and
1549      * let the boot ROM sort them out.
1550      * The usual case is that we do use QEMU's PSCI implementation;
1551      * if the guest has EL2 then we will use SMC as the conduit,
1552      * and otherwise we will use HVC (for backwards compatibility and
1553      * because if we're using KVM then we must use HVC).
1554      */
1555     if (vms->secure && firmware_loaded) {
1556         vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
1557     } else if (vms->virt) {
1558         vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
1559     } else {
1560         vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
1561     }
1562 
1563     /* The maximum number of CPUs depends on the GIC version, or on how
1564      * many redistributors we can fit into the memory map.
1565      */
1566     if (vms->gic_version == 3) {
1567         virt_max_cpus =
1568             vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
1569         virt_max_cpus +=
1570             vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
1571     } else {
1572         virt_max_cpus = GIC_NCPU;
1573     }
1574 
1575     if (max_cpus > virt_max_cpus) {
1576         error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1577                      "supported by machine 'mach-virt' (%d)",
1578                      max_cpus, virt_max_cpus);
1579         exit(1);
1580     }
1581 
1582     vms->smp_cpus = smp_cpus;
1583 
1584     if (vms->virt && kvm_enabled()) {
1585         error_report("mach-virt: KVM does not support providing "
1586                      "Virtualization extensions to the guest CPU");
1587         exit(1);
1588     }
1589 
1590     create_fdt(vms);
1591 
1592     possible_cpus = mc->possible_cpu_arch_ids(machine);
1593     for (n = 0; n < possible_cpus->len; n++) {
1594         Object *cpuobj;
1595         CPUState *cs;
1596 
1597         if (n >= smp_cpus) {
1598             break;
1599         }
1600 
1601         cpuobj = object_new(possible_cpus->cpus[n].type);
1602         object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,
1603                                 "mp-affinity", NULL);
1604 
1605         cs = CPU(cpuobj);
1606         cs->cpu_index = n;
1607 
1608         numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
1609                           &error_fatal);
1610 
1611         aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
1612 
1613         if (!vms->secure) {
1614             object_property_set_bool(cpuobj, false, "has_el3", NULL);
1615         }
1616 
1617         if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) {
1618             object_property_set_bool(cpuobj, false, "has_el2", NULL);
1619         }
1620 
1621         if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
1622             object_property_set_int(cpuobj, vms->psci_conduit,
1623                                     "psci-conduit", NULL);
1624 
1625             /* Secondary CPUs start in PSCI powered-down state */
1626             if (n > 0) {
1627                 object_property_set_bool(cpuobj, true,
1628                                          "start-powered-off", NULL);
1629             }
1630         }
1631 
1632         if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) {
1633             object_property_set_bool(cpuobj, false, "pmu", NULL);
1634         }
1635 
1636         if (object_property_find(cpuobj, "reset-cbar", NULL)) {
1637             object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base,
1638                                     "reset-cbar", &error_abort);
1639         }
1640 
1641         object_property_set_link(cpuobj, OBJECT(sysmem), "memory",
1642                                  &error_abort);
1643         if (vms->secure) {
1644             object_property_set_link(cpuobj, OBJECT(secure_sysmem),
1645                                      "secure-memory", &error_abort);
1646         }
1647 
1648         object_property_set_bool(cpuobj, true, "realized", &error_fatal);
1649         object_unref(cpuobj);
1650     }
1651     fdt_add_timer_nodes(vms);
1652     fdt_add_cpu_nodes(vms);
1653 
1654    if (!kvm_enabled()) {
1655         ARMCPU *cpu = ARM_CPU(first_cpu);
1656         bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL);
1657 
1658         if (aarch64 && vms->highmem) {
1659             int requested_pa_size, pamax = arm_pamax(cpu);
1660 
1661             requested_pa_size = 64 - clz64(vms->highest_gpa);
1662             if (pamax < requested_pa_size) {
1663                 error_report("VCPU supports less PA bits (%d) than requested "
1664                             "by the memory map (%d)", pamax, requested_pa_size);
1665                 exit(1);
1666             }
1667         }
1668     }
1669 
1670     memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram",
1671                                          machine->ram_size);
1672     memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram);
1673     if (machine->device_memory) {
1674         memory_region_add_subregion(sysmem, machine->device_memory->base,
1675                                     &machine->device_memory->mr);
1676     }
1677 
1678     virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
1679 
1680     create_gic(vms, pic);
1681 
1682     fdt_add_pmu_nodes(vms);
1683 
1684     create_uart(vms, pic, VIRT_UART, sysmem, serial_hd(0));
1685 
1686     if (vms->secure) {
1687         create_secure_ram(vms, secure_sysmem);
1688         create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
1689     }
1690 
1691     vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64);
1692 
1693     create_rtc(vms, pic);
1694 
1695     create_pcie(vms, pic);
1696 
1697     create_gpio(vms, pic);
1698 
1699     /* Create mmio transports, so the user can create virtio backends
1700      * (which will be automatically plugged in to the transports). If
1701      * no backend is created the transport will just sit harmlessly idle.
1702      */
1703     create_virtio_devices(vms, pic);
1704 
1705     vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
1706     rom_set_fw(vms->fw_cfg);
1707 
1708     create_platform_bus(vms, pic);
1709 
1710     vms->bootinfo.ram_size = machine->ram_size;
1711     vms->bootinfo.kernel_filename = machine->kernel_filename;
1712     vms->bootinfo.kernel_cmdline = machine->kernel_cmdline;
1713     vms->bootinfo.initrd_filename = machine->initrd_filename;
1714     vms->bootinfo.nb_cpus = smp_cpus;
1715     vms->bootinfo.board_id = -1;
1716     vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
1717     vms->bootinfo.get_dtb = machvirt_dtb;
1718     vms->bootinfo.skip_dtb_autoload = true;
1719     vms->bootinfo.firmware_loaded = firmware_loaded;
1720     arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo);
1721 
1722     vms->machine_done.notify = virt_machine_done;
1723     qemu_add_machine_init_done_notifier(&vms->machine_done);
1724 }
1725 
1726 static bool virt_get_secure(Object *obj, Error **errp)
1727 {
1728     VirtMachineState *vms = VIRT_MACHINE(obj);
1729 
1730     return vms->secure;
1731 }
1732 
1733 static void virt_set_secure(Object *obj, bool value, Error **errp)
1734 {
1735     VirtMachineState *vms = VIRT_MACHINE(obj);
1736 
1737     vms->secure = value;
1738 }
1739 
1740 static bool virt_get_virt(Object *obj, Error **errp)
1741 {
1742     VirtMachineState *vms = VIRT_MACHINE(obj);
1743 
1744     return vms->virt;
1745 }
1746 
1747 static void virt_set_virt(Object *obj, bool value, Error **errp)
1748 {
1749     VirtMachineState *vms = VIRT_MACHINE(obj);
1750 
1751     vms->virt = value;
1752 }
1753 
1754 static bool virt_get_highmem(Object *obj, Error **errp)
1755 {
1756     VirtMachineState *vms = VIRT_MACHINE(obj);
1757 
1758     return vms->highmem;
1759 }
1760 
1761 static void virt_set_highmem(Object *obj, bool value, Error **errp)
1762 {
1763     VirtMachineState *vms = VIRT_MACHINE(obj);
1764 
1765     vms->highmem = value;
1766 }
1767 
1768 static bool virt_get_its(Object *obj, Error **errp)
1769 {
1770     VirtMachineState *vms = VIRT_MACHINE(obj);
1771 
1772     return vms->its;
1773 }
1774 
1775 static void virt_set_its(Object *obj, bool value, Error **errp)
1776 {
1777     VirtMachineState *vms = VIRT_MACHINE(obj);
1778 
1779     vms->its = value;
1780 }
1781 
1782 static char *virt_get_gic_version(Object *obj, Error **errp)
1783 {
1784     VirtMachineState *vms = VIRT_MACHINE(obj);
1785     const char *val = vms->gic_version == 3 ? "3" : "2";
1786 
1787     return g_strdup(val);
1788 }
1789 
1790 static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
1791 {
1792     VirtMachineState *vms = VIRT_MACHINE(obj);
1793 
1794     if (!strcmp(value, "3")) {
1795         vms->gic_version = 3;
1796     } else if (!strcmp(value, "2")) {
1797         vms->gic_version = 2;
1798     } else if (!strcmp(value, "host")) {
1799         vms->gic_version = 0; /* Will probe later */
1800     } else if (!strcmp(value, "max")) {
1801         vms->gic_version = -1; /* Will probe later */
1802     } else {
1803         error_setg(errp, "Invalid gic-version value");
1804         error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
1805     }
1806 }
1807 
1808 static char *virt_get_iommu(Object *obj, Error **errp)
1809 {
1810     VirtMachineState *vms = VIRT_MACHINE(obj);
1811 
1812     switch (vms->iommu) {
1813     case VIRT_IOMMU_NONE:
1814         return g_strdup("none");
1815     case VIRT_IOMMU_SMMUV3:
1816         return g_strdup("smmuv3");
1817     default:
1818         g_assert_not_reached();
1819     }
1820 }
1821 
1822 static void virt_set_iommu(Object *obj, const char *value, Error **errp)
1823 {
1824     VirtMachineState *vms = VIRT_MACHINE(obj);
1825 
1826     if (!strcmp(value, "smmuv3")) {
1827         vms->iommu = VIRT_IOMMU_SMMUV3;
1828     } else if (!strcmp(value, "none")) {
1829         vms->iommu = VIRT_IOMMU_NONE;
1830     } else {
1831         error_setg(errp, "Invalid iommu value");
1832         error_append_hint(errp, "Valid values are none, smmuv3.\n");
1833     }
1834 }
1835 
1836 static CpuInstanceProperties
1837 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
1838 {
1839     MachineClass *mc = MACHINE_GET_CLASS(ms);
1840     const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
1841 
1842     assert(cpu_index < possible_cpus->len);
1843     return possible_cpus->cpus[cpu_index].props;
1844 }
1845 
1846 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
1847 {
1848     return idx % nb_numa_nodes;
1849 }
1850 
1851 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
1852 {
1853     int n;
1854     unsigned int max_cpus = ms->smp.max_cpus;
1855     VirtMachineState *vms = VIRT_MACHINE(ms);
1856 
1857     if (ms->possible_cpus) {
1858         assert(ms->possible_cpus->len == max_cpus);
1859         return ms->possible_cpus;
1860     }
1861 
1862     ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
1863                                   sizeof(CPUArchId) * max_cpus);
1864     ms->possible_cpus->len = max_cpus;
1865     for (n = 0; n < ms->possible_cpus->len; n++) {
1866         ms->possible_cpus->cpus[n].type = ms->cpu_type;
1867         ms->possible_cpus->cpus[n].arch_id =
1868             virt_cpu_mp_affinity(vms, n);
1869         ms->possible_cpus->cpus[n].props.has_thread_id = true;
1870         ms->possible_cpus->cpus[n].props.thread_id = n;
1871     }
1872     return ms->possible_cpus;
1873 }
1874 
1875 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1876                                         DeviceState *dev, Error **errp)
1877 {
1878     VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
1879 
1880     if (vms->platform_bus_dev) {
1881         if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
1882             platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
1883                                      SYS_BUS_DEVICE(dev));
1884         }
1885     }
1886 }
1887 
1888 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
1889                                                         DeviceState *dev)
1890 {
1891     if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
1892         return HOTPLUG_HANDLER(machine);
1893     }
1894 
1895     return NULL;
1896 }
1897 
1898 /*
1899  * for arm64 kvm_type [7-0] encodes the requested number of bits
1900  * in the IPA address space
1901  */
1902 static int virt_kvm_type(MachineState *ms, const char *type_str)
1903 {
1904     VirtMachineState *vms = VIRT_MACHINE(ms);
1905     int max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms);
1906     int requested_pa_size;
1907 
1908     /* we freeze the memory map to compute the highest gpa */
1909     virt_set_memmap(vms);
1910 
1911     requested_pa_size = 64 - clz64(vms->highest_gpa);
1912 
1913     if (requested_pa_size > max_vm_pa_size) {
1914         error_report("-m and ,maxmem option values "
1915                      "require an IPA range (%d bits) larger than "
1916                      "the one supported by the host (%d bits)",
1917                      requested_pa_size, max_vm_pa_size);
1918        exit(1);
1919     }
1920     /*
1921      * By default we return 0 which corresponds to an implicit legacy
1922      * 40b IPA setting. Otherwise we return the actual requested PA
1923      * logsize
1924      */
1925     return requested_pa_size > 40 ? requested_pa_size : 0;
1926 }
1927 
1928 static void virt_machine_class_init(ObjectClass *oc, void *data)
1929 {
1930     MachineClass *mc = MACHINE_CLASS(oc);
1931     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1932 
1933     mc->init = machvirt_init;
1934     /* Start with max_cpus set to 512, which is the maximum supported by KVM.
1935      * The value may be reduced later when we have more information about the
1936      * configuration of the particular instance.
1937      */
1938     mc->max_cpus = 512;
1939     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
1940     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
1941     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
1942     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
1943     mc->block_default_type = IF_VIRTIO;
1944     mc->no_cdrom = 1;
1945     mc->pci_allow_0_address = true;
1946     /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
1947     mc->minimum_page_bits = 12;
1948     mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
1949     mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
1950     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
1951     mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
1952     mc->kvm_type = virt_kvm_type;
1953     assert(!mc->get_hotplug_handler);
1954     mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
1955     hc->plug = virt_machine_device_plug_cb;
1956     mc->numa_mem_supported = true;
1957 }
1958 
1959 static void virt_instance_init(Object *obj)
1960 {
1961     VirtMachineState *vms = VIRT_MACHINE(obj);
1962     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1963 
1964     /* EL3 is disabled by default on virt: this makes us consistent
1965      * between KVM and TCG for this board, and it also allows us to
1966      * boot UEFI blobs which assume no TrustZone support.
1967      */
1968     vms->secure = false;
1969     object_property_add_bool(obj, "secure", virt_get_secure,
1970                              virt_set_secure, NULL);
1971     object_property_set_description(obj, "secure",
1972                                     "Set on/off to enable/disable the ARM "
1973                                     "Security Extensions (TrustZone)",
1974                                     NULL);
1975 
1976     /* EL2 is also disabled by default, for similar reasons */
1977     vms->virt = false;
1978     object_property_add_bool(obj, "virtualization", virt_get_virt,
1979                              virt_set_virt, NULL);
1980     object_property_set_description(obj, "virtualization",
1981                                     "Set on/off to enable/disable emulating a "
1982                                     "guest CPU which implements the ARM "
1983                                     "Virtualization Extensions",
1984                                     NULL);
1985 
1986     /* High memory is enabled by default */
1987     vms->highmem = true;
1988     object_property_add_bool(obj, "highmem", virt_get_highmem,
1989                              virt_set_highmem, NULL);
1990     object_property_set_description(obj, "highmem",
1991                                     "Set on/off to enable/disable using "
1992                                     "physical address space above 32 bits",
1993                                     NULL);
1994     /* Default GIC type is v2 */
1995     vms->gic_version = 2;
1996     object_property_add_str(obj, "gic-version", virt_get_gic_version,
1997                         virt_set_gic_version, NULL);
1998     object_property_set_description(obj, "gic-version",
1999                                     "Set GIC version. "
2000                                     "Valid values are 2, 3 and host", NULL);
2001 
2002     vms->highmem_ecam = !vmc->no_highmem_ecam;
2003 
2004     if (vmc->no_its) {
2005         vms->its = false;
2006     } else {
2007         /* Default allows ITS instantiation */
2008         vms->its = true;
2009         object_property_add_bool(obj, "its", virt_get_its,
2010                                  virt_set_its, NULL);
2011         object_property_set_description(obj, "its",
2012                                         "Set on/off to enable/disable "
2013                                         "ITS instantiation",
2014                                         NULL);
2015     }
2016 
2017     /* Default disallows iommu instantiation */
2018     vms->iommu = VIRT_IOMMU_NONE;
2019     object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu, NULL);
2020     object_property_set_description(obj, "iommu",
2021                                     "Set the IOMMU type. "
2022                                     "Valid values are none and smmuv3",
2023                                     NULL);
2024 
2025     vms->irqmap = a15irqmap;
2026 
2027     virt_flash_create(vms);
2028 }
2029 
2030 static const TypeInfo virt_machine_info = {
2031     .name          = TYPE_VIRT_MACHINE,
2032     .parent        = TYPE_MACHINE,
2033     .abstract      = true,
2034     .instance_size = sizeof(VirtMachineState),
2035     .class_size    = sizeof(VirtMachineClass),
2036     .class_init    = virt_machine_class_init,
2037     .instance_init = virt_instance_init,
2038     .interfaces = (InterfaceInfo[]) {
2039          { TYPE_HOTPLUG_HANDLER },
2040          { }
2041     },
2042 };
2043 
2044 static void machvirt_machine_init(void)
2045 {
2046     type_register_static(&virt_machine_info);
2047 }
2048 type_init(machvirt_machine_init);
2049 
2050 static void virt_machine_4_1_options(MachineClass *mc)
2051 {
2052 }
2053 DEFINE_VIRT_MACHINE_AS_LATEST(4, 1)
2054 
2055 static void virt_machine_4_0_options(MachineClass *mc)
2056 {
2057     virt_machine_4_1_options(mc);
2058     compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
2059 }
2060 DEFINE_VIRT_MACHINE(4, 0)
2061 
2062 static void virt_machine_3_1_options(MachineClass *mc)
2063 {
2064     virt_machine_4_0_options(mc);
2065     compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
2066 }
2067 DEFINE_VIRT_MACHINE(3, 1)
2068 
2069 static void virt_machine_3_0_options(MachineClass *mc)
2070 {
2071     virt_machine_3_1_options(mc);
2072     compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
2073 }
2074 DEFINE_VIRT_MACHINE(3, 0)
2075 
2076 static void virt_machine_2_12_options(MachineClass *mc)
2077 {
2078     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2079 
2080     virt_machine_3_0_options(mc);
2081     compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
2082     vmc->no_highmem_ecam = true;
2083     mc->max_cpus = 255;
2084 }
2085 DEFINE_VIRT_MACHINE(2, 12)
2086 
2087 static void virt_machine_2_11_options(MachineClass *mc)
2088 {
2089     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2090 
2091     virt_machine_2_12_options(mc);
2092     compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
2093     vmc->smbios_old_sys_ver = true;
2094 }
2095 DEFINE_VIRT_MACHINE(2, 11)
2096 
2097 static void virt_machine_2_10_options(MachineClass *mc)
2098 {
2099     virt_machine_2_11_options(mc);
2100     compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
2101     /* before 2.11 we never faulted accesses to bad addresses */
2102     mc->ignore_memory_transaction_failures = true;
2103 }
2104 DEFINE_VIRT_MACHINE(2, 10)
2105 
2106 static void virt_machine_2_9_options(MachineClass *mc)
2107 {
2108     virt_machine_2_10_options(mc);
2109     compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
2110 }
2111 DEFINE_VIRT_MACHINE(2, 9)
2112 
2113 static void virt_machine_2_8_options(MachineClass *mc)
2114 {
2115     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2116 
2117     virt_machine_2_9_options(mc);
2118     compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
2119     /* For 2.8 and earlier we falsely claimed in the DT that
2120      * our timers were edge-triggered, not level-triggered.
2121      */
2122     vmc->claim_edge_triggered_timers = true;
2123 }
2124 DEFINE_VIRT_MACHINE(2, 8)
2125 
2126 static void virt_machine_2_7_options(MachineClass *mc)
2127 {
2128     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2129 
2130     virt_machine_2_8_options(mc);
2131     compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
2132     /* ITS was introduced with 2.8 */
2133     vmc->no_its = true;
2134     /* Stick with 1K pages for migration compatibility */
2135     mc->minimum_page_bits = 0;
2136 }
2137 DEFINE_VIRT_MACHINE(2, 7)
2138 
2139 static void virt_machine_2_6_options(MachineClass *mc)
2140 {
2141     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2142 
2143     virt_machine_2_7_options(mc);
2144     compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
2145     vmc->disallow_affinity_adjustment = true;
2146     /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
2147     vmc->no_pmu = true;
2148 }
2149 DEFINE_VIRT_MACHINE(2, 6)
2150