1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qapi/error.h" 33 #include "hw/sysbus.h" 34 #include "hw/arm/arm.h" 35 #include "hw/arm/primecell.h" 36 #include "hw/arm/virt.h" 37 #include "hw/vfio/vfio-calxeda-xgmac.h" 38 #include "hw/vfio/vfio-amd-xgbe.h" 39 #include "hw/display/ramfb.h" 40 #include "hw/devices.h" 41 #include "net/net.h" 42 #include "sysemu/device_tree.h" 43 #include "sysemu/numa.h" 44 #include "sysemu/sysemu.h" 45 #include "sysemu/kvm.h" 46 #include "hw/compat.h" 47 #include "hw/loader.h" 48 #include "exec/address-spaces.h" 49 #include "qemu/bitops.h" 50 #include "qemu/error-report.h" 51 #include "hw/pci-host/gpex.h" 52 #include "hw/arm/sysbus-fdt.h" 53 #include "hw/platform-bus.h" 54 #include "hw/arm/fdt.h" 55 #include "hw/intc/arm_gic.h" 56 #include "hw/intc/arm_gicv3_common.h" 57 #include "kvm_arm.h" 58 #include "hw/smbios/smbios.h" 59 #include "qapi/visitor.h" 60 #include "standard-headers/linux/input.h" 61 #include "hw/arm/smmuv3.h" 62 63 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 64 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 65 void *data) \ 66 { \ 67 MachineClass *mc = MACHINE_CLASS(oc); \ 68 virt_machine_##major##_##minor##_options(mc); \ 69 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 70 if (latest) { \ 71 mc->alias = "virt"; \ 72 } \ 73 } \ 74 static const TypeInfo machvirt_##major##_##minor##_info = { \ 75 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 76 .parent = TYPE_VIRT_MACHINE, \ 77 .instance_init = virt_##major##_##minor##_instance_init, \ 78 .class_init = virt_##major##_##minor##_class_init, \ 79 }; \ 80 static void machvirt_machine_##major##_##minor##_init(void) \ 81 { \ 82 type_register_static(&machvirt_##major##_##minor##_info); \ 83 } \ 84 type_init(machvirt_machine_##major##_##minor##_init); 85 86 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 87 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 88 #define DEFINE_VIRT_MACHINE(major, minor) \ 89 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 90 91 92 /* Number of external interrupt lines to configure the GIC with */ 93 #define NUM_IRQS 256 94 95 #define PLATFORM_BUS_NUM_IRQS 64 96 97 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means 98 * RAM can go up to the 256GB mark, leaving 256GB of the physical 99 * address space unallocated and free for future use between 256G and 512G. 100 * If we need to provide more RAM to VMs in the future then we need to: 101 * * allocate a second bank of RAM starting at 2TB and working up 102 * * fix the DT and ACPI table generation code in QEMU to correctly 103 * report two split lumps of RAM to the guest 104 * * fix KVM in the host kernel to allow guests with >40 bit address spaces 105 * (We don't want to fill all the way up to 512GB with RAM because 106 * we might want it for non-RAM purposes later. Conversely it seems 107 * reasonable to assume that anybody configuring a VM with a quarter 108 * of a terabyte of RAM will be doing it on a host with more than a 109 * terabyte of physical address space.) 110 */ 111 #define RAMLIMIT_GB 255 112 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) 113 114 /* Addresses and sizes of our components. 115 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 116 * 128MB..256MB is used for miscellaneous device I/O. 117 * 256MB..1GB is reserved for possible future PCI support (ie where the 118 * PCI memory window will go if we add a PCI host controller). 119 * 1GB and up is RAM (which may happily spill over into the 120 * high memory region beyond 4GB). 121 * This represents a compromise between how much RAM can be given to 122 * a 32 bit VM and leaving space for expansion and in particular for PCI. 123 * Note that devices should generally be placed at multiples of 0x10000, 124 * to accommodate guests using 64K pages. 125 */ 126 static const MemMapEntry a15memmap[] = { 127 /* Space up to 0x8000000 is reserved for a boot ROM */ 128 [VIRT_FLASH] = { 0, 0x08000000 }, 129 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 130 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 131 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 132 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 133 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 134 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 135 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 136 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 137 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 138 /* This redistributor space allows up to 2*64kB*123 CPUs */ 139 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 140 [VIRT_UART] = { 0x09000000, 0x00001000 }, 141 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 142 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 143 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 144 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 145 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 146 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 147 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 148 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 149 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 150 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 151 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 152 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 153 [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES }, 154 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 155 [VIRT_GIC_REDIST2] = { 0x4000000000ULL, 0x4000000 }, 156 [VIRT_PCIE_ECAM_HIGH] = { 0x4010000000ULL, 0x10000000 }, 157 /* Second PCIe window, 512GB wide at the 512GB boundary */ 158 [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL }, 159 }; 160 161 static const int a15irqmap[] = { 162 [VIRT_UART] = 1, 163 [VIRT_RTC] = 2, 164 [VIRT_PCIE] = 3, /* ... to 6 */ 165 [VIRT_GPIO] = 7, 166 [VIRT_SECURE_UART] = 8, 167 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 168 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 169 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 170 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 171 }; 172 173 static const char *valid_cpus[] = { 174 ARM_CPU_TYPE_NAME("cortex-a15"), 175 ARM_CPU_TYPE_NAME("cortex-a53"), 176 ARM_CPU_TYPE_NAME("cortex-a57"), 177 ARM_CPU_TYPE_NAME("cortex-a72"), 178 ARM_CPU_TYPE_NAME("host"), 179 ARM_CPU_TYPE_NAME("max"), 180 }; 181 182 static bool cpu_type_valid(const char *cpu) 183 { 184 int i; 185 186 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 187 if (strcmp(cpu, valid_cpus[i]) == 0) { 188 return true; 189 } 190 } 191 return false; 192 } 193 194 static void create_fdt(VirtMachineState *vms) 195 { 196 void *fdt = create_device_tree(&vms->fdt_size); 197 198 if (!fdt) { 199 error_report("create_device_tree() failed"); 200 exit(1); 201 } 202 203 vms->fdt = fdt; 204 205 /* Header */ 206 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 207 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 208 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 209 210 /* /chosen must exist for load_dtb to fill in necessary properties later */ 211 qemu_fdt_add_subnode(fdt, "/chosen"); 212 213 /* Clock node, for the benefit of the UART. The kernel device tree 214 * binding documentation claims the PL011 node clock properties are 215 * optional but in practice if you omit them the kernel refuses to 216 * probe for the device. 217 */ 218 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 219 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 220 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 221 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 222 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 223 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 224 "clk24mhz"); 225 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 226 227 if (have_numa_distance) { 228 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 229 uint32_t *matrix = g_malloc0(size); 230 int idx, i, j; 231 232 for (i = 0; i < nb_numa_nodes; i++) { 233 for (j = 0; j < nb_numa_nodes; j++) { 234 idx = (i * nb_numa_nodes + j) * 3; 235 matrix[idx + 0] = cpu_to_be32(i); 236 matrix[idx + 1] = cpu_to_be32(j); 237 matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]); 238 } 239 } 240 241 qemu_fdt_add_subnode(fdt, "/distance-map"); 242 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 243 "numa-distance-map-v1"); 244 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 245 matrix, size); 246 g_free(matrix); 247 } 248 } 249 250 static void fdt_add_timer_nodes(const VirtMachineState *vms) 251 { 252 /* On real hardware these interrupts are level-triggered. 253 * On KVM they were edge-triggered before host kernel version 4.4, 254 * and level-triggered afterwards. 255 * On emulated QEMU they are level-triggered. 256 * 257 * Getting the DTB info about them wrong is awkward for some 258 * guest kernels: 259 * pre-4.8 ignore the DT and leave the interrupt configured 260 * with whatever the GIC reset value (or the bootloader) left it at 261 * 4.8 before rc6 honour the incorrect data by programming it back 262 * into the GIC, causing problems 263 * 4.8rc6 and later ignore the DT and always write "level triggered" 264 * into the GIC 265 * 266 * For backwards-compatibility, virt-2.8 and earlier will continue 267 * to say these are edge-triggered, but later machines will report 268 * the correct information. 269 */ 270 ARMCPU *armcpu; 271 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 272 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 273 274 if (vmc->claim_edge_triggered_timers) { 275 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 276 } 277 278 if (vms->gic_version == 2) { 279 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 280 GIC_FDT_IRQ_PPI_CPU_WIDTH, 281 (1 << vms->smp_cpus) - 1); 282 } 283 284 qemu_fdt_add_subnode(vms->fdt, "/timer"); 285 286 armcpu = ARM_CPU(qemu_get_cpu(0)); 287 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 288 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 289 qemu_fdt_setprop(vms->fdt, "/timer", "compatible", 290 compat, sizeof(compat)); 291 } else { 292 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible", 293 "arm,armv7-timer"); 294 } 295 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0); 296 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts", 297 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 298 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 299 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 300 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 301 } 302 303 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 304 { 305 int cpu; 306 int addr_cells = 1; 307 const MachineState *ms = MACHINE(vms); 308 309 /* 310 * From Documentation/devicetree/bindings/arm/cpus.txt 311 * On ARM v8 64-bit systems value should be set to 2, 312 * that corresponds to the MPIDR_EL1 register size. 313 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 314 * in the system, #address-cells can be set to 1, since 315 * MPIDR_EL1[63:32] bits are not used for CPUs 316 * identification. 317 * 318 * Here we actually don't know whether our system is 32- or 64-bit one. 319 * The simplest way to go is to examine affinity IDs of all our CPUs. If 320 * at least one of them has Aff3 populated, we set #address-cells to 2. 321 */ 322 for (cpu = 0; cpu < vms->smp_cpus; cpu++) { 323 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 324 325 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 326 addr_cells = 2; 327 break; 328 } 329 } 330 331 qemu_fdt_add_subnode(vms->fdt, "/cpus"); 332 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); 333 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); 334 335 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { 336 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 337 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 338 CPUState *cs = CPU(armcpu); 339 340 qemu_fdt_add_subnode(vms->fdt, nodename); 341 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); 342 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 343 armcpu->dtb_compatible); 344 345 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED 346 && vms->smp_cpus > 1) { 347 qemu_fdt_setprop_string(vms->fdt, nodename, 348 "enable-method", "psci"); 349 } 350 351 if (addr_cells == 2) { 352 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", 353 armcpu->mp_affinity); 354 } else { 355 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", 356 armcpu->mp_affinity); 357 } 358 359 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 360 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", 361 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 362 } 363 364 g_free(nodename); 365 } 366 } 367 368 static void fdt_add_its_gic_node(VirtMachineState *vms) 369 { 370 char *nodename; 371 372 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 373 nodename = g_strdup_printf("/intc/its@%" PRIx64, 374 vms->memmap[VIRT_GIC_ITS].base); 375 qemu_fdt_add_subnode(vms->fdt, nodename); 376 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 377 "arm,gic-v3-its"); 378 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); 379 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 380 2, vms->memmap[VIRT_GIC_ITS].base, 381 2, vms->memmap[VIRT_GIC_ITS].size); 382 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); 383 g_free(nodename); 384 } 385 386 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 387 { 388 char *nodename; 389 390 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 391 vms->memmap[VIRT_GIC_V2M].base); 392 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 393 qemu_fdt_add_subnode(vms->fdt, nodename); 394 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 395 "arm,gic-v2m-frame"); 396 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); 397 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 398 2, vms->memmap[VIRT_GIC_V2M].base, 399 2, vms->memmap[VIRT_GIC_V2M].size); 400 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); 401 g_free(nodename); 402 } 403 404 static void fdt_add_gic_node(VirtMachineState *vms) 405 { 406 char *nodename; 407 408 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt); 409 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle); 410 411 nodename = g_strdup_printf("/intc@%" PRIx64, 412 vms->memmap[VIRT_GIC_DIST].base); 413 qemu_fdt_add_subnode(vms->fdt, nodename); 414 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 3); 415 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-controller", NULL, 0); 416 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2); 417 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2); 418 qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0); 419 if (vms->gic_version == 3) { 420 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 421 422 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 423 "arm,gic-v3"); 424 425 qemu_fdt_setprop_cell(vms->fdt, nodename, 426 "#redistributor-regions", nb_redist_regions); 427 428 if (nb_redist_regions == 1) { 429 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 430 2, vms->memmap[VIRT_GIC_DIST].base, 431 2, vms->memmap[VIRT_GIC_DIST].size, 432 2, vms->memmap[VIRT_GIC_REDIST].base, 433 2, vms->memmap[VIRT_GIC_REDIST].size); 434 } else { 435 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 436 2, vms->memmap[VIRT_GIC_DIST].base, 437 2, vms->memmap[VIRT_GIC_DIST].size, 438 2, vms->memmap[VIRT_GIC_REDIST].base, 439 2, vms->memmap[VIRT_GIC_REDIST].size, 440 2, vms->memmap[VIRT_GIC_REDIST2].base, 441 2, vms->memmap[VIRT_GIC_REDIST2].size); 442 } 443 444 if (vms->virt) { 445 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 446 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 447 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 448 } 449 } else { 450 /* 'cortex-a15-gic' means 'GIC v2' */ 451 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 452 "arm,cortex-a15-gic"); 453 if (!vms->virt) { 454 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 455 2, vms->memmap[VIRT_GIC_DIST].base, 456 2, vms->memmap[VIRT_GIC_DIST].size, 457 2, vms->memmap[VIRT_GIC_CPU].base, 458 2, vms->memmap[VIRT_GIC_CPU].size); 459 } else { 460 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 461 2, vms->memmap[VIRT_GIC_DIST].base, 462 2, vms->memmap[VIRT_GIC_DIST].size, 463 2, vms->memmap[VIRT_GIC_CPU].base, 464 2, vms->memmap[VIRT_GIC_CPU].size, 465 2, vms->memmap[VIRT_GIC_HYP].base, 466 2, vms->memmap[VIRT_GIC_HYP].size, 467 2, vms->memmap[VIRT_GIC_VCPU].base, 468 2, vms->memmap[VIRT_GIC_VCPU].size); 469 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 470 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 471 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 472 } 473 } 474 475 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle); 476 g_free(nodename); 477 } 478 479 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 480 { 481 CPUState *cpu; 482 ARMCPU *armcpu; 483 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 484 485 CPU_FOREACH(cpu) { 486 armcpu = ARM_CPU(cpu); 487 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 488 return; 489 } 490 if (kvm_enabled()) { 491 if (kvm_irqchip_in_kernel()) { 492 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 493 } 494 kvm_arm_pmu_init(cpu); 495 } 496 } 497 498 if (vms->gic_version == 2) { 499 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 500 GIC_FDT_IRQ_PPI_CPU_WIDTH, 501 (1 << vms->smp_cpus) - 1); 502 } 503 504 armcpu = ARM_CPU(qemu_get_cpu(0)); 505 qemu_fdt_add_subnode(vms->fdt, "/pmu"); 506 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 507 const char compat[] = "arm,armv8-pmuv3"; 508 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible", 509 compat, sizeof(compat)); 510 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts", 511 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 512 } 513 } 514 515 static void create_its(VirtMachineState *vms, DeviceState *gicdev) 516 { 517 const char *itsclass = its_class_name(); 518 DeviceState *dev; 519 520 if (!itsclass) { 521 /* Do nothing if not supported */ 522 return; 523 } 524 525 dev = qdev_create(NULL, itsclass); 526 527 object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3", 528 &error_abort); 529 qdev_init_nofail(dev); 530 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 531 532 fdt_add_its_gic_node(vms); 533 } 534 535 static void create_v2m(VirtMachineState *vms, qemu_irq *pic) 536 { 537 int i; 538 int irq = vms->irqmap[VIRT_GIC_V2M]; 539 DeviceState *dev; 540 541 dev = qdev_create(NULL, "arm-gicv2m"); 542 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 543 qdev_prop_set_uint32(dev, "base-spi", irq); 544 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 545 qdev_init_nofail(dev); 546 547 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 548 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 549 } 550 551 fdt_add_v2m_gic_node(vms); 552 } 553 554 static void create_gic(VirtMachineState *vms, qemu_irq *pic) 555 { 556 /* We create a standalone GIC */ 557 DeviceState *gicdev; 558 SysBusDevice *gicbusdev; 559 const char *gictype; 560 int type = vms->gic_version, i; 561 uint32_t nb_redist_regions = 0; 562 563 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 564 565 gicdev = qdev_create(NULL, gictype); 566 qdev_prop_set_uint32(gicdev, "revision", type); 567 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 568 /* Note that the num-irq property counts both internal and external 569 * interrupts; there are always 32 of the former (mandated by GIC spec). 570 */ 571 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 572 if (!kvm_irqchip_in_kernel()) { 573 qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure); 574 } 575 576 if (type == 3) { 577 uint32_t redist0_capacity = 578 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 579 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 580 581 nb_redist_regions = virt_gicv3_redist_region_count(vms); 582 583 qdev_prop_set_uint32(gicdev, "len-redist-region-count", 584 nb_redist_regions); 585 qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count); 586 587 if (nb_redist_regions == 2) { 588 uint32_t redist1_capacity = 589 vms->memmap[VIRT_GIC_REDIST2].size / GICV3_REDIST_SIZE; 590 591 qdev_prop_set_uint32(gicdev, "redist-region-count[1]", 592 MIN(smp_cpus - redist0_count, redist1_capacity)); 593 } 594 } else { 595 if (!kvm_irqchip_in_kernel()) { 596 qdev_prop_set_bit(gicdev, "has-virtualization-extensions", 597 vms->virt); 598 } 599 } 600 qdev_init_nofail(gicdev); 601 gicbusdev = SYS_BUS_DEVICE(gicdev); 602 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 603 if (type == 3) { 604 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 605 if (nb_redist_regions == 2) { 606 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_REDIST2].base); 607 } 608 } else { 609 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 610 if (vms->virt) { 611 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 612 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 613 } 614 } 615 616 /* Wire the outputs from each CPU's generic timer and the GICv3 617 * maintenance interrupt signal to the appropriate GIC PPI inputs, 618 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 619 */ 620 for (i = 0; i < smp_cpus; i++) { 621 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 622 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 623 int irq; 624 /* Mapping from the output timer irq lines from the CPU to the 625 * GIC PPI inputs we use for the virt board. 626 */ 627 const int timer_irq[] = { 628 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 629 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 630 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 631 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 632 }; 633 634 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 635 qdev_connect_gpio_out(cpudev, irq, 636 qdev_get_gpio_in(gicdev, 637 ppibase + timer_irq[irq])); 638 } 639 640 if (type == 3) { 641 qemu_irq irq = qdev_get_gpio_in(gicdev, 642 ppibase + ARCH_GIC_MAINT_IRQ); 643 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 644 0, irq); 645 } else if (vms->virt) { 646 qemu_irq irq = qdev_get_gpio_in(gicdev, 647 ppibase + ARCH_GIC_MAINT_IRQ); 648 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 649 } 650 651 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 652 qdev_get_gpio_in(gicdev, ppibase 653 + VIRTUAL_PMU_IRQ)); 654 655 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 656 sysbus_connect_irq(gicbusdev, i + smp_cpus, 657 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 658 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 659 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 660 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 661 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 662 } 663 664 for (i = 0; i < NUM_IRQS; i++) { 665 pic[i] = qdev_get_gpio_in(gicdev, i); 666 } 667 668 fdt_add_gic_node(vms); 669 670 if (type == 3 && vms->its) { 671 create_its(vms, gicdev); 672 } else if (type == 2) { 673 create_v2m(vms, pic); 674 } 675 } 676 677 static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart, 678 MemoryRegion *mem, Chardev *chr) 679 { 680 char *nodename; 681 hwaddr base = vms->memmap[uart].base; 682 hwaddr size = vms->memmap[uart].size; 683 int irq = vms->irqmap[uart]; 684 const char compat[] = "arm,pl011\0arm,primecell"; 685 const char clocknames[] = "uartclk\0apb_pclk"; 686 DeviceState *dev = qdev_create(NULL, "pl011"); 687 SysBusDevice *s = SYS_BUS_DEVICE(dev); 688 689 qdev_prop_set_chr(dev, "chardev", chr); 690 qdev_init_nofail(dev); 691 memory_region_add_subregion(mem, base, 692 sysbus_mmio_get_region(s, 0)); 693 sysbus_connect_irq(s, 0, pic[irq]); 694 695 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 696 qemu_fdt_add_subnode(vms->fdt, nodename); 697 /* Note that we can't use setprop_string because of the embedded NUL */ 698 qemu_fdt_setprop(vms->fdt, nodename, "compatible", 699 compat, sizeof(compat)); 700 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 701 2, base, 2, size); 702 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 703 GIC_FDT_IRQ_TYPE_SPI, irq, 704 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 705 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks", 706 vms->clock_phandle, vms->clock_phandle); 707 qemu_fdt_setprop(vms->fdt, nodename, "clock-names", 708 clocknames, sizeof(clocknames)); 709 710 if (uart == VIRT_UART) { 711 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); 712 } else { 713 /* Mark as not usable by the normal world */ 714 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 715 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 716 717 qemu_fdt_add_subnode(vms->fdt, "/secure-chosen"); 718 qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path", 719 nodename); 720 } 721 722 g_free(nodename); 723 } 724 725 static void create_rtc(const VirtMachineState *vms, qemu_irq *pic) 726 { 727 char *nodename; 728 hwaddr base = vms->memmap[VIRT_RTC].base; 729 hwaddr size = vms->memmap[VIRT_RTC].size; 730 int irq = vms->irqmap[VIRT_RTC]; 731 const char compat[] = "arm,pl031\0arm,primecell"; 732 733 sysbus_create_simple("pl031", base, pic[irq]); 734 735 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 736 qemu_fdt_add_subnode(vms->fdt, nodename); 737 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 738 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 739 2, base, 2, size); 740 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 741 GIC_FDT_IRQ_TYPE_SPI, irq, 742 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 743 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 744 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 745 g_free(nodename); 746 } 747 748 static DeviceState *gpio_key_dev; 749 static void virt_powerdown_req(Notifier *n, void *opaque) 750 { 751 /* use gpio Pin 3 for power button event */ 752 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 753 } 754 755 static Notifier virt_system_powerdown_notifier = { 756 .notify = virt_powerdown_req 757 }; 758 759 static void create_gpio(const VirtMachineState *vms, qemu_irq *pic) 760 { 761 char *nodename; 762 DeviceState *pl061_dev; 763 hwaddr base = vms->memmap[VIRT_GPIO].base; 764 hwaddr size = vms->memmap[VIRT_GPIO].size; 765 int irq = vms->irqmap[VIRT_GPIO]; 766 const char compat[] = "arm,pl061\0arm,primecell"; 767 768 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); 769 770 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); 771 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 772 qemu_fdt_add_subnode(vms->fdt, nodename); 773 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 774 2, base, 2, size); 775 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 776 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); 777 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); 778 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 779 GIC_FDT_IRQ_TYPE_SPI, irq, 780 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 781 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 782 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 783 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); 784 785 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 786 qdev_get_gpio_in(pl061_dev, 3)); 787 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); 788 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); 789 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); 790 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); 791 792 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); 793 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", 794 "label", "GPIO Key Poweroff"); 795 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", 796 KEY_POWER); 797 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", 798 "gpios", phandle, 3, 0); 799 800 /* connect powerdown request */ 801 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier); 802 803 g_free(nodename); 804 } 805 806 static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic) 807 { 808 int i; 809 hwaddr size = vms->memmap[VIRT_MMIO].size; 810 811 /* We create the transports in forwards order. Since qbus_realize() 812 * prepends (not appends) new child buses, the incrementing loop below will 813 * create a list of virtio-mmio buses with decreasing base addresses. 814 * 815 * When a -device option is processed from the command line, 816 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 817 * order. The upshot is that -device options in increasing command line 818 * order are mapped to virtio-mmio buses with decreasing base addresses. 819 * 820 * When this code was originally written, that arrangement ensured that the 821 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 822 * the first -device on the command line. (The end-to-end order is a 823 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 824 * guest kernel's name-to-address assignment strategy.) 825 * 826 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 827 * the message, if not necessarily the code, of commit 70161ff336. 828 * Therefore the loop now establishes the inverse of the original intent. 829 * 830 * Unfortunately, we can't counteract the kernel change by reversing the 831 * loop; it would break existing command lines. 832 * 833 * In any case, the kernel makes no guarantee about the stability of 834 * enumeration order of virtio devices (as demonstrated by it changing 835 * between kernel versions). For reliable and stable identification 836 * of disks users must use UUIDs or similar mechanisms. 837 */ 838 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 839 int irq = vms->irqmap[VIRT_MMIO] + i; 840 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 841 842 sysbus_create_simple("virtio-mmio", base, pic[irq]); 843 } 844 845 /* We add dtb nodes in reverse order so that they appear in the finished 846 * device tree lowest address first. 847 * 848 * Note that this mapping is independent of the loop above. The previous 849 * loop influences virtio device to virtio transport assignment, whereas 850 * this loop controls how virtio transports are laid out in the dtb. 851 */ 852 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 853 char *nodename; 854 int irq = vms->irqmap[VIRT_MMIO] + i; 855 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 856 857 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 858 qemu_fdt_add_subnode(vms->fdt, nodename); 859 qemu_fdt_setprop_string(vms->fdt, nodename, 860 "compatible", "virtio,mmio"); 861 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 862 2, base, 2, size); 863 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 864 GIC_FDT_IRQ_TYPE_SPI, irq, 865 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 866 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 867 g_free(nodename); 868 } 869 } 870 871 static void create_one_flash(const char *name, hwaddr flashbase, 872 hwaddr flashsize, const char *file, 873 MemoryRegion *sysmem) 874 { 875 /* Create and map a single flash device. We use the same 876 * parameters as the flash devices on the Versatile Express board. 877 */ 878 DriveInfo *dinfo = drive_get_next(IF_PFLASH); 879 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 880 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 881 const uint64_t sectorlength = 256 * 1024; 882 883 if (dinfo) { 884 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 885 &error_abort); 886 } 887 888 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); 889 qdev_prop_set_uint64(dev, "sector-length", sectorlength); 890 qdev_prop_set_uint8(dev, "width", 4); 891 qdev_prop_set_uint8(dev, "device-width", 2); 892 qdev_prop_set_bit(dev, "big-endian", false); 893 qdev_prop_set_uint16(dev, "id0", 0x89); 894 qdev_prop_set_uint16(dev, "id1", 0x18); 895 qdev_prop_set_uint16(dev, "id2", 0x00); 896 qdev_prop_set_uint16(dev, "id3", 0x00); 897 qdev_prop_set_string(dev, "name", name); 898 qdev_init_nofail(dev); 899 900 memory_region_add_subregion(sysmem, flashbase, 901 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 902 903 if (file) { 904 char *fn; 905 int image_size; 906 907 if (drive_get(IF_PFLASH, 0, 0)) { 908 error_report("The contents of the first flash device may be " 909 "specified with -bios or with -drive if=pflash... " 910 "but you cannot use both options at once"); 911 exit(1); 912 } 913 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file); 914 if (!fn) { 915 error_report("Could not find ROM image '%s'", file); 916 exit(1); 917 } 918 image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0)); 919 g_free(fn); 920 if (image_size < 0) { 921 error_report("Could not load ROM image '%s'", file); 922 exit(1); 923 } 924 } 925 } 926 927 static void create_flash(const VirtMachineState *vms, 928 MemoryRegion *sysmem, 929 MemoryRegion *secure_sysmem) 930 { 931 /* Create two flash devices to fill the VIRT_FLASH space in the memmap. 932 * Any file passed via -bios goes in the first of these. 933 * sysmem is the system memory space. secure_sysmem is the secure view 934 * of the system, and the first flash device should be made visible only 935 * there. The second flash device is visible to both secure and nonsecure. 936 * If sysmem == secure_sysmem this means there is no separate Secure 937 * address space and both flash devices are generally visible. 938 */ 939 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 940 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 941 char *nodename; 942 943 create_one_flash("virt.flash0", flashbase, flashsize, 944 bios_name, secure_sysmem); 945 create_one_flash("virt.flash1", flashbase + flashsize, flashsize, 946 NULL, sysmem); 947 948 if (sysmem == secure_sysmem) { 949 /* Report both flash devices as a single node in the DT */ 950 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 951 qemu_fdt_add_subnode(vms->fdt, nodename); 952 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 953 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 954 2, flashbase, 2, flashsize, 955 2, flashbase + flashsize, 2, flashsize); 956 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 957 g_free(nodename); 958 } else { 959 /* Report the devices as separate nodes so we can mark one as 960 * only visible to the secure world. 961 */ 962 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 963 qemu_fdt_add_subnode(vms->fdt, nodename); 964 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 965 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 966 2, flashbase, 2, flashsize); 967 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 968 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 969 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 970 g_free(nodename); 971 972 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 973 qemu_fdt_add_subnode(vms->fdt, nodename); 974 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 975 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 976 2, flashbase + flashsize, 2, flashsize); 977 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 978 g_free(nodename); 979 } 980 } 981 982 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 983 { 984 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 985 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 986 FWCfgState *fw_cfg; 987 char *nodename; 988 989 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 990 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 991 992 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 993 qemu_fdt_add_subnode(vms->fdt, nodename); 994 qemu_fdt_setprop_string(vms->fdt, nodename, 995 "compatible", "qemu,fw-cfg-mmio"); 996 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 997 2, base, 2, size); 998 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 999 g_free(nodename); 1000 return fw_cfg; 1001 } 1002 1003 static void create_pcie_irq_map(const VirtMachineState *vms, 1004 uint32_t gic_phandle, 1005 int first_irq, const char *nodename) 1006 { 1007 int devfn, pin; 1008 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1009 uint32_t *irq_map = full_irq_map; 1010 1011 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1012 for (pin = 0; pin < 4; pin++) { 1013 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1014 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1015 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1016 int i; 1017 1018 uint32_t map[] = { 1019 devfn << 8, 0, 0, /* devfn */ 1020 pin + 1, /* PCI pin */ 1021 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1022 1023 /* Convert map to big endian */ 1024 for (i = 0; i < 10; i++) { 1025 irq_map[i] = cpu_to_be32(map[i]); 1026 } 1027 irq_map += 10; 1028 } 1029 } 1030 1031 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map", 1032 full_irq_map, sizeof(full_irq_map)); 1033 1034 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask", 1035 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 1036 0x7 /* PCI irq */); 1037 } 1038 1039 static void create_smmu(const VirtMachineState *vms, qemu_irq *pic, 1040 PCIBus *bus) 1041 { 1042 char *node; 1043 const char compat[] = "arm,smmu-v3"; 1044 int irq = vms->irqmap[VIRT_SMMU]; 1045 int i; 1046 hwaddr base = vms->memmap[VIRT_SMMU].base; 1047 hwaddr size = vms->memmap[VIRT_SMMU].size; 1048 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1049 DeviceState *dev; 1050 1051 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1052 return; 1053 } 1054 1055 dev = qdev_create(NULL, "arm-smmuv3"); 1056 1057 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", 1058 &error_abort); 1059 qdev_init_nofail(dev); 1060 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1061 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1062 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 1063 } 1064 1065 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1066 qemu_fdt_add_subnode(vms->fdt, node); 1067 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat)); 1068 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size); 1069 1070 qemu_fdt_setprop_cells(vms->fdt, node, "interrupts", 1071 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1072 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1073 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1074 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1075 1076 qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names, 1077 sizeof(irq_names)); 1078 1079 qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle); 1080 qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk"); 1081 qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0); 1082 1083 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1); 1084 1085 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle); 1086 g_free(node); 1087 } 1088 1089 static void create_pcie(VirtMachineState *vms, qemu_irq *pic) 1090 { 1091 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1092 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1093 hwaddr base_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].base; 1094 hwaddr size_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].size; 1095 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1096 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1097 hwaddr base_ecam, size_ecam; 1098 hwaddr base = base_mmio; 1099 int nr_pcie_buses; 1100 int irq = vms->irqmap[VIRT_PCIE]; 1101 MemoryRegion *mmio_alias; 1102 MemoryRegion *mmio_reg; 1103 MemoryRegion *ecam_alias; 1104 MemoryRegion *ecam_reg; 1105 DeviceState *dev; 1106 char *nodename; 1107 int i, ecam_id; 1108 PCIHostState *pci; 1109 1110 dev = qdev_create(NULL, TYPE_GPEX_HOST); 1111 qdev_init_nofail(dev); 1112 1113 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1114 base_ecam = vms->memmap[ecam_id].base; 1115 size_ecam = vms->memmap[ecam_id].size; 1116 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1117 /* Map only the first size_ecam bytes of ECAM space */ 1118 ecam_alias = g_new0(MemoryRegion, 1); 1119 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1120 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1121 ecam_reg, 0, size_ecam); 1122 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1123 1124 /* Map the MMIO window into system address space so as to expose 1125 * the section of PCI MMIO space which starts at the same base address 1126 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1127 * the window). 1128 */ 1129 mmio_alias = g_new0(MemoryRegion, 1); 1130 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1131 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1132 mmio_reg, base_mmio, size_mmio); 1133 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1134 1135 if (vms->highmem) { 1136 /* Map high MMIO space */ 1137 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1138 1139 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1140 mmio_reg, base_mmio_high, size_mmio_high); 1141 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1142 high_mmio_alias); 1143 } 1144 1145 /* Map IO port space */ 1146 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1147 1148 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1149 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 1150 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1151 } 1152 1153 pci = PCI_HOST_BRIDGE(dev); 1154 if (pci->bus) { 1155 for (i = 0; i < nb_nics; i++) { 1156 NICInfo *nd = &nd_table[i]; 1157 1158 if (!nd->model) { 1159 nd->model = g_strdup("virtio"); 1160 } 1161 1162 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1163 } 1164 } 1165 1166 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1167 qemu_fdt_add_subnode(vms->fdt, nodename); 1168 qemu_fdt_setprop_string(vms->fdt, nodename, 1169 "compatible", "pci-host-ecam-generic"); 1170 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci"); 1171 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3); 1172 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2); 1173 qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0); 1174 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0, 1175 nr_pcie_buses - 1); 1176 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1177 1178 if (vms->msi_phandle) { 1179 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", 1180 vms->msi_phandle); 1181 } 1182 1183 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1184 2, base_ecam, 2, size_ecam); 1185 1186 if (vms->highmem) { 1187 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1188 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1189 2, base_pio, 2, size_pio, 1190 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1191 2, base_mmio, 2, size_mmio, 1192 1, FDT_PCI_RANGE_MMIO_64BIT, 1193 2, base_mmio_high, 1194 2, base_mmio_high, 2, size_mmio_high); 1195 } else { 1196 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1197 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1198 2, base_pio, 2, size_pio, 1199 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1200 2, base_mmio, 2, size_mmio); 1201 } 1202 1203 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); 1204 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); 1205 1206 if (vms->iommu) { 1207 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt); 1208 1209 create_smmu(vms, pic, pci->bus); 1210 1211 qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map", 1212 0x0, vms->iommu_phandle, 0x0, 0x10000); 1213 } 1214 1215 g_free(nodename); 1216 } 1217 1218 static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic) 1219 { 1220 DeviceState *dev; 1221 SysBusDevice *s; 1222 int i; 1223 MemoryRegion *sysmem = get_system_memory(); 1224 1225 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1226 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1227 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1228 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1229 qdev_init_nofail(dev); 1230 vms->platform_bus_dev = dev; 1231 1232 s = SYS_BUS_DEVICE(dev); 1233 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1234 int irqn = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1235 sysbus_connect_irq(s, i, pic[irqn]); 1236 } 1237 1238 memory_region_add_subregion(sysmem, 1239 vms->memmap[VIRT_PLATFORM_BUS].base, 1240 sysbus_mmio_get_region(s, 0)); 1241 } 1242 1243 static void create_secure_ram(VirtMachineState *vms, 1244 MemoryRegion *secure_sysmem) 1245 { 1246 MemoryRegion *secram = g_new(MemoryRegion, 1); 1247 char *nodename; 1248 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1249 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1250 1251 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1252 &error_fatal); 1253 memory_region_add_subregion(secure_sysmem, base, secram); 1254 1255 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1256 qemu_fdt_add_subnode(vms->fdt, nodename); 1257 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory"); 1258 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size); 1259 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1260 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1261 1262 g_free(nodename); 1263 } 1264 1265 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1266 { 1267 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1268 bootinfo); 1269 1270 *fdt_size = board->fdt_size; 1271 return board->fdt; 1272 } 1273 1274 static void virt_build_smbios(VirtMachineState *vms) 1275 { 1276 MachineClass *mc = MACHINE_GET_CLASS(vms); 1277 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1278 uint8_t *smbios_tables, *smbios_anchor; 1279 size_t smbios_tables_len, smbios_anchor_len; 1280 const char *product = "QEMU Virtual Machine"; 1281 1282 if (!vms->fw_cfg) { 1283 return; 1284 } 1285 1286 if (kvm_enabled()) { 1287 product = "KVM Virtual Machine"; 1288 } 1289 1290 smbios_set_defaults("QEMU", product, 1291 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1292 true, SMBIOS_ENTRY_POINT_30); 1293 1294 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, 1295 &smbios_anchor, &smbios_anchor_len); 1296 1297 if (smbios_anchor) { 1298 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1299 smbios_tables, smbios_tables_len); 1300 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1301 smbios_anchor, smbios_anchor_len); 1302 } 1303 } 1304 1305 static 1306 void virt_machine_done(Notifier *notifier, void *data) 1307 { 1308 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1309 machine_done); 1310 ARMCPU *cpu = ARM_CPU(first_cpu); 1311 struct arm_boot_info *info = &vms->bootinfo; 1312 AddressSpace *as = arm_boot_address_space(cpu, info); 1313 1314 /* 1315 * If the user provided a dtb, we assume the dynamic sysbus nodes 1316 * already are integrated there. This corresponds to a use case where 1317 * the dynamic sysbus nodes are complex and their generation is not yet 1318 * supported. In that case the user can take charge of the guest dt 1319 * while qemu takes charge of the qom stuff. 1320 */ 1321 if (info->dtb_filename == NULL) { 1322 platform_bus_add_all_fdt_nodes(vms->fdt, "/intc", 1323 vms->memmap[VIRT_PLATFORM_BUS].base, 1324 vms->memmap[VIRT_PLATFORM_BUS].size, 1325 vms->irqmap[VIRT_PLATFORM_BUS]); 1326 } 1327 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) { 1328 exit(1); 1329 } 1330 1331 virt_acpi_setup(vms); 1332 virt_build_smbios(vms); 1333 } 1334 1335 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1336 { 1337 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1338 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1339 1340 if (!vmc->disallow_affinity_adjustment) { 1341 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1342 * GIC's target-list limitations. 32-bit KVM hosts currently 1343 * always create clusters of 4 CPUs, but that is expected to 1344 * change when they gain support for gicv3. When KVM is enabled 1345 * it will override the changes we make here, therefore our 1346 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1347 * and to improve SGI efficiency. 1348 */ 1349 if (vms->gic_version == 3) { 1350 clustersz = GICV3_TARGETLIST_BITS; 1351 } else { 1352 clustersz = GIC_TARGETLIST_BITS; 1353 } 1354 } 1355 return arm_cpu_mp_affinity(idx, clustersz); 1356 } 1357 1358 static void machvirt_init(MachineState *machine) 1359 { 1360 VirtMachineState *vms = VIRT_MACHINE(machine); 1361 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1362 MachineClass *mc = MACHINE_GET_CLASS(machine); 1363 const CPUArchIdList *possible_cpus; 1364 qemu_irq pic[NUM_IRQS]; 1365 MemoryRegion *sysmem = get_system_memory(); 1366 MemoryRegion *secure_sysmem = NULL; 1367 int n, virt_max_cpus; 1368 MemoryRegion *ram = g_new(MemoryRegion, 1); 1369 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); 1370 bool aarch64 = true; 1371 1372 /* We can probe only here because during property set 1373 * KVM is not available yet 1374 */ 1375 if (vms->gic_version <= 0) { 1376 /* "host" or "max" */ 1377 if (!kvm_enabled()) { 1378 if (vms->gic_version == 0) { 1379 error_report("gic-version=host requires KVM"); 1380 exit(1); 1381 } else { 1382 /* "max": currently means 3 for TCG */ 1383 vms->gic_version = 3; 1384 } 1385 } else { 1386 vms->gic_version = kvm_arm_vgic_probe(); 1387 if (!vms->gic_version) { 1388 error_report( 1389 "Unable to determine GIC version supported by host"); 1390 exit(1); 1391 } 1392 } 1393 } 1394 1395 if (!cpu_type_valid(machine->cpu_type)) { 1396 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 1397 exit(1); 1398 } 1399 1400 /* If we have an EL3 boot ROM then the assumption is that it will 1401 * implement PSCI itself, so disable QEMU's internal implementation 1402 * so it doesn't get in the way. Instead of starting secondary 1403 * CPUs in PSCI powerdown state we will start them all running and 1404 * let the boot ROM sort them out. 1405 * The usual case is that we do use QEMU's PSCI implementation; 1406 * if the guest has EL2 then we will use SMC as the conduit, 1407 * and otherwise we will use HVC (for backwards compatibility and 1408 * because if we're using KVM then we must use HVC). 1409 */ 1410 if (vms->secure && firmware_loaded) { 1411 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1412 } else if (vms->virt) { 1413 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 1414 } else { 1415 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 1416 } 1417 1418 /* The maximum number of CPUs depends on the GIC version, or on how 1419 * many redistributors we can fit into the memory map. 1420 */ 1421 if (vms->gic_version == 3) { 1422 virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 1423 virt_max_cpus += vms->memmap[VIRT_GIC_REDIST2].size / GICV3_REDIST_SIZE; 1424 } else { 1425 virt_max_cpus = GIC_NCPU; 1426 } 1427 1428 if (max_cpus > virt_max_cpus) { 1429 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1430 "supported by machine 'mach-virt' (%d)", 1431 max_cpus, virt_max_cpus); 1432 exit(1); 1433 } 1434 1435 vms->smp_cpus = smp_cpus; 1436 1437 if (machine->ram_size > vms->memmap[VIRT_MEM].size) { 1438 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB); 1439 exit(1); 1440 } 1441 1442 if (vms->virt && kvm_enabled()) { 1443 error_report("mach-virt: KVM does not support providing " 1444 "Virtualization extensions to the guest CPU"); 1445 exit(1); 1446 } 1447 1448 if (vms->secure) { 1449 if (kvm_enabled()) { 1450 error_report("mach-virt: KVM does not support Security extensions"); 1451 exit(1); 1452 } 1453 1454 /* The Secure view of the world is the same as the NonSecure, 1455 * but with a few extra devices. Create it as a container region 1456 * containing the system memory at low priority; any secure-only 1457 * devices go in at higher priority and take precedence. 1458 */ 1459 secure_sysmem = g_new(MemoryRegion, 1); 1460 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1461 UINT64_MAX); 1462 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1463 } 1464 1465 create_fdt(vms); 1466 1467 possible_cpus = mc->possible_cpu_arch_ids(machine); 1468 for (n = 0; n < possible_cpus->len; n++) { 1469 Object *cpuobj; 1470 CPUState *cs; 1471 1472 if (n >= smp_cpus) { 1473 break; 1474 } 1475 1476 cpuobj = object_new(possible_cpus->cpus[n].type); 1477 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 1478 "mp-affinity", NULL); 1479 1480 cs = CPU(cpuobj); 1481 cs->cpu_index = n; 1482 1483 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 1484 &error_fatal); 1485 1486 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 1487 1488 if (!vms->secure) { 1489 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1490 } 1491 1492 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { 1493 object_property_set_bool(cpuobj, false, "has_el2", NULL); 1494 } 1495 1496 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1497 object_property_set_int(cpuobj, vms->psci_conduit, 1498 "psci-conduit", NULL); 1499 1500 /* Secondary CPUs start in PSCI powered-down state */ 1501 if (n > 0) { 1502 object_property_set_bool(cpuobj, true, 1503 "start-powered-off", NULL); 1504 } 1505 } 1506 1507 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { 1508 object_property_set_bool(cpuobj, false, "pmu", NULL); 1509 } 1510 1511 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1512 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, 1513 "reset-cbar", &error_abort); 1514 } 1515 1516 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1517 &error_abort); 1518 if (vms->secure) { 1519 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1520 "secure-memory", &error_abort); 1521 } 1522 1523 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 1524 object_unref(cpuobj); 1525 } 1526 fdt_add_timer_nodes(vms); 1527 fdt_add_cpu_nodes(vms); 1528 1529 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", 1530 machine->ram_size); 1531 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); 1532 1533 create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem); 1534 1535 create_gic(vms, pic); 1536 1537 fdt_add_pmu_nodes(vms); 1538 1539 create_uart(vms, pic, VIRT_UART, sysmem, serial_hd(0)); 1540 1541 if (vms->secure) { 1542 create_secure_ram(vms, secure_sysmem); 1543 create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 1544 } 1545 1546 vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64); 1547 1548 create_rtc(vms, pic); 1549 1550 create_pcie(vms, pic); 1551 1552 create_gpio(vms, pic); 1553 1554 /* Create mmio transports, so the user can create virtio backends 1555 * (which will be automatically plugged in to the transports). If 1556 * no backend is created the transport will just sit harmlessly idle. 1557 */ 1558 create_virtio_devices(vms, pic); 1559 1560 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 1561 rom_set_fw(vms->fw_cfg); 1562 1563 create_platform_bus(vms, pic); 1564 1565 vms->bootinfo.ram_size = machine->ram_size; 1566 vms->bootinfo.kernel_filename = machine->kernel_filename; 1567 vms->bootinfo.kernel_cmdline = machine->kernel_cmdline; 1568 vms->bootinfo.initrd_filename = machine->initrd_filename; 1569 vms->bootinfo.nb_cpus = smp_cpus; 1570 vms->bootinfo.board_id = -1; 1571 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 1572 vms->bootinfo.get_dtb = machvirt_dtb; 1573 vms->bootinfo.skip_dtb_autoload = true; 1574 vms->bootinfo.firmware_loaded = firmware_loaded; 1575 arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo); 1576 1577 vms->machine_done.notify = virt_machine_done; 1578 qemu_add_machine_init_done_notifier(&vms->machine_done); 1579 } 1580 1581 static bool virt_get_secure(Object *obj, Error **errp) 1582 { 1583 VirtMachineState *vms = VIRT_MACHINE(obj); 1584 1585 return vms->secure; 1586 } 1587 1588 static void virt_set_secure(Object *obj, bool value, Error **errp) 1589 { 1590 VirtMachineState *vms = VIRT_MACHINE(obj); 1591 1592 vms->secure = value; 1593 } 1594 1595 static bool virt_get_virt(Object *obj, Error **errp) 1596 { 1597 VirtMachineState *vms = VIRT_MACHINE(obj); 1598 1599 return vms->virt; 1600 } 1601 1602 static void virt_set_virt(Object *obj, bool value, Error **errp) 1603 { 1604 VirtMachineState *vms = VIRT_MACHINE(obj); 1605 1606 vms->virt = value; 1607 } 1608 1609 static bool virt_get_highmem(Object *obj, Error **errp) 1610 { 1611 VirtMachineState *vms = VIRT_MACHINE(obj); 1612 1613 return vms->highmem; 1614 } 1615 1616 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1617 { 1618 VirtMachineState *vms = VIRT_MACHINE(obj); 1619 1620 vms->highmem = value; 1621 } 1622 1623 static bool virt_get_its(Object *obj, Error **errp) 1624 { 1625 VirtMachineState *vms = VIRT_MACHINE(obj); 1626 1627 return vms->its; 1628 } 1629 1630 static void virt_set_its(Object *obj, bool value, Error **errp) 1631 { 1632 VirtMachineState *vms = VIRT_MACHINE(obj); 1633 1634 vms->its = value; 1635 } 1636 1637 static char *virt_get_gic_version(Object *obj, Error **errp) 1638 { 1639 VirtMachineState *vms = VIRT_MACHINE(obj); 1640 const char *val = vms->gic_version == 3 ? "3" : "2"; 1641 1642 return g_strdup(val); 1643 } 1644 1645 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 1646 { 1647 VirtMachineState *vms = VIRT_MACHINE(obj); 1648 1649 if (!strcmp(value, "3")) { 1650 vms->gic_version = 3; 1651 } else if (!strcmp(value, "2")) { 1652 vms->gic_version = 2; 1653 } else if (!strcmp(value, "host")) { 1654 vms->gic_version = 0; /* Will probe later */ 1655 } else if (!strcmp(value, "max")) { 1656 vms->gic_version = -1; /* Will probe later */ 1657 } else { 1658 error_setg(errp, "Invalid gic-version value"); 1659 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 1660 } 1661 } 1662 1663 static char *virt_get_iommu(Object *obj, Error **errp) 1664 { 1665 VirtMachineState *vms = VIRT_MACHINE(obj); 1666 1667 switch (vms->iommu) { 1668 case VIRT_IOMMU_NONE: 1669 return g_strdup("none"); 1670 case VIRT_IOMMU_SMMUV3: 1671 return g_strdup("smmuv3"); 1672 default: 1673 g_assert_not_reached(); 1674 } 1675 } 1676 1677 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 1678 { 1679 VirtMachineState *vms = VIRT_MACHINE(obj); 1680 1681 if (!strcmp(value, "smmuv3")) { 1682 vms->iommu = VIRT_IOMMU_SMMUV3; 1683 } else if (!strcmp(value, "none")) { 1684 vms->iommu = VIRT_IOMMU_NONE; 1685 } else { 1686 error_setg(errp, "Invalid iommu value"); 1687 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 1688 } 1689 } 1690 1691 static CpuInstanceProperties 1692 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1693 { 1694 MachineClass *mc = MACHINE_GET_CLASS(ms); 1695 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1696 1697 assert(cpu_index < possible_cpus->len); 1698 return possible_cpus->cpus[cpu_index].props; 1699 } 1700 1701 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1702 { 1703 return idx % nb_numa_nodes; 1704 } 1705 1706 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1707 { 1708 int n; 1709 VirtMachineState *vms = VIRT_MACHINE(ms); 1710 1711 if (ms->possible_cpus) { 1712 assert(ms->possible_cpus->len == max_cpus); 1713 return ms->possible_cpus; 1714 } 1715 1716 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1717 sizeof(CPUArchId) * max_cpus); 1718 ms->possible_cpus->len = max_cpus; 1719 for (n = 0; n < ms->possible_cpus->len; n++) { 1720 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1721 ms->possible_cpus->cpus[n].arch_id = 1722 virt_cpu_mp_affinity(vms, n); 1723 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1724 ms->possible_cpus->cpus[n].props.thread_id = n; 1725 } 1726 return ms->possible_cpus; 1727 } 1728 1729 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1730 DeviceState *dev, Error **errp) 1731 { 1732 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 1733 1734 if (vms->platform_bus_dev) { 1735 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) { 1736 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 1737 SYS_BUS_DEVICE(dev)); 1738 } 1739 } 1740 } 1741 1742 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1743 DeviceState *dev) 1744 { 1745 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) { 1746 return HOTPLUG_HANDLER(machine); 1747 } 1748 1749 return NULL; 1750 } 1751 1752 static void virt_machine_class_init(ObjectClass *oc, void *data) 1753 { 1754 MachineClass *mc = MACHINE_CLASS(oc); 1755 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1756 1757 mc->init = machvirt_init; 1758 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 1759 * The value may be reduced later when we have more information about the 1760 * configuration of the particular instance. 1761 */ 1762 mc->max_cpus = 512; 1763 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 1764 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 1765 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1766 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 1767 mc->block_default_type = IF_VIRTIO; 1768 mc->no_cdrom = 1; 1769 mc->pci_allow_0_address = true; 1770 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 1771 mc->minimum_page_bits = 12; 1772 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1773 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1774 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 1775 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1776 assert(!mc->get_hotplug_handler); 1777 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1778 hc->plug = virt_machine_device_plug_cb; 1779 } 1780 1781 static const TypeInfo virt_machine_info = { 1782 .name = TYPE_VIRT_MACHINE, 1783 .parent = TYPE_MACHINE, 1784 .abstract = true, 1785 .instance_size = sizeof(VirtMachineState), 1786 .class_size = sizeof(VirtMachineClass), 1787 .class_init = virt_machine_class_init, 1788 .interfaces = (InterfaceInfo[]) { 1789 { TYPE_HOTPLUG_HANDLER }, 1790 { } 1791 }, 1792 }; 1793 1794 static void machvirt_machine_init(void) 1795 { 1796 type_register_static(&virt_machine_info); 1797 } 1798 type_init(machvirt_machine_init); 1799 1800 static void virt_3_1_instance_init(Object *obj) 1801 { 1802 VirtMachineState *vms = VIRT_MACHINE(obj); 1803 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1804 1805 /* EL3 is disabled by default on virt: this makes us consistent 1806 * between KVM and TCG for this board, and it also allows us to 1807 * boot UEFI blobs which assume no TrustZone support. 1808 */ 1809 vms->secure = false; 1810 object_property_add_bool(obj, "secure", virt_get_secure, 1811 virt_set_secure, NULL); 1812 object_property_set_description(obj, "secure", 1813 "Set on/off to enable/disable the ARM " 1814 "Security Extensions (TrustZone)", 1815 NULL); 1816 1817 /* EL2 is also disabled by default, for similar reasons */ 1818 vms->virt = false; 1819 object_property_add_bool(obj, "virtualization", virt_get_virt, 1820 virt_set_virt, NULL); 1821 object_property_set_description(obj, "virtualization", 1822 "Set on/off to enable/disable emulating a " 1823 "guest CPU which implements the ARM " 1824 "Virtualization Extensions", 1825 NULL); 1826 1827 /* High memory is enabled by default */ 1828 vms->highmem = true; 1829 object_property_add_bool(obj, "highmem", virt_get_highmem, 1830 virt_set_highmem, NULL); 1831 object_property_set_description(obj, "highmem", 1832 "Set on/off to enable/disable using " 1833 "physical address space above 32 bits", 1834 NULL); 1835 /* Default GIC type is v2 */ 1836 vms->gic_version = 2; 1837 object_property_add_str(obj, "gic-version", virt_get_gic_version, 1838 virt_set_gic_version, NULL); 1839 object_property_set_description(obj, "gic-version", 1840 "Set GIC version. " 1841 "Valid values are 2, 3 and host", NULL); 1842 1843 vms->highmem_ecam = !vmc->no_highmem_ecam; 1844 1845 if (vmc->no_its) { 1846 vms->its = false; 1847 } else { 1848 /* Default allows ITS instantiation */ 1849 vms->its = true; 1850 object_property_add_bool(obj, "its", virt_get_its, 1851 virt_set_its, NULL); 1852 object_property_set_description(obj, "its", 1853 "Set on/off to enable/disable " 1854 "ITS instantiation", 1855 NULL); 1856 } 1857 1858 /* Default disallows iommu instantiation */ 1859 vms->iommu = VIRT_IOMMU_NONE; 1860 object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu, NULL); 1861 object_property_set_description(obj, "iommu", 1862 "Set the IOMMU type. " 1863 "Valid values are none and smmuv3", 1864 NULL); 1865 1866 vms->memmap = a15memmap; 1867 vms->irqmap = a15irqmap; 1868 } 1869 1870 static void virt_machine_3_1_options(MachineClass *mc) 1871 { 1872 } 1873 DEFINE_VIRT_MACHINE_AS_LATEST(3, 1) 1874 1875 #define VIRT_COMPAT_3_0 \ 1876 HW_COMPAT_3_0 1877 1878 static void virt_3_0_instance_init(Object *obj) 1879 { 1880 virt_3_1_instance_init(obj); 1881 } 1882 1883 static void virt_machine_3_0_options(MachineClass *mc) 1884 { 1885 virt_machine_3_1_options(mc); 1886 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_3_0); 1887 } 1888 DEFINE_VIRT_MACHINE(3, 0) 1889 1890 #define VIRT_COMPAT_2_12 \ 1891 HW_COMPAT_2_12 1892 1893 static void virt_2_12_instance_init(Object *obj) 1894 { 1895 virt_3_0_instance_init(obj); 1896 } 1897 1898 static void virt_machine_2_12_options(MachineClass *mc) 1899 { 1900 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1901 1902 virt_machine_3_0_options(mc); 1903 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_12); 1904 vmc->no_highmem_ecam = true; 1905 mc->max_cpus = 255; 1906 } 1907 DEFINE_VIRT_MACHINE(2, 12) 1908 1909 #define VIRT_COMPAT_2_11 \ 1910 HW_COMPAT_2_11 1911 1912 static void virt_2_11_instance_init(Object *obj) 1913 { 1914 virt_2_12_instance_init(obj); 1915 } 1916 1917 static void virt_machine_2_11_options(MachineClass *mc) 1918 { 1919 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1920 1921 virt_machine_2_12_options(mc); 1922 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_11); 1923 vmc->smbios_old_sys_ver = true; 1924 } 1925 DEFINE_VIRT_MACHINE(2, 11) 1926 1927 #define VIRT_COMPAT_2_10 \ 1928 HW_COMPAT_2_10 1929 1930 static void virt_2_10_instance_init(Object *obj) 1931 { 1932 virt_2_11_instance_init(obj); 1933 } 1934 1935 static void virt_machine_2_10_options(MachineClass *mc) 1936 { 1937 virt_machine_2_11_options(mc); 1938 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_10); 1939 /* before 2.11 we never faulted accesses to bad addresses */ 1940 mc->ignore_memory_transaction_failures = true; 1941 } 1942 DEFINE_VIRT_MACHINE(2, 10) 1943 1944 #define VIRT_COMPAT_2_9 \ 1945 HW_COMPAT_2_9 1946 1947 static void virt_2_9_instance_init(Object *obj) 1948 { 1949 virt_2_10_instance_init(obj); 1950 } 1951 1952 static void virt_machine_2_9_options(MachineClass *mc) 1953 { 1954 virt_machine_2_10_options(mc); 1955 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_9); 1956 } 1957 DEFINE_VIRT_MACHINE(2, 9) 1958 1959 #define VIRT_COMPAT_2_8 \ 1960 HW_COMPAT_2_8 1961 1962 static void virt_2_8_instance_init(Object *obj) 1963 { 1964 virt_2_9_instance_init(obj); 1965 } 1966 1967 static void virt_machine_2_8_options(MachineClass *mc) 1968 { 1969 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1970 1971 virt_machine_2_9_options(mc); 1972 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_8); 1973 /* For 2.8 and earlier we falsely claimed in the DT that 1974 * our timers were edge-triggered, not level-triggered. 1975 */ 1976 vmc->claim_edge_triggered_timers = true; 1977 } 1978 DEFINE_VIRT_MACHINE(2, 8) 1979 1980 #define VIRT_COMPAT_2_7 \ 1981 HW_COMPAT_2_7 1982 1983 static void virt_2_7_instance_init(Object *obj) 1984 { 1985 virt_2_8_instance_init(obj); 1986 } 1987 1988 static void virt_machine_2_7_options(MachineClass *mc) 1989 { 1990 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1991 1992 virt_machine_2_8_options(mc); 1993 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_7); 1994 /* ITS was introduced with 2.8 */ 1995 vmc->no_its = true; 1996 /* Stick with 1K pages for migration compatibility */ 1997 mc->minimum_page_bits = 0; 1998 } 1999 DEFINE_VIRT_MACHINE(2, 7) 2000 2001 #define VIRT_COMPAT_2_6 \ 2002 HW_COMPAT_2_6 2003 2004 static void virt_2_6_instance_init(Object *obj) 2005 { 2006 virt_2_7_instance_init(obj); 2007 } 2008 2009 static void virt_machine_2_6_options(MachineClass *mc) 2010 { 2011 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2012 2013 virt_machine_2_7_options(mc); 2014 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6); 2015 vmc->disallow_affinity_adjustment = true; 2016 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 2017 vmc->no_pmu = true; 2018 } 2019 DEFINE_VIRT_MACHINE(2, 6) 2020