1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/datadir.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "hw/sysbus.h" 37 #include "hw/arm/boot.h" 38 #include "hw/arm/primecell.h" 39 #include "hw/arm/virt.h" 40 #include "hw/block/flash.h" 41 #include "hw/vfio/vfio-calxeda-xgmac.h" 42 #include "hw/vfio/vfio-amd-xgbe.h" 43 #include "hw/display/ramfb.h" 44 #include "net/net.h" 45 #include "system/device_tree.h" 46 #include "system/numa.h" 47 #include "system/runstate.h" 48 #include "system/tpm.h" 49 #include "system/tcg.h" 50 #include "system/kvm.h" 51 #include "system/hvf.h" 52 #include "system/qtest.h" 53 #include "hw/loader.h" 54 #include "qapi/error.h" 55 #include "qemu/bitops.h" 56 #include "qemu/cutils.h" 57 #include "qemu/error-report.h" 58 #include "qemu/module.h" 59 #include "hw/pci-host/gpex.h" 60 #include "hw/pci-bridge/pci_expander_bridge.h" 61 #include "hw/virtio/virtio-pci.h" 62 #include "hw/core/sysbus-fdt.h" 63 #include "hw/platform-bus.h" 64 #include "hw/qdev-properties.h" 65 #include "hw/arm/fdt.h" 66 #include "hw/intc/arm_gic.h" 67 #include "hw/intc/arm_gicv3_common.h" 68 #include "hw/intc/arm_gicv3_its_common.h" 69 #include "hw/irq.h" 70 #include "kvm_arm.h" 71 #include "hvf_arm.h" 72 #include "hw/firmware/smbios.h" 73 #include "qapi/visitor.h" 74 #include "qapi/qapi-visit-common.h" 75 #include "qobject/qlist.h" 76 #include "standard-headers/linux/input.h" 77 #include "hw/arm/smmuv3.h" 78 #include "hw/acpi/acpi.h" 79 #include "target/arm/cpu-qom.h" 80 #include "target/arm/internals.h" 81 #include "target/arm/multiprocessing.h" 82 #include "target/arm/gtimer.h" 83 #include "hw/mem/pc-dimm.h" 84 #include "hw/mem/nvdimm.h" 85 #include "hw/acpi/generic_event_device.h" 86 #include "hw/uefi/var-service-api.h" 87 #include "hw/virtio/virtio-md-pci.h" 88 #include "hw/virtio/virtio-iommu.h" 89 #include "hw/char/pl011.h" 90 #include "hw/cxl/cxl.h" 91 #include "hw/cxl/cxl_host.h" 92 #include "qemu/guest-random.h" 93 94 static GlobalProperty arm_virt_compat[] = { 95 { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "48" }, 96 }; 97 static const size_t arm_virt_compat_len = G_N_ELEMENTS(arm_virt_compat); 98 99 /* 100 * This cannot be called from the virt_machine_class_init() because 101 * TYPE_VIRT_MACHINE is abstract and mc->compat_props g_ptr_array_new() 102 * only is called on virt non abstract class init. 103 */ 104 static void arm_virt_compat_set(MachineClass *mc) 105 { 106 compat_props_add(mc->compat_props, arm_virt_compat, 107 arm_virt_compat_len); 108 } 109 110 #define DEFINE_VIRT_MACHINE_IMPL(latest, ...) \ 111 static void MACHINE_VER_SYM(class_init, virt, __VA_ARGS__)( \ 112 ObjectClass *oc, \ 113 const void *data) \ 114 { \ 115 MachineClass *mc = MACHINE_CLASS(oc); \ 116 arm_virt_compat_set(mc); \ 117 MACHINE_VER_SYM(options, virt, __VA_ARGS__)(mc); \ 118 mc->desc = "QEMU " MACHINE_VER_STR(__VA_ARGS__) " ARM Virtual Machine"; \ 119 MACHINE_VER_DEPRECATION(__VA_ARGS__); \ 120 if (latest) { \ 121 mc->alias = "virt"; \ 122 } \ 123 } \ 124 static const TypeInfo MACHINE_VER_SYM(info, virt, __VA_ARGS__) = \ 125 { \ 126 .name = MACHINE_VER_TYPE_NAME("virt", __VA_ARGS__), \ 127 .parent = TYPE_VIRT_MACHINE, \ 128 .class_init = MACHINE_VER_SYM(class_init, virt, __VA_ARGS__), \ 129 }; \ 130 static void MACHINE_VER_SYM(register, virt, __VA_ARGS__)(void) \ 131 { \ 132 MACHINE_VER_DELETION(__VA_ARGS__); \ 133 type_register_static(&MACHINE_VER_SYM(info, virt, __VA_ARGS__)); \ 134 } \ 135 type_init(MACHINE_VER_SYM(register, virt, __VA_ARGS__)); 136 137 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 138 DEFINE_VIRT_MACHINE_IMPL(true, major, minor) 139 #define DEFINE_VIRT_MACHINE(major, minor) \ 140 DEFINE_VIRT_MACHINE_IMPL(false, major, minor) 141 142 143 /* Number of external interrupt lines to configure the GIC with */ 144 #define NUM_IRQS 256 145 146 #define PLATFORM_BUS_NUM_IRQS 64 147 148 /* Legacy RAM limit in GB (< version 4.0) */ 149 #define LEGACY_RAMLIMIT_GB 255 150 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 151 152 /* Addresses and sizes of our components. 153 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 154 * 128MB..256MB is used for miscellaneous device I/O. 155 * 256MB..1GB is reserved for possible future PCI support (ie where the 156 * PCI memory window will go if we add a PCI host controller). 157 * 1GB and up is RAM (which may happily spill over into the 158 * high memory region beyond 4GB). 159 * This represents a compromise between how much RAM can be given to 160 * a 32 bit VM and leaving space for expansion and in particular for PCI. 161 * Note that devices should generally be placed at multiples of 0x10000, 162 * to accommodate guests using 64K pages. 163 */ 164 static const MemMapEntry base_memmap[] = { 165 /* Space up to 0x8000000 is reserved for a boot ROM */ 166 [VIRT_FLASH] = { 0, 0x08000000 }, 167 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 168 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 169 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 170 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 171 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 172 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 173 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 174 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 175 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 176 /* This redistributor space allows up to 2*64kB*123 CPUs */ 177 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 178 [VIRT_UART0] = { 0x09000000, 0x00001000 }, 179 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 180 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 181 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 182 [VIRT_UART1] = { 0x09040000, 0x00001000 }, 183 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 184 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 185 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 186 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 187 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, 188 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, 189 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 190 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 191 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 192 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 193 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 194 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 195 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 196 /* Actual RAM size depends on initial RAM and device memory settings */ 197 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 198 }; 199 200 /* Update the docs for highmem-mmio-size when changing this default */ 201 #define DEFAULT_HIGH_PCIE_MMIO_SIZE_GB 512 202 #define DEFAULT_HIGH_PCIE_MMIO_SIZE (DEFAULT_HIGH_PCIE_MMIO_SIZE_GB * GiB) 203 204 /* 205 * Highmem IO Regions: This memory map is floating, located after the RAM. 206 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 207 * top of the RAM, so that its base get the same alignment as the size, 208 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 209 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 210 * Note the extended_memmap is sized so that it eventually also includes the 211 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 212 * index of base_memmap). 213 * 214 * The memory map for these Highmem IO Regions can be in legacy or compact 215 * layout, depending on 'compact-highmem' property. With legacy layout, the 216 * PA space for one specific region is always reserved, even if the region 217 * has been disabled or doesn't fit into the PA space. However, the PA space 218 * for the region won't be reserved in these circumstances with compact layout. 219 * 220 * Note that the highmem-mmio-size property will update the high PCIE MMIO size 221 * field in this array. 222 */ 223 static MemMapEntry extended_memmap[] = { 224 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 225 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 226 [VIRT_CXL_HOST] = { 0x0, 64 * KiB * 16 }, /* 16 UID */ 227 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 228 /* Second PCIe window */ 229 [VIRT_HIGH_PCIE_MMIO] = { 0x0, DEFAULT_HIGH_PCIE_MMIO_SIZE }, 230 /* Any CXL Fixed memory windows come here */ 231 }; 232 233 static const int a15irqmap[] = { 234 [VIRT_UART0] = 1, 235 [VIRT_RTC] = 2, 236 [VIRT_PCIE] = 3, /* ... to 6 */ 237 [VIRT_GPIO] = 7, 238 [VIRT_UART1] = 8, 239 [VIRT_ACPI_GED] = 9, 240 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 241 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 242 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 243 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 244 }; 245 246 static void create_randomness(MachineState *ms, const char *node) 247 { 248 struct { 249 uint64_t kaslr; 250 uint8_t rng[32]; 251 } seed; 252 253 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { 254 return; 255 } 256 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr); 257 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); 258 } 259 260 /* 261 * The CPU object always exposes the NS EL2 virt timer IRQ line, 262 * but we don't want to advertise it to the guest in the dtb or ACPI 263 * table unless it's really going to do something. 264 */ 265 static bool ns_el2_virt_timer_present(void) 266 { 267 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0)); 268 CPUARMState *env = &cpu->env; 269 270 return arm_feature(env, ARM_FEATURE_AARCH64) && 271 arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu); 272 } 273 274 static void create_fdt(VirtMachineState *vms) 275 { 276 MachineState *ms = MACHINE(vms); 277 int nb_numa_nodes = ms->numa_state->num_nodes; 278 void *fdt = create_device_tree(&vms->fdt_size); 279 280 if (!fdt) { 281 error_report("create_device_tree() failed"); 282 exit(1); 283 } 284 285 ms->fdt = fdt; 286 287 /* Header */ 288 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 289 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 290 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 291 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt"); 292 293 /* 294 * For QEMU, all DMA is coherent. Advertising this in the root node 295 * has two benefits: 296 * 297 * - It avoids potential bugs where we forget to mark a DMA 298 * capable device as being dma-coherent 299 * - It avoids spurious warnings from the Linux kernel about 300 * devices which can't do DMA at all 301 */ 302 qemu_fdt_setprop(fdt, "/", "dma-coherent", NULL, 0); 303 304 /* /chosen must exist for load_dtb to fill in necessary properties later */ 305 qemu_fdt_add_subnode(fdt, "/chosen"); 306 if (vms->dtb_randomness) { 307 create_randomness(ms, "/chosen"); 308 } 309 310 if (vms->secure) { 311 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 312 if (vms->dtb_randomness) { 313 create_randomness(ms, "/secure-chosen"); 314 } 315 } 316 317 qemu_fdt_add_subnode(fdt, "/aliases"); 318 319 /* Clock node, for the benefit of the UART. The kernel device tree 320 * binding documentation claims the PL011 node clock properties are 321 * optional but in practice if you omit them the kernel refuses to 322 * probe for the device. 323 */ 324 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 325 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 326 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 327 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 328 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 329 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 330 "clk24mhz"); 331 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 332 333 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 334 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 335 uint32_t *matrix = g_malloc0(size); 336 int idx, i, j; 337 338 for (i = 0; i < nb_numa_nodes; i++) { 339 for (j = 0; j < nb_numa_nodes; j++) { 340 idx = (i * nb_numa_nodes + j) * 3; 341 matrix[idx + 0] = cpu_to_be32(i); 342 matrix[idx + 1] = cpu_to_be32(j); 343 matrix[idx + 2] = 344 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 345 } 346 } 347 348 qemu_fdt_add_subnode(fdt, "/distance-map"); 349 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 350 "numa-distance-map-v1"); 351 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 352 matrix, size); 353 g_free(matrix); 354 } 355 } 356 357 static void fdt_add_timer_nodes(const VirtMachineState *vms) 358 { 359 /* On real hardware these interrupts are level-triggered. 360 * On KVM they were edge-triggered before host kernel version 4.4, 361 * and level-triggered afterwards. 362 * On emulated QEMU they are level-triggered. 363 * 364 * Getting the DTB info about them wrong is awkward for some 365 * guest kernels: 366 * pre-4.8 ignore the DT and leave the interrupt configured 367 * with whatever the GIC reset value (or the bootloader) left it at 368 * 4.8 before rc6 honour the incorrect data by programming it back 369 * into the GIC, causing problems 370 * 4.8rc6 and later ignore the DT and always write "level triggered" 371 * into the GIC 372 * 373 * For backwards-compatibility, virt-2.8 and earlier will continue 374 * to say these are edge-triggered, but later machines will report 375 * the correct information. 376 */ 377 ARMCPU *armcpu; 378 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 379 MachineState *ms = MACHINE(vms); 380 381 if (vms->gic_version == VIRT_GIC_VERSION_2) { 382 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 383 GIC_FDT_IRQ_PPI_CPU_WIDTH, 384 (1 << MACHINE(vms)->smp.cpus) - 1); 385 } 386 387 qemu_fdt_add_subnode(ms->fdt, "/timer"); 388 389 armcpu = ARM_CPU(qemu_get_cpu(0)); 390 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 391 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 392 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", 393 compat, sizeof(compat)); 394 } else { 395 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", 396 "arm,armv7-timer"); 397 } 398 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); 399 if (vms->ns_el2_virt_timer_irq) { 400 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 401 GIC_FDT_IRQ_TYPE_PPI, 402 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, 403 GIC_FDT_IRQ_TYPE_PPI, 404 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, 405 GIC_FDT_IRQ_TYPE_PPI, 406 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, 407 GIC_FDT_IRQ_TYPE_PPI, 408 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags, 409 GIC_FDT_IRQ_TYPE_PPI, 410 INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags); 411 } else { 412 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 413 GIC_FDT_IRQ_TYPE_PPI, 414 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, 415 GIC_FDT_IRQ_TYPE_PPI, 416 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, 417 GIC_FDT_IRQ_TYPE_PPI, 418 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, 419 GIC_FDT_IRQ_TYPE_PPI, 420 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags); 421 } 422 } 423 424 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 425 { 426 int cpu; 427 int addr_cells = 1; 428 const MachineState *ms = MACHINE(vms); 429 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 430 int smp_cpus = ms->smp.cpus; 431 432 /* 433 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml 434 * On ARM v8 64-bit systems value should be set to 2, 435 * that corresponds to the MPIDR_EL1 register size. 436 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 437 * in the system, #address-cells can be set to 1, since 438 * MPIDR_EL1[63:32] bits are not used for CPUs 439 * identification. 440 * 441 * Here we actually don't know whether our system is 32- or 64-bit one. 442 * The simplest way to go is to examine affinity IDs of all our CPUs. If 443 * at least one of them has Aff3 populated, we set #address-cells to 2. 444 */ 445 for (cpu = 0; cpu < smp_cpus; cpu++) { 446 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 447 448 if (arm_cpu_mp_affinity(armcpu) & ARM_AFF3_MASK) { 449 addr_cells = 2; 450 break; 451 } 452 } 453 454 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 455 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); 456 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 457 458 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 459 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 460 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 461 CPUState *cs = CPU(armcpu); 462 463 qemu_fdt_add_subnode(ms->fdt, nodename); 464 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 465 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 466 armcpu->dtb_compatible); 467 468 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { 469 qemu_fdt_setprop_string(ms->fdt, nodename, 470 "enable-method", "psci"); 471 } 472 473 if (addr_cells == 2) { 474 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", 475 arm_cpu_mp_affinity(armcpu)); 476 } else { 477 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", 478 arm_cpu_mp_affinity(armcpu)); 479 } 480 481 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 482 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 483 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 484 } 485 486 if (!vmc->no_cpu_topology) { 487 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 488 qemu_fdt_alloc_phandle(ms->fdt)); 489 } 490 491 g_free(nodename); 492 } 493 494 if (!vmc->no_cpu_topology) { 495 /* 496 * Add vCPU topology description through fdt node cpu-map. 497 * 498 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt 499 * In a SMP system, the hierarchy of CPUs can be defined through 500 * four entities that are used to describe the layout of CPUs in 501 * the system: socket/cluster/core/thread. 502 * 503 * A socket node represents the boundary of system physical package 504 * and its child nodes must be one or more cluster nodes. A system 505 * can contain several layers of clustering within a single physical 506 * package and cluster nodes can be contained in parent cluster nodes. 507 * 508 * Note: currently we only support one layer of clustering within 509 * each physical package. 510 */ 511 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 512 513 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 514 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); 515 char *map_path; 516 517 if (ms->smp.threads > 1) { 518 map_path = g_strdup_printf( 519 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", 520 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), 521 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, 522 (cpu / ms->smp.threads) % ms->smp.cores, 523 cpu % ms->smp.threads); 524 } else { 525 map_path = g_strdup_printf( 526 "/cpus/cpu-map/socket%d/cluster%d/core%d", 527 cpu / (ms->smp.clusters * ms->smp.cores), 528 (cpu / ms->smp.cores) % ms->smp.clusters, 529 cpu % ms->smp.cores); 530 } 531 qemu_fdt_add_path(ms->fdt, map_path); 532 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 533 534 g_free(map_path); 535 g_free(cpu_path); 536 } 537 } 538 } 539 540 static void fdt_add_its_gic_node(VirtMachineState *vms) 541 { 542 char *nodename; 543 MachineState *ms = MACHINE(vms); 544 545 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 546 nodename = g_strdup_printf("/intc/its@%" PRIx64, 547 vms->memmap[VIRT_GIC_ITS].base); 548 qemu_fdt_add_subnode(ms->fdt, nodename); 549 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 550 "arm,gic-v3-its"); 551 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 552 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1); 553 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 554 2, vms->memmap[VIRT_GIC_ITS].base, 555 2, vms->memmap[VIRT_GIC_ITS].size); 556 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 557 g_free(nodename); 558 } 559 560 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 561 { 562 MachineState *ms = MACHINE(vms); 563 char *nodename; 564 565 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 566 vms->memmap[VIRT_GIC_V2M].base); 567 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 568 qemu_fdt_add_subnode(ms->fdt, nodename); 569 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 570 "arm,gic-v2m-frame"); 571 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 572 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 573 2, vms->memmap[VIRT_GIC_V2M].base, 574 2, vms->memmap[VIRT_GIC_V2M].size); 575 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 576 g_free(nodename); 577 } 578 579 static void fdt_add_gic_node(VirtMachineState *vms) 580 { 581 MachineState *ms = MACHINE(vms); 582 char *nodename; 583 584 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 585 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); 586 587 nodename = g_strdup_printf("/intc@%" PRIx64, 588 vms->memmap[VIRT_GIC_DIST].base); 589 qemu_fdt_add_subnode(ms->fdt, nodename); 590 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 591 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 592 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 593 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 594 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 595 if (vms->gic_version != VIRT_GIC_VERSION_2) { 596 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 597 598 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 599 "arm,gic-v3"); 600 601 qemu_fdt_setprop_cell(ms->fdt, nodename, 602 "#redistributor-regions", nb_redist_regions); 603 604 if (nb_redist_regions == 1) { 605 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 606 2, vms->memmap[VIRT_GIC_DIST].base, 607 2, vms->memmap[VIRT_GIC_DIST].size, 608 2, vms->memmap[VIRT_GIC_REDIST].base, 609 2, vms->memmap[VIRT_GIC_REDIST].size); 610 } else { 611 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 612 2, vms->memmap[VIRT_GIC_DIST].base, 613 2, vms->memmap[VIRT_GIC_DIST].size, 614 2, vms->memmap[VIRT_GIC_REDIST].base, 615 2, vms->memmap[VIRT_GIC_REDIST].size, 616 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 617 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 618 } 619 620 if (vms->virt) { 621 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 622 GIC_FDT_IRQ_TYPE_PPI, 623 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), 624 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 625 } 626 } else { 627 /* 'cortex-a15-gic' means 'GIC v2' */ 628 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 629 "arm,cortex-a15-gic"); 630 if (!vms->virt) { 631 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 632 2, vms->memmap[VIRT_GIC_DIST].base, 633 2, vms->memmap[VIRT_GIC_DIST].size, 634 2, vms->memmap[VIRT_GIC_CPU].base, 635 2, vms->memmap[VIRT_GIC_CPU].size); 636 } else { 637 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 638 2, vms->memmap[VIRT_GIC_DIST].base, 639 2, vms->memmap[VIRT_GIC_DIST].size, 640 2, vms->memmap[VIRT_GIC_CPU].base, 641 2, vms->memmap[VIRT_GIC_CPU].size, 642 2, vms->memmap[VIRT_GIC_HYP].base, 643 2, vms->memmap[VIRT_GIC_HYP].size, 644 2, vms->memmap[VIRT_GIC_VCPU].base, 645 2, vms->memmap[VIRT_GIC_VCPU].size); 646 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 647 GIC_FDT_IRQ_TYPE_PPI, 648 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), 649 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 650 } 651 } 652 653 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); 654 g_free(nodename); 655 } 656 657 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 658 { 659 ARMCPU *armcpu = ARM_CPU(first_cpu); 660 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 661 MachineState *ms = MACHINE(vms); 662 663 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 664 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); 665 return; 666 } 667 668 if (vms->gic_version == VIRT_GIC_VERSION_2) { 669 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 670 GIC_FDT_IRQ_PPI_CPU_WIDTH, 671 (1 << MACHINE(vms)->smp.cpus) - 1); 672 } 673 674 qemu_fdt_add_subnode(ms->fdt, "/pmu"); 675 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 676 const char compat[] = "arm,armv8-pmuv3"; 677 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", 678 compat, sizeof(compat)); 679 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", 680 GIC_FDT_IRQ_TYPE_PPI, 681 INTID_TO_PPI(VIRTUAL_PMU_IRQ), irqflags); 682 } 683 } 684 685 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 686 { 687 DeviceState *dev; 688 MachineState *ms = MACHINE(vms); 689 int irq = vms->irqmap[VIRT_ACPI_GED]; 690 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 691 692 if (ms->ram_slots) { 693 event |= ACPI_GED_MEM_HOTPLUG_EVT; 694 } 695 696 if (ms->nvdimms_state->is_enabled) { 697 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 698 } 699 700 dev = qdev_new(TYPE_ACPI_GED); 701 qdev_prop_set_uint32(dev, "ged-event", event); 702 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 703 704 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 705 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 706 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 707 708 return dev; 709 } 710 711 static void create_its(VirtMachineState *vms) 712 { 713 DeviceState *dev; 714 715 assert(vms->its); 716 if (!kvm_irqchip_in_kernel() && !vms->tcg_its) { 717 /* 718 * Do nothing if ITS is neither supported by the host nor emulated by 719 * the machine. 720 */ 721 return; 722 } 723 724 dev = qdev_new(its_class_name()); 725 726 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 727 &error_abort); 728 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 729 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 730 731 fdt_add_its_gic_node(vms); 732 vms->msi_controller = VIRT_MSI_CTRL_ITS; 733 } 734 735 static void create_v2m(VirtMachineState *vms) 736 { 737 int i; 738 int irq = vms->irqmap[VIRT_GIC_V2M]; 739 DeviceState *dev; 740 741 dev = qdev_new("arm-gicv2m"); 742 qdev_prop_set_uint32(dev, "base-spi", irq); 743 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 744 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 745 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 746 747 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 748 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 749 qdev_get_gpio_in(vms->gic, irq + i)); 750 } 751 752 fdt_add_v2m_gic_node(vms); 753 vms->msi_controller = VIRT_MSI_CTRL_GICV2M; 754 } 755 756 /* 757 * If the CPU has FEAT_NMI, then turn on the NMI support in the GICv3 too. 758 * It's permitted to have a configuration with NMI in the CPU (and thus the 759 * GICv3 CPU interface) but not in the distributor/redistributors, but it's 760 * not very useful. 761 */ 762 static bool gicv3_nmi_present(VirtMachineState *vms) 763 { 764 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0)); 765 766 return tcg_enabled() && cpu_isar_feature(aa64_nmi, cpu) && 767 (vms->gic_version != VIRT_GIC_VERSION_2); 768 } 769 770 static void create_gic(VirtMachineState *vms, MemoryRegion *mem) 771 { 772 MachineState *ms = MACHINE(vms); 773 /* We create a standalone GIC */ 774 SysBusDevice *gicbusdev; 775 const char *gictype; 776 int i; 777 unsigned int smp_cpus = ms->smp.cpus; 778 uint32_t nb_redist_regions = 0; 779 int revision; 780 781 if (vms->gic_version == VIRT_GIC_VERSION_2) { 782 gictype = gic_class_name(); 783 } else { 784 gictype = gicv3_class_name(); 785 } 786 787 switch (vms->gic_version) { 788 case VIRT_GIC_VERSION_2: 789 revision = 2; 790 break; 791 case VIRT_GIC_VERSION_3: 792 revision = 3; 793 break; 794 case VIRT_GIC_VERSION_4: 795 revision = 4; 796 break; 797 default: 798 g_assert_not_reached(); 799 } 800 801 if (kvm_enabled() && vms->virt && 802 (revision != 3 || !kvm_irqchip_in_kernel())) { 803 error_report("KVM EL2 is only supported with in-kernel GICv3"); 804 exit(1); 805 } 806 807 vms->gic = qdev_new(gictype); 808 qdev_prop_set_uint32(vms->gic, "revision", revision); 809 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 810 /* Note that the num-irq property counts both internal and external 811 * interrupts; there are always 32 of the former (mandated by GIC spec). 812 */ 813 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 814 if (!kvm_irqchip_in_kernel()) { 815 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 816 } 817 818 if (vms->gic_version != VIRT_GIC_VERSION_2) { 819 QList *redist_region_count; 820 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); 821 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 822 823 nb_redist_regions = virt_gicv3_redist_region_count(vms); 824 825 redist_region_count = qlist_new(); 826 qlist_append_int(redist_region_count, redist0_count); 827 if (nb_redist_regions == 2) { 828 uint32_t redist1_capacity = 829 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 830 831 qlist_append_int(redist_region_count, 832 MIN(smp_cpus - redist0_count, redist1_capacity)); 833 } 834 qdev_prop_set_array(vms->gic, "redist-region-count", 835 redist_region_count); 836 837 if (!kvm_irqchip_in_kernel()) { 838 if (vms->tcg_its) { 839 object_property_set_link(OBJECT(vms->gic), "sysmem", 840 OBJECT(mem), &error_fatal); 841 qdev_prop_set_bit(vms->gic, "has-lpi", true); 842 } 843 } else if (vms->virt) { 844 qdev_prop_set_uint32(vms->gic, "maintenance-interrupt-id", 845 ARCH_GIC_MAINT_IRQ); 846 } 847 } else { 848 if (!kvm_irqchip_in_kernel()) { 849 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 850 vms->virt); 851 } 852 } 853 854 if (gicv3_nmi_present(vms)) { 855 qdev_prop_set_bit(vms->gic, "has-nmi", true); 856 } 857 858 gicbusdev = SYS_BUS_DEVICE(vms->gic); 859 sysbus_realize_and_unref(gicbusdev, &error_fatal); 860 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 861 if (vms->gic_version != VIRT_GIC_VERSION_2) { 862 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 863 if (nb_redist_regions == 2) { 864 sysbus_mmio_map(gicbusdev, 2, 865 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 866 } 867 } else { 868 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 869 if (vms->virt) { 870 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 871 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 872 } 873 } 874 875 /* Wire the outputs from each CPU's generic timer and the GICv3 876 * maintenance interrupt signal to the appropriate GIC PPI inputs, 877 * and the GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to the 878 * CPU's inputs. 879 */ 880 for (i = 0; i < smp_cpus; i++) { 881 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 882 int intidbase = NUM_IRQS + i * GIC_INTERNAL; 883 /* Mapping from the output timer irq lines from the CPU to the 884 * GIC PPI inputs we use for the virt board. 885 */ 886 const int timer_irq[] = { 887 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 888 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 889 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 890 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 891 [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, 892 [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ, 893 [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ, 894 }; 895 896 for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 897 qdev_connect_gpio_out(cpudev, irq, 898 qdev_get_gpio_in(vms->gic, 899 intidbase + timer_irq[irq])); 900 } 901 902 if (vms->gic_version != VIRT_GIC_VERSION_2) { 903 qemu_irq irq = qdev_get_gpio_in(vms->gic, 904 intidbase + ARCH_GIC_MAINT_IRQ); 905 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 906 0, irq); 907 } else if (vms->virt) { 908 qemu_irq irq = qdev_get_gpio_in(vms->gic, 909 intidbase + ARCH_GIC_MAINT_IRQ); 910 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 911 } 912 913 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 914 qdev_get_gpio_in(vms->gic, intidbase 915 + VIRTUAL_PMU_IRQ)); 916 917 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 918 sysbus_connect_irq(gicbusdev, i + smp_cpus, 919 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 920 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 921 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 922 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 923 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 924 925 if (vms->gic_version != VIRT_GIC_VERSION_2) { 926 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, 927 qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); 928 sysbus_connect_irq(gicbusdev, i + 5 * smp_cpus, 929 qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); 930 } 931 } 932 933 fdt_add_gic_node(vms); 934 935 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) { 936 create_its(vms); 937 } else if (vms->gic_version == VIRT_GIC_VERSION_2) { 938 create_v2m(vms); 939 } 940 } 941 942 static void create_uart(const VirtMachineState *vms, int uart, 943 MemoryRegion *mem, Chardev *chr, bool secure) 944 { 945 char *nodename; 946 hwaddr base = vms->memmap[uart].base; 947 hwaddr size = vms->memmap[uart].size; 948 int irq = vms->irqmap[uart]; 949 const char compat[] = "arm,pl011\0arm,primecell"; 950 const char clocknames[] = "uartclk\0apb_pclk"; 951 DeviceState *dev = qdev_new(TYPE_PL011); 952 SysBusDevice *s = SYS_BUS_DEVICE(dev); 953 MachineState *ms = MACHINE(vms); 954 955 qdev_prop_set_chr(dev, "chardev", chr); 956 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 957 memory_region_add_subregion(mem, base, 958 sysbus_mmio_get_region(s, 0)); 959 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 960 961 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 962 qemu_fdt_add_subnode(ms->fdt, nodename); 963 /* Note that we can't use setprop_string because of the embedded NUL */ 964 qemu_fdt_setprop(ms->fdt, nodename, "compatible", 965 compat, sizeof(compat)); 966 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 967 2, base, 2, size); 968 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 969 GIC_FDT_IRQ_TYPE_SPI, irq, 970 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 971 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", 972 vms->clock_phandle, vms->clock_phandle); 973 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", 974 clocknames, sizeof(clocknames)); 975 976 if (uart == VIRT_UART0) { 977 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 978 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", nodename); 979 } else { 980 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial1", nodename); 981 } 982 if (secure) { 983 /* Mark as not usable by the normal world */ 984 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 985 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 986 987 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", 988 nodename); 989 } 990 991 g_free(nodename); 992 } 993 994 static void create_rtc(const VirtMachineState *vms) 995 { 996 char *nodename; 997 hwaddr base = vms->memmap[VIRT_RTC].base; 998 hwaddr size = vms->memmap[VIRT_RTC].size; 999 int irq = vms->irqmap[VIRT_RTC]; 1000 const char compat[] = "arm,pl031\0arm,primecell"; 1001 MachineState *ms = MACHINE(vms); 1002 1003 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 1004 1005 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 1006 qemu_fdt_add_subnode(ms->fdt, nodename); 1007 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 1008 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1009 2, base, 2, size); 1010 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1011 GIC_FDT_IRQ_TYPE_SPI, irq, 1012 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1013 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1014 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1015 g_free(nodename); 1016 } 1017 1018 static DeviceState *gpio_key_dev; 1019 static void virt_powerdown_req(Notifier *n, void *opaque) 1020 { 1021 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 1022 1023 if (s->acpi_dev) { 1024 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 1025 } else { 1026 /* use gpio Pin for power button event */ 1027 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 1028 } 1029 } 1030 1031 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, 1032 uint32_t phandle) 1033 { 1034 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 1035 qdev_get_gpio_in(pl061_dev, 1036 GPIO_PIN_POWER_BUTTON)); 1037 1038 qemu_fdt_add_subnode(fdt, "/gpio-keys"); 1039 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); 1040 1041 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); 1042 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", 1043 "label", "GPIO Key Poweroff"); 1044 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", 1045 KEY_POWER); 1046 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", 1047 "gpios", phandle, GPIO_PIN_POWER_BUTTON, 0); 1048 } 1049 1050 #define SECURE_GPIO_POWEROFF 0 1051 #define SECURE_GPIO_RESET 1 1052 1053 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, 1054 uint32_t phandle) 1055 { 1056 DeviceState *gpio_pwr_dev; 1057 1058 /* gpio-pwr */ 1059 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); 1060 1061 /* connect secure pl061 to gpio-pwr */ 1062 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, 1063 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); 1064 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, 1065 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); 1066 1067 qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); 1068 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", 1069 "gpio-poweroff"); 1070 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", 1071 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); 1072 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); 1073 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", 1074 "okay"); 1075 1076 qemu_fdt_add_subnode(fdt, "/gpio-restart"); 1077 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", 1078 "gpio-restart"); 1079 qemu_fdt_setprop_cells(fdt, "/gpio-restart", 1080 "gpios", phandle, SECURE_GPIO_RESET, 0); 1081 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); 1082 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", 1083 "okay"); 1084 } 1085 1086 static void create_gpio_devices(const VirtMachineState *vms, int gpio, 1087 MemoryRegion *mem) 1088 { 1089 char *nodename; 1090 DeviceState *pl061_dev; 1091 hwaddr base = vms->memmap[gpio].base; 1092 hwaddr size = vms->memmap[gpio].size; 1093 int irq = vms->irqmap[gpio]; 1094 const char compat[] = "arm,pl061\0arm,primecell"; 1095 SysBusDevice *s; 1096 MachineState *ms = MACHINE(vms); 1097 1098 pl061_dev = qdev_new("pl061"); 1099 /* Pull lines down to 0 if not driven by the PL061 */ 1100 qdev_prop_set_uint32(pl061_dev, "pullups", 0); 1101 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); 1102 s = SYS_BUS_DEVICE(pl061_dev); 1103 sysbus_realize_and_unref(s, &error_fatal); 1104 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); 1105 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 1106 1107 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); 1108 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 1109 qemu_fdt_add_subnode(ms->fdt, nodename); 1110 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1111 2, base, 2, size); 1112 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 1113 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); 1114 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); 1115 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1116 GIC_FDT_IRQ_TYPE_SPI, irq, 1117 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1118 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1119 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1120 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); 1121 1122 if (gpio != VIRT_GPIO) { 1123 /* Mark as not usable by the normal world */ 1124 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1125 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1126 } 1127 g_free(nodename); 1128 1129 /* Child gpio devices */ 1130 if (gpio == VIRT_GPIO) { 1131 create_gpio_keys(ms->fdt, pl061_dev, phandle); 1132 } else { 1133 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); 1134 } 1135 } 1136 1137 static void create_virtio_devices(const VirtMachineState *vms) 1138 { 1139 int i; 1140 hwaddr size = vms->memmap[VIRT_MMIO].size; 1141 MachineState *ms = MACHINE(vms); 1142 1143 /* We create the transports in forwards order. Since qbus_realize() 1144 * prepends (not appends) new child buses, the incrementing loop below will 1145 * create a list of virtio-mmio buses with decreasing base addresses. 1146 * 1147 * When a -device option is processed from the command line, 1148 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 1149 * order. The upshot is that -device options in increasing command line 1150 * order are mapped to virtio-mmio buses with decreasing base addresses. 1151 * 1152 * When this code was originally written, that arrangement ensured that the 1153 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 1154 * the first -device on the command line. (The end-to-end order is a 1155 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 1156 * guest kernel's name-to-address assignment strategy.) 1157 * 1158 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 1159 * the message, if not necessarily the code, of commit 70161ff336. 1160 * Therefore the loop now establishes the inverse of the original intent. 1161 * 1162 * Unfortunately, we can't counteract the kernel change by reversing the 1163 * loop; it would break existing command lines. 1164 * 1165 * In any case, the kernel makes no guarantee about the stability of 1166 * enumeration order of virtio devices (as demonstrated by it changing 1167 * between kernel versions). For reliable and stable identification 1168 * of disks users must use UUIDs or similar mechanisms. 1169 */ 1170 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 1171 int irq = vms->irqmap[VIRT_MMIO] + i; 1172 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1173 1174 sysbus_create_simple("virtio-mmio", base, 1175 qdev_get_gpio_in(vms->gic, irq)); 1176 } 1177 1178 /* We add dtb nodes in reverse order so that they appear in the finished 1179 * device tree lowest address first. 1180 * 1181 * Note that this mapping is independent of the loop above. The previous 1182 * loop influences virtio device to virtio transport assignment, whereas 1183 * this loop controls how virtio transports are laid out in the dtb. 1184 */ 1185 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 1186 char *nodename; 1187 int irq = vms->irqmap[VIRT_MMIO] + i; 1188 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1189 1190 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 1191 qemu_fdt_add_subnode(ms->fdt, nodename); 1192 qemu_fdt_setprop_string(ms->fdt, nodename, 1193 "compatible", "virtio,mmio"); 1194 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1195 2, base, 2, size); 1196 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1197 GIC_FDT_IRQ_TYPE_SPI, irq, 1198 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1199 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1200 g_free(nodename); 1201 } 1202 } 1203 1204 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 1205 1206 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 1207 const char *name, 1208 const char *alias_prop_name) 1209 { 1210 /* 1211 * Create a single flash device. We use the same parameters as 1212 * the flash devices on the Versatile Express board. 1213 */ 1214 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 1215 1216 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 1217 qdev_prop_set_uint8(dev, "width", 4); 1218 qdev_prop_set_uint8(dev, "device-width", 2); 1219 qdev_prop_set_bit(dev, "big-endian", false); 1220 qdev_prop_set_uint16(dev, "id0", 0x89); 1221 qdev_prop_set_uint16(dev, "id1", 0x18); 1222 qdev_prop_set_uint16(dev, "id2", 0x00); 1223 qdev_prop_set_uint16(dev, "id3", 0x00); 1224 qdev_prop_set_string(dev, "name", name); 1225 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 1226 object_property_add_alias(OBJECT(vms), alias_prop_name, 1227 OBJECT(dev), "drive"); 1228 return PFLASH_CFI01(dev); 1229 } 1230 1231 static void virt_flash_create(VirtMachineState *vms) 1232 { 1233 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 1234 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 1235 } 1236 1237 static void virt_flash_map1(PFlashCFI01 *flash, 1238 hwaddr base, hwaddr size, 1239 MemoryRegion *sysmem) 1240 { 1241 DeviceState *dev = DEVICE(flash); 1242 1243 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 1244 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 1245 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 1246 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1247 1248 memory_region_add_subregion(sysmem, base, 1249 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1250 0)); 1251 } 1252 1253 static void virt_flash_map(VirtMachineState *vms, 1254 MemoryRegion *sysmem, 1255 MemoryRegion *secure_sysmem) 1256 { 1257 /* 1258 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 1259 * sysmem is the system memory space. secure_sysmem is the secure view 1260 * of the system, and the first flash device should be made visible only 1261 * there. The second flash device is visible to both secure and nonsecure. 1262 * If sysmem == secure_sysmem this means there is no separate Secure 1263 * address space and both flash devices are generally visible. 1264 */ 1265 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1266 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1267 1268 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1269 secure_sysmem); 1270 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1271 sysmem); 1272 } 1273 1274 static void virt_flash_fdt(VirtMachineState *vms, 1275 MemoryRegion *sysmem, 1276 MemoryRegion *secure_sysmem) 1277 { 1278 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1279 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1280 MachineState *ms = MACHINE(vms); 1281 char *nodename; 1282 1283 if (sysmem == secure_sysmem) { 1284 /* Report both flash devices as a single node in the DT */ 1285 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1286 qemu_fdt_add_subnode(ms->fdt, nodename); 1287 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1288 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1289 2, flashbase, 2, flashsize, 1290 2, flashbase + flashsize, 2, flashsize); 1291 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1292 g_free(nodename); 1293 } else { 1294 /* 1295 * Report the devices as separate nodes so we can mark one as 1296 * only visible to the secure world. 1297 */ 1298 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1299 qemu_fdt_add_subnode(ms->fdt, nodename); 1300 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1301 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1302 2, flashbase, 2, flashsize); 1303 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1304 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1305 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1306 g_free(nodename); 1307 1308 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize); 1309 qemu_fdt_add_subnode(ms->fdt, nodename); 1310 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1311 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1312 2, flashbase + flashsize, 2, flashsize); 1313 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1314 g_free(nodename); 1315 } 1316 } 1317 1318 static bool virt_firmware_init(VirtMachineState *vms, 1319 MemoryRegion *sysmem, 1320 MemoryRegion *secure_sysmem) 1321 { 1322 int i; 1323 const char *bios_name; 1324 BlockBackend *pflash_blk0; 1325 1326 /* Map legacy -drive if=pflash to machine properties */ 1327 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1328 pflash_cfi01_legacy_drive(vms->flash[i], 1329 drive_get(IF_PFLASH, 0, i)); 1330 } 1331 1332 virt_flash_map(vms, sysmem, secure_sysmem); 1333 1334 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1335 1336 bios_name = MACHINE(vms)->firmware; 1337 if (bios_name) { 1338 char *fname; 1339 MemoryRegion *mr; 1340 int image_size; 1341 1342 if (pflash_blk0) { 1343 error_report("The contents of the first flash device may be " 1344 "specified with -bios or with -drive if=pflash... " 1345 "but you cannot use both options at once"); 1346 exit(1); 1347 } 1348 1349 /* Fall back to -bios */ 1350 1351 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1352 if (!fname) { 1353 error_report("Could not find ROM image '%s'", bios_name); 1354 exit(1); 1355 } 1356 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1357 image_size = load_image_mr(fname, mr); 1358 g_free(fname); 1359 if (image_size < 0) { 1360 error_report("Could not load ROM image '%s'", bios_name); 1361 exit(1); 1362 } 1363 } 1364 1365 return pflash_blk0 || bios_name; 1366 } 1367 1368 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1369 { 1370 MachineState *ms = MACHINE(vms); 1371 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1372 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1373 FWCfgState *fw_cfg; 1374 char *nodename; 1375 1376 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1377 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1378 1379 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1380 qemu_fdt_add_subnode(ms->fdt, nodename); 1381 qemu_fdt_setprop_string(ms->fdt, nodename, 1382 "compatible", "qemu,fw-cfg-mmio"); 1383 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1384 2, base, 2, size); 1385 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1386 g_free(nodename); 1387 return fw_cfg; 1388 } 1389 1390 static void create_pcie_irq_map(const MachineState *ms, 1391 uint32_t gic_phandle, 1392 int first_irq, const char *nodename) 1393 { 1394 int devfn, pin; 1395 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1396 uint32_t *irq_map = full_irq_map; 1397 1398 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1399 for (pin = 0; pin < 4; pin++) { 1400 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1401 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1402 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1403 int i; 1404 1405 uint32_t map[] = { 1406 devfn << 8, 0, 0, /* devfn */ 1407 pin + 1, /* PCI pin */ 1408 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1409 1410 /* Convert map to big endian */ 1411 for (i = 0; i < 10; i++) { 1412 irq_map[i] = cpu_to_be32(map[i]); 1413 } 1414 irq_map += 10; 1415 } 1416 } 1417 1418 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", 1419 full_irq_map, sizeof(full_irq_map)); 1420 1421 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 1422 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ 1423 0, 0, 1424 0x7 /* PCI irq */); 1425 } 1426 1427 static void create_smmu(const VirtMachineState *vms, 1428 PCIBus *bus) 1429 { 1430 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1431 char *node; 1432 const char compat[] = "arm,smmu-v3"; 1433 int irq = vms->irqmap[VIRT_SMMU]; 1434 int i; 1435 hwaddr base = vms->memmap[VIRT_SMMU].base; 1436 hwaddr size = vms->memmap[VIRT_SMMU].size; 1437 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1438 DeviceState *dev; 1439 MachineState *ms = MACHINE(vms); 1440 1441 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1442 return; 1443 } 1444 1445 dev = qdev_new(TYPE_ARM_SMMUV3); 1446 1447 if (!vmc->no_nested_smmu) { 1448 object_property_set_str(OBJECT(dev), "stage", "nested", &error_fatal); 1449 } 1450 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1451 &error_abort); 1452 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1453 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1454 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1455 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1456 qdev_get_gpio_in(vms->gic, irq + i)); 1457 } 1458 1459 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1460 qemu_fdt_add_subnode(ms->fdt, node); 1461 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1462 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); 1463 1464 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", 1465 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1466 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1467 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1468 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1469 1470 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, 1471 sizeof(irq_names)); 1472 1473 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); 1474 1475 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1476 1477 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1478 g_free(node); 1479 } 1480 1481 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1482 { 1483 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1484 uint16_t bdf = vms->virtio_iommu_bdf; 1485 MachineState *ms = MACHINE(vms); 1486 char *node; 1487 1488 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1489 1490 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename, 1491 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1492 qemu_fdt_add_subnode(ms->fdt, node); 1493 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1494 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 1495 1, bdf << 8, 1, 0, 1, 0, 1496 1, 0, 1, 0); 1497 1498 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1499 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1500 g_free(node); 1501 1502 if (!vms->default_bus_bypass_iommu) { 1503 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", 1504 0x0, vms->iommu_phandle, 0x0, bdf, 1505 bdf + 1, vms->iommu_phandle, bdf + 1, 1506 0xffff - bdf); 1507 } 1508 } 1509 1510 static void create_pcie(VirtMachineState *vms) 1511 { 1512 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1513 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1514 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1515 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1516 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1517 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1518 hwaddr base_ecam, size_ecam; 1519 hwaddr base = base_mmio; 1520 int nr_pcie_buses; 1521 int irq = vms->irqmap[VIRT_PCIE]; 1522 MemoryRegion *mmio_alias; 1523 MemoryRegion *mmio_reg; 1524 MemoryRegion *ecam_alias; 1525 MemoryRegion *ecam_reg; 1526 DeviceState *dev; 1527 char *nodename; 1528 int i, ecam_id; 1529 PCIHostState *pci; 1530 MachineState *ms = MACHINE(vms); 1531 MachineClass *mc = MACHINE_GET_CLASS(ms); 1532 1533 dev = qdev_new(TYPE_GPEX_HOST); 1534 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1535 1536 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1537 base_ecam = vms->memmap[ecam_id].base; 1538 size_ecam = vms->memmap[ecam_id].size; 1539 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1540 /* Map only the first size_ecam bytes of ECAM space */ 1541 ecam_alias = g_new0(MemoryRegion, 1); 1542 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1543 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1544 ecam_reg, 0, size_ecam); 1545 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1546 1547 /* Map the MMIO window into system address space so as to expose 1548 * the section of PCI MMIO space which starts at the same base address 1549 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1550 * the window). 1551 */ 1552 mmio_alias = g_new0(MemoryRegion, 1); 1553 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1554 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1555 mmio_reg, base_mmio, size_mmio); 1556 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1557 1558 if (vms->highmem_mmio) { 1559 /* Map high MMIO space */ 1560 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1561 1562 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1563 mmio_reg, base_mmio_high, size_mmio_high); 1564 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1565 high_mmio_alias); 1566 } 1567 1568 /* Map IO port space */ 1569 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1570 1571 for (i = 0; i < PCI_NUM_PINS; i++) { 1572 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1573 qdev_get_gpio_in(vms->gic, irq + i)); 1574 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1575 } 1576 1577 pci = PCI_HOST_BRIDGE(dev); 1578 pci->bypass_iommu = vms->default_bus_bypass_iommu; 1579 vms->bus = pci->bus; 1580 if (vms->bus) { 1581 pci_init_nic_devices(pci->bus, mc->default_nic); 1582 } 1583 1584 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1585 qemu_fdt_add_subnode(ms->fdt, nodename); 1586 qemu_fdt_setprop_string(ms->fdt, nodename, 1587 "compatible", "pci-host-ecam-generic"); 1588 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 1589 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 1590 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 1591 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 1592 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 1593 nr_pcie_buses - 1); 1594 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1595 1596 if (vms->msi_phandle) { 1597 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 1598 0, vms->msi_phandle, 0, 0x10000); 1599 } 1600 1601 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1602 2, base_ecam, 2, size_ecam); 1603 1604 if (vms->highmem_mmio) { 1605 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1606 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1607 2, base_pio, 2, size_pio, 1608 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1609 2, base_mmio, 2, size_mmio, 1610 1, FDT_PCI_RANGE_MMIO_64BIT, 1611 2, base_mmio_high, 1612 2, base_mmio_high, 2, size_mmio_high); 1613 } else { 1614 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1615 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1616 2, base_pio, 2, size_pio, 1617 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1618 2, base_mmio, 2, size_mmio); 1619 } 1620 1621 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 1622 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); 1623 1624 if (vms->iommu) { 1625 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1626 1627 switch (vms->iommu) { 1628 case VIRT_IOMMU_SMMUV3: 1629 create_smmu(vms, vms->bus); 1630 if (!vms->default_bus_bypass_iommu) { 1631 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 1632 0x0, vms->iommu_phandle, 0x0, 0x10000); 1633 } 1634 break; 1635 default: 1636 g_assert_not_reached(); 1637 } 1638 } 1639 } 1640 1641 static void create_cxl_host_reg_region(VirtMachineState *vms) 1642 { 1643 MemoryRegion *sysmem = get_system_memory(); 1644 MemoryRegion *mr = &vms->cxl_devices_state.host_mr; 1645 1646 memory_region_init(mr, OBJECT(vms), "cxl_host_reg", 1647 vms->memmap[VIRT_CXL_HOST].size); 1648 memory_region_add_subregion(sysmem, vms->memmap[VIRT_CXL_HOST].base, mr); 1649 vms->highmem_cxl = true; 1650 } 1651 1652 static void create_platform_bus(VirtMachineState *vms) 1653 { 1654 DeviceState *dev; 1655 SysBusDevice *s; 1656 int i; 1657 MemoryRegion *sysmem = get_system_memory(); 1658 1659 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1660 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1661 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1662 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1663 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1664 vms->platform_bus_dev = dev; 1665 1666 s = SYS_BUS_DEVICE(dev); 1667 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1668 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1669 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1670 } 1671 1672 memory_region_add_subregion(sysmem, 1673 vms->memmap[VIRT_PLATFORM_BUS].base, 1674 sysbus_mmio_get_region(s, 0)); 1675 } 1676 1677 static void create_tag_ram(MemoryRegion *tag_sysmem, 1678 hwaddr base, hwaddr size, 1679 const char *name) 1680 { 1681 MemoryRegion *tagram = g_new(MemoryRegion, 1); 1682 1683 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); 1684 memory_region_add_subregion(tag_sysmem, base / 32, tagram); 1685 } 1686 1687 static void create_secure_ram(VirtMachineState *vms, 1688 MemoryRegion *secure_sysmem, 1689 MemoryRegion *secure_tag_sysmem) 1690 { 1691 MemoryRegion *secram = g_new(MemoryRegion, 1); 1692 char *nodename; 1693 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1694 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1695 MachineState *ms = MACHINE(vms); 1696 1697 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1698 &error_fatal); 1699 memory_region_add_subregion(secure_sysmem, base, secram); 1700 1701 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1702 qemu_fdt_add_subnode(ms->fdt, nodename); 1703 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 1704 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 1705 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1706 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1707 1708 if (secure_tag_sysmem) { 1709 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); 1710 } 1711 1712 g_free(nodename); 1713 } 1714 1715 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1716 { 1717 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1718 bootinfo); 1719 MachineState *ms = MACHINE(board); 1720 1721 1722 *fdt_size = board->fdt_size; 1723 return ms->fdt; 1724 } 1725 1726 static void virt_build_smbios(VirtMachineState *vms) 1727 { 1728 MachineClass *mc = MACHINE_GET_CLASS(vms); 1729 MachineState *ms = MACHINE(vms); 1730 uint8_t *smbios_tables, *smbios_anchor; 1731 size_t smbios_tables_len, smbios_anchor_len; 1732 struct smbios_phys_mem_area mem_array; 1733 const char *product = "QEMU Virtual Machine"; 1734 1735 if (kvm_enabled()) { 1736 product = "KVM Virtual Machine"; 1737 } 1738 1739 smbios_set_defaults("QEMU", product, mc->name); 1740 1741 /* build the array of physical mem area from base_memmap */ 1742 mem_array.address = vms->memmap[VIRT_MEM].base; 1743 mem_array.length = ms->ram_size; 1744 1745 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, &mem_array, 1, 1746 &smbios_tables, &smbios_tables_len, 1747 &smbios_anchor, &smbios_anchor_len, 1748 &error_fatal); 1749 1750 if (smbios_anchor) { 1751 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1752 smbios_tables, smbios_tables_len); 1753 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1754 smbios_anchor, smbios_anchor_len); 1755 } 1756 } 1757 1758 static 1759 void virt_machine_done(Notifier *notifier, void *data) 1760 { 1761 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1762 machine_done); 1763 MachineState *ms = MACHINE(vms); 1764 ARMCPU *cpu = ARM_CPU(first_cpu); 1765 struct arm_boot_info *info = &vms->bootinfo; 1766 AddressSpace *as = arm_boot_address_space(cpu, info); 1767 1768 cxl_hook_up_pxb_registers(vms->bus, &vms->cxl_devices_state, 1769 &error_fatal); 1770 1771 if (vms->cxl_devices_state.is_enabled) { 1772 cxl_fmws_link_targets(&error_fatal); 1773 } 1774 /* 1775 * If the user provided a dtb, we assume the dynamic sysbus nodes 1776 * already are integrated there. This corresponds to a use case where 1777 * the dynamic sysbus nodes are complex and their generation is not yet 1778 * supported. In that case the user can take charge of the guest dt 1779 * while qemu takes charge of the qom stuff. 1780 */ 1781 if (info->dtb_filename == NULL) { 1782 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", 1783 vms->memmap[VIRT_PLATFORM_BUS].base, 1784 vms->memmap[VIRT_PLATFORM_BUS].size, 1785 vms->irqmap[VIRT_PLATFORM_BUS]); 1786 } 1787 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms, cpu) < 0) { 1788 exit(1); 1789 } 1790 1791 pci_bus_add_fw_cfg_extra_pci_roots(vms->fw_cfg, vms->bus, 1792 &error_abort); 1793 1794 virt_acpi_setup(vms); 1795 virt_build_smbios(vms); 1796 } 1797 1798 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1799 { 1800 uint8_t clustersz; 1801 1802 /* 1803 * Adjust MPIDR to make TCG consistent (with 64-bit KVM hosts) 1804 * and to improve SGI efficiency. 1805 */ 1806 if (vms->gic_version == VIRT_GIC_VERSION_2) { 1807 clustersz = GIC_TARGETLIST_BITS; 1808 } else { 1809 clustersz = GICV3_TARGETLIST_BITS; 1810 } 1811 1812 return arm_build_mp_affinity(idx, clustersz); 1813 } 1814 1815 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, 1816 int index) 1817 { 1818 bool *enabled_array[] = { 1819 &vms->highmem_redists, 1820 &vms->highmem_cxl, 1821 &vms->highmem_ecam, 1822 &vms->highmem_mmio, 1823 }; 1824 1825 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST == 1826 ARRAY_SIZE(enabled_array)); 1827 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array)); 1828 1829 return enabled_array[index - VIRT_LOWMEMMAP_LAST]; 1830 } 1831 1832 static void virt_set_high_memmap(VirtMachineState *vms, 1833 hwaddr base, int pa_bits) 1834 { 1835 hwaddr region_base, region_size; 1836 bool *region_enabled, fits; 1837 int i; 1838 1839 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1840 region_enabled = virt_get_high_memmap_enabled(vms, i); 1841 region_base = ROUND_UP(base, extended_memmap[i].size); 1842 region_size = extended_memmap[i].size; 1843 1844 vms->memmap[i].base = region_base; 1845 vms->memmap[i].size = region_size; 1846 1847 /* 1848 * Check each device to see if it fits in the PA space, 1849 * moving highest_gpa as we go. For compatibility, move 1850 * highest_gpa for disabled fitting devices as well, if 1851 * the compact layout has been disabled. 1852 * 1853 * For each device that doesn't fit, disable it. 1854 */ 1855 fits = (region_base + region_size) <= BIT_ULL(pa_bits); 1856 *region_enabled &= fits; 1857 if (vms->highmem_compact && !*region_enabled) { 1858 continue; 1859 } 1860 1861 base = region_base + region_size; 1862 if (fits) { 1863 vms->highest_gpa = base - 1; 1864 } 1865 } 1866 } 1867 1868 static void virt_set_memmap(VirtMachineState *vms, int pa_bits) 1869 { 1870 MachineState *ms = MACHINE(vms); 1871 hwaddr base, device_memory_base, device_memory_size, memtop; 1872 int i; 1873 1874 vms->memmap = extended_memmap; 1875 1876 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1877 vms->memmap[i] = base_memmap[i]; 1878 } 1879 1880 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1881 error_report("unsupported number of memory slots: %"PRIu64, 1882 ms->ram_slots); 1883 exit(EXIT_FAILURE); 1884 } 1885 1886 /* 1887 * !highmem is exactly the same as limiting the PA space to 32bit, 1888 * irrespective of the underlying capabilities of the HW. 1889 */ 1890 if (!vms->highmem) { 1891 pa_bits = 32; 1892 } 1893 1894 /* 1895 * We compute the base of the high IO region depending on the 1896 * amount of initial and device memory. The device memory start/size 1897 * is aligned on 1GiB. We never put the high IO region below 256GiB 1898 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1899 * The device region size assumes 1GiB page max alignment per slot. 1900 */ 1901 device_memory_base = 1902 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1903 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1904 1905 /* Base address of the high IO region */ 1906 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1907 if (memtop > BIT_ULL(pa_bits)) { 1908 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes", 1909 pa_bits, memtop - BIT_ULL(pa_bits)); 1910 exit(EXIT_FAILURE); 1911 } 1912 if (base < device_memory_base) { 1913 error_report("maxmem/slots too huge"); 1914 exit(EXIT_FAILURE); 1915 } 1916 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1917 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1918 } 1919 1920 /* We know for sure that at least the memory fits in the PA space */ 1921 vms->highest_gpa = memtop - 1; 1922 1923 virt_set_high_memmap(vms, base, pa_bits); 1924 1925 if (device_memory_size > 0) { 1926 machine_memory_devices_init(ms, device_memory_base, device_memory_size); 1927 } 1928 vms->highest_gpa = cxl_fmws_set_memmap(ROUND_UP(vms->highest_gpa + 1, 1929 256 * MiB), 1930 BIT_ULL(pa_bits)) - 1; 1931 } 1932 1933 static VirtGICType finalize_gic_version_do(const char *accel_name, 1934 VirtGICType gic_version, 1935 int gics_supported, 1936 unsigned int max_cpus) 1937 { 1938 /* Convert host/max/nosel to GIC version number */ 1939 switch (gic_version) { 1940 case VIRT_GIC_VERSION_HOST: 1941 if (!kvm_enabled()) { 1942 error_report("gic-version=host requires KVM"); 1943 exit(1); 1944 } 1945 1946 /* For KVM, gic-version=host means gic-version=max */ 1947 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX, 1948 gics_supported, max_cpus); 1949 case VIRT_GIC_VERSION_MAX: 1950 if (gics_supported & VIRT_GIC_VERSION_4_MASK) { 1951 gic_version = VIRT_GIC_VERSION_4; 1952 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1953 gic_version = VIRT_GIC_VERSION_3; 1954 } else { 1955 gic_version = VIRT_GIC_VERSION_2; 1956 } 1957 break; 1958 case VIRT_GIC_VERSION_NOSEL: 1959 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) && 1960 max_cpus <= GIC_NCPU) { 1961 gic_version = VIRT_GIC_VERSION_2; 1962 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1963 /* 1964 * in case the host does not support v2 emulation or 1965 * the end-user requested more than 8 VCPUs we now default 1966 * to v3. In any case defaulting to v2 would be broken. 1967 */ 1968 gic_version = VIRT_GIC_VERSION_3; 1969 } else if (max_cpus > GIC_NCPU) { 1970 error_report("%s only supports GICv2 emulation but more than 8 " 1971 "vcpus are requested", accel_name); 1972 exit(1); 1973 } 1974 break; 1975 case VIRT_GIC_VERSION_2: 1976 case VIRT_GIC_VERSION_3: 1977 case VIRT_GIC_VERSION_4: 1978 break; 1979 } 1980 1981 /* Check chosen version is effectively supported */ 1982 switch (gic_version) { 1983 case VIRT_GIC_VERSION_2: 1984 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) { 1985 error_report("%s does not support GICv2 emulation", accel_name); 1986 exit(1); 1987 } 1988 break; 1989 case VIRT_GIC_VERSION_3: 1990 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) { 1991 error_report("%s does not support GICv3 emulation", accel_name); 1992 exit(1); 1993 } 1994 break; 1995 case VIRT_GIC_VERSION_4: 1996 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) { 1997 error_report("%s does not support GICv4 emulation, is virtualization=on?", 1998 accel_name); 1999 exit(1); 2000 } 2001 break; 2002 default: 2003 error_report("logic error in finalize_gic_version"); 2004 exit(1); 2005 break; 2006 } 2007 2008 return gic_version; 2009 } 2010 2011 /* 2012 * finalize_gic_version - Determines the final gic_version 2013 * according to the gic-version property 2014 * 2015 * Default GIC type is v2 2016 */ 2017 static void finalize_gic_version(VirtMachineState *vms) 2018 { 2019 const char *accel_name = current_accel_name(); 2020 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 2021 int gics_supported = 0; 2022 2023 /* Determine which GIC versions the current environment supports */ 2024 if (kvm_enabled() && kvm_irqchip_in_kernel()) { 2025 int probe_bitmap = kvm_arm_vgic_probe(); 2026 2027 if (!probe_bitmap) { 2028 error_report("Unable to determine GIC version supported by host"); 2029 exit(1); 2030 } 2031 2032 if (probe_bitmap & KVM_ARM_VGIC_V2) { 2033 gics_supported |= VIRT_GIC_VERSION_2_MASK; 2034 } 2035 if (probe_bitmap & KVM_ARM_VGIC_V3) { 2036 gics_supported |= VIRT_GIC_VERSION_3_MASK; 2037 } 2038 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) { 2039 /* KVM w/o kernel irqchip can only deal with GICv2 */ 2040 gics_supported |= VIRT_GIC_VERSION_2_MASK; 2041 accel_name = "KVM with kernel-irqchip=off"; 2042 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { 2043 gics_supported |= VIRT_GIC_VERSION_2_MASK; 2044 if (module_object_class_by_name("arm-gicv3")) { 2045 gics_supported |= VIRT_GIC_VERSION_3_MASK; 2046 if (vms->virt) { 2047 /* GICv4 only makes sense if CPU has EL2 */ 2048 gics_supported |= VIRT_GIC_VERSION_4_MASK; 2049 } 2050 } 2051 } else { 2052 error_report("Unsupported accelerator, can not determine GIC support"); 2053 exit(1); 2054 } 2055 2056 /* 2057 * Then convert helpers like host/max to concrete GIC versions and ensure 2058 * the desired version is supported 2059 */ 2060 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version, 2061 gics_supported, max_cpus); 2062 } 2063 2064 /* 2065 * virt_post_cpus_gic_realized() must be called after the CPUs and 2066 * the GIC have both been realized. 2067 */ 2068 static void virt_post_cpus_gic_realized(VirtMachineState *vms, 2069 MemoryRegion *sysmem) 2070 { 2071 int max_cpus = MACHINE(vms)->smp.max_cpus; 2072 bool aarch64, pmu, steal_time; 2073 CPUState *cpu; 2074 2075 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); 2076 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); 2077 steal_time = object_property_get_bool(OBJECT(first_cpu), 2078 "kvm-steal-time", NULL); 2079 2080 if (kvm_enabled()) { 2081 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; 2082 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; 2083 2084 if (steal_time) { 2085 MemoryRegion *pvtime = g_new(MemoryRegion, 1); 2086 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; 2087 2088 /* The memory region size must be a multiple of host page size. */ 2089 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); 2090 2091 if (pvtime_size > pvtime_reg_size) { 2092 error_report("pvtime requires a %" HWADDR_PRId 2093 " byte memory region for %d CPUs," 2094 " but only %" HWADDR_PRId " has been reserved", 2095 pvtime_size, max_cpus, pvtime_reg_size); 2096 exit(1); 2097 } 2098 2099 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); 2100 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); 2101 } 2102 if (!aarch64 && vms->virt) { 2103 error_report("KVM does not support EL2 on an AArch32 vCPU"); 2104 exit(1); 2105 } 2106 2107 CPU_FOREACH(cpu) { 2108 if (pmu) { 2109 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); 2110 if (kvm_irqchip_in_kernel()) { 2111 kvm_arm_pmu_set_irq(ARM_CPU(cpu), VIRTUAL_PMU_IRQ); 2112 } 2113 kvm_arm_pmu_init(ARM_CPU(cpu)); 2114 } 2115 if (steal_time) { 2116 kvm_arm_pvtime_init(ARM_CPU(cpu), pvtime_reg_base 2117 + cpu->cpu_index 2118 * PVTIME_SIZE_PER_CPU); 2119 } 2120 } 2121 } else { 2122 if (aarch64 && vms->highmem) { 2123 int requested_pa_size = 64 - clz64(vms->highest_gpa); 2124 int pamax = arm_pamax(ARM_CPU(first_cpu)); 2125 2126 if (pamax < requested_pa_size) { 2127 error_report("VCPU supports less PA bits (%d) than " 2128 "requested by the memory map (%d)", 2129 pamax, requested_pa_size); 2130 exit(1); 2131 } 2132 } 2133 } 2134 } 2135 2136 static void machvirt_init(MachineState *machine) 2137 { 2138 VirtMachineState *vms = VIRT_MACHINE(machine); 2139 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 2140 MachineClass *mc = MACHINE_GET_CLASS(machine); 2141 const CPUArchIdList *possible_cpus; 2142 MemoryRegion *sysmem = get_system_memory(); 2143 MemoryRegion *secure_sysmem = NULL; 2144 MemoryRegion *tag_sysmem = NULL; 2145 MemoryRegion *secure_tag_sysmem = NULL; 2146 int n, virt_max_cpus; 2147 bool firmware_loaded; 2148 bool aarch64 = true; 2149 bool has_ged = !vmc->no_ged; 2150 unsigned int smp_cpus = machine->smp.cpus; 2151 unsigned int max_cpus = machine->smp.max_cpus; 2152 2153 possible_cpus = mc->possible_cpu_arch_ids(machine); 2154 2155 /* 2156 * In accelerated mode, the memory map is computed earlier in kvm_type() 2157 * for Linux, or hvf_get_physical_address_range() for macOS to create a 2158 * VM with the right number of IPA bits. 2159 */ 2160 if (!vms->memmap) { 2161 Object *cpuobj; 2162 ARMCPU *armcpu; 2163 int pa_bits; 2164 2165 /* 2166 * Instantiate a temporary CPU object to find out about what 2167 * we are about to deal with. Once this is done, get rid of 2168 * the object. 2169 */ 2170 cpuobj = object_new(possible_cpus->cpus[0].type); 2171 armcpu = ARM_CPU(cpuobj); 2172 2173 pa_bits = arm_pamax(armcpu); 2174 2175 object_unref(cpuobj); 2176 2177 virt_set_memmap(vms, pa_bits); 2178 } 2179 2180 /* We can probe only here because during property set 2181 * KVM is not available yet 2182 */ 2183 finalize_gic_version(vms); 2184 2185 if (vms->secure) { 2186 /* 2187 * The Secure view of the world is the same as the NonSecure, 2188 * but with a few extra devices. Create it as a container region 2189 * containing the system memory at low priority; any secure-only 2190 * devices go in at higher priority and take precedence. 2191 */ 2192 secure_sysmem = g_new(MemoryRegion, 1); 2193 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 2194 UINT64_MAX); 2195 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 2196 } 2197 2198 firmware_loaded = virt_firmware_init(vms, sysmem, 2199 secure_sysmem ?: sysmem); 2200 2201 /* If we have an EL3 boot ROM then the assumption is that it will 2202 * implement PSCI itself, so disable QEMU's internal implementation 2203 * so it doesn't get in the way. Instead of starting secondary 2204 * CPUs in PSCI powerdown state we will start them all running and 2205 * let the boot ROM sort them out. 2206 * The usual case is that we do use QEMU's PSCI implementation; 2207 * if the guest has EL2 then we will use SMC as the conduit, 2208 * and otherwise we will use HVC (for backwards compatibility and 2209 * because if we're using KVM then we must use HVC). 2210 */ 2211 if (vms->secure && firmware_loaded) { 2212 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 2213 } else if (vms->virt) { 2214 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 2215 } else { 2216 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 2217 } 2218 2219 /* 2220 * The maximum number of CPUs depends on the GIC version, or on how 2221 * many redistributors we can fit into the memory map (which in turn 2222 * depends on whether this is a GICv3 or v4). 2223 */ 2224 if (vms->gic_version == VIRT_GIC_VERSION_2) { 2225 virt_max_cpus = GIC_NCPU; 2226 } else { 2227 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST); 2228 if (vms->highmem_redists) { 2229 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 2230 } 2231 } 2232 2233 if (max_cpus > virt_max_cpus) { 2234 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 2235 "supported by machine 'mach-virt' (%d)", 2236 max_cpus, virt_max_cpus); 2237 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) { 2238 error_printf("Try 'highmem-redists=on' for more CPUs\n"); 2239 } 2240 2241 exit(1); 2242 } 2243 2244 if (vms->secure && !tcg_enabled() && !qtest_enabled()) { 2245 error_report("mach-virt: %s does not support providing " 2246 "Security extensions (TrustZone) to the guest CPU", 2247 current_accel_name()); 2248 exit(1); 2249 } 2250 2251 if (vms->virt && kvm_enabled() && !kvm_arm_el2_supported()) { 2252 error_report("mach-virt: host kernel KVM does not support providing " 2253 "Virtualization extensions to the guest CPU"); 2254 exit(1); 2255 } 2256 2257 if (vms->virt && !kvm_enabled() && !tcg_enabled() && !qtest_enabled()) { 2258 error_report("mach-virt: %s does not support providing " 2259 "Virtualization extensions to the guest CPU", 2260 current_accel_name()); 2261 exit(1); 2262 } 2263 2264 if (vms->mte && hvf_enabled()) { 2265 error_report("mach-virt: %s does not support providing " 2266 "MTE to the guest CPU", 2267 current_accel_name()); 2268 exit(1); 2269 } 2270 2271 create_fdt(vms); 2272 2273 assert(possible_cpus->len == max_cpus); 2274 for (n = 0; n < possible_cpus->len; n++) { 2275 Object *cpuobj; 2276 CPUState *cs; 2277 2278 if (n >= smp_cpus) { 2279 break; 2280 } 2281 2282 cpuobj = object_new(possible_cpus->cpus[n].type); 2283 object_property_set_int(cpuobj, "mp-affinity", 2284 possible_cpus->cpus[n].arch_id, NULL); 2285 2286 cs = CPU(cpuobj); 2287 cs->cpu_index = n; 2288 2289 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 2290 &error_fatal); 2291 2292 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 2293 2294 if (!vms->secure) { 2295 object_property_set_bool(cpuobj, "has_el3", false, NULL); 2296 } 2297 2298 if (!vms->virt && object_property_find(cpuobj, "has_el2")) { 2299 object_property_set_bool(cpuobj, "has_el2", false, NULL); 2300 } 2301 2302 if (vmc->kvm_no_adjvtime && 2303 object_property_find(cpuobj, "kvm-no-adjvtime")) { 2304 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 2305 } 2306 2307 if (vmc->no_kvm_steal_time && 2308 object_property_find(cpuobj, "kvm-steal-time")) { 2309 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); 2310 } 2311 2312 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { 2313 object_property_set_bool(cpuobj, "lpa2", false, NULL); 2314 } 2315 2316 if (object_property_find(cpuobj, "reset-cbar")) { 2317 object_property_set_int(cpuobj, "reset-cbar", 2318 vms->memmap[VIRT_CPUPERIPHS].base, 2319 &error_abort); 2320 } 2321 2322 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 2323 &error_abort); 2324 if (vms->secure) { 2325 object_property_set_link(cpuobj, "secure-memory", 2326 OBJECT(secure_sysmem), &error_abort); 2327 } 2328 2329 if (vms->mte) { 2330 if (tcg_enabled()) { 2331 /* Create the memory region only once, but link to all cpus. */ 2332 if (!tag_sysmem) { 2333 /* 2334 * The property exists only if MemTag is supported. 2335 * If it is, we must allocate the ram to back that up. 2336 */ 2337 if (!object_property_find(cpuobj, "tag-memory")) { 2338 error_report("MTE requested, but not supported " 2339 "by the guest CPU"); 2340 exit(1); 2341 } 2342 2343 tag_sysmem = g_new(MemoryRegion, 1); 2344 memory_region_init(tag_sysmem, OBJECT(machine), 2345 "tag-memory", UINT64_MAX / 32); 2346 2347 if (vms->secure) { 2348 secure_tag_sysmem = g_new(MemoryRegion, 1); 2349 memory_region_init(secure_tag_sysmem, OBJECT(machine), 2350 "secure-tag-memory", 2351 UINT64_MAX / 32); 2352 2353 /* As with ram, secure-tag takes precedence over tag. */ 2354 memory_region_add_subregion_overlap(secure_tag_sysmem, 2355 0, tag_sysmem, -1); 2356 } 2357 } 2358 2359 object_property_set_link(cpuobj, "tag-memory", 2360 OBJECT(tag_sysmem), &error_abort); 2361 if (vms->secure) { 2362 object_property_set_link(cpuobj, "secure-tag-memory", 2363 OBJECT(secure_tag_sysmem), 2364 &error_abort); 2365 } 2366 } else if (kvm_enabled()) { 2367 if (!kvm_arm_mte_supported()) { 2368 error_report("MTE requested, but not supported by KVM"); 2369 exit(1); 2370 } 2371 kvm_arm_enable_mte(cpuobj, &error_abort); 2372 } else { 2373 error_report("MTE requested, but not supported "); 2374 exit(1); 2375 } 2376 } 2377 2378 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 2379 object_unref(cpuobj); 2380 } 2381 2382 /* Now we've created the CPUs we can see if they have the hypvirt timer */ 2383 vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() && 2384 !vmc->no_ns_el2_virt_timer_irq; 2385 2386 fdt_add_timer_nodes(vms); 2387 fdt_add_cpu_nodes(vms); 2388 2389 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 2390 machine->ram); 2391 2392 cxl_fmws_update_mmio(); 2393 2394 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 2395 2396 create_gic(vms, sysmem); 2397 2398 virt_post_cpus_gic_realized(vms, sysmem); 2399 2400 fdt_add_pmu_nodes(vms); 2401 2402 /* 2403 * The first UART always exists. If the security extensions are 2404 * enabled, the second UART also always exists. Otherwise, it only exists 2405 * if a backend is configured explicitly via '-serial <backend>'. 2406 * This avoids potentially breaking existing user setups that expect 2407 * only one NonSecure UART to be present (for instance, older EDK2 2408 * binaries). 2409 * 2410 * The nodes end up in the DTB in reverse order of creation, so we must 2411 * create UART0 last to ensure it appears as the first node in the DTB, 2412 * for compatibility with guest software that just iterates through the 2413 * DTB to find the first UART, as older versions of EDK2 do. 2414 * DTB readers that follow the spec, as Linux does, should honour the 2415 * aliases node information and /chosen/stdout-path regardless of 2416 * the order that nodes appear in the DTB. 2417 * 2418 * For similar back-compatibility reasons, if UART1 is the secure UART 2419 * we create it second (and so it appears first in the DTB), because 2420 * that's what QEMU has always done. 2421 */ 2422 if (!vms->secure) { 2423 Chardev *serial1 = serial_hd(1); 2424 2425 if (serial1) { 2426 vms->second_ns_uart_present = true; 2427 create_uart(vms, VIRT_UART1, sysmem, serial1, false); 2428 } 2429 } 2430 create_uart(vms, VIRT_UART0, sysmem, serial_hd(0), false); 2431 if (vms->secure) { 2432 create_uart(vms, VIRT_UART1, secure_sysmem, serial_hd(1), true); 2433 } 2434 2435 if (vms->secure) { 2436 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); 2437 } 2438 2439 if (tag_sysmem) { 2440 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, 2441 machine->ram_size, "mach-virt.tag"); 2442 } 2443 2444 vms->highmem_ecam &= (!firmware_loaded || aarch64); 2445 2446 create_rtc(vms); 2447 2448 create_pcie(vms); 2449 create_cxl_host_reg_region(vms); 2450 2451 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 2452 vms->acpi_dev = create_acpi_ged(vms); 2453 } else { 2454 create_gpio_devices(vms, VIRT_GPIO, sysmem); 2455 } 2456 2457 if (vms->secure && !vmc->no_secure_gpio) { 2458 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); 2459 } 2460 2461 /* connect powerdown request */ 2462 vms->powerdown_notifier.notify = virt_powerdown_req; 2463 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 2464 2465 /* Create mmio transports, so the user can create virtio backends 2466 * (which will be automatically plugged in to the transports). If 2467 * no backend is created the transport will just sit harmlessly idle. 2468 */ 2469 create_virtio_devices(vms); 2470 2471 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 2472 rom_set_fw(vms->fw_cfg); 2473 2474 create_platform_bus(vms); 2475 2476 if (machine->nvdimms_state->is_enabled) { 2477 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 2478 .space_id = AML_AS_SYSTEM_MEMORY, 2479 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 2480 .bit_width = NVDIMM_ACPI_IO_LEN << 3 2481 }; 2482 2483 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 2484 arm_virt_nvdimm_acpi_dsmio, 2485 vms->fw_cfg, OBJECT(vms)); 2486 } 2487 2488 vms->bootinfo.ram_size = machine->ram_size; 2489 vms->bootinfo.board_id = -1; 2490 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 2491 vms->bootinfo.get_dtb = machvirt_dtb; 2492 vms->bootinfo.skip_dtb_autoload = true; 2493 vms->bootinfo.firmware_loaded = firmware_loaded; 2494 vms->bootinfo.psci_conduit = vms->psci_conduit; 2495 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 2496 2497 vms->machine_done.notify = virt_machine_done; 2498 qemu_add_machine_init_done_notifier(&vms->machine_done); 2499 } 2500 2501 static bool virt_get_secure(Object *obj, Error **errp) 2502 { 2503 VirtMachineState *vms = VIRT_MACHINE(obj); 2504 2505 return vms->secure; 2506 } 2507 2508 static void virt_set_secure(Object *obj, bool value, Error **errp) 2509 { 2510 VirtMachineState *vms = VIRT_MACHINE(obj); 2511 2512 vms->secure = value; 2513 } 2514 2515 static bool virt_get_virt(Object *obj, Error **errp) 2516 { 2517 VirtMachineState *vms = VIRT_MACHINE(obj); 2518 2519 return vms->virt; 2520 } 2521 2522 static void virt_set_virt(Object *obj, bool value, Error **errp) 2523 { 2524 VirtMachineState *vms = VIRT_MACHINE(obj); 2525 2526 vms->virt = value; 2527 } 2528 2529 static bool virt_get_highmem(Object *obj, Error **errp) 2530 { 2531 VirtMachineState *vms = VIRT_MACHINE(obj); 2532 2533 return vms->highmem; 2534 } 2535 2536 static void virt_set_highmem(Object *obj, bool value, Error **errp) 2537 { 2538 VirtMachineState *vms = VIRT_MACHINE(obj); 2539 2540 vms->highmem = value; 2541 } 2542 2543 static bool virt_get_compact_highmem(Object *obj, Error **errp) 2544 { 2545 VirtMachineState *vms = VIRT_MACHINE(obj); 2546 2547 return vms->highmem_compact; 2548 } 2549 2550 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp) 2551 { 2552 VirtMachineState *vms = VIRT_MACHINE(obj); 2553 2554 vms->highmem_compact = value; 2555 } 2556 2557 static bool virt_get_highmem_redists(Object *obj, Error **errp) 2558 { 2559 VirtMachineState *vms = VIRT_MACHINE(obj); 2560 2561 return vms->highmem_redists; 2562 } 2563 2564 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp) 2565 { 2566 VirtMachineState *vms = VIRT_MACHINE(obj); 2567 2568 vms->highmem_redists = value; 2569 } 2570 2571 static bool virt_get_highmem_ecam(Object *obj, Error **errp) 2572 { 2573 VirtMachineState *vms = VIRT_MACHINE(obj); 2574 2575 return vms->highmem_ecam; 2576 } 2577 2578 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp) 2579 { 2580 VirtMachineState *vms = VIRT_MACHINE(obj); 2581 2582 vms->highmem_ecam = value; 2583 } 2584 2585 static bool virt_get_highmem_mmio(Object *obj, Error **errp) 2586 { 2587 VirtMachineState *vms = VIRT_MACHINE(obj); 2588 2589 return vms->highmem_mmio; 2590 } 2591 2592 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp) 2593 { 2594 VirtMachineState *vms = VIRT_MACHINE(obj); 2595 2596 vms->highmem_mmio = value; 2597 } 2598 2599 static void virt_get_highmem_mmio_size(Object *obj, Visitor *v, 2600 const char *name, void *opaque, 2601 Error **errp) 2602 { 2603 uint64_t size = extended_memmap[VIRT_HIGH_PCIE_MMIO].size; 2604 2605 visit_type_size(v, name, &size, errp); 2606 } 2607 2608 static void virt_set_highmem_mmio_size(Object *obj, Visitor *v, 2609 const char *name, void *opaque, 2610 Error **errp) 2611 { 2612 uint64_t size; 2613 2614 if (!visit_type_size(v, name, &size, errp)) { 2615 return; 2616 } 2617 2618 if (!is_power_of_2(size)) { 2619 error_setg(errp, "highmem-mmio-size is not a power of 2"); 2620 return; 2621 } 2622 2623 if (size < DEFAULT_HIGH_PCIE_MMIO_SIZE) { 2624 char *sz = size_to_str(DEFAULT_HIGH_PCIE_MMIO_SIZE); 2625 error_setg(errp, "highmem-mmio-size cannot be set to a lower value " 2626 "than the default (%s)", sz); 2627 g_free(sz); 2628 return; 2629 } 2630 2631 extended_memmap[VIRT_HIGH_PCIE_MMIO].size = size; 2632 } 2633 2634 static bool virt_get_its(Object *obj, Error **errp) 2635 { 2636 VirtMachineState *vms = VIRT_MACHINE(obj); 2637 2638 return vms->its; 2639 } 2640 2641 static void virt_set_its(Object *obj, bool value, Error **errp) 2642 { 2643 VirtMachineState *vms = VIRT_MACHINE(obj); 2644 2645 vms->its = value; 2646 } 2647 2648 static bool virt_get_dtb_randomness(Object *obj, Error **errp) 2649 { 2650 VirtMachineState *vms = VIRT_MACHINE(obj); 2651 2652 return vms->dtb_randomness; 2653 } 2654 2655 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp) 2656 { 2657 VirtMachineState *vms = VIRT_MACHINE(obj); 2658 2659 vms->dtb_randomness = value; 2660 } 2661 2662 static char *virt_get_oem_id(Object *obj, Error **errp) 2663 { 2664 VirtMachineState *vms = VIRT_MACHINE(obj); 2665 2666 return g_strdup(vms->oem_id); 2667 } 2668 2669 static void virt_set_oem_id(Object *obj, const char *value, Error **errp) 2670 { 2671 VirtMachineState *vms = VIRT_MACHINE(obj); 2672 size_t len = strlen(value); 2673 2674 if (len > 6) { 2675 error_setg(errp, 2676 "User specified oem-id value is bigger than 6 bytes in size"); 2677 return; 2678 } 2679 2680 strncpy(vms->oem_id, value, 6); 2681 } 2682 2683 static char *virt_get_oem_table_id(Object *obj, Error **errp) 2684 { 2685 VirtMachineState *vms = VIRT_MACHINE(obj); 2686 2687 return g_strdup(vms->oem_table_id); 2688 } 2689 2690 static void virt_set_oem_table_id(Object *obj, const char *value, 2691 Error **errp) 2692 { 2693 VirtMachineState *vms = VIRT_MACHINE(obj); 2694 size_t len = strlen(value); 2695 2696 if (len > 8) { 2697 error_setg(errp, 2698 "User specified oem-table-id value is bigger than 8 bytes in size"); 2699 return; 2700 } 2701 strncpy(vms->oem_table_id, value, 8); 2702 } 2703 2704 2705 bool virt_is_acpi_enabled(VirtMachineState *vms) 2706 { 2707 if (vms->acpi == ON_OFF_AUTO_OFF) { 2708 return false; 2709 } 2710 return true; 2711 } 2712 2713 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 2714 void *opaque, Error **errp) 2715 { 2716 VirtMachineState *vms = VIRT_MACHINE(obj); 2717 OnOffAuto acpi = vms->acpi; 2718 2719 visit_type_OnOffAuto(v, name, &acpi, errp); 2720 } 2721 2722 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 2723 void *opaque, Error **errp) 2724 { 2725 VirtMachineState *vms = VIRT_MACHINE(obj); 2726 2727 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 2728 } 2729 2730 static bool virt_get_ras(Object *obj, Error **errp) 2731 { 2732 VirtMachineState *vms = VIRT_MACHINE(obj); 2733 2734 return vms->ras; 2735 } 2736 2737 static void virt_set_ras(Object *obj, bool value, Error **errp) 2738 { 2739 VirtMachineState *vms = VIRT_MACHINE(obj); 2740 2741 vms->ras = value; 2742 } 2743 2744 static bool virt_get_mte(Object *obj, Error **errp) 2745 { 2746 VirtMachineState *vms = VIRT_MACHINE(obj); 2747 2748 return vms->mte; 2749 } 2750 2751 static void virt_set_mte(Object *obj, bool value, Error **errp) 2752 { 2753 VirtMachineState *vms = VIRT_MACHINE(obj); 2754 2755 vms->mte = value; 2756 } 2757 2758 static char *virt_get_gic_version(Object *obj, Error **errp) 2759 { 2760 VirtMachineState *vms = VIRT_MACHINE(obj); 2761 const char *val; 2762 2763 switch (vms->gic_version) { 2764 case VIRT_GIC_VERSION_4: 2765 val = "4"; 2766 break; 2767 case VIRT_GIC_VERSION_3: 2768 val = "3"; 2769 break; 2770 default: 2771 val = "2"; 2772 break; 2773 } 2774 return g_strdup(val); 2775 } 2776 2777 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2778 { 2779 VirtMachineState *vms = VIRT_MACHINE(obj); 2780 2781 if (!strcmp(value, "4")) { 2782 vms->gic_version = VIRT_GIC_VERSION_4; 2783 } else if (!strcmp(value, "3")) { 2784 vms->gic_version = VIRT_GIC_VERSION_3; 2785 } else if (!strcmp(value, "2")) { 2786 vms->gic_version = VIRT_GIC_VERSION_2; 2787 } else if (!strcmp(value, "host")) { 2788 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2789 } else if (!strcmp(value, "max")) { 2790 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2791 } else { 2792 error_setg(errp, "Invalid gic-version value"); 2793 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2794 } 2795 } 2796 2797 static char *virt_get_iommu(Object *obj, Error **errp) 2798 { 2799 VirtMachineState *vms = VIRT_MACHINE(obj); 2800 2801 switch (vms->iommu) { 2802 case VIRT_IOMMU_NONE: 2803 return g_strdup("none"); 2804 case VIRT_IOMMU_SMMUV3: 2805 return g_strdup("smmuv3"); 2806 default: 2807 g_assert_not_reached(); 2808 } 2809 } 2810 2811 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2812 { 2813 VirtMachineState *vms = VIRT_MACHINE(obj); 2814 2815 if (!strcmp(value, "smmuv3")) { 2816 vms->iommu = VIRT_IOMMU_SMMUV3; 2817 } else if (!strcmp(value, "none")) { 2818 vms->iommu = VIRT_IOMMU_NONE; 2819 } else { 2820 error_setg(errp, "Invalid iommu value"); 2821 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2822 } 2823 } 2824 2825 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp) 2826 { 2827 VirtMachineState *vms = VIRT_MACHINE(obj); 2828 2829 return vms->default_bus_bypass_iommu; 2830 } 2831 2832 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value, 2833 Error **errp) 2834 { 2835 VirtMachineState *vms = VIRT_MACHINE(obj); 2836 2837 vms->default_bus_bypass_iommu = value; 2838 } 2839 2840 static CpuInstanceProperties 2841 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2842 { 2843 MachineClass *mc = MACHINE_GET_CLASS(ms); 2844 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2845 2846 assert(cpu_index < possible_cpus->len); 2847 return possible_cpus->cpus[cpu_index].props; 2848 } 2849 2850 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2851 { 2852 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 2853 2854 return socket_id % ms->numa_state->num_nodes; 2855 } 2856 2857 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2858 { 2859 int n; 2860 unsigned int max_cpus = ms->smp.max_cpus; 2861 VirtMachineState *vms = VIRT_MACHINE(ms); 2862 MachineClass *mc = MACHINE_GET_CLASS(vms); 2863 2864 if (ms->possible_cpus) { 2865 assert(ms->possible_cpus->len == max_cpus); 2866 return ms->possible_cpus; 2867 } 2868 2869 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2870 sizeof(CPUArchId) * max_cpus); 2871 ms->possible_cpus->len = max_cpus; 2872 for (n = 0; n < ms->possible_cpus->len; n++) { 2873 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2874 ms->possible_cpus->cpus[n].arch_id = 2875 virt_cpu_mp_affinity(vms, n); 2876 2877 assert(!mc->smp_props.dies_supported); 2878 ms->possible_cpus->cpus[n].props.has_socket_id = true; 2879 ms->possible_cpus->cpus[n].props.socket_id = 2880 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); 2881 ms->possible_cpus->cpus[n].props.has_cluster_id = true; 2882 ms->possible_cpus->cpus[n].props.cluster_id = 2883 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; 2884 ms->possible_cpus->cpus[n].props.has_core_id = true; 2885 ms->possible_cpus->cpus[n].props.core_id = 2886 (n / ms->smp.threads) % ms->smp.cores; 2887 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2888 ms->possible_cpus->cpus[n].props.thread_id = 2889 n % ms->smp.threads; 2890 } 2891 return ms->possible_cpus; 2892 } 2893 2894 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2895 Error **errp) 2896 { 2897 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2898 const MachineState *ms = MACHINE(hotplug_dev); 2899 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2900 2901 if (!vms->acpi_dev) { 2902 error_setg(errp, 2903 "memory hotplug is not enabled: missing acpi-ged device"); 2904 return; 2905 } 2906 2907 if (vms->mte) { 2908 error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); 2909 return; 2910 } 2911 2912 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2913 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2914 return; 2915 } 2916 2917 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp); 2918 } 2919 2920 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2921 DeviceState *dev, Error **errp) 2922 { 2923 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2924 MachineState *ms = MACHINE(hotplug_dev); 2925 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2926 2927 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); 2928 2929 if (is_nvdimm) { 2930 nvdimm_plug(ms->nvdimms_state); 2931 } 2932 2933 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2934 dev, &error_abort); 2935 } 2936 2937 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2938 DeviceState *dev, Error **errp) 2939 { 2940 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2941 2942 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2943 virt_memory_pre_plug(hotplug_dev, dev, errp); 2944 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2945 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2946 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2947 hwaddr db_start = 0, db_end = 0; 2948 QList *reserved_regions; 2949 char *resv_prop_str; 2950 2951 if (vms->iommu != VIRT_IOMMU_NONE) { 2952 error_setg(errp, "virt machine does not support multiple IOMMUs"); 2953 return; 2954 } 2955 2956 switch (vms->msi_controller) { 2957 case VIRT_MSI_CTRL_NONE: 2958 return; 2959 case VIRT_MSI_CTRL_ITS: 2960 /* GITS_TRANSLATER page */ 2961 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; 2962 db_end = base_memmap[VIRT_GIC_ITS].base + 2963 base_memmap[VIRT_GIC_ITS].size - 1; 2964 break; 2965 case VIRT_MSI_CTRL_GICV2M: 2966 /* MSI_SETSPI_NS page */ 2967 db_start = base_memmap[VIRT_GIC_V2M].base; 2968 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; 2969 break; 2970 } 2971 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", 2972 db_start, db_end, 2973 VIRTIO_IOMMU_RESV_MEM_T_MSI); 2974 2975 reserved_regions = qlist_new(); 2976 qlist_append_str(reserved_regions, resv_prop_str); 2977 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 2978 g_free(resv_prop_str); 2979 } 2980 } 2981 2982 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2983 DeviceState *dev, Error **errp) 2984 { 2985 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2986 2987 if (vms->platform_bus_dev) { 2988 MachineClass *mc = MACHINE_GET_CLASS(vms); 2989 2990 if (device_is_dynamic_sysbus(mc, dev)) { 2991 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2992 SYS_BUS_DEVICE(dev)); 2993 } 2994 } 2995 2996 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2997 virt_memory_plug(hotplug_dev, dev, errp); 2998 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2999 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 3000 } 3001 3002 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 3003 PCIDevice *pdev = PCI_DEVICE(dev); 3004 3005 vms->iommu = VIRT_IOMMU_VIRTIO; 3006 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 3007 create_virtio_iommu_dt_bindings(vms); 3008 } 3009 } 3010 3011 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, 3012 DeviceState *dev, Error **errp) 3013 { 3014 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 3015 3016 if (!vms->acpi_dev) { 3017 error_setg(errp, 3018 "memory hotplug is not enabled: missing acpi-ged device"); 3019 return; 3020 } 3021 3022 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3023 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3024 return; 3025 } 3026 3027 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, 3028 errp); 3029 } 3030 3031 static void virt_dimm_unplug(HotplugHandler *hotplug_dev, 3032 DeviceState *dev, Error **errp) 3033 { 3034 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 3035 Error *local_err = NULL; 3036 3037 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); 3038 if (local_err) { 3039 goto out; 3040 } 3041 3042 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); 3043 qdev_unrealize(dev); 3044 3045 out: 3046 error_propagate(errp, local_err); 3047 } 3048 3049 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 3050 DeviceState *dev, Error **errp) 3051 { 3052 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3053 virt_dimm_unplug_request(hotplug_dev, dev, errp); 3054 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 3055 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 3056 errp); 3057 } else { 3058 error_setg(errp, "device unplug request for unsupported device" 3059 " type: %s", object_get_typename(OBJECT(dev))); 3060 } 3061 } 3062 3063 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 3064 DeviceState *dev, Error **errp) 3065 { 3066 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3067 virt_dimm_unplug(hotplug_dev, dev, errp); 3068 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 3069 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 3070 } else { 3071 error_setg(errp, "virt: device unplug for unsupported device" 3072 " type: %s", object_get_typename(OBJECT(dev))); 3073 } 3074 } 3075 3076 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 3077 DeviceState *dev) 3078 { 3079 MachineClass *mc = MACHINE_GET_CLASS(machine); 3080 3081 if (device_is_dynamic_sysbus(mc, dev) || 3082 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3083 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 3084 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 3085 return HOTPLUG_HANDLER(machine); 3086 } 3087 return NULL; 3088 } 3089 3090 /* 3091 * for arm64 kvm_type [7-0] encodes the requested number of bits 3092 * in the IPA address space 3093 */ 3094 static int virt_kvm_type(MachineState *ms, const char *type_str) 3095 { 3096 VirtMachineState *vms = VIRT_MACHINE(ms); 3097 int max_vm_pa_size, requested_pa_size; 3098 bool fixed_ipa; 3099 3100 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 3101 3102 /* we freeze the memory map to compute the highest gpa */ 3103 virt_set_memmap(vms, max_vm_pa_size); 3104 3105 requested_pa_size = 64 - clz64(vms->highest_gpa); 3106 3107 /* 3108 * KVM requires the IPA size to be at least 32 bits. 3109 */ 3110 if (requested_pa_size < 32) { 3111 requested_pa_size = 32; 3112 } 3113 3114 if (requested_pa_size > max_vm_pa_size) { 3115 error_report("-m and ,maxmem option values " 3116 "require an IPA range (%d bits) larger than " 3117 "the one supported by the host (%d bits)", 3118 requested_pa_size, max_vm_pa_size); 3119 return -1; 3120 } 3121 /* 3122 * We return the requested PA log size, unless KVM only supports 3123 * the implicit legacy 40b IPA setting, in which case the kvm_type 3124 * must be 0. 3125 */ 3126 return fixed_ipa ? 0 : requested_pa_size; 3127 } 3128 3129 static int virt_hvf_get_physical_address_range(MachineState *ms) 3130 { 3131 VirtMachineState *vms = VIRT_MACHINE(ms); 3132 3133 int default_ipa_size = hvf_arm_get_default_ipa_bit_size(); 3134 int max_ipa_size = hvf_arm_get_max_ipa_bit_size(); 3135 3136 /* We freeze the memory map to compute the highest gpa */ 3137 virt_set_memmap(vms, max_ipa_size); 3138 3139 int requested_ipa_size = 64 - clz64(vms->highest_gpa); 3140 3141 /* 3142 * If we're <= the default IPA size just use the default. 3143 * If we're above the default but below the maximum, round up to 3144 * the maximum. hvf_arm_get_max_ipa_bit_size() conveniently only 3145 * returns values that are valid ARM PARange values. 3146 */ 3147 if (requested_ipa_size <= default_ipa_size) { 3148 requested_ipa_size = default_ipa_size; 3149 } else if (requested_ipa_size <= max_ipa_size) { 3150 requested_ipa_size = max_ipa_size; 3151 } else { 3152 error_report("-m and ,maxmem option values " 3153 "require an IPA range (%d bits) larger than " 3154 "the one supported by the host (%d bits)", 3155 requested_ipa_size, max_ipa_size); 3156 return -1; 3157 } 3158 3159 return requested_ipa_size; 3160 } 3161 3162 static void virt_machine_class_init(ObjectClass *oc, const void *data) 3163 { 3164 MachineClass *mc = MACHINE_CLASS(oc); 3165 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3166 static const char * const valid_cpu_types[] = { 3167 #ifdef CONFIG_TCG 3168 ARM_CPU_TYPE_NAME("cortex-a7"), 3169 ARM_CPU_TYPE_NAME("cortex-a15"), 3170 #ifdef TARGET_AARCH64 3171 ARM_CPU_TYPE_NAME("cortex-a35"), 3172 ARM_CPU_TYPE_NAME("cortex-a55"), 3173 ARM_CPU_TYPE_NAME("cortex-a72"), 3174 ARM_CPU_TYPE_NAME("cortex-a76"), 3175 ARM_CPU_TYPE_NAME("cortex-a710"), 3176 ARM_CPU_TYPE_NAME("a64fx"), 3177 ARM_CPU_TYPE_NAME("neoverse-n1"), 3178 ARM_CPU_TYPE_NAME("neoverse-v1"), 3179 ARM_CPU_TYPE_NAME("neoverse-n2"), 3180 #endif /* TARGET_AARCH64 */ 3181 #endif /* CONFIG_TCG */ 3182 #ifdef TARGET_AARCH64 3183 ARM_CPU_TYPE_NAME("cortex-a53"), 3184 ARM_CPU_TYPE_NAME("cortex-a57"), 3185 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 3186 ARM_CPU_TYPE_NAME("host"), 3187 #endif /* CONFIG_KVM || CONFIG_HVF */ 3188 #endif /* TARGET_AARCH64 */ 3189 ARM_CPU_TYPE_NAME("max"), 3190 NULL 3191 }; 3192 3193 mc->init = machvirt_init; 3194 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 3195 * The value may be reduced later when we have more information about the 3196 * configuration of the particular instance. 3197 */ 3198 mc->max_cpus = 512; 3199 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 3200 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 3201 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 3202 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 3203 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS); 3204 #ifdef CONFIG_TPM 3205 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 3206 #endif 3207 mc->block_default_type = IF_VIRTIO; 3208 mc->no_cdrom = 1; 3209 mc->pci_allow_0_address = true; 3210 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 3211 mc->minimum_page_bits = 12; 3212 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 3213 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 3214 #ifdef CONFIG_TCG 3215 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 3216 #else 3217 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); 3218 #endif 3219 mc->valid_cpu_types = valid_cpu_types; 3220 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 3221 mc->kvm_type = virt_kvm_type; 3222 mc->hvf_get_physical_address_range = virt_hvf_get_physical_address_range; 3223 assert(!mc->get_hotplug_handler); 3224 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 3225 hc->pre_plug = virt_machine_device_pre_plug_cb; 3226 hc->plug = virt_machine_device_plug_cb; 3227 hc->unplug_request = virt_machine_device_unplug_request_cb; 3228 hc->unplug = virt_machine_device_unplug_cb; 3229 mc->nvdimm_supported = true; 3230 mc->smp_props.clusters_supported = true; 3231 mc->auto_enable_numa_with_memhp = true; 3232 mc->auto_enable_numa_with_memdev = true; 3233 /* platform instead of architectural choice */ 3234 mc->cpu_cluster_has_numa_boundary = true; 3235 mc->default_ram_id = "mach-virt.ram"; 3236 mc->default_nic = "virtio-net-pci"; 3237 3238 object_class_property_add(oc, "acpi", "OnOffAuto", 3239 virt_get_acpi, virt_set_acpi, 3240 NULL, NULL); 3241 object_class_property_set_description(oc, "acpi", 3242 "Enable ACPI"); 3243 object_class_property_add_bool(oc, "secure", virt_get_secure, 3244 virt_set_secure); 3245 object_class_property_set_description(oc, "secure", 3246 "Set on/off to enable/disable the ARM " 3247 "Security Extensions (TrustZone)"); 3248 3249 object_class_property_add_bool(oc, "virtualization", virt_get_virt, 3250 virt_set_virt); 3251 object_class_property_set_description(oc, "virtualization", 3252 "Set on/off to enable/disable emulating a " 3253 "guest CPU which implements the ARM " 3254 "Virtualization Extensions"); 3255 3256 object_class_property_add_bool(oc, "highmem", virt_get_highmem, 3257 virt_set_highmem); 3258 object_class_property_set_description(oc, "highmem", 3259 "Set on/off to enable/disable using " 3260 "physical address space above 32 bits"); 3261 3262 object_class_property_add_bool(oc, "compact-highmem", 3263 virt_get_compact_highmem, 3264 virt_set_compact_highmem); 3265 object_class_property_set_description(oc, "compact-highmem", 3266 "Set on/off to enable/disable compact " 3267 "layout for high memory regions"); 3268 3269 object_class_property_add_bool(oc, "highmem-redists", 3270 virt_get_highmem_redists, 3271 virt_set_highmem_redists); 3272 object_class_property_set_description(oc, "highmem-redists", 3273 "Set on/off to enable/disable high " 3274 "memory region for GICv3 or GICv4 " 3275 "redistributor"); 3276 3277 object_class_property_add_bool(oc, "highmem-ecam", 3278 virt_get_highmem_ecam, 3279 virt_set_highmem_ecam); 3280 object_class_property_set_description(oc, "highmem-ecam", 3281 "Set on/off to enable/disable high " 3282 "memory region for PCI ECAM"); 3283 3284 object_class_property_add_bool(oc, "highmem-mmio", 3285 virt_get_highmem_mmio, 3286 virt_set_highmem_mmio); 3287 object_class_property_set_description(oc, "highmem-mmio", 3288 "Set on/off to enable/disable high " 3289 "memory region for PCI MMIO"); 3290 3291 object_class_property_add(oc, "highmem-mmio-size", "size", 3292 virt_get_highmem_mmio_size, 3293 virt_set_highmem_mmio_size, 3294 NULL, NULL); 3295 object_class_property_set_description(oc, "highmem-mmio-size", 3296 "Set the high memory region size " 3297 "for PCI MMIO"); 3298 3299 object_class_property_add_str(oc, "gic-version", virt_get_gic_version, 3300 virt_set_gic_version); 3301 object_class_property_set_description(oc, "gic-version", 3302 "Set GIC version. " 3303 "Valid values are 2, 3, 4, host and max"); 3304 3305 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); 3306 object_class_property_set_description(oc, "iommu", 3307 "Set the IOMMU type. " 3308 "Valid values are none and smmuv3"); 3309 3310 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 3311 virt_get_default_bus_bypass_iommu, 3312 virt_set_default_bus_bypass_iommu); 3313 object_class_property_set_description(oc, "default-bus-bypass-iommu", 3314 "Set on/off to enable/disable " 3315 "bypass_iommu for default root bus"); 3316 3317 object_class_property_add_bool(oc, "ras", virt_get_ras, 3318 virt_set_ras); 3319 object_class_property_set_description(oc, "ras", 3320 "Set on/off to enable/disable reporting host memory errors " 3321 "to a KVM guest using ACPI and guest external abort exceptions"); 3322 3323 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); 3324 object_class_property_set_description(oc, "mte", 3325 "Set on/off to enable/disable emulating a " 3326 "guest CPU which implements the ARM " 3327 "Memory Tagging Extension"); 3328 3329 object_class_property_add_bool(oc, "its", virt_get_its, 3330 virt_set_its); 3331 object_class_property_set_description(oc, "its", 3332 "Set on/off to enable/disable " 3333 "ITS instantiation"); 3334 3335 object_class_property_add_bool(oc, "dtb-randomness", 3336 virt_get_dtb_randomness, 3337 virt_set_dtb_randomness); 3338 object_class_property_set_description(oc, "dtb-randomness", 3339 "Set off to disable passing random or " 3340 "non-deterministic dtb nodes to guest"); 3341 3342 object_class_property_add_bool(oc, "dtb-kaslr-seed", 3343 virt_get_dtb_randomness, 3344 virt_set_dtb_randomness); 3345 object_class_property_set_description(oc, "dtb-kaslr-seed", 3346 "Deprecated synonym of dtb-randomness"); 3347 3348 object_class_property_add_str(oc, "x-oem-id", 3349 virt_get_oem_id, 3350 virt_set_oem_id); 3351 object_class_property_set_description(oc, "x-oem-id", 3352 "Override the default value of field OEMID " 3353 "in ACPI table header." 3354 "The string may be up to 6 bytes in size"); 3355 3356 3357 object_class_property_add_str(oc, "x-oem-table-id", 3358 virt_get_oem_table_id, 3359 virt_set_oem_table_id); 3360 object_class_property_set_description(oc, "x-oem-table-id", 3361 "Override the default value of field OEM Table ID " 3362 "in ACPI table header." 3363 "The string may be up to 8 bytes in size"); 3364 3365 } 3366 3367 static void virt_instance_init(Object *obj) 3368 { 3369 VirtMachineState *vms = VIRT_MACHINE(obj); 3370 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 3371 3372 /* EL3 is disabled by default on virt: this makes us consistent 3373 * between KVM and TCG for this board, and it also allows us to 3374 * boot UEFI blobs which assume no TrustZone support. 3375 */ 3376 vms->secure = false; 3377 3378 /* EL2 is also disabled by default, for similar reasons */ 3379 vms->virt = false; 3380 3381 /* High memory is enabled by default */ 3382 vms->highmem = true; 3383 vms->highmem_compact = !vmc->no_highmem_compact; 3384 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 3385 3386 vms->highmem_ecam = true; 3387 vms->highmem_mmio = true; 3388 vms->highmem_redists = true; 3389 3390 /* Default allows ITS instantiation */ 3391 vms->its = true; 3392 /* Allow ITS emulation if the machine version supports it */ 3393 vms->tcg_its = !vmc->no_tcg_its; 3394 3395 /* Default disallows iommu instantiation */ 3396 vms->iommu = VIRT_IOMMU_NONE; 3397 3398 /* The default root bus is attached to iommu by default */ 3399 vms->default_bus_bypass_iommu = false; 3400 3401 /* Default disallows RAS instantiation */ 3402 vms->ras = false; 3403 3404 /* MTE is disabled by default. */ 3405 vms->mte = false; 3406 3407 /* Supply kaslr-seed and rng-seed by default */ 3408 vms->dtb_randomness = true; 3409 3410 vms->irqmap = a15irqmap; 3411 3412 virt_flash_create(vms); 3413 3414 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 3415 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 3416 cxl_machine_init(obj, &vms->cxl_devices_state); 3417 } 3418 3419 static const TypeInfo virt_machine_info = { 3420 .name = TYPE_VIRT_MACHINE, 3421 .parent = TYPE_MACHINE, 3422 .abstract = true, 3423 .instance_size = sizeof(VirtMachineState), 3424 .class_size = sizeof(VirtMachineClass), 3425 .class_init = virt_machine_class_init, 3426 .instance_init = virt_instance_init, 3427 .interfaces = (const InterfaceInfo[]) { 3428 { TYPE_HOTPLUG_HANDLER }, 3429 { } 3430 }, 3431 }; 3432 3433 static void machvirt_machine_init(void) 3434 { 3435 type_register_static(&virt_machine_info); 3436 } 3437 type_init(machvirt_machine_init); 3438 3439 static void virt_machine_10_1_options(MachineClass *mc) 3440 { 3441 } 3442 DEFINE_VIRT_MACHINE_AS_LATEST(10, 1) 3443 3444 static void virt_machine_10_0_options(MachineClass *mc) 3445 { 3446 virt_machine_10_1_options(mc); 3447 compat_props_add(mc->compat_props, hw_compat_10_0, hw_compat_10_0_len); 3448 } 3449 DEFINE_VIRT_MACHINE(10, 0) 3450 3451 static void virt_machine_9_2_options(MachineClass *mc) 3452 { 3453 virt_machine_10_0_options(mc); 3454 compat_props_add(mc->compat_props, hw_compat_9_2, hw_compat_9_2_len); 3455 } 3456 DEFINE_VIRT_MACHINE(9, 2) 3457 3458 static void virt_machine_9_1_options(MachineClass *mc) 3459 { 3460 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3461 3462 virt_machine_9_2_options(mc); 3463 compat_props_add(mc->compat_props, hw_compat_9_1, hw_compat_9_1_len); 3464 /* 9.1 and earlier have only a stage-1 SMMU, not a nested s1+2 one */ 3465 vmc->no_nested_smmu = true; 3466 } 3467 DEFINE_VIRT_MACHINE(9, 1) 3468 3469 static void virt_machine_9_0_options(MachineClass *mc) 3470 { 3471 virt_machine_9_1_options(mc); 3472 mc->smbios_memory_device_size = 16 * GiB; 3473 compat_props_add(mc->compat_props, hw_compat_9_0, hw_compat_9_0_len); 3474 } 3475 DEFINE_VIRT_MACHINE(9, 0) 3476 3477 static void virt_machine_8_2_options(MachineClass *mc) 3478 { 3479 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3480 3481 virt_machine_9_0_options(mc); 3482 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len); 3483 /* 3484 * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and 3485 * earlier machines. (Exposing it tickles a bug in older EDK2 3486 * guest BIOS binaries.) 3487 */ 3488 vmc->no_ns_el2_virt_timer_irq = true; 3489 } 3490 DEFINE_VIRT_MACHINE(8, 2) 3491 3492 static void virt_machine_8_1_options(MachineClass *mc) 3493 { 3494 virt_machine_8_2_options(mc); 3495 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len); 3496 } 3497 DEFINE_VIRT_MACHINE(8, 1) 3498 3499 static void virt_machine_8_0_options(MachineClass *mc) 3500 { 3501 virt_machine_8_1_options(mc); 3502 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 3503 } 3504 DEFINE_VIRT_MACHINE(8, 0) 3505 3506 static void virt_machine_7_2_options(MachineClass *mc) 3507 { 3508 virt_machine_8_0_options(mc); 3509 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 3510 } 3511 DEFINE_VIRT_MACHINE(7, 2) 3512 3513 static void virt_machine_7_1_options(MachineClass *mc) 3514 { 3515 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3516 3517 virt_machine_7_2_options(mc); 3518 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 3519 /* Compact layout for high memory regions was introduced with 7.2 */ 3520 vmc->no_highmem_compact = true; 3521 } 3522 DEFINE_VIRT_MACHINE(7, 1) 3523 3524 static void virt_machine_7_0_options(MachineClass *mc) 3525 { 3526 virt_machine_7_1_options(mc); 3527 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 3528 } 3529 DEFINE_VIRT_MACHINE(7, 0) 3530 3531 static void virt_machine_6_2_options(MachineClass *mc) 3532 { 3533 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3534 3535 virt_machine_7_0_options(mc); 3536 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 3537 vmc->no_tcg_lpa2 = true; 3538 } 3539 DEFINE_VIRT_MACHINE(6, 2) 3540 3541 static void virt_machine_6_1_options(MachineClass *mc) 3542 { 3543 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3544 3545 virt_machine_6_2_options(mc); 3546 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 3547 mc->smp_props.prefer_sockets = true; 3548 vmc->no_cpu_topology = true; 3549 3550 /* qemu ITS was introduced with 6.2 */ 3551 vmc->no_tcg_its = true; 3552 } 3553 DEFINE_VIRT_MACHINE(6, 1) 3554 3555 static void virt_machine_6_0_options(MachineClass *mc) 3556 { 3557 virt_machine_6_1_options(mc); 3558 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 3559 } 3560 DEFINE_VIRT_MACHINE(6, 0) 3561 3562 static void virt_machine_5_2_options(MachineClass *mc) 3563 { 3564 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3565 3566 virt_machine_6_0_options(mc); 3567 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 3568 vmc->no_secure_gpio = true; 3569 } 3570 DEFINE_VIRT_MACHINE(5, 2) 3571 3572 static void virt_machine_5_1_options(MachineClass *mc) 3573 { 3574 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3575 3576 virt_machine_5_2_options(mc); 3577 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 3578 vmc->no_kvm_steal_time = true; 3579 } 3580 DEFINE_VIRT_MACHINE(5, 1) 3581 3582 static void virt_machine_5_0_options(MachineClass *mc) 3583 { 3584 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3585 3586 virt_machine_5_1_options(mc); 3587 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 3588 mc->numa_mem_supported = true; 3589 vmc->acpi_expose_flash = true; 3590 mc->auto_enable_numa_with_memdev = false; 3591 } 3592 DEFINE_VIRT_MACHINE(5, 0) 3593 3594 static void virt_machine_4_2_options(MachineClass *mc) 3595 { 3596 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3597 3598 virt_machine_5_0_options(mc); 3599 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 3600 vmc->kvm_no_adjvtime = true; 3601 } 3602 DEFINE_VIRT_MACHINE(4, 2) 3603 3604 static void virt_machine_4_1_options(MachineClass *mc) 3605 { 3606 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3607 3608 virt_machine_4_2_options(mc); 3609 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 3610 vmc->no_ged = true; 3611 mc->auto_enable_numa_with_memhp = false; 3612 } 3613 DEFINE_VIRT_MACHINE(4, 1) 3614