1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "hw/sysbus.h" 32 #include "hw/arm/arm.h" 33 #include "hw/arm/primecell.h" 34 #include "hw/devices.h" 35 #include "net/net.h" 36 #include "sysemu/device_tree.h" 37 #include "sysemu/sysemu.h" 38 #include "sysemu/kvm.h" 39 #include "hw/boards.h" 40 #include "exec/address-spaces.h" 41 #include "qemu/bitops.h" 42 #include "qemu/error-report.h" 43 44 #define NUM_VIRTIO_TRANSPORTS 32 45 46 /* Number of external interrupt lines to configure the GIC with */ 47 #define NUM_IRQS 128 48 49 #define GIC_FDT_IRQ_TYPE_SPI 0 50 #define GIC_FDT_IRQ_TYPE_PPI 1 51 52 #define GIC_FDT_IRQ_FLAGS_EDGE_LO_HI 1 53 #define GIC_FDT_IRQ_FLAGS_EDGE_HI_LO 2 54 #define GIC_FDT_IRQ_FLAGS_LEVEL_HI 4 55 #define GIC_FDT_IRQ_FLAGS_LEVEL_LO 8 56 57 #define GIC_FDT_IRQ_PPI_CPU_START 8 58 #define GIC_FDT_IRQ_PPI_CPU_WIDTH 8 59 60 enum { 61 VIRT_FLASH, 62 VIRT_MEM, 63 VIRT_CPUPERIPHS, 64 VIRT_GIC_DIST, 65 VIRT_GIC_CPU, 66 VIRT_UART, 67 VIRT_MMIO, 68 VIRT_RTC, 69 }; 70 71 typedef struct MemMapEntry { 72 hwaddr base; 73 hwaddr size; 74 } MemMapEntry; 75 76 typedef struct VirtBoardInfo { 77 struct arm_boot_info bootinfo; 78 const char *cpu_model; 79 const MemMapEntry *memmap; 80 const int *irqmap; 81 int smp_cpus; 82 void *fdt; 83 int fdt_size; 84 uint32_t clock_phandle; 85 } VirtBoardInfo; 86 87 /* Addresses and sizes of our components. 88 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 89 * 128MB..256MB is used for miscellaneous device I/O. 90 * 256MB..1GB is reserved for possible future PCI support (ie where the 91 * PCI memory window will go if we add a PCI host controller). 92 * 1GB and up is RAM (which may happily spill over into the 93 * high memory region beyond 4GB). 94 * This represents a compromise between how much RAM can be given to 95 * a 32 bit VM and leaving space for expansion and in particular for PCI. 96 * Note that devices should generally be placed at multiples of 0x10000, 97 * to accommodate guests using 64K pages. 98 */ 99 static const MemMapEntry a15memmap[] = { 100 /* Space up to 0x8000000 is reserved for a boot ROM */ 101 [VIRT_FLASH] = { 0, 0x08000000 }, 102 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 103 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 104 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 105 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 106 [VIRT_UART] = { 0x09000000, 0x00001000 }, 107 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 108 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 109 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 110 /* 0x10000000 .. 0x40000000 reserved for PCI */ 111 [VIRT_MEM] = { 0x40000000, 30ULL * 1024 * 1024 * 1024 }, 112 }; 113 114 static const int a15irqmap[] = { 115 [VIRT_UART] = 1, 116 [VIRT_RTC] = 2, 117 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 118 }; 119 120 static VirtBoardInfo machines[] = { 121 { 122 .cpu_model = "cortex-a15", 123 .memmap = a15memmap, 124 .irqmap = a15irqmap, 125 }, 126 { 127 .cpu_model = "cortex-a57", 128 .memmap = a15memmap, 129 .irqmap = a15irqmap, 130 }, 131 { 132 .cpu_model = "host", 133 .memmap = a15memmap, 134 .irqmap = a15irqmap, 135 }, 136 }; 137 138 static VirtBoardInfo *find_machine_info(const char *cpu) 139 { 140 int i; 141 142 for (i = 0; i < ARRAY_SIZE(machines); i++) { 143 if (strcmp(cpu, machines[i].cpu_model) == 0) { 144 return &machines[i]; 145 } 146 } 147 return NULL; 148 } 149 150 static void create_fdt(VirtBoardInfo *vbi) 151 { 152 void *fdt = create_device_tree(&vbi->fdt_size); 153 154 if (!fdt) { 155 error_report("create_device_tree() failed"); 156 exit(1); 157 } 158 159 vbi->fdt = fdt; 160 161 /* Header */ 162 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 163 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 164 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 165 166 /* 167 * /chosen and /memory nodes must exist for load_dtb 168 * to fill in necessary properties later 169 */ 170 qemu_fdt_add_subnode(fdt, "/chosen"); 171 qemu_fdt_add_subnode(fdt, "/memory"); 172 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 173 174 /* Clock node, for the benefit of the UART. The kernel device tree 175 * binding documentation claims the PL011 node clock properties are 176 * optional but in practice if you omit them the kernel refuses to 177 * probe for the device. 178 */ 179 vbi->clock_phandle = qemu_fdt_alloc_phandle(fdt); 180 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 181 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 182 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 183 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 184 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 185 "clk24mhz"); 186 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vbi->clock_phandle); 187 188 } 189 190 static void fdt_add_psci_node(const VirtBoardInfo *vbi) 191 { 192 void *fdt = vbi->fdt; 193 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 194 195 /* No PSCI for TCG yet */ 196 if (kvm_enabled()) { 197 uint32_t cpu_suspend_fn; 198 uint32_t cpu_off_fn; 199 uint32_t cpu_on_fn; 200 uint32_t migrate_fn; 201 202 qemu_fdt_add_subnode(fdt, "/psci"); 203 if (armcpu->psci_version == 2) { 204 const char comp[] = "arm,psci-0.2\0arm,psci"; 205 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 206 207 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 208 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 209 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 210 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 211 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 212 } else { 213 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 214 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 215 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 216 } 217 } else { 218 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 219 220 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 221 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 222 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 223 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 224 } 225 226 qemu_fdt_setprop_string(fdt, "/psci", "method", "hvc"); 227 228 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 229 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 230 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 231 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 232 } 233 } 234 235 static void fdt_add_timer_nodes(const VirtBoardInfo *vbi) 236 { 237 /* Note that on A15 h/w these interrupts are level-triggered, 238 * but for the GIC implementation provided by both QEMU and KVM 239 * they are edge-triggered. 240 */ 241 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 242 243 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 244 GIC_FDT_IRQ_PPI_CPU_WIDTH, (1 << vbi->smp_cpus) - 1); 245 246 qemu_fdt_add_subnode(vbi->fdt, "/timer"); 247 qemu_fdt_setprop_string(vbi->fdt, "/timer", 248 "compatible", "arm,armv7-timer"); 249 qemu_fdt_setprop_cells(vbi->fdt, "/timer", "interrupts", 250 GIC_FDT_IRQ_TYPE_PPI, 13, irqflags, 251 GIC_FDT_IRQ_TYPE_PPI, 14, irqflags, 252 GIC_FDT_IRQ_TYPE_PPI, 11, irqflags, 253 GIC_FDT_IRQ_TYPE_PPI, 10, irqflags); 254 } 255 256 static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi) 257 { 258 int cpu; 259 260 qemu_fdt_add_subnode(vbi->fdt, "/cpus"); 261 qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#address-cells", 0x1); 262 qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#size-cells", 0x0); 263 264 for (cpu = vbi->smp_cpus - 1; cpu >= 0; cpu--) { 265 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 266 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 267 268 qemu_fdt_add_subnode(vbi->fdt, nodename); 269 qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "cpu"); 270 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", 271 armcpu->dtb_compatible); 272 273 if (vbi->smp_cpus > 1) { 274 qemu_fdt_setprop_string(vbi->fdt, nodename, 275 "enable-method", "psci"); 276 } 277 278 qemu_fdt_setprop_cell(vbi->fdt, nodename, "reg", cpu); 279 g_free(nodename); 280 } 281 } 282 283 static void fdt_add_gic_node(const VirtBoardInfo *vbi) 284 { 285 uint32_t gic_phandle; 286 287 gic_phandle = qemu_fdt_alloc_phandle(vbi->fdt); 288 qemu_fdt_setprop_cell(vbi->fdt, "/", "interrupt-parent", gic_phandle); 289 290 qemu_fdt_add_subnode(vbi->fdt, "/intc"); 291 /* 'cortex-a15-gic' means 'GIC v2' */ 292 qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", 293 "arm,cortex-a15-gic"); 294 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#interrupt-cells", 3); 295 qemu_fdt_setprop(vbi->fdt, "/intc", "interrupt-controller", NULL, 0); 296 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", 297 2, vbi->memmap[VIRT_GIC_DIST].base, 298 2, vbi->memmap[VIRT_GIC_DIST].size, 299 2, vbi->memmap[VIRT_GIC_CPU].base, 300 2, vbi->memmap[VIRT_GIC_CPU].size); 301 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", gic_phandle); 302 } 303 304 static void create_gic(const VirtBoardInfo *vbi, qemu_irq *pic) 305 { 306 /* We create a standalone GIC v2 */ 307 DeviceState *gicdev; 308 SysBusDevice *gicbusdev; 309 const char *gictype = "arm_gic"; 310 int i; 311 312 if (kvm_irqchip_in_kernel()) { 313 gictype = "kvm-arm-gic"; 314 } 315 316 gicdev = qdev_create(NULL, gictype); 317 qdev_prop_set_uint32(gicdev, "revision", 2); 318 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 319 /* Note that the num-irq property counts both internal and external 320 * interrupts; there are always 32 of the former (mandated by GIC spec). 321 */ 322 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 323 qdev_init_nofail(gicdev); 324 gicbusdev = SYS_BUS_DEVICE(gicdev); 325 sysbus_mmio_map(gicbusdev, 0, vbi->memmap[VIRT_GIC_DIST].base); 326 sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base); 327 328 /* Wire the outputs from each CPU's generic timer to the 329 * appropriate GIC PPI inputs, and the GIC's IRQ output to 330 * the CPU's IRQ input. 331 */ 332 for (i = 0; i < smp_cpus; i++) { 333 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 334 int ppibase = NUM_IRQS + i * 32; 335 /* physical timer; we wire it up to the non-secure timer's ID, 336 * since a real A15 always has TrustZone but QEMU doesn't. 337 */ 338 qdev_connect_gpio_out(cpudev, 0, 339 qdev_get_gpio_in(gicdev, ppibase + 30)); 340 /* virtual timer */ 341 qdev_connect_gpio_out(cpudev, 1, 342 qdev_get_gpio_in(gicdev, ppibase + 27)); 343 344 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 345 } 346 347 for (i = 0; i < NUM_IRQS; i++) { 348 pic[i] = qdev_get_gpio_in(gicdev, i); 349 } 350 351 fdt_add_gic_node(vbi); 352 } 353 354 static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic) 355 { 356 char *nodename; 357 hwaddr base = vbi->memmap[VIRT_UART].base; 358 hwaddr size = vbi->memmap[VIRT_UART].size; 359 int irq = vbi->irqmap[VIRT_UART]; 360 const char compat[] = "arm,pl011\0arm,primecell"; 361 const char clocknames[] = "uartclk\0apb_pclk"; 362 363 sysbus_create_simple("pl011", base, pic[irq]); 364 365 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 366 qemu_fdt_add_subnode(vbi->fdt, nodename); 367 /* Note that we can't use setprop_string because of the embedded NUL */ 368 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", 369 compat, sizeof(compat)); 370 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 371 2, base, 2, size); 372 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 373 GIC_FDT_IRQ_TYPE_SPI, irq, 374 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 375 qemu_fdt_setprop_cells(vbi->fdt, nodename, "clocks", 376 vbi->clock_phandle, vbi->clock_phandle); 377 qemu_fdt_setprop(vbi->fdt, nodename, "clock-names", 378 clocknames, sizeof(clocknames)); 379 g_free(nodename); 380 } 381 382 static void create_rtc(const VirtBoardInfo *vbi, qemu_irq *pic) 383 { 384 char *nodename; 385 hwaddr base = vbi->memmap[VIRT_RTC].base; 386 hwaddr size = vbi->memmap[VIRT_RTC].size; 387 int irq = vbi->irqmap[VIRT_RTC]; 388 const char compat[] = "arm,pl031\0arm,primecell"; 389 390 sysbus_create_simple("pl031", base, pic[irq]); 391 392 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 393 qemu_fdt_add_subnode(vbi->fdt, nodename); 394 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat)); 395 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 396 2, base, 2, size); 397 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 398 GIC_FDT_IRQ_TYPE_SPI, irq, 399 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 400 qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle); 401 qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk"); 402 g_free(nodename); 403 } 404 405 static void create_virtio_devices(const VirtBoardInfo *vbi, qemu_irq *pic) 406 { 407 int i; 408 hwaddr size = vbi->memmap[VIRT_MMIO].size; 409 410 /* Note that we have to create the transports in forwards order 411 * so that command line devices are inserted lowest address first, 412 * and then add dtb nodes in reverse order so that they appear in 413 * the finished device tree lowest address first. 414 */ 415 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 416 int irq = vbi->irqmap[VIRT_MMIO] + i; 417 hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size; 418 419 sysbus_create_simple("virtio-mmio", base, pic[irq]); 420 } 421 422 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 423 char *nodename; 424 int irq = vbi->irqmap[VIRT_MMIO] + i; 425 hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size; 426 427 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 428 qemu_fdt_add_subnode(vbi->fdt, nodename); 429 qemu_fdt_setprop_string(vbi->fdt, nodename, 430 "compatible", "virtio,mmio"); 431 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 432 2, base, 2, size); 433 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 434 GIC_FDT_IRQ_TYPE_SPI, irq, 435 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 436 g_free(nodename); 437 } 438 } 439 440 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 441 { 442 const VirtBoardInfo *board = (const VirtBoardInfo *)binfo; 443 444 *fdt_size = board->fdt_size; 445 return board->fdt; 446 } 447 448 static void machvirt_init(MachineState *machine) 449 { 450 qemu_irq pic[NUM_IRQS]; 451 MemoryRegion *sysmem = get_system_memory(); 452 int n; 453 MemoryRegion *ram = g_new(MemoryRegion, 1); 454 const char *cpu_model = machine->cpu_model; 455 VirtBoardInfo *vbi; 456 457 if (!cpu_model) { 458 cpu_model = "cortex-a15"; 459 } 460 461 vbi = find_machine_info(cpu_model); 462 463 if (!vbi) { 464 error_report("mach-virt: CPU %s not supported", cpu_model); 465 exit(1); 466 } 467 468 vbi->smp_cpus = smp_cpus; 469 470 /* 471 * Only supported method of starting secondary CPUs is PSCI and 472 * PSCI is not yet supported with TCG, so limit smp_cpus to 1 473 * if we're not using KVM. 474 */ 475 if (!kvm_enabled() && smp_cpus > 1) { 476 error_report("mach-virt: must enable KVM to use multiple CPUs"); 477 exit(1); 478 } 479 480 if (machine->ram_size > vbi->memmap[VIRT_MEM].size) { 481 error_report("mach-virt: cannot model more than 30GB RAM"); 482 exit(1); 483 } 484 485 create_fdt(vbi); 486 fdt_add_timer_nodes(vbi); 487 488 for (n = 0; n < smp_cpus; n++) { 489 ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 490 Object *cpuobj; 491 492 if (!oc) { 493 fprintf(stderr, "Unable to find CPU definition\n"); 494 exit(1); 495 } 496 cpuobj = object_new(object_class_get_name(oc)); 497 498 /* Secondary CPUs start in PSCI powered-down state */ 499 if (n > 0) { 500 object_property_set_bool(cpuobj, true, "start-powered-off", NULL); 501 } 502 503 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 504 object_property_set_int(cpuobj, vbi->memmap[VIRT_CPUPERIPHS].base, 505 "reset-cbar", &error_abort); 506 } 507 508 object_property_set_bool(cpuobj, true, "realized", NULL); 509 } 510 fdt_add_cpu_nodes(vbi); 511 fdt_add_psci_node(vbi); 512 513 memory_region_init_ram(ram, NULL, "mach-virt.ram", machine->ram_size, 514 &error_abort); 515 vmstate_register_ram_global(ram); 516 memory_region_add_subregion(sysmem, vbi->memmap[VIRT_MEM].base, ram); 517 518 create_gic(vbi, pic); 519 520 create_uart(vbi, pic); 521 522 create_rtc(vbi, pic); 523 524 /* Create mmio transports, so the user can create virtio backends 525 * (which will be automatically plugged in to the transports). If 526 * no backend is created the transport will just sit harmlessly idle. 527 */ 528 create_virtio_devices(vbi, pic); 529 530 vbi->bootinfo.ram_size = machine->ram_size; 531 vbi->bootinfo.kernel_filename = machine->kernel_filename; 532 vbi->bootinfo.kernel_cmdline = machine->kernel_cmdline; 533 vbi->bootinfo.initrd_filename = machine->initrd_filename; 534 vbi->bootinfo.nb_cpus = smp_cpus; 535 vbi->bootinfo.board_id = -1; 536 vbi->bootinfo.loader_start = vbi->memmap[VIRT_MEM].base; 537 vbi->bootinfo.get_dtb = machvirt_dtb; 538 arm_load_kernel(ARM_CPU(first_cpu), &vbi->bootinfo); 539 } 540 541 static QEMUMachine machvirt_a15_machine = { 542 .name = "virt", 543 .desc = "ARM Virtual Machine", 544 .init = machvirt_init, 545 .max_cpus = 8, 546 }; 547 548 static void machvirt_machine_init(void) 549 { 550 qemu_register_machine(&machvirt_a15_machine); 551 } 552 553 machine_init(machvirt_machine_init); 554