1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qapi/error.h" 33 #include "hw/sysbus.h" 34 #include "hw/arm/arm.h" 35 #include "hw/arm/primecell.h" 36 #include "hw/arm/virt.h" 37 #include "hw/devices.h" 38 #include "net/net.h" 39 #include "sysemu/block-backend.h" 40 #include "sysemu/device_tree.h" 41 #include "sysemu/numa.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/kvm.h" 44 #include "hw/compat.h" 45 #include "hw/loader.h" 46 #include "exec/address-spaces.h" 47 #include "qemu/bitops.h" 48 #include "qemu/error-report.h" 49 #include "hw/pci-host/gpex.h" 50 #include "hw/arm/sysbus-fdt.h" 51 #include "hw/platform-bus.h" 52 #include "hw/arm/fdt.h" 53 #include "hw/intc/arm_gic.h" 54 #include "hw/intc/arm_gicv3_common.h" 55 #include "kvm_arm.h" 56 #include "hw/smbios/smbios.h" 57 #include "qapi/visitor.h" 58 #include "standard-headers/linux/input.h" 59 60 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 61 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 62 void *data) \ 63 { \ 64 MachineClass *mc = MACHINE_CLASS(oc); \ 65 virt_machine_##major##_##minor##_options(mc); \ 66 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 67 if (latest) { \ 68 mc->alias = "virt"; \ 69 } \ 70 } \ 71 static const TypeInfo machvirt_##major##_##minor##_info = { \ 72 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 73 .parent = TYPE_VIRT_MACHINE, \ 74 .instance_init = virt_##major##_##minor##_instance_init, \ 75 .class_init = virt_##major##_##minor##_class_init, \ 76 }; \ 77 static void machvirt_machine_##major##_##minor##_init(void) \ 78 { \ 79 type_register_static(&machvirt_##major##_##minor##_info); \ 80 } \ 81 type_init(machvirt_machine_##major##_##minor##_init); 82 83 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 84 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 85 #define DEFINE_VIRT_MACHINE(major, minor) \ 86 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 87 88 89 /* Number of external interrupt lines to configure the GIC with */ 90 #define NUM_IRQS 256 91 92 #define PLATFORM_BUS_NUM_IRQS 64 93 94 static ARMPlatformBusSystemParams platform_bus_params; 95 96 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means 97 * RAM can go up to the 256GB mark, leaving 256GB of the physical 98 * address space unallocated and free for future use between 256G and 512G. 99 * If we need to provide more RAM to VMs in the future then we need to: 100 * * allocate a second bank of RAM starting at 2TB and working up 101 * * fix the DT and ACPI table generation code in QEMU to correctly 102 * report two split lumps of RAM to the guest 103 * * fix KVM in the host kernel to allow guests with >40 bit address spaces 104 * (We don't want to fill all the way up to 512GB with RAM because 105 * we might want it for non-RAM purposes later. Conversely it seems 106 * reasonable to assume that anybody configuring a VM with a quarter 107 * of a terabyte of RAM will be doing it on a host with more than a 108 * terabyte of physical address space.) 109 */ 110 #define RAMLIMIT_GB 255 111 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) 112 113 /* Addresses and sizes of our components. 114 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 115 * 128MB..256MB is used for miscellaneous device I/O. 116 * 256MB..1GB is reserved for possible future PCI support (ie where the 117 * PCI memory window will go if we add a PCI host controller). 118 * 1GB and up is RAM (which may happily spill over into the 119 * high memory region beyond 4GB). 120 * This represents a compromise between how much RAM can be given to 121 * a 32 bit VM and leaving space for expansion and in particular for PCI. 122 * Note that devices should generally be placed at multiples of 0x10000, 123 * to accommodate guests using 64K pages. 124 */ 125 static const MemMapEntry a15memmap[] = { 126 /* Space up to 0x8000000 is reserved for a boot ROM */ 127 [VIRT_FLASH] = { 0, 0x08000000 }, 128 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 129 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 130 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 131 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 132 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 133 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 134 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 135 /* This redistributor space allows up to 2*64kB*123 CPUs */ 136 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 137 [VIRT_UART] = { 0x09000000, 0x00001000 }, 138 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 139 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 140 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 141 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 142 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 143 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 144 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 145 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 146 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 147 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 148 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 149 [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES }, 150 /* Second PCIe window, 512GB wide at the 512GB boundary */ 151 [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL }, 152 }; 153 154 static const int a15irqmap[] = { 155 [VIRT_UART] = 1, 156 [VIRT_RTC] = 2, 157 [VIRT_PCIE] = 3, /* ... to 6 */ 158 [VIRT_GPIO] = 7, 159 [VIRT_SECURE_UART] = 8, 160 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 161 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 162 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 163 }; 164 165 static const char *valid_cpus[] = { 166 ARM_CPU_TYPE_NAME("cortex-a15"), 167 ARM_CPU_TYPE_NAME("cortex-a53"), 168 ARM_CPU_TYPE_NAME("cortex-a57"), 169 ARM_CPU_TYPE_NAME("host"), 170 }; 171 172 static bool cpu_type_valid(const char *cpu) 173 { 174 int i; 175 176 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 177 if (strcmp(cpu, valid_cpus[i]) == 0) { 178 return true; 179 } 180 } 181 return false; 182 } 183 184 static void create_fdt(VirtMachineState *vms) 185 { 186 void *fdt = create_device_tree(&vms->fdt_size); 187 188 if (!fdt) { 189 error_report("create_device_tree() failed"); 190 exit(1); 191 } 192 193 vms->fdt = fdt; 194 195 /* Header */ 196 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 197 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 198 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 199 200 /* 201 * /chosen and /memory nodes must exist for load_dtb 202 * to fill in necessary properties later 203 */ 204 qemu_fdt_add_subnode(fdt, "/chosen"); 205 qemu_fdt_add_subnode(fdt, "/memory"); 206 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 207 208 /* Clock node, for the benefit of the UART. The kernel device tree 209 * binding documentation claims the PL011 node clock properties are 210 * optional but in practice if you omit them the kernel refuses to 211 * probe for the device. 212 */ 213 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 214 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 215 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 216 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 217 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 218 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 219 "clk24mhz"); 220 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 221 222 if (have_numa_distance) { 223 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 224 uint32_t *matrix = g_malloc0(size); 225 int idx, i, j; 226 227 for (i = 0; i < nb_numa_nodes; i++) { 228 for (j = 0; j < nb_numa_nodes; j++) { 229 idx = (i * nb_numa_nodes + j) * 3; 230 matrix[idx + 0] = cpu_to_be32(i); 231 matrix[idx + 1] = cpu_to_be32(j); 232 matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]); 233 } 234 } 235 236 qemu_fdt_add_subnode(fdt, "/distance-map"); 237 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 238 "numa-distance-map-v1"); 239 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 240 matrix, size); 241 g_free(matrix); 242 } 243 } 244 245 static void fdt_add_psci_node(const VirtMachineState *vms) 246 { 247 uint32_t cpu_suspend_fn; 248 uint32_t cpu_off_fn; 249 uint32_t cpu_on_fn; 250 uint32_t migrate_fn; 251 void *fdt = vms->fdt; 252 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 253 const char *psci_method; 254 255 switch (vms->psci_conduit) { 256 case QEMU_PSCI_CONDUIT_DISABLED: 257 return; 258 case QEMU_PSCI_CONDUIT_HVC: 259 psci_method = "hvc"; 260 break; 261 case QEMU_PSCI_CONDUIT_SMC: 262 psci_method = "smc"; 263 break; 264 default: 265 g_assert_not_reached(); 266 } 267 268 qemu_fdt_add_subnode(fdt, "/psci"); 269 if (armcpu->psci_version == 2) { 270 const char comp[] = "arm,psci-0.2\0arm,psci"; 271 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 272 273 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 274 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 275 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 276 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 277 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 278 } else { 279 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 280 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 281 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 282 } 283 } else { 284 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 285 286 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 287 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 288 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 289 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 290 } 291 292 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 293 * to the instruction that should be used to invoke PSCI functions. 294 * However, the device tree binding uses 'method' instead, so that is 295 * what we should use here. 296 */ 297 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 298 299 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 300 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 301 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 302 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 303 } 304 305 static void fdt_add_timer_nodes(const VirtMachineState *vms) 306 { 307 /* On real hardware these interrupts are level-triggered. 308 * On KVM they were edge-triggered before host kernel version 4.4, 309 * and level-triggered afterwards. 310 * On emulated QEMU they are level-triggered. 311 * 312 * Getting the DTB info about them wrong is awkward for some 313 * guest kernels: 314 * pre-4.8 ignore the DT and leave the interrupt configured 315 * with whatever the GIC reset value (or the bootloader) left it at 316 * 4.8 before rc6 honour the incorrect data by programming it back 317 * into the GIC, causing problems 318 * 4.8rc6 and later ignore the DT and always write "level triggered" 319 * into the GIC 320 * 321 * For backwards-compatibility, virt-2.8 and earlier will continue 322 * to say these are edge-triggered, but later machines will report 323 * the correct information. 324 */ 325 ARMCPU *armcpu; 326 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 327 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 328 329 if (vmc->claim_edge_triggered_timers) { 330 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 331 } 332 333 if (vms->gic_version == 2) { 334 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 335 GIC_FDT_IRQ_PPI_CPU_WIDTH, 336 (1 << vms->smp_cpus) - 1); 337 } 338 339 qemu_fdt_add_subnode(vms->fdt, "/timer"); 340 341 armcpu = ARM_CPU(qemu_get_cpu(0)); 342 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 343 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 344 qemu_fdt_setprop(vms->fdt, "/timer", "compatible", 345 compat, sizeof(compat)); 346 } else { 347 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible", 348 "arm,armv7-timer"); 349 } 350 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0); 351 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts", 352 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 353 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 354 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 355 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 356 } 357 358 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 359 { 360 int cpu; 361 int addr_cells = 1; 362 const MachineState *ms = MACHINE(vms); 363 364 /* 365 * From Documentation/devicetree/bindings/arm/cpus.txt 366 * On ARM v8 64-bit systems value should be set to 2, 367 * that corresponds to the MPIDR_EL1 register size. 368 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 369 * in the system, #address-cells can be set to 1, since 370 * MPIDR_EL1[63:32] bits are not used for CPUs 371 * identification. 372 * 373 * Here we actually don't know whether our system is 32- or 64-bit one. 374 * The simplest way to go is to examine affinity IDs of all our CPUs. If 375 * at least one of them has Aff3 populated, we set #address-cells to 2. 376 */ 377 for (cpu = 0; cpu < vms->smp_cpus; cpu++) { 378 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 379 380 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 381 addr_cells = 2; 382 break; 383 } 384 } 385 386 qemu_fdt_add_subnode(vms->fdt, "/cpus"); 387 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); 388 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); 389 390 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { 391 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 392 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 393 CPUState *cs = CPU(armcpu); 394 395 qemu_fdt_add_subnode(vms->fdt, nodename); 396 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); 397 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 398 armcpu->dtb_compatible); 399 400 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED 401 && vms->smp_cpus > 1) { 402 qemu_fdt_setprop_string(vms->fdt, nodename, 403 "enable-method", "psci"); 404 } 405 406 if (addr_cells == 2) { 407 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", 408 armcpu->mp_affinity); 409 } else { 410 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", 411 armcpu->mp_affinity); 412 } 413 414 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 415 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", 416 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 417 } 418 419 g_free(nodename); 420 } 421 } 422 423 static void fdt_add_its_gic_node(VirtMachineState *vms) 424 { 425 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 426 qemu_fdt_add_subnode(vms->fdt, "/intc/its"); 427 qemu_fdt_setprop_string(vms->fdt, "/intc/its", "compatible", 428 "arm,gic-v3-its"); 429 qemu_fdt_setprop(vms->fdt, "/intc/its", "msi-controller", NULL, 0); 430 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/its", "reg", 431 2, vms->memmap[VIRT_GIC_ITS].base, 432 2, vms->memmap[VIRT_GIC_ITS].size); 433 qemu_fdt_setprop_cell(vms->fdt, "/intc/its", "phandle", vms->msi_phandle); 434 } 435 436 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 437 { 438 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 439 qemu_fdt_add_subnode(vms->fdt, "/intc/v2m"); 440 qemu_fdt_setprop_string(vms->fdt, "/intc/v2m", "compatible", 441 "arm,gic-v2m-frame"); 442 qemu_fdt_setprop(vms->fdt, "/intc/v2m", "msi-controller", NULL, 0); 443 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/v2m", "reg", 444 2, vms->memmap[VIRT_GIC_V2M].base, 445 2, vms->memmap[VIRT_GIC_V2M].size); 446 qemu_fdt_setprop_cell(vms->fdt, "/intc/v2m", "phandle", vms->msi_phandle); 447 } 448 449 static void fdt_add_gic_node(VirtMachineState *vms) 450 { 451 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt); 452 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle); 453 454 qemu_fdt_add_subnode(vms->fdt, "/intc"); 455 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#interrupt-cells", 3); 456 qemu_fdt_setprop(vms->fdt, "/intc", "interrupt-controller", NULL, 0); 457 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#address-cells", 0x2); 458 qemu_fdt_setprop_cell(vms->fdt, "/intc", "#size-cells", 0x2); 459 qemu_fdt_setprop(vms->fdt, "/intc", "ranges", NULL, 0); 460 if (vms->gic_version == 3) { 461 qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", 462 "arm,gic-v3"); 463 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", 464 2, vms->memmap[VIRT_GIC_DIST].base, 465 2, vms->memmap[VIRT_GIC_DIST].size, 466 2, vms->memmap[VIRT_GIC_REDIST].base, 467 2, vms->memmap[VIRT_GIC_REDIST].size); 468 if (vms->virt) { 469 qemu_fdt_setprop_cells(vms->fdt, "/intc", "interrupts", 470 GIC_FDT_IRQ_TYPE_PPI, ARCH_GICV3_MAINT_IRQ, 471 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 472 } 473 } else { 474 /* 'cortex-a15-gic' means 'GIC v2' */ 475 qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", 476 "arm,cortex-a15-gic"); 477 qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", 478 2, vms->memmap[VIRT_GIC_DIST].base, 479 2, vms->memmap[VIRT_GIC_DIST].size, 480 2, vms->memmap[VIRT_GIC_CPU].base, 481 2, vms->memmap[VIRT_GIC_CPU].size); 482 } 483 484 qemu_fdt_setprop_cell(vms->fdt, "/intc", "phandle", vms->gic_phandle); 485 } 486 487 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 488 { 489 CPUState *cpu; 490 ARMCPU *armcpu; 491 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 492 493 CPU_FOREACH(cpu) { 494 armcpu = ARM_CPU(cpu); 495 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 496 return; 497 } 498 if (kvm_enabled()) { 499 if (kvm_irqchip_in_kernel()) { 500 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 501 } 502 kvm_arm_pmu_init(cpu); 503 } 504 } 505 506 if (vms->gic_version == 2) { 507 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 508 GIC_FDT_IRQ_PPI_CPU_WIDTH, 509 (1 << vms->smp_cpus) - 1); 510 } 511 512 armcpu = ARM_CPU(qemu_get_cpu(0)); 513 qemu_fdt_add_subnode(vms->fdt, "/pmu"); 514 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 515 const char compat[] = "arm,armv8-pmuv3"; 516 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible", 517 compat, sizeof(compat)); 518 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts", 519 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 520 } 521 } 522 523 static void create_its(VirtMachineState *vms, DeviceState *gicdev) 524 { 525 const char *itsclass = its_class_name(); 526 DeviceState *dev; 527 528 if (!itsclass) { 529 /* Do nothing if not supported */ 530 return; 531 } 532 533 dev = qdev_create(NULL, itsclass); 534 535 object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3", 536 &error_abort); 537 qdev_init_nofail(dev); 538 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 539 540 fdt_add_its_gic_node(vms); 541 } 542 543 static void create_v2m(VirtMachineState *vms, qemu_irq *pic) 544 { 545 int i; 546 int irq = vms->irqmap[VIRT_GIC_V2M]; 547 DeviceState *dev; 548 549 dev = qdev_create(NULL, "arm-gicv2m"); 550 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 551 qdev_prop_set_uint32(dev, "base-spi", irq); 552 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 553 qdev_init_nofail(dev); 554 555 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 556 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 557 } 558 559 fdt_add_v2m_gic_node(vms); 560 } 561 562 static void create_gic(VirtMachineState *vms, qemu_irq *pic) 563 { 564 /* We create a standalone GIC */ 565 DeviceState *gicdev; 566 SysBusDevice *gicbusdev; 567 const char *gictype; 568 int type = vms->gic_version, i; 569 570 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 571 572 gicdev = qdev_create(NULL, gictype); 573 qdev_prop_set_uint32(gicdev, "revision", type); 574 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 575 /* Note that the num-irq property counts both internal and external 576 * interrupts; there are always 32 of the former (mandated by GIC spec). 577 */ 578 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 579 if (!kvm_irqchip_in_kernel()) { 580 qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure); 581 } 582 qdev_init_nofail(gicdev); 583 gicbusdev = SYS_BUS_DEVICE(gicdev); 584 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 585 if (type == 3) { 586 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 587 } else { 588 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 589 } 590 591 /* Wire the outputs from each CPU's generic timer and the GICv3 592 * maintenance interrupt signal to the appropriate GIC PPI inputs, 593 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 594 */ 595 for (i = 0; i < smp_cpus; i++) { 596 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 597 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 598 int irq; 599 /* Mapping from the output timer irq lines from the CPU to the 600 * GIC PPI inputs we use for the virt board. 601 */ 602 const int timer_irq[] = { 603 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 604 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 605 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 606 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 607 }; 608 609 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 610 qdev_connect_gpio_out(cpudev, irq, 611 qdev_get_gpio_in(gicdev, 612 ppibase + timer_irq[irq])); 613 } 614 615 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 616 qdev_get_gpio_in(gicdev, ppibase 617 + ARCH_GICV3_MAINT_IRQ)); 618 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 619 qdev_get_gpio_in(gicdev, ppibase 620 + VIRTUAL_PMU_IRQ)); 621 622 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 623 sysbus_connect_irq(gicbusdev, i + smp_cpus, 624 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 625 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 626 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 627 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 628 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 629 } 630 631 for (i = 0; i < NUM_IRQS; i++) { 632 pic[i] = qdev_get_gpio_in(gicdev, i); 633 } 634 635 fdt_add_gic_node(vms); 636 637 if (type == 3 && vms->its) { 638 create_its(vms, gicdev); 639 } else if (type == 2) { 640 create_v2m(vms, pic); 641 } 642 } 643 644 static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart, 645 MemoryRegion *mem, Chardev *chr) 646 { 647 char *nodename; 648 hwaddr base = vms->memmap[uart].base; 649 hwaddr size = vms->memmap[uart].size; 650 int irq = vms->irqmap[uart]; 651 const char compat[] = "arm,pl011\0arm,primecell"; 652 const char clocknames[] = "uartclk\0apb_pclk"; 653 DeviceState *dev = qdev_create(NULL, "pl011"); 654 SysBusDevice *s = SYS_BUS_DEVICE(dev); 655 656 qdev_prop_set_chr(dev, "chardev", chr); 657 qdev_init_nofail(dev); 658 memory_region_add_subregion(mem, base, 659 sysbus_mmio_get_region(s, 0)); 660 sysbus_connect_irq(s, 0, pic[irq]); 661 662 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 663 qemu_fdt_add_subnode(vms->fdt, nodename); 664 /* Note that we can't use setprop_string because of the embedded NUL */ 665 qemu_fdt_setprop(vms->fdt, nodename, "compatible", 666 compat, sizeof(compat)); 667 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 668 2, base, 2, size); 669 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 670 GIC_FDT_IRQ_TYPE_SPI, irq, 671 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 672 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks", 673 vms->clock_phandle, vms->clock_phandle); 674 qemu_fdt_setprop(vms->fdt, nodename, "clock-names", 675 clocknames, sizeof(clocknames)); 676 677 if (uart == VIRT_UART) { 678 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); 679 } else { 680 /* Mark as not usable by the normal world */ 681 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 682 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 683 } 684 685 g_free(nodename); 686 } 687 688 static void create_rtc(const VirtMachineState *vms, qemu_irq *pic) 689 { 690 char *nodename; 691 hwaddr base = vms->memmap[VIRT_RTC].base; 692 hwaddr size = vms->memmap[VIRT_RTC].size; 693 int irq = vms->irqmap[VIRT_RTC]; 694 const char compat[] = "arm,pl031\0arm,primecell"; 695 696 sysbus_create_simple("pl031", base, pic[irq]); 697 698 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 699 qemu_fdt_add_subnode(vms->fdt, nodename); 700 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 701 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 702 2, base, 2, size); 703 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 704 GIC_FDT_IRQ_TYPE_SPI, irq, 705 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 706 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 707 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 708 g_free(nodename); 709 } 710 711 static DeviceState *gpio_key_dev; 712 static void virt_powerdown_req(Notifier *n, void *opaque) 713 { 714 /* use gpio Pin 3 for power button event */ 715 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 716 } 717 718 static Notifier virt_system_powerdown_notifier = { 719 .notify = virt_powerdown_req 720 }; 721 722 static void create_gpio(const VirtMachineState *vms, qemu_irq *pic) 723 { 724 char *nodename; 725 DeviceState *pl061_dev; 726 hwaddr base = vms->memmap[VIRT_GPIO].base; 727 hwaddr size = vms->memmap[VIRT_GPIO].size; 728 int irq = vms->irqmap[VIRT_GPIO]; 729 const char compat[] = "arm,pl061\0arm,primecell"; 730 731 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); 732 733 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); 734 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 735 qemu_fdt_add_subnode(vms->fdt, nodename); 736 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 737 2, base, 2, size); 738 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 739 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); 740 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); 741 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 742 GIC_FDT_IRQ_TYPE_SPI, irq, 743 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 744 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 745 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 746 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); 747 748 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 749 qdev_get_gpio_in(pl061_dev, 3)); 750 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); 751 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); 752 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); 753 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); 754 755 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); 756 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", 757 "label", "GPIO Key Poweroff"); 758 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", 759 KEY_POWER); 760 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", 761 "gpios", phandle, 3, 0); 762 763 /* connect powerdown request */ 764 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier); 765 766 g_free(nodename); 767 } 768 769 static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic) 770 { 771 int i; 772 hwaddr size = vms->memmap[VIRT_MMIO].size; 773 774 /* We create the transports in forwards order. Since qbus_realize() 775 * prepends (not appends) new child buses, the incrementing loop below will 776 * create a list of virtio-mmio buses with decreasing base addresses. 777 * 778 * When a -device option is processed from the command line, 779 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 780 * order. The upshot is that -device options in increasing command line 781 * order are mapped to virtio-mmio buses with decreasing base addresses. 782 * 783 * When this code was originally written, that arrangement ensured that the 784 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 785 * the first -device on the command line. (The end-to-end order is a 786 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 787 * guest kernel's name-to-address assignment strategy.) 788 * 789 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 790 * the message, if not necessarily the code, of commit 70161ff336. 791 * Therefore the loop now establishes the inverse of the original intent. 792 * 793 * Unfortunately, we can't counteract the kernel change by reversing the 794 * loop; it would break existing command lines. 795 * 796 * In any case, the kernel makes no guarantee about the stability of 797 * enumeration order of virtio devices (as demonstrated by it changing 798 * between kernel versions). For reliable and stable identification 799 * of disks users must use UUIDs or similar mechanisms. 800 */ 801 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 802 int irq = vms->irqmap[VIRT_MMIO] + i; 803 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 804 805 sysbus_create_simple("virtio-mmio", base, pic[irq]); 806 } 807 808 /* We add dtb nodes in reverse order so that they appear in the finished 809 * device tree lowest address first. 810 * 811 * Note that this mapping is independent of the loop above. The previous 812 * loop influences virtio device to virtio transport assignment, whereas 813 * this loop controls how virtio transports are laid out in the dtb. 814 */ 815 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 816 char *nodename; 817 int irq = vms->irqmap[VIRT_MMIO] + i; 818 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 819 820 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 821 qemu_fdt_add_subnode(vms->fdt, nodename); 822 qemu_fdt_setprop_string(vms->fdt, nodename, 823 "compatible", "virtio,mmio"); 824 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 825 2, base, 2, size); 826 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 827 GIC_FDT_IRQ_TYPE_SPI, irq, 828 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 829 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 830 g_free(nodename); 831 } 832 } 833 834 static void create_one_flash(const char *name, hwaddr flashbase, 835 hwaddr flashsize, const char *file, 836 MemoryRegion *sysmem) 837 { 838 /* Create and map a single flash device. We use the same 839 * parameters as the flash devices on the Versatile Express board. 840 */ 841 DriveInfo *dinfo = drive_get_next(IF_PFLASH); 842 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 843 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 844 const uint64_t sectorlength = 256 * 1024; 845 846 if (dinfo) { 847 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 848 &error_abort); 849 } 850 851 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); 852 qdev_prop_set_uint64(dev, "sector-length", sectorlength); 853 qdev_prop_set_uint8(dev, "width", 4); 854 qdev_prop_set_uint8(dev, "device-width", 2); 855 qdev_prop_set_bit(dev, "big-endian", false); 856 qdev_prop_set_uint16(dev, "id0", 0x89); 857 qdev_prop_set_uint16(dev, "id1", 0x18); 858 qdev_prop_set_uint16(dev, "id2", 0x00); 859 qdev_prop_set_uint16(dev, "id3", 0x00); 860 qdev_prop_set_string(dev, "name", name); 861 qdev_init_nofail(dev); 862 863 memory_region_add_subregion(sysmem, flashbase, 864 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 865 866 if (file) { 867 char *fn; 868 int image_size; 869 870 if (drive_get(IF_PFLASH, 0, 0)) { 871 error_report("The contents of the first flash device may be " 872 "specified with -bios or with -drive if=pflash... " 873 "but you cannot use both options at once"); 874 exit(1); 875 } 876 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file); 877 if (!fn) { 878 error_report("Could not find ROM image '%s'", file); 879 exit(1); 880 } 881 image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0)); 882 g_free(fn); 883 if (image_size < 0) { 884 error_report("Could not load ROM image '%s'", file); 885 exit(1); 886 } 887 } 888 } 889 890 static void create_flash(const VirtMachineState *vms, 891 MemoryRegion *sysmem, 892 MemoryRegion *secure_sysmem) 893 { 894 /* Create two flash devices to fill the VIRT_FLASH space in the memmap. 895 * Any file passed via -bios goes in the first of these. 896 * sysmem is the system memory space. secure_sysmem is the secure view 897 * of the system, and the first flash device should be made visible only 898 * there. The second flash device is visible to both secure and nonsecure. 899 * If sysmem == secure_sysmem this means there is no separate Secure 900 * address space and both flash devices are generally visible. 901 */ 902 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 903 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 904 char *nodename; 905 906 create_one_flash("virt.flash0", flashbase, flashsize, 907 bios_name, secure_sysmem); 908 create_one_flash("virt.flash1", flashbase + flashsize, flashsize, 909 NULL, sysmem); 910 911 if (sysmem == secure_sysmem) { 912 /* Report both flash devices as a single node in the DT */ 913 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 914 qemu_fdt_add_subnode(vms->fdt, nodename); 915 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 916 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 917 2, flashbase, 2, flashsize, 918 2, flashbase + flashsize, 2, flashsize); 919 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 920 g_free(nodename); 921 } else { 922 /* Report the devices as separate nodes so we can mark one as 923 * only visible to the secure world. 924 */ 925 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 926 qemu_fdt_add_subnode(vms->fdt, nodename); 927 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 928 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 929 2, flashbase, 2, flashsize); 930 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 931 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 932 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 933 g_free(nodename); 934 935 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 936 qemu_fdt_add_subnode(vms->fdt, nodename); 937 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 938 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 939 2, flashbase + flashsize, 2, flashsize); 940 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 941 g_free(nodename); 942 } 943 } 944 945 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 946 { 947 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 948 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 949 FWCfgState *fw_cfg; 950 char *nodename; 951 952 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 953 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 954 955 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 956 qemu_fdt_add_subnode(vms->fdt, nodename); 957 qemu_fdt_setprop_string(vms->fdt, nodename, 958 "compatible", "qemu,fw-cfg-mmio"); 959 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 960 2, base, 2, size); 961 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 962 g_free(nodename); 963 return fw_cfg; 964 } 965 966 static void create_pcie_irq_map(const VirtMachineState *vms, 967 uint32_t gic_phandle, 968 int first_irq, const char *nodename) 969 { 970 int devfn, pin; 971 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 972 uint32_t *irq_map = full_irq_map; 973 974 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 975 for (pin = 0; pin < 4; pin++) { 976 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 977 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 978 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 979 int i; 980 981 uint32_t map[] = { 982 devfn << 8, 0, 0, /* devfn */ 983 pin + 1, /* PCI pin */ 984 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 985 986 /* Convert map to big endian */ 987 for (i = 0; i < 10; i++) { 988 irq_map[i] = cpu_to_be32(map[i]); 989 } 990 irq_map += 10; 991 } 992 } 993 994 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map", 995 full_irq_map, sizeof(full_irq_map)); 996 997 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask", 998 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 999 0x7 /* PCI irq */); 1000 } 1001 1002 static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) 1003 { 1004 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1005 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1006 hwaddr base_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].base; 1007 hwaddr size_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].size; 1008 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1009 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1010 hwaddr base_ecam = vms->memmap[VIRT_PCIE_ECAM].base; 1011 hwaddr size_ecam = vms->memmap[VIRT_PCIE_ECAM].size; 1012 hwaddr base = base_mmio; 1013 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1014 int irq = vms->irqmap[VIRT_PCIE]; 1015 MemoryRegion *mmio_alias; 1016 MemoryRegion *mmio_reg; 1017 MemoryRegion *ecam_alias; 1018 MemoryRegion *ecam_reg; 1019 DeviceState *dev; 1020 char *nodename; 1021 int i; 1022 PCIHostState *pci; 1023 1024 dev = qdev_create(NULL, TYPE_GPEX_HOST); 1025 qdev_init_nofail(dev); 1026 1027 /* Map only the first size_ecam bytes of ECAM space */ 1028 ecam_alias = g_new0(MemoryRegion, 1); 1029 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1030 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1031 ecam_reg, 0, size_ecam); 1032 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1033 1034 /* Map the MMIO window into system address space so as to expose 1035 * the section of PCI MMIO space which starts at the same base address 1036 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1037 * the window). 1038 */ 1039 mmio_alias = g_new0(MemoryRegion, 1); 1040 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1041 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1042 mmio_reg, base_mmio, size_mmio); 1043 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1044 1045 if (vms->highmem) { 1046 /* Map high MMIO space */ 1047 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1048 1049 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1050 mmio_reg, base_mmio_high, size_mmio_high); 1051 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1052 high_mmio_alias); 1053 } 1054 1055 /* Map IO port space */ 1056 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1057 1058 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1059 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 1060 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1061 } 1062 1063 pci = PCI_HOST_BRIDGE(dev); 1064 if (pci->bus) { 1065 for (i = 0; i < nb_nics; i++) { 1066 NICInfo *nd = &nd_table[i]; 1067 1068 if (!nd->model) { 1069 nd->model = g_strdup("virtio"); 1070 } 1071 1072 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1073 } 1074 } 1075 1076 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1077 qemu_fdt_add_subnode(vms->fdt, nodename); 1078 qemu_fdt_setprop_string(vms->fdt, nodename, 1079 "compatible", "pci-host-ecam-generic"); 1080 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci"); 1081 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3); 1082 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2); 1083 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0, 1084 nr_pcie_buses - 1); 1085 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1086 1087 if (vms->msi_phandle) { 1088 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", 1089 vms->msi_phandle); 1090 } 1091 1092 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1093 2, base_ecam, 2, size_ecam); 1094 1095 if (vms->highmem) { 1096 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1097 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1098 2, base_pio, 2, size_pio, 1099 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1100 2, base_mmio, 2, size_mmio, 1101 1, FDT_PCI_RANGE_MMIO_64BIT, 1102 2, base_mmio_high, 1103 2, base_mmio_high, 2, size_mmio_high); 1104 } else { 1105 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1106 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1107 2, base_pio, 2, size_pio, 1108 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1109 2, base_mmio, 2, size_mmio); 1110 } 1111 1112 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); 1113 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); 1114 1115 g_free(nodename); 1116 } 1117 1118 static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic) 1119 { 1120 DeviceState *dev; 1121 SysBusDevice *s; 1122 int i; 1123 ARMPlatformBusFDTParams *fdt_params = g_new(ARMPlatformBusFDTParams, 1); 1124 MemoryRegion *sysmem = get_system_memory(); 1125 1126 platform_bus_params.platform_bus_base = vms->memmap[VIRT_PLATFORM_BUS].base; 1127 platform_bus_params.platform_bus_size = vms->memmap[VIRT_PLATFORM_BUS].size; 1128 platform_bus_params.platform_bus_first_irq = vms->irqmap[VIRT_PLATFORM_BUS]; 1129 platform_bus_params.platform_bus_num_irqs = PLATFORM_BUS_NUM_IRQS; 1130 1131 fdt_params->system_params = &platform_bus_params; 1132 fdt_params->binfo = &vms->bootinfo; 1133 fdt_params->intc = "/intc"; 1134 /* 1135 * register a machine init done notifier that creates the device tree 1136 * nodes of the platform bus and its children dynamic sysbus devices 1137 */ 1138 arm_register_platform_bus_fdt_creator(fdt_params); 1139 1140 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1141 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1142 qdev_prop_set_uint32(dev, "num_irqs", 1143 platform_bus_params.platform_bus_num_irqs); 1144 qdev_prop_set_uint32(dev, "mmio_size", 1145 platform_bus_params.platform_bus_size); 1146 qdev_init_nofail(dev); 1147 s = SYS_BUS_DEVICE(dev); 1148 1149 for (i = 0; i < platform_bus_params.platform_bus_num_irqs; i++) { 1150 int irqn = platform_bus_params.platform_bus_first_irq + i; 1151 sysbus_connect_irq(s, i, pic[irqn]); 1152 } 1153 1154 memory_region_add_subregion(sysmem, 1155 platform_bus_params.platform_bus_base, 1156 sysbus_mmio_get_region(s, 0)); 1157 } 1158 1159 static void create_secure_ram(VirtMachineState *vms, 1160 MemoryRegion *secure_sysmem) 1161 { 1162 MemoryRegion *secram = g_new(MemoryRegion, 1); 1163 char *nodename; 1164 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1165 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1166 1167 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1168 &error_fatal); 1169 memory_region_add_subregion(secure_sysmem, base, secram); 1170 1171 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1172 qemu_fdt_add_subnode(vms->fdt, nodename); 1173 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory"); 1174 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size); 1175 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1176 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1177 1178 g_free(nodename); 1179 } 1180 1181 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1182 { 1183 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1184 bootinfo); 1185 1186 *fdt_size = board->fdt_size; 1187 return board->fdt; 1188 } 1189 1190 static void virt_build_smbios(VirtMachineState *vms) 1191 { 1192 uint8_t *smbios_tables, *smbios_anchor; 1193 size_t smbios_tables_len, smbios_anchor_len; 1194 const char *product = "QEMU Virtual Machine"; 1195 1196 if (!vms->fw_cfg) { 1197 return; 1198 } 1199 1200 if (kvm_enabled()) { 1201 product = "KVM Virtual Machine"; 1202 } 1203 1204 smbios_set_defaults("QEMU", product, 1205 "1.0", false, true, SMBIOS_ENTRY_POINT_30); 1206 1207 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, 1208 &smbios_anchor, &smbios_anchor_len); 1209 1210 if (smbios_anchor) { 1211 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1212 smbios_tables, smbios_tables_len); 1213 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1214 smbios_anchor, smbios_anchor_len); 1215 } 1216 } 1217 1218 static 1219 void virt_machine_done(Notifier *notifier, void *data) 1220 { 1221 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1222 machine_done); 1223 1224 virt_acpi_setup(vms); 1225 virt_build_smbios(vms); 1226 } 1227 1228 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1229 { 1230 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1231 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1232 1233 if (!vmc->disallow_affinity_adjustment) { 1234 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1235 * GIC's target-list limitations. 32-bit KVM hosts currently 1236 * always create clusters of 4 CPUs, but that is expected to 1237 * change when they gain support for gicv3. When KVM is enabled 1238 * it will override the changes we make here, therefore our 1239 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1240 * and to improve SGI efficiency. 1241 */ 1242 if (vms->gic_version == 3) { 1243 clustersz = GICV3_TARGETLIST_BITS; 1244 } else { 1245 clustersz = GIC_TARGETLIST_BITS; 1246 } 1247 } 1248 return arm_cpu_mp_affinity(idx, clustersz); 1249 } 1250 1251 static void machvirt_init(MachineState *machine) 1252 { 1253 VirtMachineState *vms = VIRT_MACHINE(machine); 1254 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1255 MachineClass *mc = MACHINE_GET_CLASS(machine); 1256 const CPUArchIdList *possible_cpus; 1257 qemu_irq pic[NUM_IRQS]; 1258 MemoryRegion *sysmem = get_system_memory(); 1259 MemoryRegion *secure_sysmem = NULL; 1260 int n, virt_max_cpus; 1261 MemoryRegion *ram = g_new(MemoryRegion, 1); 1262 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); 1263 1264 /* We can probe only here because during property set 1265 * KVM is not available yet 1266 */ 1267 if (!vms->gic_version) { 1268 if (!kvm_enabled()) { 1269 error_report("gic-version=host requires KVM"); 1270 exit(1); 1271 } 1272 1273 vms->gic_version = kvm_arm_vgic_probe(); 1274 if (!vms->gic_version) { 1275 error_report("Unable to determine GIC version supported by host"); 1276 exit(1); 1277 } 1278 } 1279 1280 if (!cpu_type_valid(machine->cpu_type)) { 1281 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 1282 exit(1); 1283 } 1284 1285 /* If we have an EL3 boot ROM then the assumption is that it will 1286 * implement PSCI itself, so disable QEMU's internal implementation 1287 * so it doesn't get in the way. Instead of starting secondary 1288 * CPUs in PSCI powerdown state we will start them all running and 1289 * let the boot ROM sort them out. 1290 * The usual case is that we do use QEMU's PSCI implementation; 1291 * if the guest has EL2 then we will use SMC as the conduit, 1292 * and otherwise we will use HVC (for backwards compatibility and 1293 * because if we're using KVM then we must use HVC). 1294 */ 1295 if (vms->secure && firmware_loaded) { 1296 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1297 } else if (vms->virt) { 1298 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 1299 } else { 1300 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 1301 } 1302 1303 /* The maximum number of CPUs depends on the GIC version, or on how 1304 * many redistributors we can fit into the memory map. 1305 */ 1306 if (vms->gic_version == 3) { 1307 virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / 0x20000; 1308 } else { 1309 virt_max_cpus = GIC_NCPU; 1310 } 1311 1312 if (max_cpus > virt_max_cpus) { 1313 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1314 "supported by machine 'mach-virt' (%d)", 1315 max_cpus, virt_max_cpus); 1316 exit(1); 1317 } 1318 1319 vms->smp_cpus = smp_cpus; 1320 1321 if (machine->ram_size > vms->memmap[VIRT_MEM].size) { 1322 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB); 1323 exit(1); 1324 } 1325 1326 if (vms->virt && kvm_enabled()) { 1327 error_report("mach-virt: KVM does not support providing " 1328 "Virtualization extensions to the guest CPU"); 1329 exit(1); 1330 } 1331 1332 if (vms->secure) { 1333 if (kvm_enabled()) { 1334 error_report("mach-virt: KVM does not support Security extensions"); 1335 exit(1); 1336 } 1337 1338 /* The Secure view of the world is the same as the NonSecure, 1339 * but with a few extra devices. Create it as a container region 1340 * containing the system memory at low priority; any secure-only 1341 * devices go in at higher priority and take precedence. 1342 */ 1343 secure_sysmem = g_new(MemoryRegion, 1); 1344 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1345 UINT64_MAX); 1346 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1347 } 1348 1349 create_fdt(vms); 1350 1351 possible_cpus = mc->possible_cpu_arch_ids(machine); 1352 for (n = 0; n < possible_cpus->len; n++) { 1353 Object *cpuobj; 1354 CPUState *cs; 1355 1356 if (n >= smp_cpus) { 1357 break; 1358 } 1359 1360 cpuobj = object_new(machine->cpu_type); 1361 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 1362 "mp-affinity", NULL); 1363 1364 cs = CPU(cpuobj); 1365 cs->cpu_index = n; 1366 1367 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 1368 &error_fatal); 1369 1370 if (!vms->secure) { 1371 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1372 } 1373 1374 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { 1375 object_property_set_bool(cpuobj, false, "has_el2", NULL); 1376 } 1377 1378 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1379 object_property_set_int(cpuobj, vms->psci_conduit, 1380 "psci-conduit", NULL); 1381 1382 /* Secondary CPUs start in PSCI powered-down state */ 1383 if (n > 0) { 1384 object_property_set_bool(cpuobj, true, 1385 "start-powered-off", NULL); 1386 } 1387 } 1388 1389 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { 1390 object_property_set_bool(cpuobj, false, "pmu", NULL); 1391 } 1392 1393 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1394 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, 1395 "reset-cbar", &error_abort); 1396 } 1397 1398 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1399 &error_abort); 1400 if (vms->secure) { 1401 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1402 "secure-memory", &error_abort); 1403 } 1404 1405 object_property_set_bool(cpuobj, true, "realized", NULL); 1406 object_unref(cpuobj); 1407 } 1408 fdt_add_timer_nodes(vms); 1409 fdt_add_cpu_nodes(vms); 1410 fdt_add_psci_node(vms); 1411 1412 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", 1413 machine->ram_size); 1414 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); 1415 1416 create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem); 1417 1418 create_gic(vms, pic); 1419 1420 fdt_add_pmu_nodes(vms); 1421 1422 create_uart(vms, pic, VIRT_UART, sysmem, serial_hds[0]); 1423 1424 if (vms->secure) { 1425 create_secure_ram(vms, secure_sysmem); 1426 create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hds[1]); 1427 } 1428 1429 create_rtc(vms, pic); 1430 1431 create_pcie(vms, pic); 1432 1433 create_gpio(vms, pic); 1434 1435 /* Create mmio transports, so the user can create virtio backends 1436 * (which will be automatically plugged in to the transports). If 1437 * no backend is created the transport will just sit harmlessly idle. 1438 */ 1439 create_virtio_devices(vms, pic); 1440 1441 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 1442 rom_set_fw(vms->fw_cfg); 1443 1444 vms->machine_done.notify = virt_machine_done; 1445 qemu_add_machine_init_done_notifier(&vms->machine_done); 1446 1447 vms->bootinfo.ram_size = machine->ram_size; 1448 vms->bootinfo.kernel_filename = machine->kernel_filename; 1449 vms->bootinfo.kernel_cmdline = machine->kernel_cmdline; 1450 vms->bootinfo.initrd_filename = machine->initrd_filename; 1451 vms->bootinfo.nb_cpus = smp_cpus; 1452 vms->bootinfo.board_id = -1; 1453 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 1454 vms->bootinfo.get_dtb = machvirt_dtb; 1455 vms->bootinfo.firmware_loaded = firmware_loaded; 1456 arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo); 1457 1458 /* 1459 * arm_load_kernel machine init done notifier registration must 1460 * happen before the platform_bus_create call. In this latter, 1461 * another notifier is registered which adds platform bus nodes. 1462 * Notifiers are executed in registration reverse order. 1463 */ 1464 create_platform_bus(vms, pic); 1465 } 1466 1467 static bool virt_get_secure(Object *obj, Error **errp) 1468 { 1469 VirtMachineState *vms = VIRT_MACHINE(obj); 1470 1471 return vms->secure; 1472 } 1473 1474 static void virt_set_secure(Object *obj, bool value, Error **errp) 1475 { 1476 VirtMachineState *vms = VIRT_MACHINE(obj); 1477 1478 vms->secure = value; 1479 } 1480 1481 static bool virt_get_virt(Object *obj, Error **errp) 1482 { 1483 VirtMachineState *vms = VIRT_MACHINE(obj); 1484 1485 return vms->virt; 1486 } 1487 1488 static void virt_set_virt(Object *obj, bool value, Error **errp) 1489 { 1490 VirtMachineState *vms = VIRT_MACHINE(obj); 1491 1492 vms->virt = value; 1493 } 1494 1495 static bool virt_get_highmem(Object *obj, Error **errp) 1496 { 1497 VirtMachineState *vms = VIRT_MACHINE(obj); 1498 1499 return vms->highmem; 1500 } 1501 1502 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1503 { 1504 VirtMachineState *vms = VIRT_MACHINE(obj); 1505 1506 vms->highmem = value; 1507 } 1508 1509 static bool virt_get_its(Object *obj, Error **errp) 1510 { 1511 VirtMachineState *vms = VIRT_MACHINE(obj); 1512 1513 return vms->its; 1514 } 1515 1516 static void virt_set_its(Object *obj, bool value, Error **errp) 1517 { 1518 VirtMachineState *vms = VIRT_MACHINE(obj); 1519 1520 vms->its = value; 1521 } 1522 1523 static char *virt_get_gic_version(Object *obj, Error **errp) 1524 { 1525 VirtMachineState *vms = VIRT_MACHINE(obj); 1526 const char *val = vms->gic_version == 3 ? "3" : "2"; 1527 1528 return g_strdup(val); 1529 } 1530 1531 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 1532 { 1533 VirtMachineState *vms = VIRT_MACHINE(obj); 1534 1535 if (!strcmp(value, "3")) { 1536 vms->gic_version = 3; 1537 } else if (!strcmp(value, "2")) { 1538 vms->gic_version = 2; 1539 } else if (!strcmp(value, "host")) { 1540 vms->gic_version = 0; /* Will probe later */ 1541 } else { 1542 error_setg(errp, "Invalid gic-version value"); 1543 error_append_hint(errp, "Valid values are 3, 2, host.\n"); 1544 } 1545 } 1546 1547 static CpuInstanceProperties 1548 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1549 { 1550 MachineClass *mc = MACHINE_GET_CLASS(ms); 1551 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1552 1553 assert(cpu_index < possible_cpus->len); 1554 return possible_cpus->cpus[cpu_index].props; 1555 } 1556 1557 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1558 { 1559 return idx % nb_numa_nodes; 1560 } 1561 1562 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1563 { 1564 int n; 1565 VirtMachineState *vms = VIRT_MACHINE(ms); 1566 1567 if (ms->possible_cpus) { 1568 assert(ms->possible_cpus->len == max_cpus); 1569 return ms->possible_cpus; 1570 } 1571 1572 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1573 sizeof(CPUArchId) * max_cpus); 1574 ms->possible_cpus->len = max_cpus; 1575 for (n = 0; n < ms->possible_cpus->len; n++) { 1576 ms->possible_cpus->cpus[n].arch_id = 1577 virt_cpu_mp_affinity(vms, n); 1578 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1579 ms->possible_cpus->cpus[n].props.thread_id = n; 1580 } 1581 return ms->possible_cpus; 1582 } 1583 1584 static void virt_machine_class_init(ObjectClass *oc, void *data) 1585 { 1586 MachineClass *mc = MACHINE_CLASS(oc); 1587 1588 mc->init = machvirt_init; 1589 /* Start max_cpus at the maximum QEMU supports. We'll further restrict 1590 * it later in machvirt_init, where we have more information about the 1591 * configuration of the particular instance. 1592 */ 1593 mc->max_cpus = 255; 1594 mc->has_dynamic_sysbus = true; 1595 mc->block_default_type = IF_VIRTIO; 1596 mc->no_cdrom = 1; 1597 mc->pci_allow_0_address = true; 1598 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 1599 mc->minimum_page_bits = 12; 1600 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1601 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1602 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 1603 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1604 } 1605 1606 static const TypeInfo virt_machine_info = { 1607 .name = TYPE_VIRT_MACHINE, 1608 .parent = TYPE_MACHINE, 1609 .abstract = true, 1610 .instance_size = sizeof(VirtMachineState), 1611 .class_size = sizeof(VirtMachineClass), 1612 .class_init = virt_machine_class_init, 1613 }; 1614 1615 static void machvirt_machine_init(void) 1616 { 1617 type_register_static(&virt_machine_info); 1618 } 1619 type_init(machvirt_machine_init); 1620 1621 static void virt_2_10_instance_init(Object *obj) 1622 { 1623 VirtMachineState *vms = VIRT_MACHINE(obj); 1624 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1625 1626 /* EL3 is disabled by default on virt: this makes us consistent 1627 * between KVM and TCG for this board, and it also allows us to 1628 * boot UEFI blobs which assume no TrustZone support. 1629 */ 1630 vms->secure = false; 1631 object_property_add_bool(obj, "secure", virt_get_secure, 1632 virt_set_secure, NULL); 1633 object_property_set_description(obj, "secure", 1634 "Set on/off to enable/disable the ARM " 1635 "Security Extensions (TrustZone)", 1636 NULL); 1637 1638 /* EL2 is also disabled by default, for similar reasons */ 1639 vms->virt = false; 1640 object_property_add_bool(obj, "virtualization", virt_get_virt, 1641 virt_set_virt, NULL); 1642 object_property_set_description(obj, "virtualization", 1643 "Set on/off to enable/disable emulating a " 1644 "guest CPU which implements the ARM " 1645 "Virtualization Extensions", 1646 NULL); 1647 1648 /* High memory is enabled by default */ 1649 vms->highmem = true; 1650 object_property_add_bool(obj, "highmem", virt_get_highmem, 1651 virt_set_highmem, NULL); 1652 object_property_set_description(obj, "highmem", 1653 "Set on/off to enable/disable using " 1654 "physical address space above 32 bits", 1655 NULL); 1656 /* Default GIC type is v2 */ 1657 vms->gic_version = 2; 1658 object_property_add_str(obj, "gic-version", virt_get_gic_version, 1659 virt_set_gic_version, NULL); 1660 object_property_set_description(obj, "gic-version", 1661 "Set GIC version. " 1662 "Valid values are 2, 3 and host", NULL); 1663 1664 if (vmc->no_its) { 1665 vms->its = false; 1666 } else { 1667 /* Default allows ITS instantiation */ 1668 vms->its = true; 1669 object_property_add_bool(obj, "its", virt_get_its, 1670 virt_set_its, NULL); 1671 object_property_set_description(obj, "its", 1672 "Set on/off to enable/disable " 1673 "ITS instantiation", 1674 NULL); 1675 } 1676 1677 vms->memmap = a15memmap; 1678 vms->irqmap = a15irqmap; 1679 } 1680 1681 static void virt_machine_2_10_options(MachineClass *mc) 1682 { 1683 } 1684 DEFINE_VIRT_MACHINE_AS_LATEST(2, 10) 1685 1686 #define VIRT_COMPAT_2_9 \ 1687 HW_COMPAT_2_9 1688 1689 static void virt_2_9_instance_init(Object *obj) 1690 { 1691 virt_2_10_instance_init(obj); 1692 } 1693 1694 static void virt_machine_2_9_options(MachineClass *mc) 1695 { 1696 virt_machine_2_10_options(mc); 1697 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_9); 1698 } 1699 DEFINE_VIRT_MACHINE(2, 9) 1700 1701 #define VIRT_COMPAT_2_8 \ 1702 HW_COMPAT_2_8 1703 1704 static void virt_2_8_instance_init(Object *obj) 1705 { 1706 virt_2_9_instance_init(obj); 1707 } 1708 1709 static void virt_machine_2_8_options(MachineClass *mc) 1710 { 1711 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1712 1713 virt_machine_2_9_options(mc); 1714 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_8); 1715 /* For 2.8 and earlier we falsely claimed in the DT that 1716 * our timers were edge-triggered, not level-triggered. 1717 */ 1718 vmc->claim_edge_triggered_timers = true; 1719 } 1720 DEFINE_VIRT_MACHINE(2, 8) 1721 1722 #define VIRT_COMPAT_2_7 \ 1723 HW_COMPAT_2_7 1724 1725 static void virt_2_7_instance_init(Object *obj) 1726 { 1727 virt_2_8_instance_init(obj); 1728 } 1729 1730 static void virt_machine_2_7_options(MachineClass *mc) 1731 { 1732 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1733 1734 virt_machine_2_8_options(mc); 1735 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_7); 1736 /* ITS was introduced with 2.8 */ 1737 vmc->no_its = true; 1738 /* Stick with 1K pages for migration compatibility */ 1739 mc->minimum_page_bits = 0; 1740 } 1741 DEFINE_VIRT_MACHINE(2, 7) 1742 1743 #define VIRT_COMPAT_2_6 \ 1744 HW_COMPAT_2_6 1745 1746 static void virt_2_6_instance_init(Object *obj) 1747 { 1748 virt_2_7_instance_init(obj); 1749 } 1750 1751 static void virt_machine_2_6_options(MachineClass *mc) 1752 { 1753 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1754 1755 virt_machine_2_7_options(mc); 1756 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6); 1757 vmc->disallow_affinity_adjustment = true; 1758 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 1759 vmc->no_pmu = true; 1760 } 1761 DEFINE_VIRT_MACHINE(2, 6) 1762