1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qapi/error.h" 33 #include "hw/sysbus.h" 34 #include "hw/arm/arm.h" 35 #include "hw/arm/primecell.h" 36 #include "hw/arm/virt.h" 37 #include "hw/vfio/vfio-calxeda-xgmac.h" 38 #include "hw/vfio/vfio-amd-xgbe.h" 39 #include "hw/display/ramfb.h" 40 #include "hw/devices.h" 41 #include "net/net.h" 42 #include "sysemu/device_tree.h" 43 #include "sysemu/numa.h" 44 #include "sysemu/sysemu.h" 45 #include "sysemu/kvm.h" 46 #include "hw/compat.h" 47 #include "hw/loader.h" 48 #include "exec/address-spaces.h" 49 #include "qemu/bitops.h" 50 #include "qemu/error-report.h" 51 #include "hw/pci-host/gpex.h" 52 #include "hw/arm/sysbus-fdt.h" 53 #include "hw/platform-bus.h" 54 #include "hw/arm/fdt.h" 55 #include "hw/intc/arm_gic.h" 56 #include "hw/intc/arm_gicv3_common.h" 57 #include "kvm_arm.h" 58 #include "hw/smbios/smbios.h" 59 #include "qapi/visitor.h" 60 #include "standard-headers/linux/input.h" 61 #include "hw/arm/smmuv3.h" 62 63 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 64 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 65 void *data) \ 66 { \ 67 MachineClass *mc = MACHINE_CLASS(oc); \ 68 virt_machine_##major##_##minor##_options(mc); \ 69 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 70 if (latest) { \ 71 mc->alias = "virt"; \ 72 } \ 73 } \ 74 static const TypeInfo machvirt_##major##_##minor##_info = { \ 75 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 76 .parent = TYPE_VIRT_MACHINE, \ 77 .instance_init = virt_##major##_##minor##_instance_init, \ 78 .class_init = virt_##major##_##minor##_class_init, \ 79 }; \ 80 static void machvirt_machine_##major##_##minor##_init(void) \ 81 { \ 82 type_register_static(&machvirt_##major##_##minor##_info); \ 83 } \ 84 type_init(machvirt_machine_##major##_##minor##_init); 85 86 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 87 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 88 #define DEFINE_VIRT_MACHINE(major, minor) \ 89 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 90 91 92 /* Number of external interrupt lines to configure the GIC with */ 93 #define NUM_IRQS 256 94 95 #define PLATFORM_BUS_NUM_IRQS 64 96 97 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means 98 * RAM can go up to the 256GB mark, leaving 256GB of the physical 99 * address space unallocated and free for future use between 256G and 512G. 100 * If we need to provide more RAM to VMs in the future then we need to: 101 * * allocate a second bank of RAM starting at 2TB and working up 102 * * fix the DT and ACPI table generation code in QEMU to correctly 103 * report two split lumps of RAM to the guest 104 * * fix KVM in the host kernel to allow guests with >40 bit address spaces 105 * (We don't want to fill all the way up to 512GB with RAM because 106 * we might want it for non-RAM purposes later. Conversely it seems 107 * reasonable to assume that anybody configuring a VM with a quarter 108 * of a terabyte of RAM will be doing it on a host with more than a 109 * terabyte of physical address space.) 110 */ 111 #define RAMLIMIT_GB 255 112 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) 113 114 /* Addresses and sizes of our components. 115 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 116 * 128MB..256MB is used for miscellaneous device I/O. 117 * 256MB..1GB is reserved for possible future PCI support (ie where the 118 * PCI memory window will go if we add a PCI host controller). 119 * 1GB and up is RAM (which may happily spill over into the 120 * high memory region beyond 4GB). 121 * This represents a compromise between how much RAM can be given to 122 * a 32 bit VM and leaving space for expansion and in particular for PCI. 123 * Note that devices should generally be placed at multiples of 0x10000, 124 * to accommodate guests using 64K pages. 125 */ 126 static const MemMapEntry a15memmap[] = { 127 /* Space up to 0x8000000 is reserved for a boot ROM */ 128 [VIRT_FLASH] = { 0, 0x08000000 }, 129 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 130 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 131 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 132 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 133 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 134 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 135 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 136 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 137 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 138 /* This redistributor space allows up to 2*64kB*123 CPUs */ 139 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 140 [VIRT_UART] = { 0x09000000, 0x00001000 }, 141 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 142 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 143 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 144 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 145 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 146 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 147 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 148 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 149 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 150 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 151 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 152 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 153 [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES }, 154 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 155 [VIRT_GIC_REDIST2] = { 0x4000000000ULL, 0x4000000 }, 156 [VIRT_PCIE_ECAM_HIGH] = { 0x4010000000ULL, 0x10000000 }, 157 /* Second PCIe window, 512GB wide at the 512GB boundary */ 158 [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL }, 159 }; 160 161 static const int a15irqmap[] = { 162 [VIRT_UART] = 1, 163 [VIRT_RTC] = 2, 164 [VIRT_PCIE] = 3, /* ... to 6 */ 165 [VIRT_GPIO] = 7, 166 [VIRT_SECURE_UART] = 8, 167 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 168 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 169 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 170 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 171 }; 172 173 static const char *valid_cpus[] = { 174 ARM_CPU_TYPE_NAME("cortex-a15"), 175 ARM_CPU_TYPE_NAME("cortex-a53"), 176 ARM_CPU_TYPE_NAME("cortex-a57"), 177 ARM_CPU_TYPE_NAME("host"), 178 ARM_CPU_TYPE_NAME("max"), 179 }; 180 181 static bool cpu_type_valid(const char *cpu) 182 { 183 int i; 184 185 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 186 if (strcmp(cpu, valid_cpus[i]) == 0) { 187 return true; 188 } 189 } 190 return false; 191 } 192 193 static void create_fdt(VirtMachineState *vms) 194 { 195 void *fdt = create_device_tree(&vms->fdt_size); 196 197 if (!fdt) { 198 error_report("create_device_tree() failed"); 199 exit(1); 200 } 201 202 vms->fdt = fdt; 203 204 /* Header */ 205 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 206 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 207 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 208 209 /* /chosen must exist for load_dtb to fill in necessary properties later */ 210 qemu_fdt_add_subnode(fdt, "/chosen"); 211 212 /* Clock node, for the benefit of the UART. The kernel device tree 213 * binding documentation claims the PL011 node clock properties are 214 * optional but in practice if you omit them the kernel refuses to 215 * probe for the device. 216 */ 217 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 218 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 219 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 220 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 221 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 222 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 223 "clk24mhz"); 224 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 225 226 if (have_numa_distance) { 227 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 228 uint32_t *matrix = g_malloc0(size); 229 int idx, i, j; 230 231 for (i = 0; i < nb_numa_nodes; i++) { 232 for (j = 0; j < nb_numa_nodes; j++) { 233 idx = (i * nb_numa_nodes + j) * 3; 234 matrix[idx + 0] = cpu_to_be32(i); 235 matrix[idx + 1] = cpu_to_be32(j); 236 matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]); 237 } 238 } 239 240 qemu_fdt_add_subnode(fdt, "/distance-map"); 241 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 242 "numa-distance-map-v1"); 243 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 244 matrix, size); 245 g_free(matrix); 246 } 247 } 248 249 static void fdt_add_timer_nodes(const VirtMachineState *vms) 250 { 251 /* On real hardware these interrupts are level-triggered. 252 * On KVM they were edge-triggered before host kernel version 4.4, 253 * and level-triggered afterwards. 254 * On emulated QEMU they are level-triggered. 255 * 256 * Getting the DTB info about them wrong is awkward for some 257 * guest kernels: 258 * pre-4.8 ignore the DT and leave the interrupt configured 259 * with whatever the GIC reset value (or the bootloader) left it at 260 * 4.8 before rc6 honour the incorrect data by programming it back 261 * into the GIC, causing problems 262 * 4.8rc6 and later ignore the DT and always write "level triggered" 263 * into the GIC 264 * 265 * For backwards-compatibility, virt-2.8 and earlier will continue 266 * to say these are edge-triggered, but later machines will report 267 * the correct information. 268 */ 269 ARMCPU *armcpu; 270 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 271 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 272 273 if (vmc->claim_edge_triggered_timers) { 274 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 275 } 276 277 if (vms->gic_version == 2) { 278 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 279 GIC_FDT_IRQ_PPI_CPU_WIDTH, 280 (1 << vms->smp_cpus) - 1); 281 } 282 283 qemu_fdt_add_subnode(vms->fdt, "/timer"); 284 285 armcpu = ARM_CPU(qemu_get_cpu(0)); 286 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 287 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 288 qemu_fdt_setprop(vms->fdt, "/timer", "compatible", 289 compat, sizeof(compat)); 290 } else { 291 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible", 292 "arm,armv7-timer"); 293 } 294 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0); 295 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts", 296 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 297 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 298 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 299 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 300 } 301 302 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 303 { 304 int cpu; 305 int addr_cells = 1; 306 const MachineState *ms = MACHINE(vms); 307 308 /* 309 * From Documentation/devicetree/bindings/arm/cpus.txt 310 * On ARM v8 64-bit systems value should be set to 2, 311 * that corresponds to the MPIDR_EL1 register size. 312 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 313 * in the system, #address-cells can be set to 1, since 314 * MPIDR_EL1[63:32] bits are not used for CPUs 315 * identification. 316 * 317 * Here we actually don't know whether our system is 32- or 64-bit one. 318 * The simplest way to go is to examine affinity IDs of all our CPUs. If 319 * at least one of them has Aff3 populated, we set #address-cells to 2. 320 */ 321 for (cpu = 0; cpu < vms->smp_cpus; cpu++) { 322 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 323 324 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 325 addr_cells = 2; 326 break; 327 } 328 } 329 330 qemu_fdt_add_subnode(vms->fdt, "/cpus"); 331 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); 332 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); 333 334 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { 335 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 336 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 337 CPUState *cs = CPU(armcpu); 338 339 qemu_fdt_add_subnode(vms->fdt, nodename); 340 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); 341 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 342 armcpu->dtb_compatible); 343 344 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED 345 && vms->smp_cpus > 1) { 346 qemu_fdt_setprop_string(vms->fdt, nodename, 347 "enable-method", "psci"); 348 } 349 350 if (addr_cells == 2) { 351 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", 352 armcpu->mp_affinity); 353 } else { 354 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", 355 armcpu->mp_affinity); 356 } 357 358 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 359 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", 360 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 361 } 362 363 g_free(nodename); 364 } 365 } 366 367 static void fdt_add_its_gic_node(VirtMachineState *vms) 368 { 369 char *nodename; 370 371 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 372 nodename = g_strdup_printf("/intc/its@%" PRIx64, 373 vms->memmap[VIRT_GIC_ITS].base); 374 qemu_fdt_add_subnode(vms->fdt, nodename); 375 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 376 "arm,gic-v3-its"); 377 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); 378 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 379 2, vms->memmap[VIRT_GIC_ITS].base, 380 2, vms->memmap[VIRT_GIC_ITS].size); 381 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); 382 g_free(nodename); 383 } 384 385 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 386 { 387 char *nodename; 388 389 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 390 vms->memmap[VIRT_GIC_V2M].base); 391 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 392 qemu_fdt_add_subnode(vms->fdt, nodename); 393 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 394 "arm,gic-v2m-frame"); 395 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); 396 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 397 2, vms->memmap[VIRT_GIC_V2M].base, 398 2, vms->memmap[VIRT_GIC_V2M].size); 399 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); 400 g_free(nodename); 401 } 402 403 static void fdt_add_gic_node(VirtMachineState *vms) 404 { 405 char *nodename; 406 407 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt); 408 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle); 409 410 nodename = g_strdup_printf("/intc@%" PRIx64, 411 vms->memmap[VIRT_GIC_DIST].base); 412 qemu_fdt_add_subnode(vms->fdt, nodename); 413 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 3); 414 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-controller", NULL, 0); 415 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2); 416 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2); 417 qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0); 418 if (vms->gic_version == 3) { 419 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 420 421 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 422 "arm,gic-v3"); 423 424 qemu_fdt_setprop_cell(vms->fdt, nodename, 425 "#redistributor-regions", nb_redist_regions); 426 427 if (nb_redist_regions == 1) { 428 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 429 2, vms->memmap[VIRT_GIC_DIST].base, 430 2, vms->memmap[VIRT_GIC_DIST].size, 431 2, vms->memmap[VIRT_GIC_REDIST].base, 432 2, vms->memmap[VIRT_GIC_REDIST].size); 433 } else { 434 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 435 2, vms->memmap[VIRT_GIC_DIST].base, 436 2, vms->memmap[VIRT_GIC_DIST].size, 437 2, vms->memmap[VIRT_GIC_REDIST].base, 438 2, vms->memmap[VIRT_GIC_REDIST].size, 439 2, vms->memmap[VIRT_GIC_REDIST2].base, 440 2, vms->memmap[VIRT_GIC_REDIST2].size); 441 } 442 443 if (vms->virt) { 444 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 445 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 446 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 447 } 448 } else { 449 /* 'cortex-a15-gic' means 'GIC v2' */ 450 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 451 "arm,cortex-a15-gic"); 452 if (!vms->virt) { 453 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 454 2, vms->memmap[VIRT_GIC_DIST].base, 455 2, vms->memmap[VIRT_GIC_DIST].size, 456 2, vms->memmap[VIRT_GIC_CPU].base, 457 2, vms->memmap[VIRT_GIC_CPU].size); 458 } else { 459 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 460 2, vms->memmap[VIRT_GIC_DIST].base, 461 2, vms->memmap[VIRT_GIC_DIST].size, 462 2, vms->memmap[VIRT_GIC_CPU].base, 463 2, vms->memmap[VIRT_GIC_CPU].size, 464 2, vms->memmap[VIRT_GIC_HYP].base, 465 2, vms->memmap[VIRT_GIC_HYP].size, 466 2, vms->memmap[VIRT_GIC_VCPU].base, 467 2, vms->memmap[VIRT_GIC_VCPU].size); 468 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 469 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 470 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 471 } 472 } 473 474 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle); 475 g_free(nodename); 476 } 477 478 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 479 { 480 CPUState *cpu; 481 ARMCPU *armcpu; 482 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 483 484 CPU_FOREACH(cpu) { 485 armcpu = ARM_CPU(cpu); 486 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 487 return; 488 } 489 if (kvm_enabled()) { 490 if (kvm_irqchip_in_kernel()) { 491 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 492 } 493 kvm_arm_pmu_init(cpu); 494 } 495 } 496 497 if (vms->gic_version == 2) { 498 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 499 GIC_FDT_IRQ_PPI_CPU_WIDTH, 500 (1 << vms->smp_cpus) - 1); 501 } 502 503 armcpu = ARM_CPU(qemu_get_cpu(0)); 504 qemu_fdt_add_subnode(vms->fdt, "/pmu"); 505 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 506 const char compat[] = "arm,armv8-pmuv3"; 507 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible", 508 compat, sizeof(compat)); 509 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts", 510 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 511 } 512 } 513 514 static void create_its(VirtMachineState *vms, DeviceState *gicdev) 515 { 516 const char *itsclass = its_class_name(); 517 DeviceState *dev; 518 519 if (!itsclass) { 520 /* Do nothing if not supported */ 521 return; 522 } 523 524 dev = qdev_create(NULL, itsclass); 525 526 object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3", 527 &error_abort); 528 qdev_init_nofail(dev); 529 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 530 531 fdt_add_its_gic_node(vms); 532 } 533 534 static void create_v2m(VirtMachineState *vms, qemu_irq *pic) 535 { 536 int i; 537 int irq = vms->irqmap[VIRT_GIC_V2M]; 538 DeviceState *dev; 539 540 dev = qdev_create(NULL, "arm-gicv2m"); 541 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 542 qdev_prop_set_uint32(dev, "base-spi", irq); 543 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 544 qdev_init_nofail(dev); 545 546 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 547 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 548 } 549 550 fdt_add_v2m_gic_node(vms); 551 } 552 553 static void create_gic(VirtMachineState *vms, qemu_irq *pic) 554 { 555 /* We create a standalone GIC */ 556 DeviceState *gicdev; 557 SysBusDevice *gicbusdev; 558 const char *gictype; 559 int type = vms->gic_version, i; 560 uint32_t nb_redist_regions = 0; 561 562 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 563 564 gicdev = qdev_create(NULL, gictype); 565 qdev_prop_set_uint32(gicdev, "revision", type); 566 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 567 /* Note that the num-irq property counts both internal and external 568 * interrupts; there are always 32 of the former (mandated by GIC spec). 569 */ 570 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 571 if (!kvm_irqchip_in_kernel()) { 572 qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure); 573 } 574 575 if (type == 3) { 576 uint32_t redist0_capacity = 577 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 578 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 579 580 nb_redist_regions = virt_gicv3_redist_region_count(vms); 581 582 qdev_prop_set_uint32(gicdev, "len-redist-region-count", 583 nb_redist_regions); 584 qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count); 585 586 if (nb_redist_regions == 2) { 587 uint32_t redist1_capacity = 588 vms->memmap[VIRT_GIC_REDIST2].size / GICV3_REDIST_SIZE; 589 590 qdev_prop_set_uint32(gicdev, "redist-region-count[1]", 591 MIN(smp_cpus - redist0_count, redist1_capacity)); 592 } 593 } else { 594 if (!kvm_irqchip_in_kernel()) { 595 qdev_prop_set_bit(gicdev, "has-virtualization-extensions", 596 vms->virt); 597 } 598 } 599 qdev_init_nofail(gicdev); 600 gicbusdev = SYS_BUS_DEVICE(gicdev); 601 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 602 if (type == 3) { 603 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 604 if (nb_redist_regions == 2) { 605 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_REDIST2].base); 606 } 607 } else { 608 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 609 if (vms->virt) { 610 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 611 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 612 } 613 } 614 615 /* Wire the outputs from each CPU's generic timer and the GICv3 616 * maintenance interrupt signal to the appropriate GIC PPI inputs, 617 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 618 */ 619 for (i = 0; i < smp_cpus; i++) { 620 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 621 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 622 int irq; 623 /* Mapping from the output timer irq lines from the CPU to the 624 * GIC PPI inputs we use for the virt board. 625 */ 626 const int timer_irq[] = { 627 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 628 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 629 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 630 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 631 }; 632 633 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 634 qdev_connect_gpio_out(cpudev, irq, 635 qdev_get_gpio_in(gicdev, 636 ppibase + timer_irq[irq])); 637 } 638 639 if (type == 3) { 640 qemu_irq irq = qdev_get_gpio_in(gicdev, 641 ppibase + ARCH_GIC_MAINT_IRQ); 642 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 643 0, irq); 644 } else if (vms->virt) { 645 qemu_irq irq = qdev_get_gpio_in(gicdev, 646 ppibase + ARCH_GIC_MAINT_IRQ); 647 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 648 } 649 650 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 651 qdev_get_gpio_in(gicdev, ppibase 652 + VIRTUAL_PMU_IRQ)); 653 654 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 655 sysbus_connect_irq(gicbusdev, i + smp_cpus, 656 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 657 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 658 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 659 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 660 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 661 } 662 663 for (i = 0; i < NUM_IRQS; i++) { 664 pic[i] = qdev_get_gpio_in(gicdev, i); 665 } 666 667 fdt_add_gic_node(vms); 668 669 if (type == 3 && vms->its) { 670 create_its(vms, gicdev); 671 } else if (type == 2) { 672 create_v2m(vms, pic); 673 } 674 } 675 676 static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart, 677 MemoryRegion *mem, Chardev *chr) 678 { 679 char *nodename; 680 hwaddr base = vms->memmap[uart].base; 681 hwaddr size = vms->memmap[uart].size; 682 int irq = vms->irqmap[uart]; 683 const char compat[] = "arm,pl011\0arm,primecell"; 684 const char clocknames[] = "uartclk\0apb_pclk"; 685 DeviceState *dev = qdev_create(NULL, "pl011"); 686 SysBusDevice *s = SYS_BUS_DEVICE(dev); 687 688 qdev_prop_set_chr(dev, "chardev", chr); 689 qdev_init_nofail(dev); 690 memory_region_add_subregion(mem, base, 691 sysbus_mmio_get_region(s, 0)); 692 sysbus_connect_irq(s, 0, pic[irq]); 693 694 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 695 qemu_fdt_add_subnode(vms->fdt, nodename); 696 /* Note that we can't use setprop_string because of the embedded NUL */ 697 qemu_fdt_setprop(vms->fdt, nodename, "compatible", 698 compat, sizeof(compat)); 699 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 700 2, base, 2, size); 701 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 702 GIC_FDT_IRQ_TYPE_SPI, irq, 703 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 704 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks", 705 vms->clock_phandle, vms->clock_phandle); 706 qemu_fdt_setprop(vms->fdt, nodename, "clock-names", 707 clocknames, sizeof(clocknames)); 708 709 if (uart == VIRT_UART) { 710 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); 711 } else { 712 /* Mark as not usable by the normal world */ 713 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 714 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 715 716 qemu_fdt_add_subnode(vms->fdt, "/secure-chosen"); 717 qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path", 718 nodename); 719 } 720 721 g_free(nodename); 722 } 723 724 static void create_rtc(const VirtMachineState *vms, qemu_irq *pic) 725 { 726 char *nodename; 727 hwaddr base = vms->memmap[VIRT_RTC].base; 728 hwaddr size = vms->memmap[VIRT_RTC].size; 729 int irq = vms->irqmap[VIRT_RTC]; 730 const char compat[] = "arm,pl031\0arm,primecell"; 731 732 sysbus_create_simple("pl031", base, pic[irq]); 733 734 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 735 qemu_fdt_add_subnode(vms->fdt, nodename); 736 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 737 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 738 2, base, 2, size); 739 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 740 GIC_FDT_IRQ_TYPE_SPI, irq, 741 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 742 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 743 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 744 g_free(nodename); 745 } 746 747 static DeviceState *gpio_key_dev; 748 static void virt_powerdown_req(Notifier *n, void *opaque) 749 { 750 /* use gpio Pin 3 for power button event */ 751 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 752 } 753 754 static Notifier virt_system_powerdown_notifier = { 755 .notify = virt_powerdown_req 756 }; 757 758 static void create_gpio(const VirtMachineState *vms, qemu_irq *pic) 759 { 760 char *nodename; 761 DeviceState *pl061_dev; 762 hwaddr base = vms->memmap[VIRT_GPIO].base; 763 hwaddr size = vms->memmap[VIRT_GPIO].size; 764 int irq = vms->irqmap[VIRT_GPIO]; 765 const char compat[] = "arm,pl061\0arm,primecell"; 766 767 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); 768 769 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); 770 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 771 qemu_fdt_add_subnode(vms->fdt, nodename); 772 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 773 2, base, 2, size); 774 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 775 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); 776 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); 777 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 778 GIC_FDT_IRQ_TYPE_SPI, irq, 779 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 780 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 781 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 782 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); 783 784 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 785 qdev_get_gpio_in(pl061_dev, 3)); 786 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); 787 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); 788 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); 789 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); 790 791 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); 792 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", 793 "label", "GPIO Key Poweroff"); 794 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", 795 KEY_POWER); 796 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", 797 "gpios", phandle, 3, 0); 798 799 /* connect powerdown request */ 800 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier); 801 802 g_free(nodename); 803 } 804 805 static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic) 806 { 807 int i; 808 hwaddr size = vms->memmap[VIRT_MMIO].size; 809 810 /* We create the transports in forwards order. Since qbus_realize() 811 * prepends (not appends) new child buses, the incrementing loop below will 812 * create a list of virtio-mmio buses with decreasing base addresses. 813 * 814 * When a -device option is processed from the command line, 815 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 816 * order. The upshot is that -device options in increasing command line 817 * order are mapped to virtio-mmio buses with decreasing base addresses. 818 * 819 * When this code was originally written, that arrangement ensured that the 820 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 821 * the first -device on the command line. (The end-to-end order is a 822 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 823 * guest kernel's name-to-address assignment strategy.) 824 * 825 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 826 * the message, if not necessarily the code, of commit 70161ff336. 827 * Therefore the loop now establishes the inverse of the original intent. 828 * 829 * Unfortunately, we can't counteract the kernel change by reversing the 830 * loop; it would break existing command lines. 831 * 832 * In any case, the kernel makes no guarantee about the stability of 833 * enumeration order of virtio devices (as demonstrated by it changing 834 * between kernel versions). For reliable and stable identification 835 * of disks users must use UUIDs or similar mechanisms. 836 */ 837 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 838 int irq = vms->irqmap[VIRT_MMIO] + i; 839 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 840 841 sysbus_create_simple("virtio-mmio", base, pic[irq]); 842 } 843 844 /* We add dtb nodes in reverse order so that they appear in the finished 845 * device tree lowest address first. 846 * 847 * Note that this mapping is independent of the loop above. The previous 848 * loop influences virtio device to virtio transport assignment, whereas 849 * this loop controls how virtio transports are laid out in the dtb. 850 */ 851 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 852 char *nodename; 853 int irq = vms->irqmap[VIRT_MMIO] + i; 854 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 855 856 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 857 qemu_fdt_add_subnode(vms->fdt, nodename); 858 qemu_fdt_setprop_string(vms->fdt, nodename, 859 "compatible", "virtio,mmio"); 860 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 861 2, base, 2, size); 862 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 863 GIC_FDT_IRQ_TYPE_SPI, irq, 864 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 865 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 866 g_free(nodename); 867 } 868 } 869 870 static void create_one_flash(const char *name, hwaddr flashbase, 871 hwaddr flashsize, const char *file, 872 MemoryRegion *sysmem) 873 { 874 /* Create and map a single flash device. We use the same 875 * parameters as the flash devices on the Versatile Express board. 876 */ 877 DriveInfo *dinfo = drive_get_next(IF_PFLASH); 878 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 879 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 880 const uint64_t sectorlength = 256 * 1024; 881 882 if (dinfo) { 883 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 884 &error_abort); 885 } 886 887 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); 888 qdev_prop_set_uint64(dev, "sector-length", sectorlength); 889 qdev_prop_set_uint8(dev, "width", 4); 890 qdev_prop_set_uint8(dev, "device-width", 2); 891 qdev_prop_set_bit(dev, "big-endian", false); 892 qdev_prop_set_uint16(dev, "id0", 0x89); 893 qdev_prop_set_uint16(dev, "id1", 0x18); 894 qdev_prop_set_uint16(dev, "id2", 0x00); 895 qdev_prop_set_uint16(dev, "id3", 0x00); 896 qdev_prop_set_string(dev, "name", name); 897 qdev_init_nofail(dev); 898 899 memory_region_add_subregion(sysmem, flashbase, 900 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 901 902 if (file) { 903 char *fn; 904 int image_size; 905 906 if (drive_get(IF_PFLASH, 0, 0)) { 907 error_report("The contents of the first flash device may be " 908 "specified with -bios or with -drive if=pflash... " 909 "but you cannot use both options at once"); 910 exit(1); 911 } 912 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file); 913 if (!fn) { 914 error_report("Could not find ROM image '%s'", file); 915 exit(1); 916 } 917 image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0)); 918 g_free(fn); 919 if (image_size < 0) { 920 error_report("Could not load ROM image '%s'", file); 921 exit(1); 922 } 923 } 924 } 925 926 static void create_flash(const VirtMachineState *vms, 927 MemoryRegion *sysmem, 928 MemoryRegion *secure_sysmem) 929 { 930 /* Create two flash devices to fill the VIRT_FLASH space in the memmap. 931 * Any file passed via -bios goes in the first of these. 932 * sysmem is the system memory space. secure_sysmem is the secure view 933 * of the system, and the first flash device should be made visible only 934 * there. The second flash device is visible to both secure and nonsecure. 935 * If sysmem == secure_sysmem this means there is no separate Secure 936 * address space and both flash devices are generally visible. 937 */ 938 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 939 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 940 char *nodename; 941 942 create_one_flash("virt.flash0", flashbase, flashsize, 943 bios_name, secure_sysmem); 944 create_one_flash("virt.flash1", flashbase + flashsize, flashsize, 945 NULL, sysmem); 946 947 if (sysmem == secure_sysmem) { 948 /* Report both flash devices as a single node in the DT */ 949 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 950 qemu_fdt_add_subnode(vms->fdt, nodename); 951 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 952 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 953 2, flashbase, 2, flashsize, 954 2, flashbase + flashsize, 2, flashsize); 955 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 956 g_free(nodename); 957 } else { 958 /* Report the devices as separate nodes so we can mark one as 959 * only visible to the secure world. 960 */ 961 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 962 qemu_fdt_add_subnode(vms->fdt, nodename); 963 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 964 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 965 2, flashbase, 2, flashsize); 966 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 967 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 968 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 969 g_free(nodename); 970 971 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 972 qemu_fdt_add_subnode(vms->fdt, nodename); 973 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 974 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 975 2, flashbase + flashsize, 2, flashsize); 976 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 977 g_free(nodename); 978 } 979 } 980 981 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 982 { 983 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 984 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 985 FWCfgState *fw_cfg; 986 char *nodename; 987 988 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 989 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 990 991 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 992 qemu_fdt_add_subnode(vms->fdt, nodename); 993 qemu_fdt_setprop_string(vms->fdt, nodename, 994 "compatible", "qemu,fw-cfg-mmio"); 995 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 996 2, base, 2, size); 997 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 998 g_free(nodename); 999 return fw_cfg; 1000 } 1001 1002 static void create_pcie_irq_map(const VirtMachineState *vms, 1003 uint32_t gic_phandle, 1004 int first_irq, const char *nodename) 1005 { 1006 int devfn, pin; 1007 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1008 uint32_t *irq_map = full_irq_map; 1009 1010 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1011 for (pin = 0; pin < 4; pin++) { 1012 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1013 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1014 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1015 int i; 1016 1017 uint32_t map[] = { 1018 devfn << 8, 0, 0, /* devfn */ 1019 pin + 1, /* PCI pin */ 1020 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1021 1022 /* Convert map to big endian */ 1023 for (i = 0; i < 10; i++) { 1024 irq_map[i] = cpu_to_be32(map[i]); 1025 } 1026 irq_map += 10; 1027 } 1028 } 1029 1030 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map", 1031 full_irq_map, sizeof(full_irq_map)); 1032 1033 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask", 1034 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 1035 0x7 /* PCI irq */); 1036 } 1037 1038 static void create_smmu(const VirtMachineState *vms, qemu_irq *pic, 1039 PCIBus *bus) 1040 { 1041 char *node; 1042 const char compat[] = "arm,smmu-v3"; 1043 int irq = vms->irqmap[VIRT_SMMU]; 1044 int i; 1045 hwaddr base = vms->memmap[VIRT_SMMU].base; 1046 hwaddr size = vms->memmap[VIRT_SMMU].size; 1047 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1048 DeviceState *dev; 1049 1050 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1051 return; 1052 } 1053 1054 dev = qdev_create(NULL, "arm-smmuv3"); 1055 1056 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", 1057 &error_abort); 1058 qdev_init_nofail(dev); 1059 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1060 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1061 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 1062 } 1063 1064 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1065 qemu_fdt_add_subnode(vms->fdt, node); 1066 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat)); 1067 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size); 1068 1069 qemu_fdt_setprop_cells(vms->fdt, node, "interrupts", 1070 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1071 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1072 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1073 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1074 1075 qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names, 1076 sizeof(irq_names)); 1077 1078 qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle); 1079 qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk"); 1080 qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0); 1081 1082 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1); 1083 1084 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle); 1085 g_free(node); 1086 } 1087 1088 static void create_pcie(VirtMachineState *vms, qemu_irq *pic) 1089 { 1090 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1091 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1092 hwaddr base_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].base; 1093 hwaddr size_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].size; 1094 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1095 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1096 hwaddr base_ecam, size_ecam; 1097 hwaddr base = base_mmio; 1098 int nr_pcie_buses; 1099 int irq = vms->irqmap[VIRT_PCIE]; 1100 MemoryRegion *mmio_alias; 1101 MemoryRegion *mmio_reg; 1102 MemoryRegion *ecam_alias; 1103 MemoryRegion *ecam_reg; 1104 DeviceState *dev; 1105 char *nodename; 1106 int i, ecam_id; 1107 PCIHostState *pci; 1108 1109 dev = qdev_create(NULL, TYPE_GPEX_HOST); 1110 qdev_init_nofail(dev); 1111 1112 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1113 base_ecam = vms->memmap[ecam_id].base; 1114 size_ecam = vms->memmap[ecam_id].size; 1115 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1116 /* Map only the first size_ecam bytes of ECAM space */ 1117 ecam_alias = g_new0(MemoryRegion, 1); 1118 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1119 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1120 ecam_reg, 0, size_ecam); 1121 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1122 1123 /* Map the MMIO window into system address space so as to expose 1124 * the section of PCI MMIO space which starts at the same base address 1125 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1126 * the window). 1127 */ 1128 mmio_alias = g_new0(MemoryRegion, 1); 1129 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1130 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1131 mmio_reg, base_mmio, size_mmio); 1132 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1133 1134 if (vms->highmem) { 1135 /* Map high MMIO space */ 1136 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1137 1138 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1139 mmio_reg, base_mmio_high, size_mmio_high); 1140 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1141 high_mmio_alias); 1142 } 1143 1144 /* Map IO port space */ 1145 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1146 1147 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1148 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 1149 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1150 } 1151 1152 pci = PCI_HOST_BRIDGE(dev); 1153 if (pci->bus) { 1154 for (i = 0; i < nb_nics; i++) { 1155 NICInfo *nd = &nd_table[i]; 1156 1157 if (!nd->model) { 1158 nd->model = g_strdup("virtio"); 1159 } 1160 1161 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1162 } 1163 } 1164 1165 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1166 qemu_fdt_add_subnode(vms->fdt, nodename); 1167 qemu_fdt_setprop_string(vms->fdt, nodename, 1168 "compatible", "pci-host-ecam-generic"); 1169 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci"); 1170 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3); 1171 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2); 1172 qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0); 1173 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0, 1174 nr_pcie_buses - 1); 1175 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1176 1177 if (vms->msi_phandle) { 1178 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", 1179 vms->msi_phandle); 1180 } 1181 1182 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1183 2, base_ecam, 2, size_ecam); 1184 1185 if (vms->highmem) { 1186 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1187 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1188 2, base_pio, 2, size_pio, 1189 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1190 2, base_mmio, 2, size_mmio, 1191 1, FDT_PCI_RANGE_MMIO_64BIT, 1192 2, base_mmio_high, 1193 2, base_mmio_high, 2, size_mmio_high); 1194 } else { 1195 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1196 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1197 2, base_pio, 2, size_pio, 1198 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1199 2, base_mmio, 2, size_mmio); 1200 } 1201 1202 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); 1203 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); 1204 1205 if (vms->iommu) { 1206 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt); 1207 1208 create_smmu(vms, pic, pci->bus); 1209 1210 qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map", 1211 0x0, vms->iommu_phandle, 0x0, 0x10000); 1212 } 1213 1214 g_free(nodename); 1215 } 1216 1217 static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic) 1218 { 1219 DeviceState *dev; 1220 SysBusDevice *s; 1221 int i; 1222 MemoryRegion *sysmem = get_system_memory(); 1223 1224 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1225 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1226 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1227 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1228 qdev_init_nofail(dev); 1229 vms->platform_bus_dev = dev; 1230 1231 s = SYS_BUS_DEVICE(dev); 1232 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1233 int irqn = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1234 sysbus_connect_irq(s, i, pic[irqn]); 1235 } 1236 1237 memory_region_add_subregion(sysmem, 1238 vms->memmap[VIRT_PLATFORM_BUS].base, 1239 sysbus_mmio_get_region(s, 0)); 1240 } 1241 1242 static void create_secure_ram(VirtMachineState *vms, 1243 MemoryRegion *secure_sysmem) 1244 { 1245 MemoryRegion *secram = g_new(MemoryRegion, 1); 1246 char *nodename; 1247 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1248 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1249 1250 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1251 &error_fatal); 1252 memory_region_add_subregion(secure_sysmem, base, secram); 1253 1254 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1255 qemu_fdt_add_subnode(vms->fdt, nodename); 1256 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory"); 1257 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size); 1258 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1259 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1260 1261 g_free(nodename); 1262 } 1263 1264 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1265 { 1266 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1267 bootinfo); 1268 1269 *fdt_size = board->fdt_size; 1270 return board->fdt; 1271 } 1272 1273 static void virt_build_smbios(VirtMachineState *vms) 1274 { 1275 MachineClass *mc = MACHINE_GET_CLASS(vms); 1276 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1277 uint8_t *smbios_tables, *smbios_anchor; 1278 size_t smbios_tables_len, smbios_anchor_len; 1279 const char *product = "QEMU Virtual Machine"; 1280 1281 if (!vms->fw_cfg) { 1282 return; 1283 } 1284 1285 if (kvm_enabled()) { 1286 product = "KVM Virtual Machine"; 1287 } 1288 1289 smbios_set_defaults("QEMU", product, 1290 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1291 true, SMBIOS_ENTRY_POINT_30); 1292 1293 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, 1294 &smbios_anchor, &smbios_anchor_len); 1295 1296 if (smbios_anchor) { 1297 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1298 smbios_tables, smbios_tables_len); 1299 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1300 smbios_anchor, smbios_anchor_len); 1301 } 1302 } 1303 1304 static 1305 void virt_machine_done(Notifier *notifier, void *data) 1306 { 1307 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1308 machine_done); 1309 ARMCPU *cpu = ARM_CPU(first_cpu); 1310 struct arm_boot_info *info = &vms->bootinfo; 1311 AddressSpace *as = arm_boot_address_space(cpu, info); 1312 1313 /* 1314 * If the user provided a dtb, we assume the dynamic sysbus nodes 1315 * already are integrated there. This corresponds to a use case where 1316 * the dynamic sysbus nodes are complex and their generation is not yet 1317 * supported. In that case the user can take charge of the guest dt 1318 * while qemu takes charge of the qom stuff. 1319 */ 1320 if (info->dtb_filename == NULL) { 1321 platform_bus_add_all_fdt_nodes(vms->fdt, "/intc", 1322 vms->memmap[VIRT_PLATFORM_BUS].base, 1323 vms->memmap[VIRT_PLATFORM_BUS].size, 1324 vms->irqmap[VIRT_PLATFORM_BUS]); 1325 } 1326 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) { 1327 exit(1); 1328 } 1329 1330 virt_acpi_setup(vms); 1331 virt_build_smbios(vms); 1332 } 1333 1334 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1335 { 1336 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1337 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1338 1339 if (!vmc->disallow_affinity_adjustment) { 1340 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1341 * GIC's target-list limitations. 32-bit KVM hosts currently 1342 * always create clusters of 4 CPUs, but that is expected to 1343 * change when they gain support for gicv3. When KVM is enabled 1344 * it will override the changes we make here, therefore our 1345 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1346 * and to improve SGI efficiency. 1347 */ 1348 if (vms->gic_version == 3) { 1349 clustersz = GICV3_TARGETLIST_BITS; 1350 } else { 1351 clustersz = GIC_TARGETLIST_BITS; 1352 } 1353 } 1354 return arm_cpu_mp_affinity(idx, clustersz); 1355 } 1356 1357 static void machvirt_init(MachineState *machine) 1358 { 1359 VirtMachineState *vms = VIRT_MACHINE(machine); 1360 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1361 MachineClass *mc = MACHINE_GET_CLASS(machine); 1362 const CPUArchIdList *possible_cpus; 1363 qemu_irq pic[NUM_IRQS]; 1364 MemoryRegion *sysmem = get_system_memory(); 1365 MemoryRegion *secure_sysmem = NULL; 1366 int n, virt_max_cpus; 1367 MemoryRegion *ram = g_new(MemoryRegion, 1); 1368 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); 1369 bool aarch64 = true; 1370 1371 /* We can probe only here because during property set 1372 * KVM is not available yet 1373 */ 1374 if (vms->gic_version <= 0) { 1375 /* "host" or "max" */ 1376 if (!kvm_enabled()) { 1377 if (vms->gic_version == 0) { 1378 error_report("gic-version=host requires KVM"); 1379 exit(1); 1380 } else { 1381 /* "max": currently means 3 for TCG */ 1382 vms->gic_version = 3; 1383 } 1384 } else { 1385 vms->gic_version = kvm_arm_vgic_probe(); 1386 if (!vms->gic_version) { 1387 error_report( 1388 "Unable to determine GIC version supported by host"); 1389 exit(1); 1390 } 1391 } 1392 } 1393 1394 if (!cpu_type_valid(machine->cpu_type)) { 1395 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 1396 exit(1); 1397 } 1398 1399 /* If we have an EL3 boot ROM then the assumption is that it will 1400 * implement PSCI itself, so disable QEMU's internal implementation 1401 * so it doesn't get in the way. Instead of starting secondary 1402 * CPUs in PSCI powerdown state we will start them all running and 1403 * let the boot ROM sort them out. 1404 * The usual case is that we do use QEMU's PSCI implementation; 1405 * if the guest has EL2 then we will use SMC as the conduit, 1406 * and otherwise we will use HVC (for backwards compatibility and 1407 * because if we're using KVM then we must use HVC). 1408 */ 1409 if (vms->secure && firmware_loaded) { 1410 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1411 } else if (vms->virt) { 1412 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 1413 } else { 1414 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 1415 } 1416 1417 /* The maximum number of CPUs depends on the GIC version, or on how 1418 * many redistributors we can fit into the memory map. 1419 */ 1420 if (vms->gic_version == 3) { 1421 virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 1422 virt_max_cpus += vms->memmap[VIRT_GIC_REDIST2].size / GICV3_REDIST_SIZE; 1423 } else { 1424 virt_max_cpus = GIC_NCPU; 1425 } 1426 1427 if (max_cpus > virt_max_cpus) { 1428 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1429 "supported by machine 'mach-virt' (%d)", 1430 max_cpus, virt_max_cpus); 1431 exit(1); 1432 } 1433 1434 vms->smp_cpus = smp_cpus; 1435 1436 if (machine->ram_size > vms->memmap[VIRT_MEM].size) { 1437 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB); 1438 exit(1); 1439 } 1440 1441 if (vms->virt && kvm_enabled()) { 1442 error_report("mach-virt: KVM does not support providing " 1443 "Virtualization extensions to the guest CPU"); 1444 exit(1); 1445 } 1446 1447 if (vms->secure) { 1448 if (kvm_enabled()) { 1449 error_report("mach-virt: KVM does not support Security extensions"); 1450 exit(1); 1451 } 1452 1453 /* The Secure view of the world is the same as the NonSecure, 1454 * but with a few extra devices. Create it as a container region 1455 * containing the system memory at low priority; any secure-only 1456 * devices go in at higher priority and take precedence. 1457 */ 1458 secure_sysmem = g_new(MemoryRegion, 1); 1459 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1460 UINT64_MAX); 1461 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1462 } 1463 1464 create_fdt(vms); 1465 1466 possible_cpus = mc->possible_cpu_arch_ids(machine); 1467 for (n = 0; n < possible_cpus->len; n++) { 1468 Object *cpuobj; 1469 CPUState *cs; 1470 1471 if (n >= smp_cpus) { 1472 break; 1473 } 1474 1475 cpuobj = object_new(possible_cpus->cpus[n].type); 1476 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 1477 "mp-affinity", NULL); 1478 1479 cs = CPU(cpuobj); 1480 cs->cpu_index = n; 1481 1482 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 1483 &error_fatal); 1484 1485 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 1486 1487 if (!vms->secure) { 1488 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1489 } 1490 1491 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { 1492 object_property_set_bool(cpuobj, false, "has_el2", NULL); 1493 } 1494 1495 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1496 object_property_set_int(cpuobj, vms->psci_conduit, 1497 "psci-conduit", NULL); 1498 1499 /* Secondary CPUs start in PSCI powered-down state */ 1500 if (n > 0) { 1501 object_property_set_bool(cpuobj, true, 1502 "start-powered-off", NULL); 1503 } 1504 } 1505 1506 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { 1507 object_property_set_bool(cpuobj, false, "pmu", NULL); 1508 } 1509 1510 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1511 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, 1512 "reset-cbar", &error_abort); 1513 } 1514 1515 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1516 &error_abort); 1517 if (vms->secure) { 1518 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1519 "secure-memory", &error_abort); 1520 } 1521 1522 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 1523 object_unref(cpuobj); 1524 } 1525 fdt_add_timer_nodes(vms); 1526 fdt_add_cpu_nodes(vms); 1527 1528 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", 1529 machine->ram_size); 1530 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); 1531 1532 create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem); 1533 1534 create_gic(vms, pic); 1535 1536 fdt_add_pmu_nodes(vms); 1537 1538 create_uart(vms, pic, VIRT_UART, sysmem, serial_hd(0)); 1539 1540 if (vms->secure) { 1541 create_secure_ram(vms, secure_sysmem); 1542 create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 1543 } 1544 1545 vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64); 1546 1547 create_rtc(vms, pic); 1548 1549 create_pcie(vms, pic); 1550 1551 create_gpio(vms, pic); 1552 1553 /* Create mmio transports, so the user can create virtio backends 1554 * (which will be automatically plugged in to the transports). If 1555 * no backend is created the transport will just sit harmlessly idle. 1556 */ 1557 create_virtio_devices(vms, pic); 1558 1559 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 1560 rom_set_fw(vms->fw_cfg); 1561 1562 create_platform_bus(vms, pic); 1563 1564 vms->bootinfo.ram_size = machine->ram_size; 1565 vms->bootinfo.kernel_filename = machine->kernel_filename; 1566 vms->bootinfo.kernel_cmdline = machine->kernel_cmdline; 1567 vms->bootinfo.initrd_filename = machine->initrd_filename; 1568 vms->bootinfo.nb_cpus = smp_cpus; 1569 vms->bootinfo.board_id = -1; 1570 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 1571 vms->bootinfo.get_dtb = machvirt_dtb; 1572 vms->bootinfo.skip_dtb_autoload = true; 1573 vms->bootinfo.firmware_loaded = firmware_loaded; 1574 arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo); 1575 1576 vms->machine_done.notify = virt_machine_done; 1577 qemu_add_machine_init_done_notifier(&vms->machine_done); 1578 } 1579 1580 static bool virt_get_secure(Object *obj, Error **errp) 1581 { 1582 VirtMachineState *vms = VIRT_MACHINE(obj); 1583 1584 return vms->secure; 1585 } 1586 1587 static void virt_set_secure(Object *obj, bool value, Error **errp) 1588 { 1589 VirtMachineState *vms = VIRT_MACHINE(obj); 1590 1591 vms->secure = value; 1592 } 1593 1594 static bool virt_get_virt(Object *obj, Error **errp) 1595 { 1596 VirtMachineState *vms = VIRT_MACHINE(obj); 1597 1598 return vms->virt; 1599 } 1600 1601 static void virt_set_virt(Object *obj, bool value, Error **errp) 1602 { 1603 VirtMachineState *vms = VIRT_MACHINE(obj); 1604 1605 vms->virt = value; 1606 } 1607 1608 static bool virt_get_highmem(Object *obj, Error **errp) 1609 { 1610 VirtMachineState *vms = VIRT_MACHINE(obj); 1611 1612 return vms->highmem; 1613 } 1614 1615 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1616 { 1617 VirtMachineState *vms = VIRT_MACHINE(obj); 1618 1619 vms->highmem = value; 1620 } 1621 1622 static bool virt_get_its(Object *obj, Error **errp) 1623 { 1624 VirtMachineState *vms = VIRT_MACHINE(obj); 1625 1626 return vms->its; 1627 } 1628 1629 static void virt_set_its(Object *obj, bool value, Error **errp) 1630 { 1631 VirtMachineState *vms = VIRT_MACHINE(obj); 1632 1633 vms->its = value; 1634 } 1635 1636 static char *virt_get_gic_version(Object *obj, Error **errp) 1637 { 1638 VirtMachineState *vms = VIRT_MACHINE(obj); 1639 const char *val = vms->gic_version == 3 ? "3" : "2"; 1640 1641 return g_strdup(val); 1642 } 1643 1644 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 1645 { 1646 VirtMachineState *vms = VIRT_MACHINE(obj); 1647 1648 if (!strcmp(value, "3")) { 1649 vms->gic_version = 3; 1650 } else if (!strcmp(value, "2")) { 1651 vms->gic_version = 2; 1652 } else if (!strcmp(value, "host")) { 1653 vms->gic_version = 0; /* Will probe later */ 1654 } else if (!strcmp(value, "max")) { 1655 vms->gic_version = -1; /* Will probe later */ 1656 } else { 1657 error_setg(errp, "Invalid gic-version value"); 1658 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 1659 } 1660 } 1661 1662 static char *virt_get_iommu(Object *obj, Error **errp) 1663 { 1664 VirtMachineState *vms = VIRT_MACHINE(obj); 1665 1666 switch (vms->iommu) { 1667 case VIRT_IOMMU_NONE: 1668 return g_strdup("none"); 1669 case VIRT_IOMMU_SMMUV3: 1670 return g_strdup("smmuv3"); 1671 default: 1672 g_assert_not_reached(); 1673 } 1674 } 1675 1676 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 1677 { 1678 VirtMachineState *vms = VIRT_MACHINE(obj); 1679 1680 if (!strcmp(value, "smmuv3")) { 1681 vms->iommu = VIRT_IOMMU_SMMUV3; 1682 } else if (!strcmp(value, "none")) { 1683 vms->iommu = VIRT_IOMMU_NONE; 1684 } else { 1685 error_setg(errp, "Invalid iommu value"); 1686 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 1687 } 1688 } 1689 1690 static CpuInstanceProperties 1691 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1692 { 1693 MachineClass *mc = MACHINE_GET_CLASS(ms); 1694 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1695 1696 assert(cpu_index < possible_cpus->len); 1697 return possible_cpus->cpus[cpu_index].props; 1698 } 1699 1700 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1701 { 1702 return idx % nb_numa_nodes; 1703 } 1704 1705 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1706 { 1707 int n; 1708 VirtMachineState *vms = VIRT_MACHINE(ms); 1709 1710 if (ms->possible_cpus) { 1711 assert(ms->possible_cpus->len == max_cpus); 1712 return ms->possible_cpus; 1713 } 1714 1715 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1716 sizeof(CPUArchId) * max_cpus); 1717 ms->possible_cpus->len = max_cpus; 1718 for (n = 0; n < ms->possible_cpus->len; n++) { 1719 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1720 ms->possible_cpus->cpus[n].arch_id = 1721 virt_cpu_mp_affinity(vms, n); 1722 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1723 ms->possible_cpus->cpus[n].props.thread_id = n; 1724 } 1725 return ms->possible_cpus; 1726 } 1727 1728 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1729 DeviceState *dev, Error **errp) 1730 { 1731 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 1732 1733 if (vms->platform_bus_dev) { 1734 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) { 1735 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 1736 SYS_BUS_DEVICE(dev)); 1737 } 1738 } 1739 } 1740 1741 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1742 DeviceState *dev) 1743 { 1744 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) { 1745 return HOTPLUG_HANDLER(machine); 1746 } 1747 1748 return NULL; 1749 } 1750 1751 static void virt_machine_class_init(ObjectClass *oc, void *data) 1752 { 1753 MachineClass *mc = MACHINE_CLASS(oc); 1754 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1755 1756 mc->init = machvirt_init; 1757 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 1758 * The value may be reduced later when we have more information about the 1759 * configuration of the particular instance. 1760 */ 1761 mc->max_cpus = 512; 1762 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 1763 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 1764 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1765 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 1766 mc->block_default_type = IF_VIRTIO; 1767 mc->no_cdrom = 1; 1768 mc->pci_allow_0_address = true; 1769 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 1770 mc->minimum_page_bits = 12; 1771 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1772 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1773 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 1774 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1775 assert(!mc->get_hotplug_handler); 1776 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1777 hc->plug = virt_machine_device_plug_cb; 1778 } 1779 1780 static const TypeInfo virt_machine_info = { 1781 .name = TYPE_VIRT_MACHINE, 1782 .parent = TYPE_MACHINE, 1783 .abstract = true, 1784 .instance_size = sizeof(VirtMachineState), 1785 .class_size = sizeof(VirtMachineClass), 1786 .class_init = virt_machine_class_init, 1787 .interfaces = (InterfaceInfo[]) { 1788 { TYPE_HOTPLUG_HANDLER }, 1789 { } 1790 }, 1791 }; 1792 1793 static void machvirt_machine_init(void) 1794 { 1795 type_register_static(&virt_machine_info); 1796 } 1797 type_init(machvirt_machine_init); 1798 1799 static void virt_3_1_instance_init(Object *obj) 1800 { 1801 VirtMachineState *vms = VIRT_MACHINE(obj); 1802 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1803 1804 /* EL3 is disabled by default on virt: this makes us consistent 1805 * between KVM and TCG for this board, and it also allows us to 1806 * boot UEFI blobs which assume no TrustZone support. 1807 */ 1808 vms->secure = false; 1809 object_property_add_bool(obj, "secure", virt_get_secure, 1810 virt_set_secure, NULL); 1811 object_property_set_description(obj, "secure", 1812 "Set on/off to enable/disable the ARM " 1813 "Security Extensions (TrustZone)", 1814 NULL); 1815 1816 /* EL2 is also disabled by default, for similar reasons */ 1817 vms->virt = false; 1818 object_property_add_bool(obj, "virtualization", virt_get_virt, 1819 virt_set_virt, NULL); 1820 object_property_set_description(obj, "virtualization", 1821 "Set on/off to enable/disable emulating a " 1822 "guest CPU which implements the ARM " 1823 "Virtualization Extensions", 1824 NULL); 1825 1826 /* High memory is enabled by default */ 1827 vms->highmem = true; 1828 object_property_add_bool(obj, "highmem", virt_get_highmem, 1829 virt_set_highmem, NULL); 1830 object_property_set_description(obj, "highmem", 1831 "Set on/off to enable/disable using " 1832 "physical address space above 32 bits", 1833 NULL); 1834 /* Default GIC type is v2 */ 1835 vms->gic_version = 2; 1836 object_property_add_str(obj, "gic-version", virt_get_gic_version, 1837 virt_set_gic_version, NULL); 1838 object_property_set_description(obj, "gic-version", 1839 "Set GIC version. " 1840 "Valid values are 2, 3 and host", NULL); 1841 1842 vms->highmem_ecam = !vmc->no_highmem_ecam; 1843 1844 if (vmc->no_its) { 1845 vms->its = false; 1846 } else { 1847 /* Default allows ITS instantiation */ 1848 vms->its = true; 1849 object_property_add_bool(obj, "its", virt_get_its, 1850 virt_set_its, NULL); 1851 object_property_set_description(obj, "its", 1852 "Set on/off to enable/disable " 1853 "ITS instantiation", 1854 NULL); 1855 } 1856 1857 /* Default disallows iommu instantiation */ 1858 vms->iommu = VIRT_IOMMU_NONE; 1859 object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu, NULL); 1860 object_property_set_description(obj, "iommu", 1861 "Set the IOMMU type. " 1862 "Valid values are none and smmuv3", 1863 NULL); 1864 1865 vms->memmap = a15memmap; 1866 vms->irqmap = a15irqmap; 1867 } 1868 1869 static void virt_machine_3_1_options(MachineClass *mc) 1870 { 1871 } 1872 DEFINE_VIRT_MACHINE_AS_LATEST(3, 1) 1873 1874 #define VIRT_COMPAT_3_0 \ 1875 HW_COMPAT_3_0 1876 1877 static void virt_3_0_instance_init(Object *obj) 1878 { 1879 virt_3_1_instance_init(obj); 1880 } 1881 1882 static void virt_machine_3_0_options(MachineClass *mc) 1883 { 1884 virt_machine_3_1_options(mc); 1885 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_3_0); 1886 } 1887 DEFINE_VIRT_MACHINE(3, 0) 1888 1889 #define VIRT_COMPAT_2_12 \ 1890 HW_COMPAT_2_12 1891 1892 static void virt_2_12_instance_init(Object *obj) 1893 { 1894 virt_3_0_instance_init(obj); 1895 } 1896 1897 static void virt_machine_2_12_options(MachineClass *mc) 1898 { 1899 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1900 1901 virt_machine_3_0_options(mc); 1902 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_12); 1903 vmc->no_highmem_ecam = true; 1904 mc->max_cpus = 255; 1905 } 1906 DEFINE_VIRT_MACHINE(2, 12) 1907 1908 #define VIRT_COMPAT_2_11 \ 1909 HW_COMPAT_2_11 1910 1911 static void virt_2_11_instance_init(Object *obj) 1912 { 1913 virt_2_12_instance_init(obj); 1914 } 1915 1916 static void virt_machine_2_11_options(MachineClass *mc) 1917 { 1918 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1919 1920 virt_machine_2_12_options(mc); 1921 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_11); 1922 vmc->smbios_old_sys_ver = true; 1923 } 1924 DEFINE_VIRT_MACHINE(2, 11) 1925 1926 #define VIRT_COMPAT_2_10 \ 1927 HW_COMPAT_2_10 1928 1929 static void virt_2_10_instance_init(Object *obj) 1930 { 1931 virt_2_11_instance_init(obj); 1932 } 1933 1934 static void virt_machine_2_10_options(MachineClass *mc) 1935 { 1936 virt_machine_2_11_options(mc); 1937 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_10); 1938 /* before 2.11 we never faulted accesses to bad addresses */ 1939 mc->ignore_memory_transaction_failures = true; 1940 } 1941 DEFINE_VIRT_MACHINE(2, 10) 1942 1943 #define VIRT_COMPAT_2_9 \ 1944 HW_COMPAT_2_9 1945 1946 static void virt_2_9_instance_init(Object *obj) 1947 { 1948 virt_2_10_instance_init(obj); 1949 } 1950 1951 static void virt_machine_2_9_options(MachineClass *mc) 1952 { 1953 virt_machine_2_10_options(mc); 1954 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_9); 1955 } 1956 DEFINE_VIRT_MACHINE(2, 9) 1957 1958 #define VIRT_COMPAT_2_8 \ 1959 HW_COMPAT_2_8 1960 1961 static void virt_2_8_instance_init(Object *obj) 1962 { 1963 virt_2_9_instance_init(obj); 1964 } 1965 1966 static void virt_machine_2_8_options(MachineClass *mc) 1967 { 1968 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1969 1970 virt_machine_2_9_options(mc); 1971 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_8); 1972 /* For 2.8 and earlier we falsely claimed in the DT that 1973 * our timers were edge-triggered, not level-triggered. 1974 */ 1975 vmc->claim_edge_triggered_timers = true; 1976 } 1977 DEFINE_VIRT_MACHINE(2, 8) 1978 1979 #define VIRT_COMPAT_2_7 \ 1980 HW_COMPAT_2_7 1981 1982 static void virt_2_7_instance_init(Object *obj) 1983 { 1984 virt_2_8_instance_init(obj); 1985 } 1986 1987 static void virt_machine_2_7_options(MachineClass *mc) 1988 { 1989 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1990 1991 virt_machine_2_8_options(mc); 1992 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_7); 1993 /* ITS was introduced with 2.8 */ 1994 vmc->no_its = true; 1995 /* Stick with 1K pages for migration compatibility */ 1996 mc->minimum_page_bits = 0; 1997 } 1998 DEFINE_VIRT_MACHINE(2, 7) 1999 2000 #define VIRT_COMPAT_2_6 \ 2001 HW_COMPAT_2_6 2002 2003 static void virt_2_6_instance_init(Object *obj) 2004 { 2005 virt_2_7_instance_init(obj); 2006 } 2007 2008 static void virt_machine_2_6_options(MachineClass *mc) 2009 { 2010 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2011 2012 virt_machine_2_7_options(mc); 2013 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6); 2014 vmc->disallow_affinity_adjustment = true; 2015 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 2016 vmc->no_pmu = true; 2017 } 2018 DEFINE_VIRT_MACHINE(2, 6) 2019