1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu-common.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "qapi/error.h" 37 #include "hw/sysbus.h" 38 #include "hw/boards.h" 39 #include "hw/arm/boot.h" 40 #include "hw/arm/primecell.h" 41 #include "hw/arm/virt.h" 42 #include "hw/block/flash.h" 43 #include "hw/vfio/vfio-calxeda-xgmac.h" 44 #include "hw/vfio/vfio-amd-xgbe.h" 45 #include "hw/display/ramfb.h" 46 #include "net/net.h" 47 #include "sysemu/device_tree.h" 48 #include "sysemu/numa.h" 49 #include "sysemu/runstate.h" 50 #include "sysemu/sysemu.h" 51 #include "sysemu/tpm.h" 52 #include "sysemu/kvm.h" 53 #include "hw/loader.h" 54 #include "exec/address-spaces.h" 55 #include "qemu/bitops.h" 56 #include "qemu/error-report.h" 57 #include "qemu/module.h" 58 #include "hw/pci-host/gpex.h" 59 #include "hw/virtio/virtio-pci.h" 60 #include "hw/arm/sysbus-fdt.h" 61 #include "hw/platform-bus.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/arm/fdt.h" 64 #include "hw/intc/arm_gic.h" 65 #include "hw/intc/arm_gicv3_common.h" 66 #include "hw/irq.h" 67 #include "kvm_arm.h" 68 #include "hw/firmware/smbios.h" 69 #include "qapi/visitor.h" 70 #include "qapi/qapi-visit-common.h" 71 #include "standard-headers/linux/input.h" 72 #include "hw/arm/smmuv3.h" 73 #include "hw/acpi/acpi.h" 74 #include "target/arm/internals.h" 75 #include "hw/mem/pc-dimm.h" 76 #include "hw/mem/nvdimm.h" 77 #include "hw/acpi/generic_event_device.h" 78 #include "hw/virtio/virtio-iommu.h" 79 #include "hw/char/pl011.h" 80 #include "qemu/guest-random.h" 81 82 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 83 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 84 void *data) \ 85 { \ 86 MachineClass *mc = MACHINE_CLASS(oc); \ 87 virt_machine_##major##_##minor##_options(mc); \ 88 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 89 if (latest) { \ 90 mc->alias = "virt"; \ 91 } \ 92 } \ 93 static const TypeInfo machvirt_##major##_##minor##_info = { \ 94 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 95 .parent = TYPE_VIRT_MACHINE, \ 96 .class_init = virt_##major##_##minor##_class_init, \ 97 }; \ 98 static void machvirt_machine_##major##_##minor##_init(void) \ 99 { \ 100 type_register_static(&machvirt_##major##_##minor##_info); \ 101 } \ 102 type_init(machvirt_machine_##major##_##minor##_init); 103 104 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 105 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 106 #define DEFINE_VIRT_MACHINE(major, minor) \ 107 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 108 109 110 /* Number of external interrupt lines to configure the GIC with */ 111 #define NUM_IRQS 256 112 113 #define PLATFORM_BUS_NUM_IRQS 64 114 115 /* Legacy RAM limit in GB (< version 4.0) */ 116 #define LEGACY_RAMLIMIT_GB 255 117 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 118 119 /* Addresses and sizes of our components. 120 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 121 * 128MB..256MB is used for miscellaneous device I/O. 122 * 256MB..1GB is reserved for possible future PCI support (ie where the 123 * PCI memory window will go if we add a PCI host controller). 124 * 1GB and up is RAM (which may happily spill over into the 125 * high memory region beyond 4GB). 126 * This represents a compromise between how much RAM can be given to 127 * a 32 bit VM and leaving space for expansion and in particular for PCI. 128 * Note that devices should generally be placed at multiples of 0x10000, 129 * to accommodate guests using 64K pages. 130 */ 131 static const MemMapEntry base_memmap[] = { 132 /* Space up to 0x8000000 is reserved for a boot ROM */ 133 [VIRT_FLASH] = { 0, 0x08000000 }, 134 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 135 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 136 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 137 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 138 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 139 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 140 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 141 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 142 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 143 /* This redistributor space allows up to 2*64kB*123 CPUs */ 144 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 145 [VIRT_UART] = { 0x09000000, 0x00001000 }, 146 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 147 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 148 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 149 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 150 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 151 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 152 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 153 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 154 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 155 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 156 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 157 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 158 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 159 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 160 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 161 /* Actual RAM size depends on initial RAM and device memory settings */ 162 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 163 }; 164 165 /* 166 * Highmem IO Regions: This memory map is floating, located after the RAM. 167 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 168 * top of the RAM, so that its base get the same alignment as the size, 169 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 170 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 171 * Note the extended_memmap is sized so that it eventually also includes the 172 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 173 * index of base_memmap). 174 */ 175 static MemMapEntry extended_memmap[] = { 176 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 177 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 178 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 179 /* Second PCIe window */ 180 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 181 }; 182 183 static const int a15irqmap[] = { 184 [VIRT_UART] = 1, 185 [VIRT_RTC] = 2, 186 [VIRT_PCIE] = 3, /* ... to 6 */ 187 [VIRT_GPIO] = 7, 188 [VIRT_SECURE_UART] = 8, 189 [VIRT_ACPI_GED] = 9, 190 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 191 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 192 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 193 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 194 }; 195 196 static const char *valid_cpus[] = { 197 ARM_CPU_TYPE_NAME("cortex-a7"), 198 ARM_CPU_TYPE_NAME("cortex-a15"), 199 ARM_CPU_TYPE_NAME("cortex-a53"), 200 ARM_CPU_TYPE_NAME("cortex-a57"), 201 ARM_CPU_TYPE_NAME("cortex-a72"), 202 ARM_CPU_TYPE_NAME("host"), 203 ARM_CPU_TYPE_NAME("max"), 204 }; 205 206 static bool cpu_type_valid(const char *cpu) 207 { 208 int i; 209 210 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 211 if (strcmp(cpu, valid_cpus[i]) == 0) { 212 return true; 213 } 214 } 215 return false; 216 } 217 218 static void create_kaslr_seed(VirtMachineState *vms, const char *node) 219 { 220 Error *err = NULL; 221 uint64_t seed; 222 223 if (qemu_guest_getrandom(&seed, sizeof(seed), &err)) { 224 error_free(err); 225 return; 226 } 227 qemu_fdt_setprop_u64(vms->fdt, node, "kaslr-seed", seed); 228 } 229 230 static void create_fdt(VirtMachineState *vms) 231 { 232 MachineState *ms = MACHINE(vms); 233 int nb_numa_nodes = ms->numa_state->num_nodes; 234 void *fdt = create_device_tree(&vms->fdt_size); 235 236 if (!fdt) { 237 error_report("create_device_tree() failed"); 238 exit(1); 239 } 240 241 vms->fdt = fdt; 242 243 /* Header */ 244 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 245 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 246 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 247 248 /* /chosen must exist for load_dtb to fill in necessary properties later */ 249 qemu_fdt_add_subnode(fdt, "/chosen"); 250 create_kaslr_seed(vms, "/chosen"); 251 252 if (vms->secure) { 253 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 254 create_kaslr_seed(vms, "/secure-chosen"); 255 } 256 257 /* Clock node, for the benefit of the UART. The kernel device tree 258 * binding documentation claims the PL011 node clock properties are 259 * optional but in practice if you omit them the kernel refuses to 260 * probe for the device. 261 */ 262 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 263 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 264 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 265 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 266 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 267 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 268 "clk24mhz"); 269 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 270 271 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 272 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 273 uint32_t *matrix = g_malloc0(size); 274 int idx, i, j; 275 276 for (i = 0; i < nb_numa_nodes; i++) { 277 for (j = 0; j < nb_numa_nodes; j++) { 278 idx = (i * nb_numa_nodes + j) * 3; 279 matrix[idx + 0] = cpu_to_be32(i); 280 matrix[idx + 1] = cpu_to_be32(j); 281 matrix[idx + 2] = 282 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 283 } 284 } 285 286 qemu_fdt_add_subnode(fdt, "/distance-map"); 287 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 288 "numa-distance-map-v1"); 289 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 290 matrix, size); 291 g_free(matrix); 292 } 293 } 294 295 static void fdt_add_timer_nodes(const VirtMachineState *vms) 296 { 297 /* On real hardware these interrupts are level-triggered. 298 * On KVM they were edge-triggered before host kernel version 4.4, 299 * and level-triggered afterwards. 300 * On emulated QEMU they are level-triggered. 301 * 302 * Getting the DTB info about them wrong is awkward for some 303 * guest kernels: 304 * pre-4.8 ignore the DT and leave the interrupt configured 305 * with whatever the GIC reset value (or the bootloader) left it at 306 * 4.8 before rc6 honour the incorrect data by programming it back 307 * into the GIC, causing problems 308 * 4.8rc6 and later ignore the DT and always write "level triggered" 309 * into the GIC 310 * 311 * For backwards-compatibility, virt-2.8 and earlier will continue 312 * to say these are edge-triggered, but later machines will report 313 * the correct information. 314 */ 315 ARMCPU *armcpu; 316 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 317 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 318 319 if (vmc->claim_edge_triggered_timers) { 320 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 321 } 322 323 if (vms->gic_version == VIRT_GIC_VERSION_2) { 324 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 325 GIC_FDT_IRQ_PPI_CPU_WIDTH, 326 (1 << vms->smp_cpus) - 1); 327 } 328 329 qemu_fdt_add_subnode(vms->fdt, "/timer"); 330 331 armcpu = ARM_CPU(qemu_get_cpu(0)); 332 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 333 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 334 qemu_fdt_setprop(vms->fdt, "/timer", "compatible", 335 compat, sizeof(compat)); 336 } else { 337 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible", 338 "arm,armv7-timer"); 339 } 340 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0); 341 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts", 342 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 343 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 344 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 345 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 346 } 347 348 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 349 { 350 int cpu; 351 int addr_cells = 1; 352 const MachineState *ms = MACHINE(vms); 353 354 /* 355 * From Documentation/devicetree/bindings/arm/cpus.txt 356 * On ARM v8 64-bit systems value should be set to 2, 357 * that corresponds to the MPIDR_EL1 register size. 358 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 359 * in the system, #address-cells can be set to 1, since 360 * MPIDR_EL1[63:32] bits are not used for CPUs 361 * identification. 362 * 363 * Here we actually don't know whether our system is 32- or 64-bit one. 364 * The simplest way to go is to examine affinity IDs of all our CPUs. If 365 * at least one of them has Aff3 populated, we set #address-cells to 2. 366 */ 367 for (cpu = 0; cpu < vms->smp_cpus; cpu++) { 368 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 369 370 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 371 addr_cells = 2; 372 break; 373 } 374 } 375 376 qemu_fdt_add_subnode(vms->fdt, "/cpus"); 377 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); 378 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); 379 380 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { 381 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 382 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 383 CPUState *cs = CPU(armcpu); 384 385 qemu_fdt_add_subnode(vms->fdt, nodename); 386 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); 387 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 388 armcpu->dtb_compatible); 389 390 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED 391 && vms->smp_cpus > 1) { 392 qemu_fdt_setprop_string(vms->fdt, nodename, 393 "enable-method", "psci"); 394 } 395 396 if (addr_cells == 2) { 397 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", 398 armcpu->mp_affinity); 399 } else { 400 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", 401 armcpu->mp_affinity); 402 } 403 404 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 405 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", 406 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 407 } 408 409 g_free(nodename); 410 } 411 } 412 413 static void fdt_add_its_gic_node(VirtMachineState *vms) 414 { 415 char *nodename; 416 417 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 418 nodename = g_strdup_printf("/intc/its@%" PRIx64, 419 vms->memmap[VIRT_GIC_ITS].base); 420 qemu_fdt_add_subnode(vms->fdt, nodename); 421 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 422 "arm,gic-v3-its"); 423 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); 424 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 425 2, vms->memmap[VIRT_GIC_ITS].base, 426 2, vms->memmap[VIRT_GIC_ITS].size); 427 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); 428 g_free(nodename); 429 } 430 431 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 432 { 433 char *nodename; 434 435 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 436 vms->memmap[VIRT_GIC_V2M].base); 437 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); 438 qemu_fdt_add_subnode(vms->fdt, nodename); 439 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 440 "arm,gic-v2m-frame"); 441 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); 442 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 443 2, vms->memmap[VIRT_GIC_V2M].base, 444 2, vms->memmap[VIRT_GIC_V2M].size); 445 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); 446 g_free(nodename); 447 } 448 449 static void fdt_add_gic_node(VirtMachineState *vms) 450 { 451 char *nodename; 452 453 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt); 454 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle); 455 456 nodename = g_strdup_printf("/intc@%" PRIx64, 457 vms->memmap[VIRT_GIC_DIST].base); 458 qemu_fdt_add_subnode(vms->fdt, nodename); 459 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 3); 460 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-controller", NULL, 0); 461 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2); 462 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2); 463 qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0); 464 if (vms->gic_version == VIRT_GIC_VERSION_3) { 465 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 466 467 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 468 "arm,gic-v3"); 469 470 qemu_fdt_setprop_cell(vms->fdt, nodename, 471 "#redistributor-regions", nb_redist_regions); 472 473 if (nb_redist_regions == 1) { 474 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 475 2, vms->memmap[VIRT_GIC_DIST].base, 476 2, vms->memmap[VIRT_GIC_DIST].size, 477 2, vms->memmap[VIRT_GIC_REDIST].base, 478 2, vms->memmap[VIRT_GIC_REDIST].size); 479 } else { 480 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 481 2, vms->memmap[VIRT_GIC_DIST].base, 482 2, vms->memmap[VIRT_GIC_DIST].size, 483 2, vms->memmap[VIRT_GIC_REDIST].base, 484 2, vms->memmap[VIRT_GIC_REDIST].size, 485 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 486 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 487 } 488 489 if (vms->virt) { 490 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 491 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 492 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 493 } 494 } else { 495 /* 'cortex-a15-gic' means 'GIC v2' */ 496 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", 497 "arm,cortex-a15-gic"); 498 if (!vms->virt) { 499 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 500 2, vms->memmap[VIRT_GIC_DIST].base, 501 2, vms->memmap[VIRT_GIC_DIST].size, 502 2, vms->memmap[VIRT_GIC_CPU].base, 503 2, vms->memmap[VIRT_GIC_CPU].size); 504 } else { 505 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 506 2, vms->memmap[VIRT_GIC_DIST].base, 507 2, vms->memmap[VIRT_GIC_DIST].size, 508 2, vms->memmap[VIRT_GIC_CPU].base, 509 2, vms->memmap[VIRT_GIC_CPU].size, 510 2, vms->memmap[VIRT_GIC_HYP].base, 511 2, vms->memmap[VIRT_GIC_HYP].size, 512 2, vms->memmap[VIRT_GIC_VCPU].base, 513 2, vms->memmap[VIRT_GIC_VCPU].size); 514 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 515 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 516 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 517 } 518 } 519 520 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle); 521 g_free(nodename); 522 } 523 524 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 525 { 526 CPUState *cpu; 527 ARMCPU *armcpu; 528 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 529 530 CPU_FOREACH(cpu) { 531 armcpu = ARM_CPU(cpu); 532 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 533 return; 534 } 535 if (kvm_enabled()) { 536 if (kvm_irqchip_in_kernel()) { 537 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 538 } 539 kvm_arm_pmu_init(cpu); 540 } 541 } 542 543 if (vms->gic_version == VIRT_GIC_VERSION_2) { 544 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 545 GIC_FDT_IRQ_PPI_CPU_WIDTH, 546 (1 << vms->smp_cpus) - 1); 547 } 548 549 armcpu = ARM_CPU(qemu_get_cpu(0)); 550 qemu_fdt_add_subnode(vms->fdt, "/pmu"); 551 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 552 const char compat[] = "arm,armv8-pmuv3"; 553 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible", 554 compat, sizeof(compat)); 555 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts", 556 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 557 } 558 } 559 560 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 561 { 562 DeviceState *dev; 563 MachineState *ms = MACHINE(vms); 564 int irq = vms->irqmap[VIRT_ACPI_GED]; 565 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 566 567 if (ms->ram_slots) { 568 event |= ACPI_GED_MEM_HOTPLUG_EVT; 569 } 570 571 if (ms->nvdimms_state->is_enabled) { 572 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 573 } 574 575 dev = qdev_new(TYPE_ACPI_GED); 576 qdev_prop_set_uint32(dev, "ged-event", event); 577 578 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 579 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 580 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 581 582 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 583 584 return dev; 585 } 586 587 static void create_its(VirtMachineState *vms) 588 { 589 const char *itsclass = its_class_name(); 590 DeviceState *dev; 591 592 if (!itsclass) { 593 /* Do nothing if not supported */ 594 return; 595 } 596 597 dev = qdev_new(itsclass); 598 599 object_property_set_link(OBJECT(dev), OBJECT(vms->gic), "parent-gicv3", 600 &error_abort); 601 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 602 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 603 604 fdt_add_its_gic_node(vms); 605 } 606 607 static void create_v2m(VirtMachineState *vms) 608 { 609 int i; 610 int irq = vms->irqmap[VIRT_GIC_V2M]; 611 DeviceState *dev; 612 613 dev = qdev_new("arm-gicv2m"); 614 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 615 qdev_prop_set_uint32(dev, "base-spi", irq); 616 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 617 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 618 619 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 620 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 621 qdev_get_gpio_in(vms->gic, irq + i)); 622 } 623 624 fdt_add_v2m_gic_node(vms); 625 } 626 627 static void create_gic(VirtMachineState *vms) 628 { 629 MachineState *ms = MACHINE(vms); 630 /* We create a standalone GIC */ 631 SysBusDevice *gicbusdev; 632 const char *gictype; 633 int type = vms->gic_version, i; 634 unsigned int smp_cpus = ms->smp.cpus; 635 uint32_t nb_redist_regions = 0; 636 637 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 638 639 vms->gic = qdev_new(gictype); 640 qdev_prop_set_uint32(vms->gic, "revision", type); 641 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 642 /* Note that the num-irq property counts both internal and external 643 * interrupts; there are always 32 of the former (mandated by GIC spec). 644 */ 645 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 646 if (!kvm_irqchip_in_kernel()) { 647 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 648 } 649 650 if (type == 3) { 651 uint32_t redist0_capacity = 652 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 653 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 654 655 nb_redist_regions = virt_gicv3_redist_region_count(vms); 656 657 qdev_prop_set_uint32(vms->gic, "len-redist-region-count", 658 nb_redist_regions); 659 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count); 660 661 if (nb_redist_regions == 2) { 662 uint32_t redist1_capacity = 663 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; 664 665 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", 666 MIN(smp_cpus - redist0_count, redist1_capacity)); 667 } 668 } else { 669 if (!kvm_irqchip_in_kernel()) { 670 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 671 vms->virt); 672 } 673 } 674 gicbusdev = SYS_BUS_DEVICE(vms->gic); 675 sysbus_realize_and_unref(gicbusdev, &error_fatal); 676 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 677 if (type == 3) { 678 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 679 if (nb_redist_regions == 2) { 680 sysbus_mmio_map(gicbusdev, 2, 681 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 682 } 683 } else { 684 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 685 if (vms->virt) { 686 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 687 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 688 } 689 } 690 691 /* Wire the outputs from each CPU's generic timer and the GICv3 692 * maintenance interrupt signal to the appropriate GIC PPI inputs, 693 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 694 */ 695 for (i = 0; i < smp_cpus; i++) { 696 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 697 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 698 int irq; 699 /* Mapping from the output timer irq lines from the CPU to the 700 * GIC PPI inputs we use for the virt board. 701 */ 702 const int timer_irq[] = { 703 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 704 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 705 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 706 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 707 }; 708 709 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 710 qdev_connect_gpio_out(cpudev, irq, 711 qdev_get_gpio_in(vms->gic, 712 ppibase + timer_irq[irq])); 713 } 714 715 if (type == 3) { 716 qemu_irq irq = qdev_get_gpio_in(vms->gic, 717 ppibase + ARCH_GIC_MAINT_IRQ); 718 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 719 0, irq); 720 } else if (vms->virt) { 721 qemu_irq irq = qdev_get_gpio_in(vms->gic, 722 ppibase + ARCH_GIC_MAINT_IRQ); 723 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 724 } 725 726 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 727 qdev_get_gpio_in(vms->gic, ppibase 728 + VIRTUAL_PMU_IRQ)); 729 730 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 731 sysbus_connect_irq(gicbusdev, i + smp_cpus, 732 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 733 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 734 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 735 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 736 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 737 } 738 739 fdt_add_gic_node(vms); 740 741 if (type == 3 && vms->its) { 742 create_its(vms); 743 } else if (type == 2) { 744 create_v2m(vms); 745 } 746 } 747 748 static void create_uart(const VirtMachineState *vms, int uart, 749 MemoryRegion *mem, Chardev *chr) 750 { 751 char *nodename; 752 hwaddr base = vms->memmap[uart].base; 753 hwaddr size = vms->memmap[uart].size; 754 int irq = vms->irqmap[uart]; 755 const char compat[] = "arm,pl011\0arm,primecell"; 756 const char clocknames[] = "uartclk\0apb_pclk"; 757 DeviceState *dev = qdev_new(TYPE_PL011); 758 SysBusDevice *s = SYS_BUS_DEVICE(dev); 759 760 qdev_prop_set_chr(dev, "chardev", chr); 761 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 762 memory_region_add_subregion(mem, base, 763 sysbus_mmio_get_region(s, 0)); 764 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 765 766 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 767 qemu_fdt_add_subnode(vms->fdt, nodename); 768 /* Note that we can't use setprop_string because of the embedded NUL */ 769 qemu_fdt_setprop(vms->fdt, nodename, "compatible", 770 compat, sizeof(compat)); 771 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 772 2, base, 2, size); 773 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 774 GIC_FDT_IRQ_TYPE_SPI, irq, 775 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 776 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks", 777 vms->clock_phandle, vms->clock_phandle); 778 qemu_fdt_setprop(vms->fdt, nodename, "clock-names", 779 clocknames, sizeof(clocknames)); 780 781 if (uart == VIRT_UART) { 782 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); 783 } else { 784 /* Mark as not usable by the normal world */ 785 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 786 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 787 788 qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path", 789 nodename); 790 } 791 792 g_free(nodename); 793 } 794 795 static void create_rtc(const VirtMachineState *vms) 796 { 797 char *nodename; 798 hwaddr base = vms->memmap[VIRT_RTC].base; 799 hwaddr size = vms->memmap[VIRT_RTC].size; 800 int irq = vms->irqmap[VIRT_RTC]; 801 const char compat[] = "arm,pl031\0arm,primecell"; 802 803 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 804 805 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 806 qemu_fdt_add_subnode(vms->fdt, nodename); 807 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 808 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 809 2, base, 2, size); 810 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 811 GIC_FDT_IRQ_TYPE_SPI, irq, 812 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 813 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 814 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 815 g_free(nodename); 816 } 817 818 static DeviceState *gpio_key_dev; 819 static void virt_powerdown_req(Notifier *n, void *opaque) 820 { 821 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 822 823 if (s->acpi_dev) { 824 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 825 } else { 826 /* use gpio Pin 3 for power button event */ 827 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 828 } 829 } 830 831 static void create_gpio(const VirtMachineState *vms) 832 { 833 char *nodename; 834 DeviceState *pl061_dev; 835 hwaddr base = vms->memmap[VIRT_GPIO].base; 836 hwaddr size = vms->memmap[VIRT_GPIO].size; 837 int irq = vms->irqmap[VIRT_GPIO]; 838 const char compat[] = "arm,pl061\0arm,primecell"; 839 840 pl061_dev = sysbus_create_simple("pl061", base, 841 qdev_get_gpio_in(vms->gic, irq)); 842 843 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); 844 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 845 qemu_fdt_add_subnode(vms->fdt, nodename); 846 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 847 2, base, 2, size); 848 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); 849 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); 850 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); 851 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 852 GIC_FDT_IRQ_TYPE_SPI, irq, 853 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 854 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); 855 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); 856 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); 857 858 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 859 qdev_get_gpio_in(pl061_dev, 3)); 860 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); 861 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); 862 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); 863 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); 864 865 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); 866 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", 867 "label", "GPIO Key Poweroff"); 868 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", 869 KEY_POWER); 870 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", 871 "gpios", phandle, 3, 0); 872 g_free(nodename); 873 } 874 875 static void create_virtio_devices(const VirtMachineState *vms) 876 { 877 int i; 878 hwaddr size = vms->memmap[VIRT_MMIO].size; 879 880 /* We create the transports in forwards order. Since qbus_realize() 881 * prepends (not appends) new child buses, the incrementing loop below will 882 * create a list of virtio-mmio buses with decreasing base addresses. 883 * 884 * When a -device option is processed from the command line, 885 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 886 * order. The upshot is that -device options in increasing command line 887 * order are mapped to virtio-mmio buses with decreasing base addresses. 888 * 889 * When this code was originally written, that arrangement ensured that the 890 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 891 * the first -device on the command line. (The end-to-end order is a 892 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 893 * guest kernel's name-to-address assignment strategy.) 894 * 895 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 896 * the message, if not necessarily the code, of commit 70161ff336. 897 * Therefore the loop now establishes the inverse of the original intent. 898 * 899 * Unfortunately, we can't counteract the kernel change by reversing the 900 * loop; it would break existing command lines. 901 * 902 * In any case, the kernel makes no guarantee about the stability of 903 * enumeration order of virtio devices (as demonstrated by it changing 904 * between kernel versions). For reliable and stable identification 905 * of disks users must use UUIDs or similar mechanisms. 906 */ 907 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 908 int irq = vms->irqmap[VIRT_MMIO] + i; 909 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 910 911 sysbus_create_simple("virtio-mmio", base, 912 qdev_get_gpio_in(vms->gic, irq)); 913 } 914 915 /* We add dtb nodes in reverse order so that they appear in the finished 916 * device tree lowest address first. 917 * 918 * Note that this mapping is independent of the loop above. The previous 919 * loop influences virtio device to virtio transport assignment, whereas 920 * this loop controls how virtio transports are laid out in the dtb. 921 */ 922 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 923 char *nodename; 924 int irq = vms->irqmap[VIRT_MMIO] + i; 925 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 926 927 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 928 qemu_fdt_add_subnode(vms->fdt, nodename); 929 qemu_fdt_setprop_string(vms->fdt, nodename, 930 "compatible", "virtio,mmio"); 931 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 932 2, base, 2, size); 933 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", 934 GIC_FDT_IRQ_TYPE_SPI, irq, 935 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 936 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 937 g_free(nodename); 938 } 939 } 940 941 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 942 943 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 944 const char *name, 945 const char *alias_prop_name) 946 { 947 /* 948 * Create a single flash device. We use the same parameters as 949 * the flash devices on the Versatile Express board. 950 */ 951 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 952 953 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 954 qdev_prop_set_uint8(dev, "width", 4); 955 qdev_prop_set_uint8(dev, "device-width", 2); 956 qdev_prop_set_bit(dev, "big-endian", false); 957 qdev_prop_set_uint16(dev, "id0", 0x89); 958 qdev_prop_set_uint16(dev, "id1", 0x18); 959 qdev_prop_set_uint16(dev, "id2", 0x00); 960 qdev_prop_set_uint16(dev, "id3", 0x00); 961 qdev_prop_set_string(dev, "name", name); 962 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 963 object_property_add_alias(OBJECT(vms), alias_prop_name, 964 OBJECT(dev), "drive"); 965 return PFLASH_CFI01(dev); 966 } 967 968 static void virt_flash_create(VirtMachineState *vms) 969 { 970 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 971 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 972 } 973 974 static void virt_flash_map1(PFlashCFI01 *flash, 975 hwaddr base, hwaddr size, 976 MemoryRegion *sysmem) 977 { 978 DeviceState *dev = DEVICE(flash); 979 980 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 981 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 982 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 983 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 984 985 memory_region_add_subregion(sysmem, base, 986 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 987 0)); 988 } 989 990 static void virt_flash_map(VirtMachineState *vms, 991 MemoryRegion *sysmem, 992 MemoryRegion *secure_sysmem) 993 { 994 /* 995 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 996 * sysmem is the system memory space. secure_sysmem is the secure view 997 * of the system, and the first flash device should be made visible only 998 * there. The second flash device is visible to both secure and nonsecure. 999 * If sysmem == secure_sysmem this means there is no separate Secure 1000 * address space and both flash devices are generally visible. 1001 */ 1002 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1003 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1004 1005 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1006 secure_sysmem); 1007 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1008 sysmem); 1009 } 1010 1011 static void virt_flash_fdt(VirtMachineState *vms, 1012 MemoryRegion *sysmem, 1013 MemoryRegion *secure_sysmem) 1014 { 1015 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1016 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1017 char *nodename; 1018 1019 if (sysmem == secure_sysmem) { 1020 /* Report both flash devices as a single node in the DT */ 1021 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1022 qemu_fdt_add_subnode(vms->fdt, nodename); 1023 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 1024 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1025 2, flashbase, 2, flashsize, 1026 2, flashbase + flashsize, 2, flashsize); 1027 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 1028 g_free(nodename); 1029 } else { 1030 /* 1031 * Report the devices as separate nodes so we can mark one as 1032 * only visible to the secure world. 1033 */ 1034 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1035 qemu_fdt_add_subnode(vms->fdt, nodename); 1036 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 1037 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1038 2, flashbase, 2, flashsize); 1039 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 1040 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1041 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1042 g_free(nodename); 1043 1044 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1045 qemu_fdt_add_subnode(vms->fdt, nodename); 1046 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); 1047 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1048 2, flashbase + flashsize, 2, flashsize); 1049 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); 1050 g_free(nodename); 1051 } 1052 } 1053 1054 static bool virt_firmware_init(VirtMachineState *vms, 1055 MemoryRegion *sysmem, 1056 MemoryRegion *secure_sysmem) 1057 { 1058 int i; 1059 BlockBackend *pflash_blk0; 1060 1061 /* Map legacy -drive if=pflash to machine properties */ 1062 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1063 pflash_cfi01_legacy_drive(vms->flash[i], 1064 drive_get(IF_PFLASH, 0, i)); 1065 } 1066 1067 virt_flash_map(vms, sysmem, secure_sysmem); 1068 1069 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1070 1071 if (bios_name) { 1072 char *fname; 1073 MemoryRegion *mr; 1074 int image_size; 1075 1076 if (pflash_blk0) { 1077 error_report("The contents of the first flash device may be " 1078 "specified with -bios or with -drive if=pflash... " 1079 "but you cannot use both options at once"); 1080 exit(1); 1081 } 1082 1083 /* Fall back to -bios */ 1084 1085 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1086 if (!fname) { 1087 error_report("Could not find ROM image '%s'", bios_name); 1088 exit(1); 1089 } 1090 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1091 image_size = load_image_mr(fname, mr); 1092 g_free(fname); 1093 if (image_size < 0) { 1094 error_report("Could not load ROM image '%s'", bios_name); 1095 exit(1); 1096 } 1097 } 1098 1099 return pflash_blk0 || bios_name; 1100 } 1101 1102 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1103 { 1104 MachineState *ms = MACHINE(vms); 1105 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1106 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1107 FWCfgState *fw_cfg; 1108 char *nodename; 1109 1110 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1111 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1112 1113 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1114 qemu_fdt_add_subnode(vms->fdt, nodename); 1115 qemu_fdt_setprop_string(vms->fdt, nodename, 1116 "compatible", "qemu,fw-cfg-mmio"); 1117 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1118 2, base, 2, size); 1119 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1120 g_free(nodename); 1121 return fw_cfg; 1122 } 1123 1124 static void create_pcie_irq_map(const VirtMachineState *vms, 1125 uint32_t gic_phandle, 1126 int first_irq, const char *nodename) 1127 { 1128 int devfn, pin; 1129 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1130 uint32_t *irq_map = full_irq_map; 1131 1132 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1133 for (pin = 0; pin < 4; pin++) { 1134 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1135 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1136 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1137 int i; 1138 1139 uint32_t map[] = { 1140 devfn << 8, 0, 0, /* devfn */ 1141 pin + 1, /* PCI pin */ 1142 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1143 1144 /* Convert map to big endian */ 1145 for (i = 0; i < 10; i++) { 1146 irq_map[i] = cpu_to_be32(map[i]); 1147 } 1148 irq_map += 10; 1149 } 1150 } 1151 1152 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map", 1153 full_irq_map, sizeof(full_irq_map)); 1154 1155 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask", 1156 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 1157 0x7 /* PCI irq */); 1158 } 1159 1160 static void create_smmu(const VirtMachineState *vms, 1161 PCIBus *bus) 1162 { 1163 char *node; 1164 const char compat[] = "arm,smmu-v3"; 1165 int irq = vms->irqmap[VIRT_SMMU]; 1166 int i; 1167 hwaddr base = vms->memmap[VIRT_SMMU].base; 1168 hwaddr size = vms->memmap[VIRT_SMMU].size; 1169 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1170 DeviceState *dev; 1171 1172 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1173 return; 1174 } 1175 1176 dev = qdev_new("arm-smmuv3"); 1177 1178 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", 1179 &error_abort); 1180 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1181 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1182 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1183 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1184 qdev_get_gpio_in(vms->gic, irq + i)); 1185 } 1186 1187 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1188 qemu_fdt_add_subnode(vms->fdt, node); 1189 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat)); 1190 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size); 1191 1192 qemu_fdt_setprop_cells(vms->fdt, node, "interrupts", 1193 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1194 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1195 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1196 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1197 1198 qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names, 1199 sizeof(irq_names)); 1200 1201 qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle); 1202 qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk"); 1203 qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0); 1204 1205 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1); 1206 1207 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle); 1208 g_free(node); 1209 } 1210 1211 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1212 { 1213 const char compat[] = "virtio,pci-iommu"; 1214 uint16_t bdf = vms->virtio_iommu_bdf; 1215 char *node; 1216 1217 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt); 1218 1219 node = g_strdup_printf("%s/virtio_iommu@%d", vms->pciehb_nodename, bdf); 1220 qemu_fdt_add_subnode(vms->fdt, node); 1221 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat)); 1222 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 1223 1, bdf << 8, 1, 0, 1, 0, 1224 1, 0, 1, 0); 1225 1226 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1); 1227 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle); 1228 g_free(node); 1229 1230 qemu_fdt_setprop_cells(vms->fdt, vms->pciehb_nodename, "iommu-map", 1231 0x0, vms->iommu_phandle, 0x0, bdf, 1232 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1233 } 1234 1235 static void create_pcie(VirtMachineState *vms) 1236 { 1237 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1238 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1239 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1240 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1241 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1242 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1243 hwaddr base_ecam, size_ecam; 1244 hwaddr base = base_mmio; 1245 int nr_pcie_buses; 1246 int irq = vms->irqmap[VIRT_PCIE]; 1247 MemoryRegion *mmio_alias; 1248 MemoryRegion *mmio_reg; 1249 MemoryRegion *ecam_alias; 1250 MemoryRegion *ecam_reg; 1251 DeviceState *dev; 1252 char *nodename; 1253 int i, ecam_id; 1254 PCIHostState *pci; 1255 1256 dev = qdev_new(TYPE_GPEX_HOST); 1257 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1258 1259 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1260 base_ecam = vms->memmap[ecam_id].base; 1261 size_ecam = vms->memmap[ecam_id].size; 1262 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1263 /* Map only the first size_ecam bytes of ECAM space */ 1264 ecam_alias = g_new0(MemoryRegion, 1); 1265 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1266 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1267 ecam_reg, 0, size_ecam); 1268 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1269 1270 /* Map the MMIO window into system address space so as to expose 1271 * the section of PCI MMIO space which starts at the same base address 1272 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1273 * the window). 1274 */ 1275 mmio_alias = g_new0(MemoryRegion, 1); 1276 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1277 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1278 mmio_reg, base_mmio, size_mmio); 1279 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1280 1281 if (vms->highmem) { 1282 /* Map high MMIO space */ 1283 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1284 1285 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1286 mmio_reg, base_mmio_high, size_mmio_high); 1287 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1288 high_mmio_alias); 1289 } 1290 1291 /* Map IO port space */ 1292 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1293 1294 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1295 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1296 qdev_get_gpio_in(vms->gic, irq + i)); 1297 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1298 } 1299 1300 pci = PCI_HOST_BRIDGE(dev); 1301 if (pci->bus) { 1302 for (i = 0; i < nb_nics; i++) { 1303 NICInfo *nd = &nd_table[i]; 1304 1305 if (!nd->model) { 1306 nd->model = g_strdup("virtio"); 1307 } 1308 1309 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1310 } 1311 } 1312 1313 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1314 qemu_fdt_add_subnode(vms->fdt, nodename); 1315 qemu_fdt_setprop_string(vms->fdt, nodename, 1316 "compatible", "pci-host-ecam-generic"); 1317 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci"); 1318 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3); 1319 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2); 1320 qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0); 1321 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0, 1322 nr_pcie_buses - 1); 1323 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); 1324 1325 if (vms->msi_phandle) { 1326 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", 1327 vms->msi_phandle); 1328 } 1329 1330 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 1331 2, base_ecam, 2, size_ecam); 1332 1333 if (vms->highmem) { 1334 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1335 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1336 2, base_pio, 2, size_pio, 1337 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1338 2, base_mmio, 2, size_mmio, 1339 1, FDT_PCI_RANGE_MMIO_64BIT, 1340 2, base_mmio_high, 1341 2, base_mmio_high, 2, size_mmio_high); 1342 } else { 1343 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", 1344 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1345 2, base_pio, 2, size_pio, 1346 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1347 2, base_mmio, 2, size_mmio); 1348 } 1349 1350 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); 1351 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); 1352 1353 if (vms->iommu) { 1354 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt); 1355 1356 switch (vms->iommu) { 1357 case VIRT_IOMMU_SMMUV3: 1358 create_smmu(vms, pci->bus); 1359 qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map", 1360 0x0, vms->iommu_phandle, 0x0, 0x10000); 1361 break; 1362 default: 1363 g_assert_not_reached(); 1364 } 1365 } 1366 } 1367 1368 static void create_platform_bus(VirtMachineState *vms) 1369 { 1370 DeviceState *dev; 1371 SysBusDevice *s; 1372 int i; 1373 MemoryRegion *sysmem = get_system_memory(); 1374 1375 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1376 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1377 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1378 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1379 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1380 vms->platform_bus_dev = dev; 1381 1382 s = SYS_BUS_DEVICE(dev); 1383 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1384 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1385 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1386 } 1387 1388 memory_region_add_subregion(sysmem, 1389 vms->memmap[VIRT_PLATFORM_BUS].base, 1390 sysbus_mmio_get_region(s, 0)); 1391 } 1392 1393 static void create_secure_ram(VirtMachineState *vms, 1394 MemoryRegion *secure_sysmem) 1395 { 1396 MemoryRegion *secram = g_new(MemoryRegion, 1); 1397 char *nodename; 1398 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1399 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1400 1401 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1402 &error_fatal); 1403 memory_region_add_subregion(secure_sysmem, base, secram); 1404 1405 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1406 qemu_fdt_add_subnode(vms->fdt, nodename); 1407 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory"); 1408 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size); 1409 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); 1410 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); 1411 1412 g_free(nodename); 1413 } 1414 1415 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1416 { 1417 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1418 bootinfo); 1419 1420 *fdt_size = board->fdt_size; 1421 return board->fdt; 1422 } 1423 1424 static void virt_build_smbios(VirtMachineState *vms) 1425 { 1426 MachineClass *mc = MACHINE_GET_CLASS(vms); 1427 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1428 uint8_t *smbios_tables, *smbios_anchor; 1429 size_t smbios_tables_len, smbios_anchor_len; 1430 const char *product = "QEMU Virtual Machine"; 1431 1432 if (kvm_enabled()) { 1433 product = "KVM Virtual Machine"; 1434 } 1435 1436 smbios_set_defaults("QEMU", product, 1437 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1438 true, SMBIOS_ENTRY_POINT_30); 1439 1440 smbios_get_tables(MACHINE(vms), NULL, 0, &smbios_tables, &smbios_tables_len, 1441 &smbios_anchor, &smbios_anchor_len); 1442 1443 if (smbios_anchor) { 1444 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1445 smbios_tables, smbios_tables_len); 1446 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1447 smbios_anchor, smbios_anchor_len); 1448 } 1449 } 1450 1451 static 1452 void virt_machine_done(Notifier *notifier, void *data) 1453 { 1454 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1455 machine_done); 1456 MachineState *ms = MACHINE(vms); 1457 ARMCPU *cpu = ARM_CPU(first_cpu); 1458 struct arm_boot_info *info = &vms->bootinfo; 1459 AddressSpace *as = arm_boot_address_space(cpu, info); 1460 1461 /* 1462 * If the user provided a dtb, we assume the dynamic sysbus nodes 1463 * already are integrated there. This corresponds to a use case where 1464 * the dynamic sysbus nodes are complex and their generation is not yet 1465 * supported. In that case the user can take charge of the guest dt 1466 * while qemu takes charge of the qom stuff. 1467 */ 1468 if (info->dtb_filename == NULL) { 1469 platform_bus_add_all_fdt_nodes(vms->fdt, "/intc", 1470 vms->memmap[VIRT_PLATFORM_BUS].base, 1471 vms->memmap[VIRT_PLATFORM_BUS].size, 1472 vms->irqmap[VIRT_PLATFORM_BUS]); 1473 } 1474 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1475 exit(1); 1476 } 1477 1478 virt_acpi_setup(vms); 1479 virt_build_smbios(vms); 1480 } 1481 1482 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1483 { 1484 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1485 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1486 1487 if (!vmc->disallow_affinity_adjustment) { 1488 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1489 * GIC's target-list limitations. 32-bit KVM hosts currently 1490 * always create clusters of 4 CPUs, but that is expected to 1491 * change when they gain support for gicv3. When KVM is enabled 1492 * it will override the changes we make here, therefore our 1493 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1494 * and to improve SGI efficiency. 1495 */ 1496 if (vms->gic_version == VIRT_GIC_VERSION_3) { 1497 clustersz = GICV3_TARGETLIST_BITS; 1498 } else { 1499 clustersz = GIC_TARGETLIST_BITS; 1500 } 1501 } 1502 return arm_cpu_mp_affinity(idx, clustersz); 1503 } 1504 1505 static void virt_set_memmap(VirtMachineState *vms) 1506 { 1507 MachineState *ms = MACHINE(vms); 1508 hwaddr base, device_memory_base, device_memory_size; 1509 int i; 1510 1511 vms->memmap = extended_memmap; 1512 1513 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1514 vms->memmap[i] = base_memmap[i]; 1515 } 1516 1517 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1518 error_report("unsupported number of memory slots: %"PRIu64, 1519 ms->ram_slots); 1520 exit(EXIT_FAILURE); 1521 } 1522 1523 /* 1524 * We compute the base of the high IO region depending on the 1525 * amount of initial and device memory. The device memory start/size 1526 * is aligned on 1GiB. We never put the high IO region below 256GiB 1527 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1528 * The device region size assumes 1GiB page max alignment per slot. 1529 */ 1530 device_memory_base = 1531 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1532 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1533 1534 /* Base address of the high IO region */ 1535 base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1536 if (base < device_memory_base) { 1537 error_report("maxmem/slots too huge"); 1538 exit(EXIT_FAILURE); 1539 } 1540 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1541 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1542 } 1543 1544 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1545 hwaddr size = extended_memmap[i].size; 1546 1547 base = ROUND_UP(base, size); 1548 vms->memmap[i].base = base; 1549 vms->memmap[i].size = size; 1550 base += size; 1551 } 1552 vms->highest_gpa = base - 1; 1553 if (device_memory_size > 0) { 1554 ms->device_memory = g_malloc0(sizeof(*ms->device_memory)); 1555 ms->device_memory->base = device_memory_base; 1556 memory_region_init(&ms->device_memory->mr, OBJECT(vms), 1557 "device-memory", device_memory_size); 1558 } 1559 } 1560 1561 /* 1562 * finalize_gic_version - Determines the final gic_version 1563 * according to the gic-version property 1564 * 1565 * Default GIC type is v2 1566 */ 1567 static void finalize_gic_version(VirtMachineState *vms) 1568 { 1569 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 1570 1571 if (kvm_enabled()) { 1572 int probe_bitmap; 1573 1574 if (!kvm_irqchip_in_kernel()) { 1575 switch (vms->gic_version) { 1576 case VIRT_GIC_VERSION_HOST: 1577 warn_report( 1578 "gic-version=host not relevant with kernel-irqchip=off " 1579 "as only userspace GICv2 is supported. Using v2 ..."); 1580 return; 1581 case VIRT_GIC_VERSION_MAX: 1582 case VIRT_GIC_VERSION_NOSEL: 1583 vms->gic_version = VIRT_GIC_VERSION_2; 1584 return; 1585 case VIRT_GIC_VERSION_2: 1586 return; 1587 case VIRT_GIC_VERSION_3: 1588 error_report( 1589 "gic-version=3 is not supported with kernel-irqchip=off"); 1590 exit(1); 1591 } 1592 } 1593 1594 probe_bitmap = kvm_arm_vgic_probe(); 1595 if (!probe_bitmap) { 1596 error_report("Unable to determine GIC version supported by host"); 1597 exit(1); 1598 } 1599 1600 switch (vms->gic_version) { 1601 case VIRT_GIC_VERSION_HOST: 1602 case VIRT_GIC_VERSION_MAX: 1603 if (probe_bitmap & KVM_ARM_VGIC_V3) { 1604 vms->gic_version = VIRT_GIC_VERSION_3; 1605 } else { 1606 vms->gic_version = VIRT_GIC_VERSION_2; 1607 } 1608 return; 1609 case VIRT_GIC_VERSION_NOSEL: 1610 if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) { 1611 vms->gic_version = VIRT_GIC_VERSION_2; 1612 } else if (probe_bitmap & KVM_ARM_VGIC_V3) { 1613 /* 1614 * in case the host does not support v2 in-kernel emulation or 1615 * the end-user requested more than 8 VCPUs we now default 1616 * to v3. In any case defaulting to v2 would be broken. 1617 */ 1618 vms->gic_version = VIRT_GIC_VERSION_3; 1619 } else if (max_cpus > GIC_NCPU) { 1620 error_report("host only supports in-kernel GICv2 emulation " 1621 "but more than 8 vcpus are requested"); 1622 exit(1); 1623 } 1624 break; 1625 case VIRT_GIC_VERSION_2: 1626 case VIRT_GIC_VERSION_3: 1627 break; 1628 } 1629 1630 /* Check chosen version is effectively supported by the host */ 1631 if (vms->gic_version == VIRT_GIC_VERSION_2 && 1632 !(probe_bitmap & KVM_ARM_VGIC_V2)) { 1633 error_report("host does not support in-kernel GICv2 emulation"); 1634 exit(1); 1635 } else if (vms->gic_version == VIRT_GIC_VERSION_3 && 1636 !(probe_bitmap & KVM_ARM_VGIC_V3)) { 1637 error_report("host does not support in-kernel GICv3 emulation"); 1638 exit(1); 1639 } 1640 return; 1641 } 1642 1643 /* TCG mode */ 1644 switch (vms->gic_version) { 1645 case VIRT_GIC_VERSION_NOSEL: 1646 vms->gic_version = VIRT_GIC_VERSION_2; 1647 break; 1648 case VIRT_GIC_VERSION_MAX: 1649 vms->gic_version = VIRT_GIC_VERSION_3; 1650 break; 1651 case VIRT_GIC_VERSION_HOST: 1652 error_report("gic-version=host requires KVM"); 1653 exit(1); 1654 case VIRT_GIC_VERSION_2: 1655 case VIRT_GIC_VERSION_3: 1656 break; 1657 } 1658 } 1659 1660 static void machvirt_init(MachineState *machine) 1661 { 1662 VirtMachineState *vms = VIRT_MACHINE(machine); 1663 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1664 MachineClass *mc = MACHINE_GET_CLASS(machine); 1665 const CPUArchIdList *possible_cpus; 1666 MemoryRegion *sysmem = get_system_memory(); 1667 MemoryRegion *secure_sysmem = NULL; 1668 int n, virt_max_cpus; 1669 bool firmware_loaded; 1670 bool aarch64 = true; 1671 bool has_ged = !vmc->no_ged; 1672 unsigned int smp_cpus = machine->smp.cpus; 1673 unsigned int max_cpus = machine->smp.max_cpus; 1674 1675 /* 1676 * In accelerated mode, the memory map is computed earlier in kvm_type() 1677 * to create a VM with the right number of IPA bits. 1678 */ 1679 if (!vms->memmap) { 1680 virt_set_memmap(vms); 1681 } 1682 1683 /* We can probe only here because during property set 1684 * KVM is not available yet 1685 */ 1686 finalize_gic_version(vms); 1687 1688 if (!cpu_type_valid(machine->cpu_type)) { 1689 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 1690 exit(1); 1691 } 1692 1693 if (vms->secure) { 1694 if (kvm_enabled()) { 1695 error_report("mach-virt: KVM does not support Security extensions"); 1696 exit(1); 1697 } 1698 1699 /* 1700 * The Secure view of the world is the same as the NonSecure, 1701 * but with a few extra devices. Create it as a container region 1702 * containing the system memory at low priority; any secure-only 1703 * devices go in at higher priority and take precedence. 1704 */ 1705 secure_sysmem = g_new(MemoryRegion, 1); 1706 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1707 UINT64_MAX); 1708 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1709 } 1710 1711 firmware_loaded = virt_firmware_init(vms, sysmem, 1712 secure_sysmem ?: sysmem); 1713 1714 /* If we have an EL3 boot ROM then the assumption is that it will 1715 * implement PSCI itself, so disable QEMU's internal implementation 1716 * so it doesn't get in the way. Instead of starting secondary 1717 * CPUs in PSCI powerdown state we will start them all running and 1718 * let the boot ROM sort them out. 1719 * The usual case is that we do use QEMU's PSCI implementation; 1720 * if the guest has EL2 then we will use SMC as the conduit, 1721 * and otherwise we will use HVC (for backwards compatibility and 1722 * because if we're using KVM then we must use HVC). 1723 */ 1724 if (vms->secure && firmware_loaded) { 1725 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1726 } else if (vms->virt) { 1727 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 1728 } else { 1729 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 1730 } 1731 1732 /* The maximum number of CPUs depends on the GIC version, or on how 1733 * many redistributors we can fit into the memory map. 1734 */ 1735 if (vms->gic_version == VIRT_GIC_VERSION_3) { 1736 virt_max_cpus = 1737 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 1738 virt_max_cpus += 1739 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; 1740 } else { 1741 virt_max_cpus = GIC_NCPU; 1742 } 1743 1744 if (max_cpus > virt_max_cpus) { 1745 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1746 "supported by machine 'mach-virt' (%d)", 1747 max_cpus, virt_max_cpus); 1748 exit(1); 1749 } 1750 1751 vms->smp_cpus = smp_cpus; 1752 1753 if (vms->virt && kvm_enabled()) { 1754 error_report("mach-virt: KVM does not support providing " 1755 "Virtualization extensions to the guest CPU"); 1756 exit(1); 1757 } 1758 1759 create_fdt(vms); 1760 1761 possible_cpus = mc->possible_cpu_arch_ids(machine); 1762 for (n = 0; n < possible_cpus->len; n++) { 1763 Object *cpuobj; 1764 CPUState *cs; 1765 1766 if (n >= smp_cpus) { 1767 break; 1768 } 1769 1770 cpuobj = object_new(possible_cpus->cpus[n].type); 1771 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 1772 "mp-affinity", NULL); 1773 1774 cs = CPU(cpuobj); 1775 cs->cpu_index = n; 1776 1777 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 1778 &error_fatal); 1779 1780 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 1781 1782 if (!vms->secure) { 1783 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1784 } 1785 1786 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { 1787 object_property_set_bool(cpuobj, false, "has_el2", NULL); 1788 } 1789 1790 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1791 object_property_set_int(cpuobj, vms->psci_conduit, 1792 "psci-conduit", NULL); 1793 1794 /* Secondary CPUs start in PSCI powered-down state */ 1795 if (n > 0) { 1796 object_property_set_bool(cpuobj, true, 1797 "start-powered-off", NULL); 1798 } 1799 } 1800 1801 if (vmc->kvm_no_adjvtime && 1802 object_property_find(cpuobj, "kvm-no-adjvtime", NULL)) { 1803 object_property_set_bool(cpuobj, true, "kvm-no-adjvtime", NULL); 1804 } 1805 1806 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { 1807 object_property_set_bool(cpuobj, false, "pmu", NULL); 1808 } 1809 1810 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1811 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, 1812 "reset-cbar", &error_abort); 1813 } 1814 1815 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1816 &error_abort); 1817 if (vms->secure) { 1818 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1819 "secure-memory", &error_abort); 1820 } 1821 1822 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 1823 object_unref(cpuobj); 1824 } 1825 fdt_add_timer_nodes(vms); 1826 fdt_add_cpu_nodes(vms); 1827 1828 if (!kvm_enabled()) { 1829 ARMCPU *cpu = ARM_CPU(first_cpu); 1830 bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL); 1831 1832 if (aarch64 && vms->highmem) { 1833 int requested_pa_size, pamax = arm_pamax(cpu); 1834 1835 requested_pa_size = 64 - clz64(vms->highest_gpa); 1836 if (pamax < requested_pa_size) { 1837 error_report("VCPU supports less PA bits (%d) than requested " 1838 "by the memory map (%d)", pamax, requested_pa_size); 1839 exit(1); 1840 } 1841 } 1842 } 1843 1844 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 1845 machine->ram); 1846 if (machine->device_memory) { 1847 memory_region_add_subregion(sysmem, machine->device_memory->base, 1848 &machine->device_memory->mr); 1849 } 1850 1851 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 1852 1853 create_gic(vms); 1854 1855 fdt_add_pmu_nodes(vms); 1856 1857 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 1858 1859 if (vms->secure) { 1860 create_secure_ram(vms, secure_sysmem); 1861 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 1862 } 1863 1864 vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64); 1865 1866 create_rtc(vms); 1867 1868 create_pcie(vms); 1869 1870 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 1871 vms->acpi_dev = create_acpi_ged(vms); 1872 } else { 1873 create_gpio(vms); 1874 } 1875 1876 /* connect powerdown request */ 1877 vms->powerdown_notifier.notify = virt_powerdown_req; 1878 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 1879 1880 /* Create mmio transports, so the user can create virtio backends 1881 * (which will be automatically plugged in to the transports). If 1882 * no backend is created the transport will just sit harmlessly idle. 1883 */ 1884 create_virtio_devices(vms); 1885 1886 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 1887 rom_set_fw(vms->fw_cfg); 1888 1889 create_platform_bus(vms); 1890 1891 if (machine->nvdimms_state->is_enabled) { 1892 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 1893 .space_id = AML_AS_SYSTEM_MEMORY, 1894 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 1895 .bit_width = NVDIMM_ACPI_IO_LEN << 3 1896 }; 1897 1898 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 1899 arm_virt_nvdimm_acpi_dsmio, 1900 vms->fw_cfg, OBJECT(vms)); 1901 } 1902 1903 vms->bootinfo.ram_size = machine->ram_size; 1904 vms->bootinfo.nb_cpus = smp_cpus; 1905 vms->bootinfo.board_id = -1; 1906 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 1907 vms->bootinfo.get_dtb = machvirt_dtb; 1908 vms->bootinfo.skip_dtb_autoload = true; 1909 vms->bootinfo.firmware_loaded = firmware_loaded; 1910 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 1911 1912 vms->machine_done.notify = virt_machine_done; 1913 qemu_add_machine_init_done_notifier(&vms->machine_done); 1914 } 1915 1916 static bool virt_get_secure(Object *obj, Error **errp) 1917 { 1918 VirtMachineState *vms = VIRT_MACHINE(obj); 1919 1920 return vms->secure; 1921 } 1922 1923 static void virt_set_secure(Object *obj, bool value, Error **errp) 1924 { 1925 VirtMachineState *vms = VIRT_MACHINE(obj); 1926 1927 vms->secure = value; 1928 } 1929 1930 static bool virt_get_virt(Object *obj, Error **errp) 1931 { 1932 VirtMachineState *vms = VIRT_MACHINE(obj); 1933 1934 return vms->virt; 1935 } 1936 1937 static void virt_set_virt(Object *obj, bool value, Error **errp) 1938 { 1939 VirtMachineState *vms = VIRT_MACHINE(obj); 1940 1941 vms->virt = value; 1942 } 1943 1944 static bool virt_get_highmem(Object *obj, Error **errp) 1945 { 1946 VirtMachineState *vms = VIRT_MACHINE(obj); 1947 1948 return vms->highmem; 1949 } 1950 1951 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1952 { 1953 VirtMachineState *vms = VIRT_MACHINE(obj); 1954 1955 vms->highmem = value; 1956 } 1957 1958 static bool virt_get_its(Object *obj, Error **errp) 1959 { 1960 VirtMachineState *vms = VIRT_MACHINE(obj); 1961 1962 return vms->its; 1963 } 1964 1965 static void virt_set_its(Object *obj, bool value, Error **errp) 1966 { 1967 VirtMachineState *vms = VIRT_MACHINE(obj); 1968 1969 vms->its = value; 1970 } 1971 1972 bool virt_is_acpi_enabled(VirtMachineState *vms) 1973 { 1974 if (vms->acpi == ON_OFF_AUTO_OFF) { 1975 return false; 1976 } 1977 return true; 1978 } 1979 1980 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1981 void *opaque, Error **errp) 1982 { 1983 VirtMachineState *vms = VIRT_MACHINE(obj); 1984 OnOffAuto acpi = vms->acpi; 1985 1986 visit_type_OnOffAuto(v, name, &acpi, errp); 1987 } 1988 1989 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1990 void *opaque, Error **errp) 1991 { 1992 VirtMachineState *vms = VIRT_MACHINE(obj); 1993 1994 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 1995 } 1996 1997 static bool virt_get_ras(Object *obj, Error **errp) 1998 { 1999 VirtMachineState *vms = VIRT_MACHINE(obj); 2000 2001 return vms->ras; 2002 } 2003 2004 static void virt_set_ras(Object *obj, bool value, Error **errp) 2005 { 2006 VirtMachineState *vms = VIRT_MACHINE(obj); 2007 2008 vms->ras = value; 2009 } 2010 2011 static char *virt_get_gic_version(Object *obj, Error **errp) 2012 { 2013 VirtMachineState *vms = VIRT_MACHINE(obj); 2014 const char *val = vms->gic_version == VIRT_GIC_VERSION_3 ? "3" : "2"; 2015 2016 return g_strdup(val); 2017 } 2018 2019 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2020 { 2021 VirtMachineState *vms = VIRT_MACHINE(obj); 2022 2023 if (!strcmp(value, "3")) { 2024 vms->gic_version = VIRT_GIC_VERSION_3; 2025 } else if (!strcmp(value, "2")) { 2026 vms->gic_version = VIRT_GIC_VERSION_2; 2027 } else if (!strcmp(value, "host")) { 2028 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2029 } else if (!strcmp(value, "max")) { 2030 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2031 } else { 2032 error_setg(errp, "Invalid gic-version value"); 2033 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2034 } 2035 } 2036 2037 static char *virt_get_iommu(Object *obj, Error **errp) 2038 { 2039 VirtMachineState *vms = VIRT_MACHINE(obj); 2040 2041 switch (vms->iommu) { 2042 case VIRT_IOMMU_NONE: 2043 return g_strdup("none"); 2044 case VIRT_IOMMU_SMMUV3: 2045 return g_strdup("smmuv3"); 2046 default: 2047 g_assert_not_reached(); 2048 } 2049 } 2050 2051 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2052 { 2053 VirtMachineState *vms = VIRT_MACHINE(obj); 2054 2055 if (!strcmp(value, "smmuv3")) { 2056 vms->iommu = VIRT_IOMMU_SMMUV3; 2057 } else if (!strcmp(value, "none")) { 2058 vms->iommu = VIRT_IOMMU_NONE; 2059 } else { 2060 error_setg(errp, "Invalid iommu value"); 2061 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2062 } 2063 } 2064 2065 static CpuInstanceProperties 2066 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2067 { 2068 MachineClass *mc = MACHINE_GET_CLASS(ms); 2069 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2070 2071 assert(cpu_index < possible_cpus->len); 2072 return possible_cpus->cpus[cpu_index].props; 2073 } 2074 2075 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2076 { 2077 return idx % ms->numa_state->num_nodes; 2078 } 2079 2080 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2081 { 2082 int n; 2083 unsigned int max_cpus = ms->smp.max_cpus; 2084 VirtMachineState *vms = VIRT_MACHINE(ms); 2085 2086 if (ms->possible_cpus) { 2087 assert(ms->possible_cpus->len == max_cpus); 2088 return ms->possible_cpus; 2089 } 2090 2091 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2092 sizeof(CPUArchId) * max_cpus); 2093 ms->possible_cpus->len = max_cpus; 2094 for (n = 0; n < ms->possible_cpus->len; n++) { 2095 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2096 ms->possible_cpus->cpus[n].arch_id = 2097 virt_cpu_mp_affinity(vms, n); 2098 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2099 ms->possible_cpus->cpus[n].props.thread_id = n; 2100 } 2101 return ms->possible_cpus; 2102 } 2103 2104 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2105 Error **errp) 2106 { 2107 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2108 const MachineState *ms = MACHINE(hotplug_dev); 2109 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2110 2111 if (!vms->acpi_dev) { 2112 error_setg(errp, 2113 "memory hotplug is not enabled: missing acpi-ged device"); 2114 return; 2115 } 2116 2117 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2118 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2119 return; 2120 } 2121 2122 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 2123 } 2124 2125 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2126 DeviceState *dev, Error **errp) 2127 { 2128 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2129 MachineState *ms = MACHINE(hotplug_dev); 2130 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2131 Error *local_err = NULL; 2132 2133 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms), &local_err); 2134 if (local_err) { 2135 goto out; 2136 } 2137 2138 if (is_nvdimm) { 2139 nvdimm_plug(ms->nvdimms_state); 2140 } 2141 2142 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2143 dev, &error_abort); 2144 2145 out: 2146 error_propagate(errp, local_err); 2147 } 2148 2149 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2150 DeviceState *dev, Error **errp) 2151 { 2152 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2153 virt_memory_pre_plug(hotplug_dev, dev, errp); 2154 } 2155 } 2156 2157 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2158 DeviceState *dev, Error **errp) 2159 { 2160 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2161 2162 if (vms->platform_bus_dev) { 2163 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) { 2164 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2165 SYS_BUS_DEVICE(dev)); 2166 } 2167 } 2168 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2169 virt_memory_plug(hotplug_dev, dev, errp); 2170 } 2171 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2172 PCIDevice *pdev = PCI_DEVICE(dev); 2173 2174 vms->iommu = VIRT_IOMMU_VIRTIO; 2175 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2176 create_virtio_iommu_dt_bindings(vms); 2177 } 2178 } 2179 2180 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2181 DeviceState *dev, Error **errp) 2182 { 2183 error_setg(errp, "device unplug request for unsupported device" 2184 " type: %s", object_get_typename(OBJECT(dev))); 2185 } 2186 2187 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2188 DeviceState *dev) 2189 { 2190 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE) || 2191 (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) { 2192 return HOTPLUG_HANDLER(machine); 2193 } 2194 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2195 VirtMachineState *vms = VIRT_MACHINE(machine); 2196 2197 if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) { 2198 return HOTPLUG_HANDLER(machine); 2199 } 2200 } 2201 return NULL; 2202 } 2203 2204 /* 2205 * for arm64 kvm_type [7-0] encodes the requested number of bits 2206 * in the IPA address space 2207 */ 2208 static int virt_kvm_type(MachineState *ms, const char *type_str) 2209 { 2210 VirtMachineState *vms = VIRT_MACHINE(ms); 2211 int max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms); 2212 int requested_pa_size; 2213 2214 /* we freeze the memory map to compute the highest gpa */ 2215 virt_set_memmap(vms); 2216 2217 requested_pa_size = 64 - clz64(vms->highest_gpa); 2218 2219 if (requested_pa_size > max_vm_pa_size) { 2220 error_report("-m and ,maxmem option values " 2221 "require an IPA range (%d bits) larger than " 2222 "the one supported by the host (%d bits)", 2223 requested_pa_size, max_vm_pa_size); 2224 exit(1); 2225 } 2226 /* 2227 * By default we return 0 which corresponds to an implicit legacy 2228 * 40b IPA setting. Otherwise we return the actual requested PA 2229 * logsize 2230 */ 2231 return requested_pa_size > 40 ? requested_pa_size : 0; 2232 } 2233 2234 static void virt_machine_class_init(ObjectClass *oc, void *data) 2235 { 2236 MachineClass *mc = MACHINE_CLASS(oc); 2237 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2238 2239 mc->init = machvirt_init; 2240 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 2241 * The value may be reduced later when we have more information about the 2242 * configuration of the particular instance. 2243 */ 2244 mc->max_cpus = 512; 2245 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 2246 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 2247 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 2248 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 2249 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 2250 mc->block_default_type = IF_VIRTIO; 2251 mc->no_cdrom = 1; 2252 mc->pci_allow_0_address = true; 2253 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 2254 mc->minimum_page_bits = 12; 2255 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 2256 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 2257 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 2258 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 2259 mc->kvm_type = virt_kvm_type; 2260 assert(!mc->get_hotplug_handler); 2261 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 2262 hc->pre_plug = virt_machine_device_pre_plug_cb; 2263 hc->plug = virt_machine_device_plug_cb; 2264 hc->unplug_request = virt_machine_device_unplug_request_cb; 2265 mc->numa_mem_supported = true; 2266 mc->nvdimm_supported = true; 2267 mc->auto_enable_numa_with_memhp = true; 2268 mc->default_ram_id = "mach-virt.ram"; 2269 2270 object_class_property_add(oc, "acpi", "OnOffAuto", 2271 virt_get_acpi, virt_set_acpi, 2272 NULL, NULL); 2273 object_class_property_set_description(oc, "acpi", 2274 "Enable ACPI"); 2275 } 2276 2277 static void virt_instance_init(Object *obj) 2278 { 2279 VirtMachineState *vms = VIRT_MACHINE(obj); 2280 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 2281 2282 /* EL3 is disabled by default on virt: this makes us consistent 2283 * between KVM and TCG for this board, and it also allows us to 2284 * boot UEFI blobs which assume no TrustZone support. 2285 */ 2286 vms->secure = false; 2287 object_property_add_bool(obj, "secure", virt_get_secure, 2288 virt_set_secure); 2289 object_property_set_description(obj, "secure", 2290 "Set on/off to enable/disable the ARM " 2291 "Security Extensions (TrustZone)"); 2292 2293 /* EL2 is also disabled by default, for similar reasons */ 2294 vms->virt = false; 2295 object_property_add_bool(obj, "virtualization", virt_get_virt, 2296 virt_set_virt); 2297 object_property_set_description(obj, "virtualization", 2298 "Set on/off to enable/disable emulating a " 2299 "guest CPU which implements the ARM " 2300 "Virtualization Extensions"); 2301 2302 /* High memory is enabled by default */ 2303 vms->highmem = true; 2304 object_property_add_bool(obj, "highmem", virt_get_highmem, 2305 virt_set_highmem); 2306 object_property_set_description(obj, "highmem", 2307 "Set on/off to enable/disable using " 2308 "physical address space above 32 bits"); 2309 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 2310 object_property_add_str(obj, "gic-version", virt_get_gic_version, 2311 virt_set_gic_version); 2312 object_property_set_description(obj, "gic-version", 2313 "Set GIC version. " 2314 "Valid values are 2, 3, host and max"); 2315 2316 vms->highmem_ecam = !vmc->no_highmem_ecam; 2317 2318 if (vmc->no_its) { 2319 vms->its = false; 2320 } else { 2321 /* Default allows ITS instantiation */ 2322 vms->its = true; 2323 object_property_add_bool(obj, "its", virt_get_its, 2324 virt_set_its); 2325 object_property_set_description(obj, "its", 2326 "Set on/off to enable/disable " 2327 "ITS instantiation"); 2328 } 2329 2330 /* Default disallows iommu instantiation */ 2331 vms->iommu = VIRT_IOMMU_NONE; 2332 object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu); 2333 object_property_set_description(obj, "iommu", 2334 "Set the IOMMU type. " 2335 "Valid values are none and smmuv3"); 2336 2337 /* Default disallows RAS instantiation */ 2338 vms->ras = false; 2339 object_property_add_bool(obj, "ras", virt_get_ras, 2340 virt_set_ras); 2341 object_property_set_description(obj, "ras", 2342 "Set on/off to enable/disable reporting host memory errors " 2343 "to a KVM guest using ACPI and guest external abort exceptions"); 2344 2345 vms->irqmap = a15irqmap; 2346 2347 virt_flash_create(vms); 2348 } 2349 2350 static const TypeInfo virt_machine_info = { 2351 .name = TYPE_VIRT_MACHINE, 2352 .parent = TYPE_MACHINE, 2353 .abstract = true, 2354 .instance_size = sizeof(VirtMachineState), 2355 .class_size = sizeof(VirtMachineClass), 2356 .class_init = virt_machine_class_init, 2357 .instance_init = virt_instance_init, 2358 .interfaces = (InterfaceInfo[]) { 2359 { TYPE_HOTPLUG_HANDLER }, 2360 { } 2361 }, 2362 }; 2363 2364 static void machvirt_machine_init(void) 2365 { 2366 type_register_static(&virt_machine_info); 2367 } 2368 type_init(machvirt_machine_init); 2369 2370 static void virt_machine_5_1_options(MachineClass *mc) 2371 { 2372 } 2373 DEFINE_VIRT_MACHINE_AS_LATEST(5, 1) 2374 2375 static void virt_machine_5_0_options(MachineClass *mc) 2376 { 2377 virt_machine_5_1_options(mc); 2378 } 2379 DEFINE_VIRT_MACHINE(5, 0) 2380 2381 static void virt_machine_4_2_options(MachineClass *mc) 2382 { 2383 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2384 2385 virt_machine_5_0_options(mc); 2386 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 2387 vmc->kvm_no_adjvtime = true; 2388 } 2389 DEFINE_VIRT_MACHINE(4, 2) 2390 2391 static void virt_machine_4_1_options(MachineClass *mc) 2392 { 2393 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2394 2395 virt_machine_4_2_options(mc); 2396 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 2397 vmc->no_ged = true; 2398 mc->auto_enable_numa_with_memhp = false; 2399 } 2400 DEFINE_VIRT_MACHINE(4, 1) 2401 2402 static void virt_machine_4_0_options(MachineClass *mc) 2403 { 2404 virt_machine_4_1_options(mc); 2405 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 2406 } 2407 DEFINE_VIRT_MACHINE(4, 0) 2408 2409 static void virt_machine_3_1_options(MachineClass *mc) 2410 { 2411 virt_machine_4_0_options(mc); 2412 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 2413 } 2414 DEFINE_VIRT_MACHINE(3, 1) 2415 2416 static void virt_machine_3_0_options(MachineClass *mc) 2417 { 2418 virt_machine_3_1_options(mc); 2419 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 2420 } 2421 DEFINE_VIRT_MACHINE(3, 0) 2422 2423 static void virt_machine_2_12_options(MachineClass *mc) 2424 { 2425 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2426 2427 virt_machine_3_0_options(mc); 2428 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 2429 vmc->no_highmem_ecam = true; 2430 mc->max_cpus = 255; 2431 } 2432 DEFINE_VIRT_MACHINE(2, 12) 2433 2434 static void virt_machine_2_11_options(MachineClass *mc) 2435 { 2436 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2437 2438 virt_machine_2_12_options(mc); 2439 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 2440 vmc->smbios_old_sys_ver = true; 2441 } 2442 DEFINE_VIRT_MACHINE(2, 11) 2443 2444 static void virt_machine_2_10_options(MachineClass *mc) 2445 { 2446 virt_machine_2_11_options(mc); 2447 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 2448 /* before 2.11 we never faulted accesses to bad addresses */ 2449 mc->ignore_memory_transaction_failures = true; 2450 } 2451 DEFINE_VIRT_MACHINE(2, 10) 2452 2453 static void virt_machine_2_9_options(MachineClass *mc) 2454 { 2455 virt_machine_2_10_options(mc); 2456 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 2457 } 2458 DEFINE_VIRT_MACHINE(2, 9) 2459 2460 static void virt_machine_2_8_options(MachineClass *mc) 2461 { 2462 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2463 2464 virt_machine_2_9_options(mc); 2465 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 2466 /* For 2.8 and earlier we falsely claimed in the DT that 2467 * our timers were edge-triggered, not level-triggered. 2468 */ 2469 vmc->claim_edge_triggered_timers = true; 2470 } 2471 DEFINE_VIRT_MACHINE(2, 8) 2472 2473 static void virt_machine_2_7_options(MachineClass *mc) 2474 { 2475 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2476 2477 virt_machine_2_8_options(mc); 2478 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 2479 /* ITS was introduced with 2.8 */ 2480 vmc->no_its = true; 2481 /* Stick with 1K pages for migration compatibility */ 2482 mc->minimum_page_bits = 0; 2483 } 2484 DEFINE_VIRT_MACHINE(2, 7) 2485 2486 static void virt_machine_2_6_options(MachineClass *mc) 2487 { 2488 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2489 2490 virt_machine_2_7_options(mc); 2491 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 2492 vmc->disallow_affinity_adjustment = true; 2493 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 2494 vmc->no_pmu = true; 2495 } 2496 DEFINE_VIRT_MACHINE(2, 6) 2497