1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/datadir.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "hw/sysbus.h" 37 #include "hw/arm/boot.h" 38 #include "hw/arm/primecell.h" 39 #include "hw/arm/virt.h" 40 #include "hw/block/flash.h" 41 #include "hw/vfio/vfio-calxeda-xgmac.h" 42 #include "hw/vfio/vfio-amd-xgbe.h" 43 #include "hw/display/ramfb.h" 44 #include "net/net.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/numa.h" 47 #include "sysemu/runstate.h" 48 #include "sysemu/tpm.h" 49 #include "sysemu/tcg.h" 50 #include "sysemu/kvm.h" 51 #include "sysemu/hvf.h" 52 #include "sysemu/qtest.h" 53 #include "hw/loader.h" 54 #include "qapi/error.h" 55 #include "qemu/bitops.h" 56 #include "qemu/error-report.h" 57 #include "qemu/module.h" 58 #include "hw/pci-host/gpex.h" 59 #include "hw/virtio/virtio-pci.h" 60 #include "hw/core/sysbus-fdt.h" 61 #include "hw/platform-bus.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/arm/fdt.h" 64 #include "hw/intc/arm_gic.h" 65 #include "hw/intc/arm_gicv3_common.h" 66 #include "hw/intc/arm_gicv3_its_common.h" 67 #include "hw/irq.h" 68 #include "kvm_arm.h" 69 #include "hw/firmware/smbios.h" 70 #include "qapi/visitor.h" 71 #include "qapi/qapi-visit-common.h" 72 #include "qapi/qmp/qlist.h" 73 #include "standard-headers/linux/input.h" 74 #include "hw/arm/smmuv3.h" 75 #include "hw/acpi/acpi.h" 76 #include "target/arm/internals.h" 77 #include "hw/mem/pc-dimm.h" 78 #include "hw/mem/nvdimm.h" 79 #include "hw/acpi/generic_event_device.h" 80 #include "hw/virtio/virtio-md-pci.h" 81 #include "hw/virtio/virtio-iommu.h" 82 #include "hw/char/pl011.h" 83 #include "qemu/guest-random.h" 84 85 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 86 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 87 void *data) \ 88 { \ 89 MachineClass *mc = MACHINE_CLASS(oc); \ 90 virt_machine_##major##_##minor##_options(mc); \ 91 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 92 if (latest) { \ 93 mc->alias = "virt"; \ 94 } \ 95 } \ 96 static const TypeInfo machvirt_##major##_##minor##_info = { \ 97 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 98 .parent = TYPE_VIRT_MACHINE, \ 99 .class_init = virt_##major##_##minor##_class_init, \ 100 }; \ 101 static void machvirt_machine_##major##_##minor##_init(void) \ 102 { \ 103 type_register_static(&machvirt_##major##_##minor##_info); \ 104 } \ 105 type_init(machvirt_machine_##major##_##minor##_init); 106 107 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 108 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 109 #define DEFINE_VIRT_MACHINE(major, minor) \ 110 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 111 112 113 /* Number of external interrupt lines to configure the GIC with */ 114 #define NUM_IRQS 256 115 116 #define PLATFORM_BUS_NUM_IRQS 64 117 118 /* Legacy RAM limit in GB (< version 4.0) */ 119 #define LEGACY_RAMLIMIT_GB 255 120 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 121 122 /* Addresses and sizes of our components. 123 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 124 * 128MB..256MB is used for miscellaneous device I/O. 125 * 256MB..1GB is reserved for possible future PCI support (ie where the 126 * PCI memory window will go if we add a PCI host controller). 127 * 1GB and up is RAM (which may happily spill over into the 128 * high memory region beyond 4GB). 129 * This represents a compromise between how much RAM can be given to 130 * a 32 bit VM and leaving space for expansion and in particular for PCI. 131 * Note that devices should generally be placed at multiples of 0x10000, 132 * to accommodate guests using 64K pages. 133 */ 134 static const MemMapEntry base_memmap[] = { 135 /* Space up to 0x8000000 is reserved for a boot ROM */ 136 [VIRT_FLASH] = { 0, 0x08000000 }, 137 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 138 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 139 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 140 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 141 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 142 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 143 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 144 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 145 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 146 /* This redistributor space allows up to 2*64kB*123 CPUs */ 147 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 148 [VIRT_UART] = { 0x09000000, 0x00001000 }, 149 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 150 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 151 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 152 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 153 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 154 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 155 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 156 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 157 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, 158 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, 159 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 160 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 161 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 162 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 163 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 164 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 165 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 166 /* Actual RAM size depends on initial RAM and device memory settings */ 167 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 168 }; 169 170 /* 171 * Highmem IO Regions: This memory map is floating, located after the RAM. 172 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 173 * top of the RAM, so that its base get the same alignment as the size, 174 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 175 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 176 * Note the extended_memmap is sized so that it eventually also includes the 177 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 178 * index of base_memmap). 179 * 180 * The memory map for these Highmem IO Regions can be in legacy or compact 181 * layout, depending on 'compact-highmem' property. With legacy layout, the 182 * PA space for one specific region is always reserved, even if the region 183 * has been disabled or doesn't fit into the PA space. However, the PA space 184 * for the region won't be reserved in these circumstances with compact layout. 185 */ 186 static MemMapEntry extended_memmap[] = { 187 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 188 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 189 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 190 /* Second PCIe window */ 191 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 192 }; 193 194 static const int a15irqmap[] = { 195 [VIRT_UART] = 1, 196 [VIRT_RTC] = 2, 197 [VIRT_PCIE] = 3, /* ... to 6 */ 198 [VIRT_GPIO] = 7, 199 [VIRT_SECURE_UART] = 8, 200 [VIRT_ACPI_GED] = 9, 201 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 202 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 203 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 204 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 205 }; 206 207 static const char *valid_cpus[] = { 208 #ifdef CONFIG_TCG 209 ARM_CPU_TYPE_NAME("cortex-a7"), 210 ARM_CPU_TYPE_NAME("cortex-a15"), 211 ARM_CPU_TYPE_NAME("cortex-a35"), 212 ARM_CPU_TYPE_NAME("cortex-a55"), 213 ARM_CPU_TYPE_NAME("cortex-a72"), 214 ARM_CPU_TYPE_NAME("cortex-a76"), 215 ARM_CPU_TYPE_NAME("cortex-a710"), 216 ARM_CPU_TYPE_NAME("a64fx"), 217 ARM_CPU_TYPE_NAME("neoverse-n1"), 218 ARM_CPU_TYPE_NAME("neoverse-v1"), 219 ARM_CPU_TYPE_NAME("neoverse-n2"), 220 #endif 221 ARM_CPU_TYPE_NAME("cortex-a53"), 222 ARM_CPU_TYPE_NAME("cortex-a57"), 223 ARM_CPU_TYPE_NAME("host"), 224 ARM_CPU_TYPE_NAME("max"), 225 }; 226 227 static bool cpu_type_valid(const char *cpu) 228 { 229 int i; 230 231 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 232 if (strcmp(cpu, valid_cpus[i]) == 0) { 233 return true; 234 } 235 } 236 return false; 237 } 238 239 static void create_randomness(MachineState *ms, const char *node) 240 { 241 struct { 242 uint64_t kaslr; 243 uint8_t rng[32]; 244 } seed; 245 246 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { 247 return; 248 } 249 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr); 250 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); 251 } 252 253 static void create_fdt(VirtMachineState *vms) 254 { 255 MachineState *ms = MACHINE(vms); 256 int nb_numa_nodes = ms->numa_state->num_nodes; 257 void *fdt = create_device_tree(&vms->fdt_size); 258 259 if (!fdt) { 260 error_report("create_device_tree() failed"); 261 exit(1); 262 } 263 264 ms->fdt = fdt; 265 266 /* Header */ 267 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 268 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 269 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 270 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt"); 271 272 /* /chosen must exist for load_dtb to fill in necessary properties later */ 273 qemu_fdt_add_subnode(fdt, "/chosen"); 274 if (vms->dtb_randomness) { 275 create_randomness(ms, "/chosen"); 276 } 277 278 if (vms->secure) { 279 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 280 if (vms->dtb_randomness) { 281 create_randomness(ms, "/secure-chosen"); 282 } 283 } 284 285 /* Clock node, for the benefit of the UART. The kernel device tree 286 * binding documentation claims the PL011 node clock properties are 287 * optional but in practice if you omit them the kernel refuses to 288 * probe for the device. 289 */ 290 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 291 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 292 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 293 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 294 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 295 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 296 "clk24mhz"); 297 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 298 299 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 300 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 301 uint32_t *matrix = g_malloc0(size); 302 int idx, i, j; 303 304 for (i = 0; i < nb_numa_nodes; i++) { 305 for (j = 0; j < nb_numa_nodes; j++) { 306 idx = (i * nb_numa_nodes + j) * 3; 307 matrix[idx + 0] = cpu_to_be32(i); 308 matrix[idx + 1] = cpu_to_be32(j); 309 matrix[idx + 2] = 310 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 311 } 312 } 313 314 qemu_fdt_add_subnode(fdt, "/distance-map"); 315 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 316 "numa-distance-map-v1"); 317 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 318 matrix, size); 319 g_free(matrix); 320 } 321 } 322 323 static void fdt_add_timer_nodes(const VirtMachineState *vms) 324 { 325 /* On real hardware these interrupts are level-triggered. 326 * On KVM they were edge-triggered before host kernel version 4.4, 327 * and level-triggered afterwards. 328 * On emulated QEMU they are level-triggered. 329 * 330 * Getting the DTB info about them wrong is awkward for some 331 * guest kernels: 332 * pre-4.8 ignore the DT and leave the interrupt configured 333 * with whatever the GIC reset value (or the bootloader) left it at 334 * 4.8 before rc6 honour the incorrect data by programming it back 335 * into the GIC, causing problems 336 * 4.8rc6 and later ignore the DT and always write "level triggered" 337 * into the GIC 338 * 339 * For backwards-compatibility, virt-2.8 and earlier will continue 340 * to say these are edge-triggered, but later machines will report 341 * the correct information. 342 */ 343 ARMCPU *armcpu; 344 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 345 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 346 MachineState *ms = MACHINE(vms); 347 348 if (vmc->claim_edge_triggered_timers) { 349 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 350 } 351 352 if (vms->gic_version == VIRT_GIC_VERSION_2) { 353 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 354 GIC_FDT_IRQ_PPI_CPU_WIDTH, 355 (1 << MACHINE(vms)->smp.cpus) - 1); 356 } 357 358 qemu_fdt_add_subnode(ms->fdt, "/timer"); 359 360 armcpu = ARM_CPU(qemu_get_cpu(0)); 361 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 362 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 363 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", 364 compat, sizeof(compat)); 365 } else { 366 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", 367 "arm,armv7-timer"); 368 } 369 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); 370 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 371 GIC_FDT_IRQ_TYPE_PPI, 372 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, 373 GIC_FDT_IRQ_TYPE_PPI, 374 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, 375 GIC_FDT_IRQ_TYPE_PPI, 376 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, 377 GIC_FDT_IRQ_TYPE_PPI, 378 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags); 379 } 380 381 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 382 { 383 int cpu; 384 int addr_cells = 1; 385 const MachineState *ms = MACHINE(vms); 386 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 387 int smp_cpus = ms->smp.cpus; 388 389 /* 390 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml 391 * On ARM v8 64-bit systems value should be set to 2, 392 * that corresponds to the MPIDR_EL1 register size. 393 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 394 * in the system, #address-cells can be set to 1, since 395 * MPIDR_EL1[63:32] bits are not used for CPUs 396 * identification. 397 * 398 * Here we actually don't know whether our system is 32- or 64-bit one. 399 * The simplest way to go is to examine affinity IDs of all our CPUs. If 400 * at least one of them has Aff3 populated, we set #address-cells to 2. 401 */ 402 for (cpu = 0; cpu < smp_cpus; cpu++) { 403 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 404 405 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 406 addr_cells = 2; 407 break; 408 } 409 } 410 411 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 412 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); 413 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 414 415 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 416 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 417 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 418 CPUState *cs = CPU(armcpu); 419 420 qemu_fdt_add_subnode(ms->fdt, nodename); 421 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 422 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 423 armcpu->dtb_compatible); 424 425 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { 426 qemu_fdt_setprop_string(ms->fdt, nodename, 427 "enable-method", "psci"); 428 } 429 430 if (addr_cells == 2) { 431 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", 432 armcpu->mp_affinity); 433 } else { 434 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", 435 armcpu->mp_affinity); 436 } 437 438 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 439 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 440 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 441 } 442 443 if (!vmc->no_cpu_topology) { 444 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 445 qemu_fdt_alloc_phandle(ms->fdt)); 446 } 447 448 g_free(nodename); 449 } 450 451 if (!vmc->no_cpu_topology) { 452 /* 453 * Add vCPU topology description through fdt node cpu-map. 454 * 455 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt 456 * In a SMP system, the hierarchy of CPUs can be defined through 457 * four entities that are used to describe the layout of CPUs in 458 * the system: socket/cluster/core/thread. 459 * 460 * A socket node represents the boundary of system physical package 461 * and its child nodes must be one or more cluster nodes. A system 462 * can contain several layers of clustering within a single physical 463 * package and cluster nodes can be contained in parent cluster nodes. 464 * 465 * Note: currently we only support one layer of clustering within 466 * each physical package. 467 */ 468 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 469 470 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 471 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); 472 char *map_path; 473 474 if (ms->smp.threads > 1) { 475 map_path = g_strdup_printf( 476 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", 477 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), 478 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, 479 (cpu / ms->smp.threads) % ms->smp.cores, 480 cpu % ms->smp.threads); 481 } else { 482 map_path = g_strdup_printf( 483 "/cpus/cpu-map/socket%d/cluster%d/core%d", 484 cpu / (ms->smp.clusters * ms->smp.cores), 485 (cpu / ms->smp.cores) % ms->smp.clusters, 486 cpu % ms->smp.cores); 487 } 488 qemu_fdt_add_path(ms->fdt, map_path); 489 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 490 491 g_free(map_path); 492 g_free(cpu_path); 493 } 494 } 495 } 496 497 static void fdt_add_its_gic_node(VirtMachineState *vms) 498 { 499 char *nodename; 500 MachineState *ms = MACHINE(vms); 501 502 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 503 nodename = g_strdup_printf("/intc/its@%" PRIx64, 504 vms->memmap[VIRT_GIC_ITS].base); 505 qemu_fdt_add_subnode(ms->fdt, nodename); 506 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 507 "arm,gic-v3-its"); 508 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 509 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1); 510 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 511 2, vms->memmap[VIRT_GIC_ITS].base, 512 2, vms->memmap[VIRT_GIC_ITS].size); 513 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 514 g_free(nodename); 515 } 516 517 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 518 { 519 MachineState *ms = MACHINE(vms); 520 char *nodename; 521 522 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 523 vms->memmap[VIRT_GIC_V2M].base); 524 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 525 qemu_fdt_add_subnode(ms->fdt, nodename); 526 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 527 "arm,gic-v2m-frame"); 528 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 529 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 530 2, vms->memmap[VIRT_GIC_V2M].base, 531 2, vms->memmap[VIRT_GIC_V2M].size); 532 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 533 g_free(nodename); 534 } 535 536 static void fdt_add_gic_node(VirtMachineState *vms) 537 { 538 MachineState *ms = MACHINE(vms); 539 char *nodename; 540 541 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 542 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); 543 544 nodename = g_strdup_printf("/intc@%" PRIx64, 545 vms->memmap[VIRT_GIC_DIST].base); 546 qemu_fdt_add_subnode(ms->fdt, nodename); 547 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 548 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 549 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 550 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 551 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 552 if (vms->gic_version != VIRT_GIC_VERSION_2) { 553 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 554 555 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 556 "arm,gic-v3"); 557 558 qemu_fdt_setprop_cell(ms->fdt, nodename, 559 "#redistributor-regions", nb_redist_regions); 560 561 if (nb_redist_regions == 1) { 562 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 563 2, vms->memmap[VIRT_GIC_DIST].base, 564 2, vms->memmap[VIRT_GIC_DIST].size, 565 2, vms->memmap[VIRT_GIC_REDIST].base, 566 2, vms->memmap[VIRT_GIC_REDIST].size); 567 } else { 568 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 569 2, vms->memmap[VIRT_GIC_DIST].base, 570 2, vms->memmap[VIRT_GIC_DIST].size, 571 2, vms->memmap[VIRT_GIC_REDIST].base, 572 2, vms->memmap[VIRT_GIC_REDIST].size, 573 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 574 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 575 } 576 577 if (vms->virt) { 578 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 579 GIC_FDT_IRQ_TYPE_PPI, 580 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), 581 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 582 } 583 } else { 584 /* 'cortex-a15-gic' means 'GIC v2' */ 585 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 586 "arm,cortex-a15-gic"); 587 if (!vms->virt) { 588 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 589 2, vms->memmap[VIRT_GIC_DIST].base, 590 2, vms->memmap[VIRT_GIC_DIST].size, 591 2, vms->memmap[VIRT_GIC_CPU].base, 592 2, vms->memmap[VIRT_GIC_CPU].size); 593 } else { 594 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 595 2, vms->memmap[VIRT_GIC_DIST].base, 596 2, vms->memmap[VIRT_GIC_DIST].size, 597 2, vms->memmap[VIRT_GIC_CPU].base, 598 2, vms->memmap[VIRT_GIC_CPU].size, 599 2, vms->memmap[VIRT_GIC_HYP].base, 600 2, vms->memmap[VIRT_GIC_HYP].size, 601 2, vms->memmap[VIRT_GIC_VCPU].base, 602 2, vms->memmap[VIRT_GIC_VCPU].size); 603 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 604 GIC_FDT_IRQ_TYPE_PPI, 605 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), 606 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 607 } 608 } 609 610 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); 611 g_free(nodename); 612 } 613 614 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 615 { 616 ARMCPU *armcpu = ARM_CPU(first_cpu); 617 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 618 MachineState *ms = MACHINE(vms); 619 620 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 621 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); 622 return; 623 } 624 625 if (vms->gic_version == VIRT_GIC_VERSION_2) { 626 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 627 GIC_FDT_IRQ_PPI_CPU_WIDTH, 628 (1 << MACHINE(vms)->smp.cpus) - 1); 629 } 630 631 qemu_fdt_add_subnode(ms->fdt, "/pmu"); 632 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 633 const char compat[] = "arm,armv8-pmuv3"; 634 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", 635 compat, sizeof(compat)); 636 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", 637 GIC_FDT_IRQ_TYPE_PPI, 638 INTID_TO_PPI(VIRTUAL_PMU_IRQ), irqflags); 639 } 640 } 641 642 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 643 { 644 DeviceState *dev; 645 MachineState *ms = MACHINE(vms); 646 int irq = vms->irqmap[VIRT_ACPI_GED]; 647 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 648 649 if (ms->ram_slots) { 650 event |= ACPI_GED_MEM_HOTPLUG_EVT; 651 } 652 653 if (ms->nvdimms_state->is_enabled) { 654 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 655 } 656 657 dev = qdev_new(TYPE_ACPI_GED); 658 qdev_prop_set_uint32(dev, "ged-event", event); 659 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 660 661 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 662 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 663 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 664 665 return dev; 666 } 667 668 static void create_its(VirtMachineState *vms) 669 { 670 const char *itsclass = its_class_name(); 671 DeviceState *dev; 672 673 if (!strcmp(itsclass, "arm-gicv3-its")) { 674 if (!vms->tcg_its) { 675 itsclass = NULL; 676 } 677 } 678 679 if (!itsclass) { 680 /* Do nothing if not supported */ 681 return; 682 } 683 684 dev = qdev_new(itsclass); 685 686 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 687 &error_abort); 688 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 689 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 690 691 fdt_add_its_gic_node(vms); 692 vms->msi_controller = VIRT_MSI_CTRL_ITS; 693 } 694 695 static void create_v2m(VirtMachineState *vms) 696 { 697 int i; 698 int irq = vms->irqmap[VIRT_GIC_V2M]; 699 DeviceState *dev; 700 701 dev = qdev_new("arm-gicv2m"); 702 qdev_prop_set_uint32(dev, "base-spi", irq); 703 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 704 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 705 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 706 707 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 708 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 709 qdev_get_gpio_in(vms->gic, irq + i)); 710 } 711 712 fdt_add_v2m_gic_node(vms); 713 vms->msi_controller = VIRT_MSI_CTRL_GICV2M; 714 } 715 716 static void create_gic(VirtMachineState *vms, MemoryRegion *mem) 717 { 718 MachineState *ms = MACHINE(vms); 719 /* We create a standalone GIC */ 720 SysBusDevice *gicbusdev; 721 const char *gictype; 722 int i; 723 unsigned int smp_cpus = ms->smp.cpus; 724 uint32_t nb_redist_regions = 0; 725 int revision; 726 727 if (vms->gic_version == VIRT_GIC_VERSION_2) { 728 gictype = gic_class_name(); 729 } else { 730 gictype = gicv3_class_name(); 731 } 732 733 switch (vms->gic_version) { 734 case VIRT_GIC_VERSION_2: 735 revision = 2; 736 break; 737 case VIRT_GIC_VERSION_3: 738 revision = 3; 739 break; 740 case VIRT_GIC_VERSION_4: 741 revision = 4; 742 break; 743 default: 744 g_assert_not_reached(); 745 } 746 vms->gic = qdev_new(gictype); 747 qdev_prop_set_uint32(vms->gic, "revision", revision); 748 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 749 /* Note that the num-irq property counts both internal and external 750 * interrupts; there are always 32 of the former (mandated by GIC spec). 751 */ 752 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 753 if (!kvm_irqchip_in_kernel()) { 754 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 755 } 756 757 if (vms->gic_version != VIRT_GIC_VERSION_2) { 758 QList *redist_region_count; 759 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); 760 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 761 762 nb_redist_regions = virt_gicv3_redist_region_count(vms); 763 764 redist_region_count = qlist_new(); 765 qlist_append_int(redist_region_count, redist0_count); 766 if (nb_redist_regions == 2) { 767 uint32_t redist1_capacity = 768 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 769 770 qlist_append_int(redist_region_count, 771 MIN(smp_cpus - redist0_count, redist1_capacity)); 772 } 773 qdev_prop_set_array(vms->gic, "redist-region-count", 774 redist_region_count); 775 776 if (!kvm_irqchip_in_kernel()) { 777 if (vms->tcg_its) { 778 object_property_set_link(OBJECT(vms->gic), "sysmem", 779 OBJECT(mem), &error_fatal); 780 qdev_prop_set_bit(vms->gic, "has-lpi", true); 781 } 782 } 783 } else { 784 if (!kvm_irqchip_in_kernel()) { 785 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 786 vms->virt); 787 } 788 } 789 gicbusdev = SYS_BUS_DEVICE(vms->gic); 790 sysbus_realize_and_unref(gicbusdev, &error_fatal); 791 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 792 if (vms->gic_version != VIRT_GIC_VERSION_2) { 793 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 794 if (nb_redist_regions == 2) { 795 sysbus_mmio_map(gicbusdev, 2, 796 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 797 } 798 } else { 799 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 800 if (vms->virt) { 801 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 802 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 803 } 804 } 805 806 /* Wire the outputs from each CPU's generic timer and the GICv3 807 * maintenance interrupt signal to the appropriate GIC PPI inputs, 808 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 809 */ 810 for (i = 0; i < smp_cpus; i++) { 811 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 812 int intidbase = NUM_IRQS + i * GIC_INTERNAL; 813 /* Mapping from the output timer irq lines from the CPU to the 814 * GIC PPI inputs we use for the virt board. 815 */ 816 const int timer_irq[] = { 817 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 818 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 819 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 820 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 821 }; 822 823 for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 824 qdev_connect_gpio_out(cpudev, irq, 825 qdev_get_gpio_in(vms->gic, 826 intidbase + timer_irq[irq])); 827 } 828 829 if (vms->gic_version != VIRT_GIC_VERSION_2) { 830 qemu_irq irq = qdev_get_gpio_in(vms->gic, 831 intidbase + ARCH_GIC_MAINT_IRQ); 832 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 833 0, irq); 834 } else if (vms->virt) { 835 qemu_irq irq = qdev_get_gpio_in(vms->gic, 836 intidbase + ARCH_GIC_MAINT_IRQ); 837 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 838 } 839 840 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 841 qdev_get_gpio_in(vms->gic, intidbase 842 + VIRTUAL_PMU_IRQ)); 843 844 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 845 sysbus_connect_irq(gicbusdev, i + smp_cpus, 846 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 847 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 848 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 849 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 850 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 851 } 852 853 fdt_add_gic_node(vms); 854 855 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) { 856 create_its(vms); 857 } else if (vms->gic_version == VIRT_GIC_VERSION_2) { 858 create_v2m(vms); 859 } 860 } 861 862 static void create_uart(const VirtMachineState *vms, int uart, 863 MemoryRegion *mem, Chardev *chr) 864 { 865 char *nodename; 866 hwaddr base = vms->memmap[uart].base; 867 hwaddr size = vms->memmap[uart].size; 868 int irq = vms->irqmap[uart]; 869 const char compat[] = "arm,pl011\0arm,primecell"; 870 const char clocknames[] = "uartclk\0apb_pclk"; 871 DeviceState *dev = qdev_new(TYPE_PL011); 872 SysBusDevice *s = SYS_BUS_DEVICE(dev); 873 MachineState *ms = MACHINE(vms); 874 875 qdev_prop_set_chr(dev, "chardev", chr); 876 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 877 memory_region_add_subregion(mem, base, 878 sysbus_mmio_get_region(s, 0)); 879 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 880 881 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 882 qemu_fdt_add_subnode(ms->fdt, nodename); 883 /* Note that we can't use setprop_string because of the embedded NUL */ 884 qemu_fdt_setprop(ms->fdt, nodename, "compatible", 885 compat, sizeof(compat)); 886 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 887 2, base, 2, size); 888 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 889 GIC_FDT_IRQ_TYPE_SPI, irq, 890 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 891 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", 892 vms->clock_phandle, vms->clock_phandle); 893 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", 894 clocknames, sizeof(clocknames)); 895 896 if (uart == VIRT_UART) { 897 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 898 } else { 899 /* Mark as not usable by the normal world */ 900 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 901 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 902 903 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", 904 nodename); 905 } 906 907 g_free(nodename); 908 } 909 910 static void create_rtc(const VirtMachineState *vms) 911 { 912 char *nodename; 913 hwaddr base = vms->memmap[VIRT_RTC].base; 914 hwaddr size = vms->memmap[VIRT_RTC].size; 915 int irq = vms->irqmap[VIRT_RTC]; 916 const char compat[] = "arm,pl031\0arm,primecell"; 917 MachineState *ms = MACHINE(vms); 918 919 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 920 921 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 922 qemu_fdt_add_subnode(ms->fdt, nodename); 923 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 924 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 925 2, base, 2, size); 926 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 927 GIC_FDT_IRQ_TYPE_SPI, irq, 928 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 929 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 930 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 931 g_free(nodename); 932 } 933 934 static DeviceState *gpio_key_dev; 935 static void virt_powerdown_req(Notifier *n, void *opaque) 936 { 937 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 938 939 if (s->acpi_dev) { 940 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 941 } else { 942 /* use gpio Pin 3 for power button event */ 943 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 944 } 945 } 946 947 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, 948 uint32_t phandle) 949 { 950 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 951 qdev_get_gpio_in(pl061_dev, 3)); 952 953 qemu_fdt_add_subnode(fdt, "/gpio-keys"); 954 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); 955 956 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); 957 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", 958 "label", "GPIO Key Poweroff"); 959 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", 960 KEY_POWER); 961 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", 962 "gpios", phandle, 3, 0); 963 } 964 965 #define SECURE_GPIO_POWEROFF 0 966 #define SECURE_GPIO_RESET 1 967 968 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, 969 uint32_t phandle) 970 { 971 DeviceState *gpio_pwr_dev; 972 973 /* gpio-pwr */ 974 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); 975 976 /* connect secure pl061 to gpio-pwr */ 977 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, 978 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); 979 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, 980 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); 981 982 qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); 983 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", 984 "gpio-poweroff"); 985 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", 986 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); 987 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); 988 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", 989 "okay"); 990 991 qemu_fdt_add_subnode(fdt, "/gpio-restart"); 992 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", 993 "gpio-restart"); 994 qemu_fdt_setprop_cells(fdt, "/gpio-restart", 995 "gpios", phandle, SECURE_GPIO_RESET, 0); 996 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); 997 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", 998 "okay"); 999 } 1000 1001 static void create_gpio_devices(const VirtMachineState *vms, int gpio, 1002 MemoryRegion *mem) 1003 { 1004 char *nodename; 1005 DeviceState *pl061_dev; 1006 hwaddr base = vms->memmap[gpio].base; 1007 hwaddr size = vms->memmap[gpio].size; 1008 int irq = vms->irqmap[gpio]; 1009 const char compat[] = "arm,pl061\0arm,primecell"; 1010 SysBusDevice *s; 1011 MachineState *ms = MACHINE(vms); 1012 1013 pl061_dev = qdev_new("pl061"); 1014 /* Pull lines down to 0 if not driven by the PL061 */ 1015 qdev_prop_set_uint32(pl061_dev, "pullups", 0); 1016 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); 1017 s = SYS_BUS_DEVICE(pl061_dev); 1018 sysbus_realize_and_unref(s, &error_fatal); 1019 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); 1020 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 1021 1022 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); 1023 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 1024 qemu_fdt_add_subnode(ms->fdt, nodename); 1025 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1026 2, base, 2, size); 1027 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 1028 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); 1029 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); 1030 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1031 GIC_FDT_IRQ_TYPE_SPI, irq, 1032 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1033 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1034 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1035 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); 1036 1037 if (gpio != VIRT_GPIO) { 1038 /* Mark as not usable by the normal world */ 1039 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1040 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1041 } 1042 g_free(nodename); 1043 1044 /* Child gpio devices */ 1045 if (gpio == VIRT_GPIO) { 1046 create_gpio_keys(ms->fdt, pl061_dev, phandle); 1047 } else { 1048 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); 1049 } 1050 } 1051 1052 static void create_virtio_devices(const VirtMachineState *vms) 1053 { 1054 int i; 1055 hwaddr size = vms->memmap[VIRT_MMIO].size; 1056 MachineState *ms = MACHINE(vms); 1057 1058 /* We create the transports in forwards order. Since qbus_realize() 1059 * prepends (not appends) new child buses, the incrementing loop below will 1060 * create a list of virtio-mmio buses with decreasing base addresses. 1061 * 1062 * When a -device option is processed from the command line, 1063 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 1064 * order. The upshot is that -device options in increasing command line 1065 * order are mapped to virtio-mmio buses with decreasing base addresses. 1066 * 1067 * When this code was originally written, that arrangement ensured that the 1068 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 1069 * the first -device on the command line. (The end-to-end order is a 1070 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 1071 * guest kernel's name-to-address assignment strategy.) 1072 * 1073 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 1074 * the message, if not necessarily the code, of commit 70161ff336. 1075 * Therefore the loop now establishes the inverse of the original intent. 1076 * 1077 * Unfortunately, we can't counteract the kernel change by reversing the 1078 * loop; it would break existing command lines. 1079 * 1080 * In any case, the kernel makes no guarantee about the stability of 1081 * enumeration order of virtio devices (as demonstrated by it changing 1082 * between kernel versions). For reliable and stable identification 1083 * of disks users must use UUIDs or similar mechanisms. 1084 */ 1085 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 1086 int irq = vms->irqmap[VIRT_MMIO] + i; 1087 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1088 1089 sysbus_create_simple("virtio-mmio", base, 1090 qdev_get_gpio_in(vms->gic, irq)); 1091 } 1092 1093 /* We add dtb nodes in reverse order so that they appear in the finished 1094 * device tree lowest address first. 1095 * 1096 * Note that this mapping is independent of the loop above. The previous 1097 * loop influences virtio device to virtio transport assignment, whereas 1098 * this loop controls how virtio transports are laid out in the dtb. 1099 */ 1100 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 1101 char *nodename; 1102 int irq = vms->irqmap[VIRT_MMIO] + i; 1103 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1104 1105 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 1106 qemu_fdt_add_subnode(ms->fdt, nodename); 1107 qemu_fdt_setprop_string(ms->fdt, nodename, 1108 "compatible", "virtio,mmio"); 1109 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1110 2, base, 2, size); 1111 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1112 GIC_FDT_IRQ_TYPE_SPI, irq, 1113 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1114 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1115 g_free(nodename); 1116 } 1117 } 1118 1119 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 1120 1121 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 1122 const char *name, 1123 const char *alias_prop_name) 1124 { 1125 /* 1126 * Create a single flash device. We use the same parameters as 1127 * the flash devices on the Versatile Express board. 1128 */ 1129 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 1130 1131 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 1132 qdev_prop_set_uint8(dev, "width", 4); 1133 qdev_prop_set_uint8(dev, "device-width", 2); 1134 qdev_prop_set_bit(dev, "big-endian", false); 1135 qdev_prop_set_uint16(dev, "id0", 0x89); 1136 qdev_prop_set_uint16(dev, "id1", 0x18); 1137 qdev_prop_set_uint16(dev, "id2", 0x00); 1138 qdev_prop_set_uint16(dev, "id3", 0x00); 1139 qdev_prop_set_string(dev, "name", name); 1140 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 1141 object_property_add_alias(OBJECT(vms), alias_prop_name, 1142 OBJECT(dev), "drive"); 1143 return PFLASH_CFI01(dev); 1144 } 1145 1146 static void virt_flash_create(VirtMachineState *vms) 1147 { 1148 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 1149 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 1150 } 1151 1152 static void virt_flash_map1(PFlashCFI01 *flash, 1153 hwaddr base, hwaddr size, 1154 MemoryRegion *sysmem) 1155 { 1156 DeviceState *dev = DEVICE(flash); 1157 1158 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 1159 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 1160 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 1161 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1162 1163 memory_region_add_subregion(sysmem, base, 1164 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1165 0)); 1166 } 1167 1168 static void virt_flash_map(VirtMachineState *vms, 1169 MemoryRegion *sysmem, 1170 MemoryRegion *secure_sysmem) 1171 { 1172 /* 1173 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 1174 * sysmem is the system memory space. secure_sysmem is the secure view 1175 * of the system, and the first flash device should be made visible only 1176 * there. The second flash device is visible to both secure and nonsecure. 1177 * If sysmem == secure_sysmem this means there is no separate Secure 1178 * address space and both flash devices are generally visible. 1179 */ 1180 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1181 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1182 1183 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1184 secure_sysmem); 1185 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1186 sysmem); 1187 } 1188 1189 static void virt_flash_fdt(VirtMachineState *vms, 1190 MemoryRegion *sysmem, 1191 MemoryRegion *secure_sysmem) 1192 { 1193 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1194 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1195 MachineState *ms = MACHINE(vms); 1196 char *nodename; 1197 1198 if (sysmem == secure_sysmem) { 1199 /* Report both flash devices as a single node in the DT */ 1200 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1201 qemu_fdt_add_subnode(ms->fdt, nodename); 1202 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1203 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1204 2, flashbase, 2, flashsize, 1205 2, flashbase + flashsize, 2, flashsize); 1206 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1207 g_free(nodename); 1208 } else { 1209 /* 1210 * Report the devices as separate nodes so we can mark one as 1211 * only visible to the secure world. 1212 */ 1213 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1214 qemu_fdt_add_subnode(ms->fdt, nodename); 1215 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1216 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1217 2, flashbase, 2, flashsize); 1218 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1219 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1220 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1221 g_free(nodename); 1222 1223 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize); 1224 qemu_fdt_add_subnode(ms->fdt, nodename); 1225 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1226 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1227 2, flashbase + flashsize, 2, flashsize); 1228 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1229 g_free(nodename); 1230 } 1231 } 1232 1233 static bool virt_firmware_init(VirtMachineState *vms, 1234 MemoryRegion *sysmem, 1235 MemoryRegion *secure_sysmem) 1236 { 1237 int i; 1238 const char *bios_name; 1239 BlockBackend *pflash_blk0; 1240 1241 /* Map legacy -drive if=pflash to machine properties */ 1242 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1243 pflash_cfi01_legacy_drive(vms->flash[i], 1244 drive_get(IF_PFLASH, 0, i)); 1245 } 1246 1247 virt_flash_map(vms, sysmem, secure_sysmem); 1248 1249 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1250 1251 bios_name = MACHINE(vms)->firmware; 1252 if (bios_name) { 1253 char *fname; 1254 MemoryRegion *mr; 1255 int image_size; 1256 1257 if (pflash_blk0) { 1258 error_report("The contents of the first flash device may be " 1259 "specified with -bios or with -drive if=pflash... " 1260 "but you cannot use both options at once"); 1261 exit(1); 1262 } 1263 1264 /* Fall back to -bios */ 1265 1266 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1267 if (!fname) { 1268 error_report("Could not find ROM image '%s'", bios_name); 1269 exit(1); 1270 } 1271 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1272 image_size = load_image_mr(fname, mr); 1273 g_free(fname); 1274 if (image_size < 0) { 1275 error_report("Could not load ROM image '%s'", bios_name); 1276 exit(1); 1277 } 1278 } 1279 1280 return pflash_blk0 || bios_name; 1281 } 1282 1283 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1284 { 1285 MachineState *ms = MACHINE(vms); 1286 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1287 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1288 FWCfgState *fw_cfg; 1289 char *nodename; 1290 1291 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1292 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1293 1294 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1295 qemu_fdt_add_subnode(ms->fdt, nodename); 1296 qemu_fdt_setprop_string(ms->fdt, nodename, 1297 "compatible", "qemu,fw-cfg-mmio"); 1298 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1299 2, base, 2, size); 1300 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1301 g_free(nodename); 1302 return fw_cfg; 1303 } 1304 1305 static void create_pcie_irq_map(const MachineState *ms, 1306 uint32_t gic_phandle, 1307 int first_irq, const char *nodename) 1308 { 1309 int devfn, pin; 1310 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1311 uint32_t *irq_map = full_irq_map; 1312 1313 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1314 for (pin = 0; pin < 4; pin++) { 1315 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1316 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1317 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1318 int i; 1319 1320 uint32_t map[] = { 1321 devfn << 8, 0, 0, /* devfn */ 1322 pin + 1, /* PCI pin */ 1323 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1324 1325 /* Convert map to big endian */ 1326 for (i = 0; i < 10; i++) { 1327 irq_map[i] = cpu_to_be32(map[i]); 1328 } 1329 irq_map += 10; 1330 } 1331 } 1332 1333 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", 1334 full_irq_map, sizeof(full_irq_map)); 1335 1336 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 1337 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ 1338 0, 0, 1339 0x7 /* PCI irq */); 1340 } 1341 1342 static void create_smmu(const VirtMachineState *vms, 1343 PCIBus *bus) 1344 { 1345 char *node; 1346 const char compat[] = "arm,smmu-v3"; 1347 int irq = vms->irqmap[VIRT_SMMU]; 1348 int i; 1349 hwaddr base = vms->memmap[VIRT_SMMU].base; 1350 hwaddr size = vms->memmap[VIRT_SMMU].size; 1351 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1352 DeviceState *dev; 1353 MachineState *ms = MACHINE(vms); 1354 1355 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1356 return; 1357 } 1358 1359 dev = qdev_new(TYPE_ARM_SMMUV3); 1360 1361 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1362 &error_abort); 1363 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1364 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1365 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1366 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1367 qdev_get_gpio_in(vms->gic, irq + i)); 1368 } 1369 1370 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1371 qemu_fdt_add_subnode(ms->fdt, node); 1372 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1373 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); 1374 1375 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", 1376 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1377 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1378 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1379 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1380 1381 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, 1382 sizeof(irq_names)); 1383 1384 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); 1385 1386 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1387 1388 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1389 g_free(node); 1390 } 1391 1392 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1393 { 1394 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1395 uint16_t bdf = vms->virtio_iommu_bdf; 1396 MachineState *ms = MACHINE(vms); 1397 char *node; 1398 1399 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1400 1401 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename, 1402 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1403 qemu_fdt_add_subnode(ms->fdt, node); 1404 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1405 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 1406 1, bdf << 8, 1, 0, 1, 0, 1407 1, 0, 1, 0); 1408 1409 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1410 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1411 g_free(node); 1412 1413 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", 1414 0x0, vms->iommu_phandle, 0x0, bdf, 1415 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1416 } 1417 1418 static void create_pcie(VirtMachineState *vms) 1419 { 1420 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1421 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1422 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1423 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1424 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1425 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1426 hwaddr base_ecam, size_ecam; 1427 hwaddr base = base_mmio; 1428 int nr_pcie_buses; 1429 int irq = vms->irqmap[VIRT_PCIE]; 1430 MemoryRegion *mmio_alias; 1431 MemoryRegion *mmio_reg; 1432 MemoryRegion *ecam_alias; 1433 MemoryRegion *ecam_reg; 1434 DeviceState *dev; 1435 char *nodename; 1436 int i, ecam_id; 1437 PCIHostState *pci; 1438 MachineState *ms = MACHINE(vms); 1439 MachineClass *mc = MACHINE_GET_CLASS(ms); 1440 1441 dev = qdev_new(TYPE_GPEX_HOST); 1442 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1443 1444 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1445 base_ecam = vms->memmap[ecam_id].base; 1446 size_ecam = vms->memmap[ecam_id].size; 1447 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1448 /* Map only the first size_ecam bytes of ECAM space */ 1449 ecam_alias = g_new0(MemoryRegion, 1); 1450 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1451 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1452 ecam_reg, 0, size_ecam); 1453 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1454 1455 /* Map the MMIO window into system address space so as to expose 1456 * the section of PCI MMIO space which starts at the same base address 1457 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1458 * the window). 1459 */ 1460 mmio_alias = g_new0(MemoryRegion, 1); 1461 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1462 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1463 mmio_reg, base_mmio, size_mmio); 1464 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1465 1466 if (vms->highmem_mmio) { 1467 /* Map high MMIO space */ 1468 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1469 1470 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1471 mmio_reg, base_mmio_high, size_mmio_high); 1472 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1473 high_mmio_alias); 1474 } 1475 1476 /* Map IO port space */ 1477 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1478 1479 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1480 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1481 qdev_get_gpio_in(vms->gic, irq + i)); 1482 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1483 } 1484 1485 pci = PCI_HOST_BRIDGE(dev); 1486 pci->bypass_iommu = vms->default_bus_bypass_iommu; 1487 vms->bus = pci->bus; 1488 if (vms->bus) { 1489 for (i = 0; i < nb_nics; i++) { 1490 pci_nic_init_nofail(&nd_table[i], pci->bus, mc->default_nic, NULL); 1491 } 1492 } 1493 1494 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1495 qemu_fdt_add_subnode(ms->fdt, nodename); 1496 qemu_fdt_setprop_string(ms->fdt, nodename, 1497 "compatible", "pci-host-ecam-generic"); 1498 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 1499 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 1500 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 1501 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 1502 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 1503 nr_pcie_buses - 1); 1504 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1505 1506 if (vms->msi_phandle) { 1507 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 1508 0, vms->msi_phandle, 0, 0x10000); 1509 } 1510 1511 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1512 2, base_ecam, 2, size_ecam); 1513 1514 if (vms->highmem_mmio) { 1515 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1516 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1517 2, base_pio, 2, size_pio, 1518 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1519 2, base_mmio, 2, size_mmio, 1520 1, FDT_PCI_RANGE_MMIO_64BIT, 1521 2, base_mmio_high, 1522 2, base_mmio_high, 2, size_mmio_high); 1523 } else { 1524 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1525 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1526 2, base_pio, 2, size_pio, 1527 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1528 2, base_mmio, 2, size_mmio); 1529 } 1530 1531 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 1532 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); 1533 1534 if (vms->iommu) { 1535 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1536 1537 switch (vms->iommu) { 1538 case VIRT_IOMMU_SMMUV3: 1539 create_smmu(vms, vms->bus); 1540 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 1541 0x0, vms->iommu_phandle, 0x0, 0x10000); 1542 break; 1543 default: 1544 g_assert_not_reached(); 1545 } 1546 } 1547 } 1548 1549 static void create_platform_bus(VirtMachineState *vms) 1550 { 1551 DeviceState *dev; 1552 SysBusDevice *s; 1553 int i; 1554 MemoryRegion *sysmem = get_system_memory(); 1555 1556 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1557 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1558 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1559 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1560 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1561 vms->platform_bus_dev = dev; 1562 1563 s = SYS_BUS_DEVICE(dev); 1564 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1565 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1566 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1567 } 1568 1569 memory_region_add_subregion(sysmem, 1570 vms->memmap[VIRT_PLATFORM_BUS].base, 1571 sysbus_mmio_get_region(s, 0)); 1572 } 1573 1574 static void create_tag_ram(MemoryRegion *tag_sysmem, 1575 hwaddr base, hwaddr size, 1576 const char *name) 1577 { 1578 MemoryRegion *tagram = g_new(MemoryRegion, 1); 1579 1580 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); 1581 memory_region_add_subregion(tag_sysmem, base / 32, tagram); 1582 } 1583 1584 static void create_secure_ram(VirtMachineState *vms, 1585 MemoryRegion *secure_sysmem, 1586 MemoryRegion *secure_tag_sysmem) 1587 { 1588 MemoryRegion *secram = g_new(MemoryRegion, 1); 1589 char *nodename; 1590 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1591 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1592 MachineState *ms = MACHINE(vms); 1593 1594 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1595 &error_fatal); 1596 memory_region_add_subregion(secure_sysmem, base, secram); 1597 1598 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1599 qemu_fdt_add_subnode(ms->fdt, nodename); 1600 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 1601 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 1602 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1603 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1604 1605 if (secure_tag_sysmem) { 1606 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); 1607 } 1608 1609 g_free(nodename); 1610 } 1611 1612 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1613 { 1614 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1615 bootinfo); 1616 MachineState *ms = MACHINE(board); 1617 1618 1619 *fdt_size = board->fdt_size; 1620 return ms->fdt; 1621 } 1622 1623 static void virt_build_smbios(VirtMachineState *vms) 1624 { 1625 MachineClass *mc = MACHINE_GET_CLASS(vms); 1626 MachineState *ms = MACHINE(vms); 1627 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1628 uint8_t *smbios_tables, *smbios_anchor; 1629 size_t smbios_tables_len, smbios_anchor_len; 1630 struct smbios_phys_mem_area mem_array; 1631 const char *product = "QEMU Virtual Machine"; 1632 1633 if (kvm_enabled()) { 1634 product = "KVM Virtual Machine"; 1635 } 1636 1637 smbios_set_defaults("QEMU", product, 1638 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1639 true, SMBIOS_ENTRY_POINT_TYPE_64); 1640 1641 /* build the array of physical mem area from base_memmap */ 1642 mem_array.address = vms->memmap[VIRT_MEM].base; 1643 mem_array.length = ms->ram_size; 1644 1645 smbios_get_tables(ms, &mem_array, 1, 1646 &smbios_tables, &smbios_tables_len, 1647 &smbios_anchor, &smbios_anchor_len, 1648 &error_fatal); 1649 1650 if (smbios_anchor) { 1651 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1652 smbios_tables, smbios_tables_len); 1653 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1654 smbios_anchor, smbios_anchor_len); 1655 } 1656 } 1657 1658 static 1659 void virt_machine_done(Notifier *notifier, void *data) 1660 { 1661 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1662 machine_done); 1663 MachineState *ms = MACHINE(vms); 1664 ARMCPU *cpu = ARM_CPU(first_cpu); 1665 struct arm_boot_info *info = &vms->bootinfo; 1666 AddressSpace *as = arm_boot_address_space(cpu, info); 1667 1668 /* 1669 * If the user provided a dtb, we assume the dynamic sysbus nodes 1670 * already are integrated there. This corresponds to a use case where 1671 * the dynamic sysbus nodes are complex and their generation is not yet 1672 * supported. In that case the user can take charge of the guest dt 1673 * while qemu takes charge of the qom stuff. 1674 */ 1675 if (info->dtb_filename == NULL) { 1676 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", 1677 vms->memmap[VIRT_PLATFORM_BUS].base, 1678 vms->memmap[VIRT_PLATFORM_BUS].size, 1679 vms->irqmap[VIRT_PLATFORM_BUS]); 1680 } 1681 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1682 exit(1); 1683 } 1684 1685 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg); 1686 1687 virt_acpi_setup(vms); 1688 virt_build_smbios(vms); 1689 } 1690 1691 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1692 { 1693 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1694 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1695 1696 if (!vmc->disallow_affinity_adjustment) { 1697 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1698 * GIC's target-list limitations. 32-bit KVM hosts currently 1699 * always create clusters of 4 CPUs, but that is expected to 1700 * change when they gain support for gicv3. When KVM is enabled 1701 * it will override the changes we make here, therefore our 1702 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1703 * and to improve SGI efficiency. 1704 */ 1705 if (vms->gic_version == VIRT_GIC_VERSION_2) { 1706 clustersz = GIC_TARGETLIST_BITS; 1707 } else { 1708 clustersz = GICV3_TARGETLIST_BITS; 1709 } 1710 } 1711 return arm_cpu_mp_affinity(idx, clustersz); 1712 } 1713 1714 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, 1715 int index) 1716 { 1717 bool *enabled_array[] = { 1718 &vms->highmem_redists, 1719 &vms->highmem_ecam, 1720 &vms->highmem_mmio, 1721 }; 1722 1723 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST == 1724 ARRAY_SIZE(enabled_array)); 1725 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array)); 1726 1727 return enabled_array[index - VIRT_LOWMEMMAP_LAST]; 1728 } 1729 1730 static void virt_set_high_memmap(VirtMachineState *vms, 1731 hwaddr base, int pa_bits) 1732 { 1733 hwaddr region_base, region_size; 1734 bool *region_enabled, fits; 1735 int i; 1736 1737 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1738 region_enabled = virt_get_high_memmap_enabled(vms, i); 1739 region_base = ROUND_UP(base, extended_memmap[i].size); 1740 region_size = extended_memmap[i].size; 1741 1742 vms->memmap[i].base = region_base; 1743 vms->memmap[i].size = region_size; 1744 1745 /* 1746 * Check each device to see if it fits in the PA space, 1747 * moving highest_gpa as we go. For compatibility, move 1748 * highest_gpa for disabled fitting devices as well, if 1749 * the compact layout has been disabled. 1750 * 1751 * For each device that doesn't fit, disable it. 1752 */ 1753 fits = (region_base + region_size) <= BIT_ULL(pa_bits); 1754 *region_enabled &= fits; 1755 if (vms->highmem_compact && !*region_enabled) { 1756 continue; 1757 } 1758 1759 base = region_base + region_size; 1760 if (fits) { 1761 vms->highest_gpa = base - 1; 1762 } 1763 } 1764 } 1765 1766 static void virt_set_memmap(VirtMachineState *vms, int pa_bits) 1767 { 1768 MachineState *ms = MACHINE(vms); 1769 hwaddr base, device_memory_base, device_memory_size, memtop; 1770 int i; 1771 1772 vms->memmap = extended_memmap; 1773 1774 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1775 vms->memmap[i] = base_memmap[i]; 1776 } 1777 1778 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1779 error_report("unsupported number of memory slots: %"PRIu64, 1780 ms->ram_slots); 1781 exit(EXIT_FAILURE); 1782 } 1783 1784 /* 1785 * !highmem is exactly the same as limiting the PA space to 32bit, 1786 * irrespective of the underlying capabilities of the HW. 1787 */ 1788 if (!vms->highmem) { 1789 pa_bits = 32; 1790 } 1791 1792 /* 1793 * We compute the base of the high IO region depending on the 1794 * amount of initial and device memory. The device memory start/size 1795 * is aligned on 1GiB. We never put the high IO region below 256GiB 1796 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1797 * The device region size assumes 1GiB page max alignment per slot. 1798 */ 1799 device_memory_base = 1800 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1801 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1802 1803 /* Base address of the high IO region */ 1804 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1805 if (memtop > BIT_ULL(pa_bits)) { 1806 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n", 1807 pa_bits, memtop - BIT_ULL(pa_bits)); 1808 exit(EXIT_FAILURE); 1809 } 1810 if (base < device_memory_base) { 1811 error_report("maxmem/slots too huge"); 1812 exit(EXIT_FAILURE); 1813 } 1814 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1815 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1816 } 1817 1818 /* We know for sure that at least the memory fits in the PA space */ 1819 vms->highest_gpa = memtop - 1; 1820 1821 virt_set_high_memmap(vms, base, pa_bits); 1822 1823 if (device_memory_size > 0) { 1824 machine_memory_devices_init(ms, device_memory_base, device_memory_size); 1825 } 1826 } 1827 1828 static VirtGICType finalize_gic_version_do(const char *accel_name, 1829 VirtGICType gic_version, 1830 int gics_supported, 1831 unsigned int max_cpus) 1832 { 1833 /* Convert host/max/nosel to GIC version number */ 1834 switch (gic_version) { 1835 case VIRT_GIC_VERSION_HOST: 1836 if (!kvm_enabled()) { 1837 error_report("gic-version=host requires KVM"); 1838 exit(1); 1839 } 1840 1841 /* For KVM, gic-version=host means gic-version=max */ 1842 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX, 1843 gics_supported, max_cpus); 1844 case VIRT_GIC_VERSION_MAX: 1845 if (gics_supported & VIRT_GIC_VERSION_4_MASK) { 1846 gic_version = VIRT_GIC_VERSION_4; 1847 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1848 gic_version = VIRT_GIC_VERSION_3; 1849 } else { 1850 gic_version = VIRT_GIC_VERSION_2; 1851 } 1852 break; 1853 case VIRT_GIC_VERSION_NOSEL: 1854 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) && 1855 max_cpus <= GIC_NCPU) { 1856 gic_version = VIRT_GIC_VERSION_2; 1857 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1858 /* 1859 * in case the host does not support v2 emulation or 1860 * the end-user requested more than 8 VCPUs we now default 1861 * to v3. In any case defaulting to v2 would be broken. 1862 */ 1863 gic_version = VIRT_GIC_VERSION_3; 1864 } else if (max_cpus > GIC_NCPU) { 1865 error_report("%s only supports GICv2 emulation but more than 8 " 1866 "vcpus are requested", accel_name); 1867 exit(1); 1868 } 1869 break; 1870 case VIRT_GIC_VERSION_2: 1871 case VIRT_GIC_VERSION_3: 1872 case VIRT_GIC_VERSION_4: 1873 break; 1874 } 1875 1876 /* Check chosen version is effectively supported */ 1877 switch (gic_version) { 1878 case VIRT_GIC_VERSION_2: 1879 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) { 1880 error_report("%s does not support GICv2 emulation", accel_name); 1881 exit(1); 1882 } 1883 break; 1884 case VIRT_GIC_VERSION_3: 1885 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) { 1886 error_report("%s does not support GICv3 emulation", accel_name); 1887 exit(1); 1888 } 1889 break; 1890 case VIRT_GIC_VERSION_4: 1891 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) { 1892 error_report("%s does not support GICv4 emulation, is virtualization=on?", 1893 accel_name); 1894 exit(1); 1895 } 1896 break; 1897 default: 1898 error_report("logic error in finalize_gic_version"); 1899 exit(1); 1900 break; 1901 } 1902 1903 return gic_version; 1904 } 1905 1906 /* 1907 * finalize_gic_version - Determines the final gic_version 1908 * according to the gic-version property 1909 * 1910 * Default GIC type is v2 1911 */ 1912 static void finalize_gic_version(VirtMachineState *vms) 1913 { 1914 const char *accel_name = current_accel_name(); 1915 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 1916 int gics_supported = 0; 1917 1918 /* Determine which GIC versions the current environment supports */ 1919 if (kvm_enabled() && kvm_irqchip_in_kernel()) { 1920 int probe_bitmap = kvm_arm_vgic_probe(); 1921 1922 if (!probe_bitmap) { 1923 error_report("Unable to determine GIC version supported by host"); 1924 exit(1); 1925 } 1926 1927 if (probe_bitmap & KVM_ARM_VGIC_V2) { 1928 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1929 } 1930 if (probe_bitmap & KVM_ARM_VGIC_V3) { 1931 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1932 } 1933 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) { 1934 /* KVM w/o kernel irqchip can only deal with GICv2 */ 1935 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1936 accel_name = "KVM with kernel-irqchip=off"; 1937 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { 1938 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1939 if (module_object_class_by_name("arm-gicv3")) { 1940 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1941 if (vms->virt) { 1942 /* GICv4 only makes sense if CPU has EL2 */ 1943 gics_supported |= VIRT_GIC_VERSION_4_MASK; 1944 } 1945 } 1946 } else { 1947 error_report("Unsupported accelerator, can not determine GIC support"); 1948 exit(1); 1949 } 1950 1951 /* 1952 * Then convert helpers like host/max to concrete GIC versions and ensure 1953 * the desired version is supported 1954 */ 1955 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version, 1956 gics_supported, max_cpus); 1957 } 1958 1959 /* 1960 * virt_cpu_post_init() must be called after the CPUs have 1961 * been realized and the GIC has been created. 1962 */ 1963 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) 1964 { 1965 int max_cpus = MACHINE(vms)->smp.max_cpus; 1966 bool aarch64, pmu, steal_time; 1967 CPUState *cpu; 1968 1969 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); 1970 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); 1971 steal_time = object_property_get_bool(OBJECT(first_cpu), 1972 "kvm-steal-time", NULL); 1973 1974 if (kvm_enabled()) { 1975 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; 1976 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; 1977 1978 if (steal_time) { 1979 MemoryRegion *pvtime = g_new(MemoryRegion, 1); 1980 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; 1981 1982 /* The memory region size must be a multiple of host page size. */ 1983 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); 1984 1985 if (pvtime_size > pvtime_reg_size) { 1986 error_report("pvtime requires a %" HWADDR_PRId 1987 " byte memory region for %d CPUs," 1988 " but only %" HWADDR_PRId " has been reserved", 1989 pvtime_size, max_cpus, pvtime_reg_size); 1990 exit(1); 1991 } 1992 1993 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); 1994 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); 1995 } 1996 1997 CPU_FOREACH(cpu) { 1998 if (pmu) { 1999 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); 2000 if (kvm_irqchip_in_kernel()) { 2001 kvm_arm_pmu_set_irq(cpu, VIRTUAL_PMU_IRQ); 2002 } 2003 kvm_arm_pmu_init(cpu); 2004 } 2005 if (steal_time) { 2006 kvm_arm_pvtime_init(cpu, pvtime_reg_base + 2007 cpu->cpu_index * PVTIME_SIZE_PER_CPU); 2008 } 2009 } 2010 } else { 2011 if (aarch64 && vms->highmem) { 2012 int requested_pa_size = 64 - clz64(vms->highest_gpa); 2013 int pamax = arm_pamax(ARM_CPU(first_cpu)); 2014 2015 if (pamax < requested_pa_size) { 2016 error_report("VCPU supports less PA bits (%d) than " 2017 "requested by the memory map (%d)", 2018 pamax, requested_pa_size); 2019 exit(1); 2020 } 2021 } 2022 } 2023 } 2024 2025 static void machvirt_init(MachineState *machine) 2026 { 2027 VirtMachineState *vms = VIRT_MACHINE(machine); 2028 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 2029 MachineClass *mc = MACHINE_GET_CLASS(machine); 2030 const CPUArchIdList *possible_cpus; 2031 MemoryRegion *sysmem = get_system_memory(); 2032 MemoryRegion *secure_sysmem = NULL; 2033 MemoryRegion *tag_sysmem = NULL; 2034 MemoryRegion *secure_tag_sysmem = NULL; 2035 int n, virt_max_cpus; 2036 bool firmware_loaded; 2037 bool aarch64 = true; 2038 bool has_ged = !vmc->no_ged; 2039 unsigned int smp_cpus = machine->smp.cpus; 2040 unsigned int max_cpus = machine->smp.max_cpus; 2041 2042 if (!cpu_type_valid(machine->cpu_type)) { 2043 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 2044 exit(1); 2045 } 2046 2047 possible_cpus = mc->possible_cpu_arch_ids(machine); 2048 2049 /* 2050 * In accelerated mode, the memory map is computed earlier in kvm_type() 2051 * to create a VM with the right number of IPA bits. 2052 */ 2053 if (!vms->memmap) { 2054 Object *cpuobj; 2055 ARMCPU *armcpu; 2056 int pa_bits; 2057 2058 /* 2059 * Instantiate a temporary CPU object to find out about what 2060 * we are about to deal with. Once this is done, get rid of 2061 * the object. 2062 */ 2063 cpuobj = object_new(possible_cpus->cpus[0].type); 2064 armcpu = ARM_CPU(cpuobj); 2065 2066 pa_bits = arm_pamax(armcpu); 2067 2068 object_unref(cpuobj); 2069 2070 virt_set_memmap(vms, pa_bits); 2071 } 2072 2073 /* We can probe only here because during property set 2074 * KVM is not available yet 2075 */ 2076 finalize_gic_version(vms); 2077 2078 if (vms->secure) { 2079 /* 2080 * The Secure view of the world is the same as the NonSecure, 2081 * but with a few extra devices. Create it as a container region 2082 * containing the system memory at low priority; any secure-only 2083 * devices go in at higher priority and take precedence. 2084 */ 2085 secure_sysmem = g_new(MemoryRegion, 1); 2086 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 2087 UINT64_MAX); 2088 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 2089 } 2090 2091 firmware_loaded = virt_firmware_init(vms, sysmem, 2092 secure_sysmem ?: sysmem); 2093 2094 /* If we have an EL3 boot ROM then the assumption is that it will 2095 * implement PSCI itself, so disable QEMU's internal implementation 2096 * so it doesn't get in the way. Instead of starting secondary 2097 * CPUs in PSCI powerdown state we will start them all running and 2098 * let the boot ROM sort them out. 2099 * The usual case is that we do use QEMU's PSCI implementation; 2100 * if the guest has EL2 then we will use SMC as the conduit, 2101 * and otherwise we will use HVC (for backwards compatibility and 2102 * because if we're using KVM then we must use HVC). 2103 */ 2104 if (vms->secure && firmware_loaded) { 2105 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 2106 } else if (vms->virt) { 2107 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 2108 } else { 2109 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 2110 } 2111 2112 /* 2113 * The maximum number of CPUs depends on the GIC version, or on how 2114 * many redistributors we can fit into the memory map (which in turn 2115 * depends on whether this is a GICv3 or v4). 2116 */ 2117 if (vms->gic_version == VIRT_GIC_VERSION_2) { 2118 virt_max_cpus = GIC_NCPU; 2119 } else { 2120 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST); 2121 if (vms->highmem_redists) { 2122 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 2123 } 2124 } 2125 2126 if (max_cpus > virt_max_cpus) { 2127 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 2128 "supported by machine 'mach-virt' (%d)", 2129 max_cpus, virt_max_cpus); 2130 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) { 2131 error_printf("Try 'highmem-redists=on' for more CPUs\n"); 2132 } 2133 2134 exit(1); 2135 } 2136 2137 if (vms->secure && (kvm_enabled() || hvf_enabled())) { 2138 error_report("mach-virt: %s does not support providing " 2139 "Security extensions (TrustZone) to the guest CPU", 2140 current_accel_name()); 2141 exit(1); 2142 } 2143 2144 if (vms->virt && (kvm_enabled() || hvf_enabled())) { 2145 error_report("mach-virt: %s does not support providing " 2146 "Virtualization extensions to the guest CPU", 2147 current_accel_name()); 2148 exit(1); 2149 } 2150 2151 if (vms->mte && (kvm_enabled() || hvf_enabled())) { 2152 error_report("mach-virt: %s does not support providing " 2153 "MTE to the guest CPU", 2154 current_accel_name()); 2155 exit(1); 2156 } 2157 2158 create_fdt(vms); 2159 2160 assert(possible_cpus->len == max_cpus); 2161 for (n = 0; n < possible_cpus->len; n++) { 2162 Object *cpuobj; 2163 CPUState *cs; 2164 2165 if (n >= smp_cpus) { 2166 break; 2167 } 2168 2169 cpuobj = object_new(possible_cpus->cpus[n].type); 2170 object_property_set_int(cpuobj, "mp-affinity", 2171 possible_cpus->cpus[n].arch_id, NULL); 2172 2173 cs = CPU(cpuobj); 2174 cs->cpu_index = n; 2175 2176 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 2177 &error_fatal); 2178 2179 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 2180 2181 if (!vms->secure) { 2182 object_property_set_bool(cpuobj, "has_el3", false, NULL); 2183 } 2184 2185 if (!vms->virt && object_property_find(cpuobj, "has_el2")) { 2186 object_property_set_bool(cpuobj, "has_el2", false, NULL); 2187 } 2188 2189 if (vmc->kvm_no_adjvtime && 2190 object_property_find(cpuobj, "kvm-no-adjvtime")) { 2191 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 2192 } 2193 2194 if (vmc->no_kvm_steal_time && 2195 object_property_find(cpuobj, "kvm-steal-time")) { 2196 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); 2197 } 2198 2199 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { 2200 object_property_set_bool(cpuobj, "pmu", false, NULL); 2201 } 2202 2203 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { 2204 object_property_set_bool(cpuobj, "lpa2", false, NULL); 2205 } 2206 2207 if (object_property_find(cpuobj, "reset-cbar")) { 2208 object_property_set_int(cpuobj, "reset-cbar", 2209 vms->memmap[VIRT_CPUPERIPHS].base, 2210 &error_abort); 2211 } 2212 2213 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 2214 &error_abort); 2215 if (vms->secure) { 2216 object_property_set_link(cpuobj, "secure-memory", 2217 OBJECT(secure_sysmem), &error_abort); 2218 } 2219 2220 if (vms->mte) { 2221 /* Create the memory region only once, but link to all cpus. */ 2222 if (!tag_sysmem) { 2223 /* 2224 * The property exists only if MemTag is supported. 2225 * If it is, we must allocate the ram to back that up. 2226 */ 2227 if (!object_property_find(cpuobj, "tag-memory")) { 2228 error_report("MTE requested, but not supported " 2229 "by the guest CPU"); 2230 exit(1); 2231 } 2232 2233 tag_sysmem = g_new(MemoryRegion, 1); 2234 memory_region_init(tag_sysmem, OBJECT(machine), 2235 "tag-memory", UINT64_MAX / 32); 2236 2237 if (vms->secure) { 2238 secure_tag_sysmem = g_new(MemoryRegion, 1); 2239 memory_region_init(secure_tag_sysmem, OBJECT(machine), 2240 "secure-tag-memory", UINT64_MAX / 32); 2241 2242 /* As with ram, secure-tag takes precedence over tag. */ 2243 memory_region_add_subregion_overlap(secure_tag_sysmem, 0, 2244 tag_sysmem, -1); 2245 } 2246 } 2247 2248 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem), 2249 &error_abort); 2250 if (vms->secure) { 2251 object_property_set_link(cpuobj, "secure-tag-memory", 2252 OBJECT(secure_tag_sysmem), 2253 &error_abort); 2254 } 2255 } 2256 2257 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 2258 object_unref(cpuobj); 2259 } 2260 fdt_add_timer_nodes(vms); 2261 fdt_add_cpu_nodes(vms); 2262 2263 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 2264 machine->ram); 2265 2266 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 2267 2268 create_gic(vms, sysmem); 2269 2270 virt_cpu_post_init(vms, sysmem); 2271 2272 fdt_add_pmu_nodes(vms); 2273 2274 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 2275 2276 if (vms->secure) { 2277 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); 2278 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 2279 } 2280 2281 if (tag_sysmem) { 2282 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, 2283 machine->ram_size, "mach-virt.tag"); 2284 } 2285 2286 vms->highmem_ecam &= (!firmware_loaded || aarch64); 2287 2288 create_rtc(vms); 2289 2290 create_pcie(vms); 2291 2292 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 2293 vms->acpi_dev = create_acpi_ged(vms); 2294 } else { 2295 create_gpio_devices(vms, VIRT_GPIO, sysmem); 2296 } 2297 2298 if (vms->secure && !vmc->no_secure_gpio) { 2299 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); 2300 } 2301 2302 /* connect powerdown request */ 2303 vms->powerdown_notifier.notify = virt_powerdown_req; 2304 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 2305 2306 /* Create mmio transports, so the user can create virtio backends 2307 * (which will be automatically plugged in to the transports). If 2308 * no backend is created the transport will just sit harmlessly idle. 2309 */ 2310 create_virtio_devices(vms); 2311 2312 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 2313 rom_set_fw(vms->fw_cfg); 2314 2315 create_platform_bus(vms); 2316 2317 if (machine->nvdimms_state->is_enabled) { 2318 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 2319 .space_id = AML_AS_SYSTEM_MEMORY, 2320 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 2321 .bit_width = NVDIMM_ACPI_IO_LEN << 3 2322 }; 2323 2324 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 2325 arm_virt_nvdimm_acpi_dsmio, 2326 vms->fw_cfg, OBJECT(vms)); 2327 } 2328 2329 vms->bootinfo.ram_size = machine->ram_size; 2330 vms->bootinfo.board_id = -1; 2331 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 2332 vms->bootinfo.get_dtb = machvirt_dtb; 2333 vms->bootinfo.skip_dtb_autoload = true; 2334 vms->bootinfo.firmware_loaded = firmware_loaded; 2335 vms->bootinfo.psci_conduit = vms->psci_conduit; 2336 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 2337 2338 vms->machine_done.notify = virt_machine_done; 2339 qemu_add_machine_init_done_notifier(&vms->machine_done); 2340 } 2341 2342 static bool virt_get_secure(Object *obj, Error **errp) 2343 { 2344 VirtMachineState *vms = VIRT_MACHINE(obj); 2345 2346 return vms->secure; 2347 } 2348 2349 static void virt_set_secure(Object *obj, bool value, Error **errp) 2350 { 2351 VirtMachineState *vms = VIRT_MACHINE(obj); 2352 2353 vms->secure = value; 2354 } 2355 2356 static bool virt_get_virt(Object *obj, Error **errp) 2357 { 2358 VirtMachineState *vms = VIRT_MACHINE(obj); 2359 2360 return vms->virt; 2361 } 2362 2363 static void virt_set_virt(Object *obj, bool value, Error **errp) 2364 { 2365 VirtMachineState *vms = VIRT_MACHINE(obj); 2366 2367 vms->virt = value; 2368 } 2369 2370 static bool virt_get_highmem(Object *obj, Error **errp) 2371 { 2372 VirtMachineState *vms = VIRT_MACHINE(obj); 2373 2374 return vms->highmem; 2375 } 2376 2377 static void virt_set_highmem(Object *obj, bool value, Error **errp) 2378 { 2379 VirtMachineState *vms = VIRT_MACHINE(obj); 2380 2381 vms->highmem = value; 2382 } 2383 2384 static bool virt_get_compact_highmem(Object *obj, Error **errp) 2385 { 2386 VirtMachineState *vms = VIRT_MACHINE(obj); 2387 2388 return vms->highmem_compact; 2389 } 2390 2391 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp) 2392 { 2393 VirtMachineState *vms = VIRT_MACHINE(obj); 2394 2395 vms->highmem_compact = value; 2396 } 2397 2398 static bool virt_get_highmem_redists(Object *obj, Error **errp) 2399 { 2400 VirtMachineState *vms = VIRT_MACHINE(obj); 2401 2402 return vms->highmem_redists; 2403 } 2404 2405 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp) 2406 { 2407 VirtMachineState *vms = VIRT_MACHINE(obj); 2408 2409 vms->highmem_redists = value; 2410 } 2411 2412 static bool virt_get_highmem_ecam(Object *obj, Error **errp) 2413 { 2414 VirtMachineState *vms = VIRT_MACHINE(obj); 2415 2416 return vms->highmem_ecam; 2417 } 2418 2419 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp) 2420 { 2421 VirtMachineState *vms = VIRT_MACHINE(obj); 2422 2423 vms->highmem_ecam = value; 2424 } 2425 2426 static bool virt_get_highmem_mmio(Object *obj, Error **errp) 2427 { 2428 VirtMachineState *vms = VIRT_MACHINE(obj); 2429 2430 return vms->highmem_mmio; 2431 } 2432 2433 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp) 2434 { 2435 VirtMachineState *vms = VIRT_MACHINE(obj); 2436 2437 vms->highmem_mmio = value; 2438 } 2439 2440 2441 static bool virt_get_its(Object *obj, Error **errp) 2442 { 2443 VirtMachineState *vms = VIRT_MACHINE(obj); 2444 2445 return vms->its; 2446 } 2447 2448 static void virt_set_its(Object *obj, bool value, Error **errp) 2449 { 2450 VirtMachineState *vms = VIRT_MACHINE(obj); 2451 2452 vms->its = value; 2453 } 2454 2455 static bool virt_get_dtb_randomness(Object *obj, Error **errp) 2456 { 2457 VirtMachineState *vms = VIRT_MACHINE(obj); 2458 2459 return vms->dtb_randomness; 2460 } 2461 2462 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp) 2463 { 2464 VirtMachineState *vms = VIRT_MACHINE(obj); 2465 2466 vms->dtb_randomness = value; 2467 } 2468 2469 static char *virt_get_oem_id(Object *obj, Error **errp) 2470 { 2471 VirtMachineState *vms = VIRT_MACHINE(obj); 2472 2473 return g_strdup(vms->oem_id); 2474 } 2475 2476 static void virt_set_oem_id(Object *obj, const char *value, Error **errp) 2477 { 2478 VirtMachineState *vms = VIRT_MACHINE(obj); 2479 size_t len = strlen(value); 2480 2481 if (len > 6) { 2482 error_setg(errp, 2483 "User specified oem-id value is bigger than 6 bytes in size"); 2484 return; 2485 } 2486 2487 strncpy(vms->oem_id, value, 6); 2488 } 2489 2490 static char *virt_get_oem_table_id(Object *obj, Error **errp) 2491 { 2492 VirtMachineState *vms = VIRT_MACHINE(obj); 2493 2494 return g_strdup(vms->oem_table_id); 2495 } 2496 2497 static void virt_set_oem_table_id(Object *obj, const char *value, 2498 Error **errp) 2499 { 2500 VirtMachineState *vms = VIRT_MACHINE(obj); 2501 size_t len = strlen(value); 2502 2503 if (len > 8) { 2504 error_setg(errp, 2505 "User specified oem-table-id value is bigger than 8 bytes in size"); 2506 return; 2507 } 2508 strncpy(vms->oem_table_id, value, 8); 2509 } 2510 2511 2512 bool virt_is_acpi_enabled(VirtMachineState *vms) 2513 { 2514 if (vms->acpi == ON_OFF_AUTO_OFF) { 2515 return false; 2516 } 2517 return true; 2518 } 2519 2520 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 2521 void *opaque, Error **errp) 2522 { 2523 VirtMachineState *vms = VIRT_MACHINE(obj); 2524 OnOffAuto acpi = vms->acpi; 2525 2526 visit_type_OnOffAuto(v, name, &acpi, errp); 2527 } 2528 2529 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 2530 void *opaque, Error **errp) 2531 { 2532 VirtMachineState *vms = VIRT_MACHINE(obj); 2533 2534 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 2535 } 2536 2537 static bool virt_get_ras(Object *obj, Error **errp) 2538 { 2539 VirtMachineState *vms = VIRT_MACHINE(obj); 2540 2541 return vms->ras; 2542 } 2543 2544 static void virt_set_ras(Object *obj, bool value, Error **errp) 2545 { 2546 VirtMachineState *vms = VIRT_MACHINE(obj); 2547 2548 vms->ras = value; 2549 } 2550 2551 static bool virt_get_mte(Object *obj, Error **errp) 2552 { 2553 VirtMachineState *vms = VIRT_MACHINE(obj); 2554 2555 return vms->mte; 2556 } 2557 2558 static void virt_set_mte(Object *obj, bool value, Error **errp) 2559 { 2560 VirtMachineState *vms = VIRT_MACHINE(obj); 2561 2562 vms->mte = value; 2563 } 2564 2565 static char *virt_get_gic_version(Object *obj, Error **errp) 2566 { 2567 VirtMachineState *vms = VIRT_MACHINE(obj); 2568 const char *val; 2569 2570 switch (vms->gic_version) { 2571 case VIRT_GIC_VERSION_4: 2572 val = "4"; 2573 break; 2574 case VIRT_GIC_VERSION_3: 2575 val = "3"; 2576 break; 2577 default: 2578 val = "2"; 2579 break; 2580 } 2581 return g_strdup(val); 2582 } 2583 2584 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2585 { 2586 VirtMachineState *vms = VIRT_MACHINE(obj); 2587 2588 if (!strcmp(value, "4")) { 2589 vms->gic_version = VIRT_GIC_VERSION_4; 2590 } else if (!strcmp(value, "3")) { 2591 vms->gic_version = VIRT_GIC_VERSION_3; 2592 } else if (!strcmp(value, "2")) { 2593 vms->gic_version = VIRT_GIC_VERSION_2; 2594 } else if (!strcmp(value, "host")) { 2595 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2596 } else if (!strcmp(value, "max")) { 2597 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2598 } else { 2599 error_setg(errp, "Invalid gic-version value"); 2600 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2601 } 2602 } 2603 2604 static char *virt_get_iommu(Object *obj, Error **errp) 2605 { 2606 VirtMachineState *vms = VIRT_MACHINE(obj); 2607 2608 switch (vms->iommu) { 2609 case VIRT_IOMMU_NONE: 2610 return g_strdup("none"); 2611 case VIRT_IOMMU_SMMUV3: 2612 return g_strdup("smmuv3"); 2613 default: 2614 g_assert_not_reached(); 2615 } 2616 } 2617 2618 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2619 { 2620 VirtMachineState *vms = VIRT_MACHINE(obj); 2621 2622 if (!strcmp(value, "smmuv3")) { 2623 vms->iommu = VIRT_IOMMU_SMMUV3; 2624 } else if (!strcmp(value, "none")) { 2625 vms->iommu = VIRT_IOMMU_NONE; 2626 } else { 2627 error_setg(errp, "Invalid iommu value"); 2628 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2629 } 2630 } 2631 2632 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp) 2633 { 2634 VirtMachineState *vms = VIRT_MACHINE(obj); 2635 2636 return vms->default_bus_bypass_iommu; 2637 } 2638 2639 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value, 2640 Error **errp) 2641 { 2642 VirtMachineState *vms = VIRT_MACHINE(obj); 2643 2644 vms->default_bus_bypass_iommu = value; 2645 } 2646 2647 static CpuInstanceProperties 2648 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2649 { 2650 MachineClass *mc = MACHINE_GET_CLASS(ms); 2651 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2652 2653 assert(cpu_index < possible_cpus->len); 2654 return possible_cpus->cpus[cpu_index].props; 2655 } 2656 2657 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2658 { 2659 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 2660 2661 return socket_id % ms->numa_state->num_nodes; 2662 } 2663 2664 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2665 { 2666 int n; 2667 unsigned int max_cpus = ms->smp.max_cpus; 2668 VirtMachineState *vms = VIRT_MACHINE(ms); 2669 MachineClass *mc = MACHINE_GET_CLASS(vms); 2670 2671 if (ms->possible_cpus) { 2672 assert(ms->possible_cpus->len == max_cpus); 2673 return ms->possible_cpus; 2674 } 2675 2676 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2677 sizeof(CPUArchId) * max_cpus); 2678 ms->possible_cpus->len = max_cpus; 2679 for (n = 0; n < ms->possible_cpus->len; n++) { 2680 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2681 ms->possible_cpus->cpus[n].arch_id = 2682 virt_cpu_mp_affinity(vms, n); 2683 2684 assert(!mc->smp_props.dies_supported); 2685 ms->possible_cpus->cpus[n].props.has_socket_id = true; 2686 ms->possible_cpus->cpus[n].props.socket_id = 2687 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); 2688 ms->possible_cpus->cpus[n].props.has_cluster_id = true; 2689 ms->possible_cpus->cpus[n].props.cluster_id = 2690 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; 2691 ms->possible_cpus->cpus[n].props.has_core_id = true; 2692 ms->possible_cpus->cpus[n].props.core_id = 2693 (n / ms->smp.threads) % ms->smp.cores; 2694 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2695 ms->possible_cpus->cpus[n].props.thread_id = 2696 n % ms->smp.threads; 2697 } 2698 return ms->possible_cpus; 2699 } 2700 2701 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2702 Error **errp) 2703 { 2704 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2705 const MachineState *ms = MACHINE(hotplug_dev); 2706 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2707 2708 if (!vms->acpi_dev) { 2709 error_setg(errp, 2710 "memory hotplug is not enabled: missing acpi-ged device"); 2711 return; 2712 } 2713 2714 if (vms->mte) { 2715 error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); 2716 return; 2717 } 2718 2719 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2720 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2721 return; 2722 } 2723 2724 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 2725 } 2726 2727 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2728 DeviceState *dev, Error **errp) 2729 { 2730 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2731 MachineState *ms = MACHINE(hotplug_dev); 2732 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2733 2734 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); 2735 2736 if (is_nvdimm) { 2737 nvdimm_plug(ms->nvdimms_state); 2738 } 2739 2740 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2741 dev, &error_abort); 2742 } 2743 2744 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2745 DeviceState *dev, Error **errp) 2746 { 2747 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2748 2749 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2750 virt_memory_pre_plug(hotplug_dev, dev, errp); 2751 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2752 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2753 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2754 hwaddr db_start = 0, db_end = 0; 2755 QList *reserved_regions; 2756 char *resv_prop_str; 2757 2758 if (vms->iommu != VIRT_IOMMU_NONE) { 2759 error_setg(errp, "virt machine does not support multiple IOMMUs"); 2760 return; 2761 } 2762 2763 switch (vms->msi_controller) { 2764 case VIRT_MSI_CTRL_NONE: 2765 return; 2766 case VIRT_MSI_CTRL_ITS: 2767 /* GITS_TRANSLATER page */ 2768 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; 2769 db_end = base_memmap[VIRT_GIC_ITS].base + 2770 base_memmap[VIRT_GIC_ITS].size - 1; 2771 break; 2772 case VIRT_MSI_CTRL_GICV2M: 2773 /* MSI_SETSPI_NS page */ 2774 db_start = base_memmap[VIRT_GIC_V2M].base; 2775 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; 2776 break; 2777 } 2778 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", 2779 db_start, db_end, 2780 VIRTIO_IOMMU_RESV_MEM_T_MSI); 2781 2782 reserved_regions = qlist_new(); 2783 qlist_append_str(reserved_regions, resv_prop_str); 2784 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 2785 g_free(resv_prop_str); 2786 } 2787 } 2788 2789 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2790 DeviceState *dev, Error **errp) 2791 { 2792 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2793 2794 if (vms->platform_bus_dev) { 2795 MachineClass *mc = MACHINE_GET_CLASS(vms); 2796 2797 if (device_is_dynamic_sysbus(mc, dev)) { 2798 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2799 SYS_BUS_DEVICE(dev)); 2800 } 2801 } 2802 2803 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2804 virt_memory_plug(hotplug_dev, dev, errp); 2805 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2806 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2807 } 2808 2809 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2810 PCIDevice *pdev = PCI_DEVICE(dev); 2811 2812 vms->iommu = VIRT_IOMMU_VIRTIO; 2813 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2814 create_virtio_iommu_dt_bindings(vms); 2815 } 2816 } 2817 2818 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, 2819 DeviceState *dev, Error **errp) 2820 { 2821 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2822 2823 if (!vms->acpi_dev) { 2824 error_setg(errp, 2825 "memory hotplug is not enabled: missing acpi-ged device"); 2826 return; 2827 } 2828 2829 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2830 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 2831 return; 2832 } 2833 2834 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, 2835 errp); 2836 } 2837 2838 static void virt_dimm_unplug(HotplugHandler *hotplug_dev, 2839 DeviceState *dev, Error **errp) 2840 { 2841 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2842 Error *local_err = NULL; 2843 2844 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); 2845 if (local_err) { 2846 goto out; 2847 } 2848 2849 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); 2850 qdev_unrealize(dev); 2851 2852 out: 2853 error_propagate(errp, local_err); 2854 } 2855 2856 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2857 DeviceState *dev, Error **errp) 2858 { 2859 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2860 virt_dimm_unplug_request(hotplug_dev, dev, errp); 2861 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2862 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 2863 errp); 2864 } else { 2865 error_setg(errp, "device unplug request for unsupported device" 2866 " type: %s", object_get_typename(OBJECT(dev))); 2867 } 2868 } 2869 2870 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2871 DeviceState *dev, Error **errp) 2872 { 2873 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2874 virt_dimm_unplug(hotplug_dev, dev, errp); 2875 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2876 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2877 } else { 2878 error_setg(errp, "virt: device unplug for unsupported device" 2879 " type: %s", object_get_typename(OBJECT(dev))); 2880 } 2881 } 2882 2883 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2884 DeviceState *dev) 2885 { 2886 MachineClass *mc = MACHINE_GET_CLASS(machine); 2887 2888 if (device_is_dynamic_sysbus(mc, dev) || 2889 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2890 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 2891 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2892 return HOTPLUG_HANDLER(machine); 2893 } 2894 return NULL; 2895 } 2896 2897 /* 2898 * for arm64 kvm_type [7-0] encodes the requested number of bits 2899 * in the IPA address space 2900 */ 2901 static int virt_kvm_type(MachineState *ms, const char *type_str) 2902 { 2903 VirtMachineState *vms = VIRT_MACHINE(ms); 2904 int max_vm_pa_size, requested_pa_size; 2905 bool fixed_ipa; 2906 2907 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 2908 2909 /* we freeze the memory map to compute the highest gpa */ 2910 virt_set_memmap(vms, max_vm_pa_size); 2911 2912 requested_pa_size = 64 - clz64(vms->highest_gpa); 2913 2914 /* 2915 * KVM requires the IPA size to be at least 32 bits. 2916 */ 2917 if (requested_pa_size < 32) { 2918 requested_pa_size = 32; 2919 } 2920 2921 if (requested_pa_size > max_vm_pa_size) { 2922 error_report("-m and ,maxmem option values " 2923 "require an IPA range (%d bits) larger than " 2924 "the one supported by the host (%d bits)", 2925 requested_pa_size, max_vm_pa_size); 2926 return -1; 2927 } 2928 /* 2929 * We return the requested PA log size, unless KVM only supports 2930 * the implicit legacy 40b IPA setting, in which case the kvm_type 2931 * must be 0. 2932 */ 2933 return fixed_ipa ? 0 : requested_pa_size; 2934 } 2935 2936 static void virt_machine_class_init(ObjectClass *oc, void *data) 2937 { 2938 MachineClass *mc = MACHINE_CLASS(oc); 2939 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2940 2941 mc->init = machvirt_init; 2942 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 2943 * The value may be reduced later when we have more information about the 2944 * configuration of the particular instance. 2945 */ 2946 mc->max_cpus = 512; 2947 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 2948 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 2949 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 2950 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 2951 #ifdef CONFIG_TPM 2952 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 2953 #endif 2954 mc->block_default_type = IF_VIRTIO; 2955 mc->no_cdrom = 1; 2956 mc->pci_allow_0_address = true; 2957 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 2958 mc->minimum_page_bits = 12; 2959 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 2960 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 2961 #ifdef CONFIG_TCG 2962 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 2963 #else 2964 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); 2965 #endif 2966 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 2967 mc->kvm_type = virt_kvm_type; 2968 assert(!mc->get_hotplug_handler); 2969 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 2970 hc->pre_plug = virt_machine_device_pre_plug_cb; 2971 hc->plug = virt_machine_device_plug_cb; 2972 hc->unplug_request = virt_machine_device_unplug_request_cb; 2973 hc->unplug = virt_machine_device_unplug_cb; 2974 mc->nvdimm_supported = true; 2975 mc->smp_props.clusters_supported = true; 2976 mc->auto_enable_numa_with_memhp = true; 2977 mc->auto_enable_numa_with_memdev = true; 2978 /* platform instead of architectural choice */ 2979 mc->cpu_cluster_has_numa_boundary = true; 2980 mc->default_ram_id = "mach-virt.ram"; 2981 mc->default_nic = "virtio-net-pci"; 2982 2983 object_class_property_add(oc, "acpi", "OnOffAuto", 2984 virt_get_acpi, virt_set_acpi, 2985 NULL, NULL); 2986 object_class_property_set_description(oc, "acpi", 2987 "Enable ACPI"); 2988 object_class_property_add_bool(oc, "secure", virt_get_secure, 2989 virt_set_secure); 2990 object_class_property_set_description(oc, "secure", 2991 "Set on/off to enable/disable the ARM " 2992 "Security Extensions (TrustZone)"); 2993 2994 object_class_property_add_bool(oc, "virtualization", virt_get_virt, 2995 virt_set_virt); 2996 object_class_property_set_description(oc, "virtualization", 2997 "Set on/off to enable/disable emulating a " 2998 "guest CPU which implements the ARM " 2999 "Virtualization Extensions"); 3000 3001 object_class_property_add_bool(oc, "highmem", virt_get_highmem, 3002 virt_set_highmem); 3003 object_class_property_set_description(oc, "highmem", 3004 "Set on/off to enable/disable using " 3005 "physical address space above 32 bits"); 3006 3007 object_class_property_add_bool(oc, "compact-highmem", 3008 virt_get_compact_highmem, 3009 virt_set_compact_highmem); 3010 object_class_property_set_description(oc, "compact-highmem", 3011 "Set on/off to enable/disable compact " 3012 "layout for high memory regions"); 3013 3014 object_class_property_add_bool(oc, "highmem-redists", 3015 virt_get_highmem_redists, 3016 virt_set_highmem_redists); 3017 object_class_property_set_description(oc, "highmem-redists", 3018 "Set on/off to enable/disable high " 3019 "memory region for GICv3 or GICv4 " 3020 "redistributor"); 3021 3022 object_class_property_add_bool(oc, "highmem-ecam", 3023 virt_get_highmem_ecam, 3024 virt_set_highmem_ecam); 3025 object_class_property_set_description(oc, "highmem-ecam", 3026 "Set on/off to enable/disable high " 3027 "memory region for PCI ECAM"); 3028 3029 object_class_property_add_bool(oc, "highmem-mmio", 3030 virt_get_highmem_mmio, 3031 virt_set_highmem_mmio); 3032 object_class_property_set_description(oc, "highmem-mmio", 3033 "Set on/off to enable/disable high " 3034 "memory region for PCI MMIO"); 3035 3036 object_class_property_add_str(oc, "gic-version", virt_get_gic_version, 3037 virt_set_gic_version); 3038 object_class_property_set_description(oc, "gic-version", 3039 "Set GIC version. " 3040 "Valid values are 2, 3, 4, host and max"); 3041 3042 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); 3043 object_class_property_set_description(oc, "iommu", 3044 "Set the IOMMU type. " 3045 "Valid values are none and smmuv3"); 3046 3047 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 3048 virt_get_default_bus_bypass_iommu, 3049 virt_set_default_bus_bypass_iommu); 3050 object_class_property_set_description(oc, "default-bus-bypass-iommu", 3051 "Set on/off to enable/disable " 3052 "bypass_iommu for default root bus"); 3053 3054 object_class_property_add_bool(oc, "ras", virt_get_ras, 3055 virt_set_ras); 3056 object_class_property_set_description(oc, "ras", 3057 "Set on/off to enable/disable reporting host memory errors " 3058 "to a KVM guest using ACPI and guest external abort exceptions"); 3059 3060 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); 3061 object_class_property_set_description(oc, "mte", 3062 "Set on/off to enable/disable emulating a " 3063 "guest CPU which implements the ARM " 3064 "Memory Tagging Extension"); 3065 3066 object_class_property_add_bool(oc, "its", virt_get_its, 3067 virt_set_its); 3068 object_class_property_set_description(oc, "its", 3069 "Set on/off to enable/disable " 3070 "ITS instantiation"); 3071 3072 object_class_property_add_bool(oc, "dtb-randomness", 3073 virt_get_dtb_randomness, 3074 virt_set_dtb_randomness); 3075 object_class_property_set_description(oc, "dtb-randomness", 3076 "Set off to disable passing random or " 3077 "non-deterministic dtb nodes to guest"); 3078 3079 object_class_property_add_bool(oc, "dtb-kaslr-seed", 3080 virt_get_dtb_randomness, 3081 virt_set_dtb_randomness); 3082 object_class_property_set_description(oc, "dtb-kaslr-seed", 3083 "Deprecated synonym of dtb-randomness"); 3084 3085 object_class_property_add_str(oc, "x-oem-id", 3086 virt_get_oem_id, 3087 virt_set_oem_id); 3088 object_class_property_set_description(oc, "x-oem-id", 3089 "Override the default value of field OEMID " 3090 "in ACPI table header." 3091 "The string may be up to 6 bytes in size"); 3092 3093 3094 object_class_property_add_str(oc, "x-oem-table-id", 3095 virt_get_oem_table_id, 3096 virt_set_oem_table_id); 3097 object_class_property_set_description(oc, "x-oem-table-id", 3098 "Override the default value of field OEM Table ID " 3099 "in ACPI table header." 3100 "The string may be up to 8 bytes in size"); 3101 3102 } 3103 3104 static void virt_instance_init(Object *obj) 3105 { 3106 VirtMachineState *vms = VIRT_MACHINE(obj); 3107 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 3108 3109 /* EL3 is disabled by default on virt: this makes us consistent 3110 * between KVM and TCG for this board, and it also allows us to 3111 * boot UEFI blobs which assume no TrustZone support. 3112 */ 3113 vms->secure = false; 3114 3115 /* EL2 is also disabled by default, for similar reasons */ 3116 vms->virt = false; 3117 3118 /* High memory is enabled by default */ 3119 vms->highmem = true; 3120 vms->highmem_compact = !vmc->no_highmem_compact; 3121 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 3122 3123 vms->highmem_ecam = !vmc->no_highmem_ecam; 3124 vms->highmem_mmio = true; 3125 vms->highmem_redists = true; 3126 3127 if (vmc->no_its) { 3128 vms->its = false; 3129 } else { 3130 /* Default allows ITS instantiation */ 3131 vms->its = true; 3132 3133 if (vmc->no_tcg_its) { 3134 vms->tcg_its = false; 3135 } else { 3136 vms->tcg_its = true; 3137 } 3138 } 3139 3140 /* Default disallows iommu instantiation */ 3141 vms->iommu = VIRT_IOMMU_NONE; 3142 3143 /* The default root bus is attached to iommu by default */ 3144 vms->default_bus_bypass_iommu = false; 3145 3146 /* Default disallows RAS instantiation */ 3147 vms->ras = false; 3148 3149 /* MTE is disabled by default. */ 3150 vms->mte = false; 3151 3152 /* Supply kaslr-seed and rng-seed by default */ 3153 vms->dtb_randomness = true; 3154 3155 vms->irqmap = a15irqmap; 3156 3157 virt_flash_create(vms); 3158 3159 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 3160 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 3161 } 3162 3163 static const TypeInfo virt_machine_info = { 3164 .name = TYPE_VIRT_MACHINE, 3165 .parent = TYPE_MACHINE, 3166 .abstract = true, 3167 .instance_size = sizeof(VirtMachineState), 3168 .class_size = sizeof(VirtMachineClass), 3169 .class_init = virt_machine_class_init, 3170 .instance_init = virt_instance_init, 3171 .interfaces = (InterfaceInfo[]) { 3172 { TYPE_HOTPLUG_HANDLER }, 3173 { } 3174 }, 3175 }; 3176 3177 static void machvirt_machine_init(void) 3178 { 3179 type_register_static(&virt_machine_info); 3180 } 3181 type_init(machvirt_machine_init); 3182 3183 static void virt_machine_8_2_options(MachineClass *mc) 3184 { 3185 } 3186 DEFINE_VIRT_MACHINE_AS_LATEST(8, 2) 3187 3188 static void virt_machine_8_1_options(MachineClass *mc) 3189 { 3190 virt_machine_8_2_options(mc); 3191 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len); 3192 } 3193 DEFINE_VIRT_MACHINE(8, 1) 3194 3195 static void virt_machine_8_0_options(MachineClass *mc) 3196 { 3197 virt_machine_8_1_options(mc); 3198 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 3199 } 3200 DEFINE_VIRT_MACHINE(8, 0) 3201 3202 static void virt_machine_7_2_options(MachineClass *mc) 3203 { 3204 virt_machine_8_0_options(mc); 3205 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 3206 } 3207 DEFINE_VIRT_MACHINE(7, 2) 3208 3209 static void virt_machine_7_1_options(MachineClass *mc) 3210 { 3211 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3212 3213 virt_machine_7_2_options(mc); 3214 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 3215 /* Compact layout for high memory regions was introduced with 7.2 */ 3216 vmc->no_highmem_compact = true; 3217 } 3218 DEFINE_VIRT_MACHINE(7, 1) 3219 3220 static void virt_machine_7_0_options(MachineClass *mc) 3221 { 3222 virt_machine_7_1_options(mc); 3223 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 3224 } 3225 DEFINE_VIRT_MACHINE(7, 0) 3226 3227 static void virt_machine_6_2_options(MachineClass *mc) 3228 { 3229 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3230 3231 virt_machine_7_0_options(mc); 3232 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 3233 vmc->no_tcg_lpa2 = true; 3234 } 3235 DEFINE_VIRT_MACHINE(6, 2) 3236 3237 static void virt_machine_6_1_options(MachineClass *mc) 3238 { 3239 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3240 3241 virt_machine_6_2_options(mc); 3242 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 3243 mc->smp_props.prefer_sockets = true; 3244 vmc->no_cpu_topology = true; 3245 3246 /* qemu ITS was introduced with 6.2 */ 3247 vmc->no_tcg_its = true; 3248 } 3249 DEFINE_VIRT_MACHINE(6, 1) 3250 3251 static void virt_machine_6_0_options(MachineClass *mc) 3252 { 3253 virt_machine_6_1_options(mc); 3254 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 3255 } 3256 DEFINE_VIRT_MACHINE(6, 0) 3257 3258 static void virt_machine_5_2_options(MachineClass *mc) 3259 { 3260 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3261 3262 virt_machine_6_0_options(mc); 3263 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 3264 vmc->no_secure_gpio = true; 3265 } 3266 DEFINE_VIRT_MACHINE(5, 2) 3267 3268 static void virt_machine_5_1_options(MachineClass *mc) 3269 { 3270 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3271 3272 virt_machine_5_2_options(mc); 3273 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 3274 vmc->no_kvm_steal_time = true; 3275 } 3276 DEFINE_VIRT_MACHINE(5, 1) 3277 3278 static void virt_machine_5_0_options(MachineClass *mc) 3279 { 3280 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3281 3282 virt_machine_5_1_options(mc); 3283 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 3284 mc->numa_mem_supported = true; 3285 vmc->acpi_expose_flash = true; 3286 mc->auto_enable_numa_with_memdev = false; 3287 } 3288 DEFINE_VIRT_MACHINE(5, 0) 3289 3290 static void virt_machine_4_2_options(MachineClass *mc) 3291 { 3292 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3293 3294 virt_machine_5_0_options(mc); 3295 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 3296 vmc->kvm_no_adjvtime = true; 3297 } 3298 DEFINE_VIRT_MACHINE(4, 2) 3299 3300 static void virt_machine_4_1_options(MachineClass *mc) 3301 { 3302 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3303 3304 virt_machine_4_2_options(mc); 3305 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 3306 vmc->no_ged = true; 3307 mc->auto_enable_numa_with_memhp = false; 3308 } 3309 DEFINE_VIRT_MACHINE(4, 1) 3310 3311 static void virt_machine_4_0_options(MachineClass *mc) 3312 { 3313 virt_machine_4_1_options(mc); 3314 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 3315 } 3316 DEFINE_VIRT_MACHINE(4, 0) 3317 3318 static void virt_machine_3_1_options(MachineClass *mc) 3319 { 3320 virt_machine_4_0_options(mc); 3321 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 3322 } 3323 DEFINE_VIRT_MACHINE(3, 1) 3324 3325 static void virt_machine_3_0_options(MachineClass *mc) 3326 { 3327 virt_machine_3_1_options(mc); 3328 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 3329 } 3330 DEFINE_VIRT_MACHINE(3, 0) 3331 3332 static void virt_machine_2_12_options(MachineClass *mc) 3333 { 3334 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3335 3336 virt_machine_3_0_options(mc); 3337 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 3338 vmc->no_highmem_ecam = true; 3339 mc->max_cpus = 255; 3340 } 3341 DEFINE_VIRT_MACHINE(2, 12) 3342 3343 static void virt_machine_2_11_options(MachineClass *mc) 3344 { 3345 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3346 3347 virt_machine_2_12_options(mc); 3348 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 3349 vmc->smbios_old_sys_ver = true; 3350 } 3351 DEFINE_VIRT_MACHINE(2, 11) 3352 3353 static void virt_machine_2_10_options(MachineClass *mc) 3354 { 3355 virt_machine_2_11_options(mc); 3356 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 3357 /* before 2.11 we never faulted accesses to bad addresses */ 3358 mc->ignore_memory_transaction_failures = true; 3359 } 3360 DEFINE_VIRT_MACHINE(2, 10) 3361 3362 static void virt_machine_2_9_options(MachineClass *mc) 3363 { 3364 virt_machine_2_10_options(mc); 3365 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 3366 } 3367 DEFINE_VIRT_MACHINE(2, 9) 3368 3369 static void virt_machine_2_8_options(MachineClass *mc) 3370 { 3371 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3372 3373 virt_machine_2_9_options(mc); 3374 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 3375 /* For 2.8 and earlier we falsely claimed in the DT that 3376 * our timers were edge-triggered, not level-triggered. 3377 */ 3378 vmc->claim_edge_triggered_timers = true; 3379 } 3380 DEFINE_VIRT_MACHINE(2, 8) 3381 3382 static void virt_machine_2_7_options(MachineClass *mc) 3383 { 3384 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3385 3386 virt_machine_2_8_options(mc); 3387 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 3388 /* ITS was introduced with 2.8 */ 3389 vmc->no_its = true; 3390 /* Stick with 1K pages for migration compatibility */ 3391 mc->minimum_page_bits = 0; 3392 } 3393 DEFINE_VIRT_MACHINE(2, 7) 3394 3395 static void virt_machine_2_6_options(MachineClass *mc) 3396 { 3397 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3398 3399 virt_machine_2_7_options(mc); 3400 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 3401 vmc->disallow_affinity_adjustment = true; 3402 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 3403 vmc->no_pmu = true; 3404 } 3405 DEFINE_VIRT_MACHINE(2, 6) 3406