1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qapi/error.h" 33 #include "hw/sysbus.h" 34 #include "hw/arm/arm.h" 35 #include "hw/arm/primecell.h" 36 #include "hw/arm/virt.h" 37 #include "hw/devices.h" 38 #include "net/net.h" 39 #include "sysemu/block-backend.h" 40 #include "sysemu/device_tree.h" 41 #include "sysemu/numa.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/kvm.h" 44 #include "hw/boards.h" 45 #include "hw/compat.h" 46 #include "hw/loader.h" 47 #include "exec/address-spaces.h" 48 #include "qemu/bitops.h" 49 #include "qemu/error-report.h" 50 #include "hw/pci-host/gpex.h" 51 #include "hw/arm/virt-acpi-build.h" 52 #include "hw/arm/sysbus-fdt.h" 53 #include "hw/platform-bus.h" 54 #include "hw/arm/fdt.h" 55 #include "hw/intc/arm_gic.h" 56 #include "hw/intc/arm_gicv3_common.h" 57 #include "kvm_arm.h" 58 #include "hw/smbios/smbios.h" 59 #include "qapi/visitor.h" 60 #include "standard-headers/linux/input.h" 61 62 /* Number of external interrupt lines to configure the GIC with */ 63 #define NUM_IRQS 256 64 65 #define PLATFORM_BUS_NUM_IRQS 64 66 67 static ARMPlatformBusSystemParams platform_bus_params; 68 69 typedef struct VirtBoardInfo { 70 struct arm_boot_info bootinfo; 71 const char *cpu_model; 72 const MemMapEntry *memmap; 73 const int *irqmap; 74 int smp_cpus; 75 void *fdt; 76 int fdt_size; 77 uint32_t clock_phandle; 78 uint32_t gic_phandle; 79 uint32_t msi_phandle; 80 bool using_psci; 81 } VirtBoardInfo; 82 83 typedef struct { 84 MachineClass parent; 85 VirtBoardInfo *daughterboard; 86 bool disallow_affinity_adjustment; 87 bool no_its; 88 } VirtMachineClass; 89 90 typedef struct { 91 MachineState parent; 92 bool secure; 93 bool highmem; 94 int32_t gic_version; 95 } VirtMachineState; 96 97 #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt") 98 #define VIRT_MACHINE(obj) \ 99 OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE) 100 #define VIRT_MACHINE_GET_CLASS(obj) \ 101 OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE) 102 #define VIRT_MACHINE_CLASS(klass) \ 103 OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE) 104 105 106 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 107 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 108 void *data) \ 109 { \ 110 MachineClass *mc = MACHINE_CLASS(oc); \ 111 virt_machine_##major##_##minor##_options(mc); \ 112 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 113 if (latest) { \ 114 mc->alias = "virt"; \ 115 } \ 116 } \ 117 static const TypeInfo machvirt_##major##_##minor##_info = { \ 118 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 119 .parent = TYPE_VIRT_MACHINE, \ 120 .instance_init = virt_##major##_##minor##_instance_init, \ 121 .class_init = virt_##major##_##minor##_class_init, \ 122 }; \ 123 static void machvirt_machine_##major##_##minor##_init(void) \ 124 { \ 125 type_register_static(&machvirt_##major##_##minor##_info); \ 126 } \ 127 type_init(machvirt_machine_##major##_##minor##_init); 128 129 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 130 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 131 #define DEFINE_VIRT_MACHINE(major, minor) \ 132 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 133 134 135 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means 136 * RAM can go up to the 256GB mark, leaving 256GB of the physical 137 * address space unallocated and free for future use between 256G and 512G. 138 * If we need to provide more RAM to VMs in the future then we need to: 139 * * allocate a second bank of RAM starting at 2TB and working up 140 * * fix the DT and ACPI table generation code in QEMU to correctly 141 * report two split lumps of RAM to the guest 142 * * fix KVM in the host kernel to allow guests with >40 bit address spaces 143 * (We don't want to fill all the way up to 512GB with RAM because 144 * we might want it for non-RAM purposes later. Conversely it seems 145 * reasonable to assume that anybody configuring a VM with a quarter 146 * of a terabyte of RAM will be doing it on a host with more than a 147 * terabyte of physical address space.) 148 */ 149 #define RAMLIMIT_GB 255 150 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) 151 152 /* Addresses and sizes of our components. 153 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 154 * 128MB..256MB is used for miscellaneous device I/O. 155 * 256MB..1GB is reserved for possible future PCI support (ie where the 156 * PCI memory window will go if we add a PCI host controller). 157 * 1GB and up is RAM (which may happily spill over into the 158 * high memory region beyond 4GB). 159 * This represents a compromise between how much RAM can be given to 160 * a 32 bit VM and leaving space for expansion and in particular for PCI. 161 * Note that devices should generally be placed at multiples of 0x10000, 162 * to accommodate guests using 64K pages. 163 */ 164 static const MemMapEntry a15memmap[] = { 165 /* Space up to 0x8000000 is reserved for a boot ROM */ 166 [VIRT_FLASH] = { 0, 0x08000000 }, 167 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 168 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 169 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 170 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 171 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 172 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 173 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 174 /* This redistributor space allows up to 2*64kB*123 CPUs */ 175 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 176 [VIRT_UART] = { 0x09000000, 0x00001000 }, 177 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 178 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 179 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 180 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 181 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 182 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 183 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 184 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 185 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 186 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 187 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 188 [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES }, 189 /* Second PCIe window, 512GB wide at the 512GB boundary */ 190 [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL }, 191 }; 192 193 static const int a15irqmap[] = { 194 [VIRT_UART] = 1, 195 [VIRT_RTC] = 2, 196 [VIRT_PCIE] = 3, /* ... to 6 */ 197 [VIRT_GPIO] = 7, 198 [VIRT_SECURE_UART] = 8, 199 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 200 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 201 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 202 }; 203 204 static VirtBoardInfo machines[] = { 205 { 206 .cpu_model = "cortex-a15", 207 .memmap = a15memmap, 208 .irqmap = a15irqmap, 209 }, 210 { 211 .cpu_model = "cortex-a53", 212 .memmap = a15memmap, 213 .irqmap = a15irqmap, 214 }, 215 { 216 .cpu_model = "cortex-a57", 217 .memmap = a15memmap, 218 .irqmap = a15irqmap, 219 }, 220 { 221 .cpu_model = "host", 222 .memmap = a15memmap, 223 .irqmap = a15irqmap, 224 }, 225 }; 226 227 static VirtBoardInfo *find_machine_info(const char *cpu) 228 { 229 int i; 230 231 for (i = 0; i < ARRAY_SIZE(machines); i++) { 232 if (strcmp(cpu, machines[i].cpu_model) == 0) { 233 return &machines[i]; 234 } 235 } 236 return NULL; 237 } 238 239 static void create_fdt(VirtBoardInfo *vbi) 240 { 241 void *fdt = create_device_tree(&vbi->fdt_size); 242 243 if (!fdt) { 244 error_report("create_device_tree() failed"); 245 exit(1); 246 } 247 248 vbi->fdt = fdt; 249 250 /* Header */ 251 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 252 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 253 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 254 255 /* 256 * /chosen and /memory nodes must exist for load_dtb 257 * to fill in necessary properties later 258 */ 259 qemu_fdt_add_subnode(fdt, "/chosen"); 260 qemu_fdt_add_subnode(fdt, "/memory"); 261 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 262 263 /* Clock node, for the benefit of the UART. The kernel device tree 264 * binding documentation claims the PL011 node clock properties are 265 * optional but in practice if you omit them the kernel refuses to 266 * probe for the device. 267 */ 268 vbi->clock_phandle = qemu_fdt_alloc_phandle(fdt); 269 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 270 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 271 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 272 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 273 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 274 "clk24mhz"); 275 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vbi->clock_phandle); 276 277 } 278 279 static void fdt_add_psci_node(const VirtBoardInfo *vbi) 280 { 281 uint32_t cpu_suspend_fn; 282 uint32_t cpu_off_fn; 283 uint32_t cpu_on_fn; 284 uint32_t migrate_fn; 285 void *fdt = vbi->fdt; 286 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 287 288 if (!vbi->using_psci) { 289 return; 290 } 291 292 qemu_fdt_add_subnode(fdt, "/psci"); 293 if (armcpu->psci_version == 2) { 294 const char comp[] = "arm,psci-0.2\0arm,psci"; 295 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 296 297 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 298 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 299 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 300 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 301 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 302 } else { 303 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 304 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 305 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 306 } 307 } else { 308 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 309 310 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 311 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 312 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 313 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 314 } 315 316 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 317 * to the instruction that should be used to invoke PSCI functions. 318 * However, the device tree binding uses 'method' instead, so that is 319 * what we should use here. 320 */ 321 qemu_fdt_setprop_string(fdt, "/psci", "method", "hvc"); 322 323 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 324 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 325 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 326 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 327 } 328 329 static void fdt_add_timer_nodes(const VirtBoardInfo *vbi, int gictype) 330 { 331 /* Note that on A15 h/w these interrupts are level-triggered, 332 * but for the GIC implementation provided by both QEMU and KVM 333 * they are edge-triggered. 334 */ 335 ARMCPU *armcpu; 336 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 337 338 if (gictype == 2) { 339 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 340 GIC_FDT_IRQ_PPI_CPU_WIDTH, 341 (1 << vbi->smp_cpus) - 1); 342 } 343 344 qemu_fdt_add_subnode(vbi->fdt, "/timer"); 345 346 armcpu = ARM_CPU(qemu_get_cpu(0)); 347 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 348 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 349 qemu_fdt_setprop(vbi->fdt, "/timer", "compatible", 350 compat, sizeof(compat)); 351 } else { 352 qemu_fdt_setprop_string(vbi->fdt, "/timer", "compatible", 353 "arm,armv7-timer"); 354 } 355 qemu_fdt_setprop(vbi->fdt, "/timer", "always-on", NULL, 0); 356 qemu_fdt_setprop_cells(vbi->fdt, "/timer", "interrupts", 357 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 358 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 359 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 360 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 361 } 362 363 static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi) 364 { 365 int cpu; 366 int addr_cells = 1; 367 unsigned int i; 368 369 /* 370 * From Documentation/devicetree/bindings/arm/cpus.txt 371 * On ARM v8 64-bit systems value should be set to 2, 372 * that corresponds to the MPIDR_EL1 register size. 373 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 374 * in the system, #address-cells can be set to 1, since 375 * MPIDR_EL1[63:32] bits are not used for CPUs 376 * identification. 377 * 378 * Here we actually don't know whether our system is 32- or 64-bit one. 379 * The simplest way to go is to examine affinity IDs of all our CPUs. If 380 * at least one of them has Aff3 populated, we set #address-cells to 2. 381 */ 382 for (cpu = 0; cpu < vbi->smp_cpus; cpu++) { 383 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 384 385 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 386 addr_cells = 2; 387 break; 388 } 389 } 390 391 qemu_fdt_add_subnode(vbi->fdt, "/cpus"); 392 qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#address-cells", addr_cells); 393 qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#size-cells", 0x0); 394 395 for (cpu = vbi->smp_cpus - 1; cpu >= 0; cpu--) { 396 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 397 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 398 399 qemu_fdt_add_subnode(vbi->fdt, nodename); 400 qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "cpu"); 401 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", 402 armcpu->dtb_compatible); 403 404 if (vbi->using_psci && vbi->smp_cpus > 1) { 405 qemu_fdt_setprop_string(vbi->fdt, nodename, 406 "enable-method", "psci"); 407 } 408 409 if (addr_cells == 2) { 410 qemu_fdt_setprop_u64(vbi->fdt, nodename, "reg", 411 armcpu->mp_affinity); 412 } else { 413 qemu_fdt_setprop_cell(vbi->fdt, nodename, "reg", 414 armcpu->mp_affinity); 415 } 416 417 i = numa_get_node_for_cpu(cpu); 418 if (i < nb_numa_nodes) { 419 qemu_fdt_setprop_cell(vbi->fdt, nodename, "numa-node-id", i); 420 } 421 422 g_free(nodename); 423 } 424 } 425 426 static void fdt_add_its_gic_node(VirtBoardInfo *vbi) 427 { 428 vbi->msi_phandle = qemu_fdt_alloc_phandle(vbi->fdt); 429 qemu_fdt_add_subnode(vbi->fdt, "/intc/its"); 430 qemu_fdt_setprop_string(vbi->fdt, "/intc/its", "compatible", 431 "arm,gic-v3-its"); 432 qemu_fdt_setprop(vbi->fdt, "/intc/its", "msi-controller", NULL, 0); 433 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc/its", "reg", 434 2, vbi->memmap[VIRT_GIC_ITS].base, 435 2, vbi->memmap[VIRT_GIC_ITS].size); 436 qemu_fdt_setprop_cell(vbi->fdt, "/intc/its", "phandle", vbi->msi_phandle); 437 } 438 439 static void fdt_add_v2m_gic_node(VirtBoardInfo *vbi) 440 { 441 vbi->msi_phandle = qemu_fdt_alloc_phandle(vbi->fdt); 442 qemu_fdt_add_subnode(vbi->fdt, "/intc/v2m"); 443 qemu_fdt_setprop_string(vbi->fdt, "/intc/v2m", "compatible", 444 "arm,gic-v2m-frame"); 445 qemu_fdt_setprop(vbi->fdt, "/intc/v2m", "msi-controller", NULL, 0); 446 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc/v2m", "reg", 447 2, vbi->memmap[VIRT_GIC_V2M].base, 448 2, vbi->memmap[VIRT_GIC_V2M].size); 449 qemu_fdt_setprop_cell(vbi->fdt, "/intc/v2m", "phandle", vbi->msi_phandle); 450 } 451 452 static void fdt_add_gic_node(VirtBoardInfo *vbi, int type) 453 { 454 vbi->gic_phandle = qemu_fdt_alloc_phandle(vbi->fdt); 455 qemu_fdt_setprop_cell(vbi->fdt, "/", "interrupt-parent", vbi->gic_phandle); 456 457 qemu_fdt_add_subnode(vbi->fdt, "/intc"); 458 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#interrupt-cells", 3); 459 qemu_fdt_setprop(vbi->fdt, "/intc", "interrupt-controller", NULL, 0); 460 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#address-cells", 0x2); 461 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#size-cells", 0x2); 462 qemu_fdt_setprop(vbi->fdt, "/intc", "ranges", NULL, 0); 463 if (type == 3) { 464 qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", 465 "arm,gic-v3"); 466 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", 467 2, vbi->memmap[VIRT_GIC_DIST].base, 468 2, vbi->memmap[VIRT_GIC_DIST].size, 469 2, vbi->memmap[VIRT_GIC_REDIST].base, 470 2, vbi->memmap[VIRT_GIC_REDIST].size); 471 } else { 472 /* 'cortex-a15-gic' means 'GIC v2' */ 473 qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", 474 "arm,cortex-a15-gic"); 475 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", 476 2, vbi->memmap[VIRT_GIC_DIST].base, 477 2, vbi->memmap[VIRT_GIC_DIST].size, 478 2, vbi->memmap[VIRT_GIC_CPU].base, 479 2, vbi->memmap[VIRT_GIC_CPU].size); 480 } 481 482 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", vbi->gic_phandle); 483 } 484 485 static void fdt_add_pmu_nodes(const VirtBoardInfo *vbi, int gictype) 486 { 487 CPUState *cpu; 488 ARMCPU *armcpu; 489 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 490 491 CPU_FOREACH(cpu) { 492 armcpu = ARM_CPU(cpu); 493 if (!armcpu->has_pmu || 494 !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ))) { 495 return; 496 } 497 } 498 499 if (gictype == 2) { 500 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 501 GIC_FDT_IRQ_PPI_CPU_WIDTH, 502 (1 << vbi->smp_cpus) - 1); 503 } 504 505 armcpu = ARM_CPU(qemu_get_cpu(0)); 506 qemu_fdt_add_subnode(vbi->fdt, "/pmu"); 507 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 508 const char compat[] = "arm,armv8-pmuv3"; 509 qemu_fdt_setprop(vbi->fdt, "/pmu", "compatible", 510 compat, sizeof(compat)); 511 qemu_fdt_setprop_cells(vbi->fdt, "/pmu", "interrupts", 512 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 513 } 514 } 515 516 static void create_its(VirtBoardInfo *vbi, DeviceState *gicdev) 517 { 518 const char *itsclass = its_class_name(); 519 DeviceState *dev; 520 521 if (!itsclass) { 522 /* Do nothing if not supported */ 523 return; 524 } 525 526 dev = qdev_create(NULL, itsclass); 527 528 object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3", 529 &error_abort); 530 qdev_init_nofail(dev); 531 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vbi->memmap[VIRT_GIC_ITS].base); 532 533 fdt_add_its_gic_node(vbi); 534 } 535 536 static void create_v2m(VirtBoardInfo *vbi, qemu_irq *pic) 537 { 538 int i; 539 int irq = vbi->irqmap[VIRT_GIC_V2M]; 540 DeviceState *dev; 541 542 dev = qdev_create(NULL, "arm-gicv2m"); 543 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vbi->memmap[VIRT_GIC_V2M].base); 544 qdev_prop_set_uint32(dev, "base-spi", irq); 545 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 546 qdev_init_nofail(dev); 547 548 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 549 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 550 } 551 552 fdt_add_v2m_gic_node(vbi); 553 } 554 555 static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic, int type, 556 bool secure, bool no_its) 557 { 558 /* We create a standalone GIC */ 559 DeviceState *gicdev; 560 SysBusDevice *gicbusdev; 561 const char *gictype; 562 int i; 563 564 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 565 566 gicdev = qdev_create(NULL, gictype); 567 qdev_prop_set_uint32(gicdev, "revision", type); 568 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 569 /* Note that the num-irq property counts both internal and external 570 * interrupts; there are always 32 of the former (mandated by GIC spec). 571 */ 572 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 573 if (!kvm_irqchip_in_kernel()) { 574 qdev_prop_set_bit(gicdev, "has-security-extensions", secure); 575 } 576 qdev_init_nofail(gicdev); 577 gicbusdev = SYS_BUS_DEVICE(gicdev); 578 sysbus_mmio_map(gicbusdev, 0, vbi->memmap[VIRT_GIC_DIST].base); 579 if (type == 3) { 580 sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_REDIST].base); 581 } else { 582 sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base); 583 } 584 585 /* Wire the outputs from each CPU's generic timer to the 586 * appropriate GIC PPI inputs, and the GIC's IRQ output to 587 * the CPU's IRQ input. 588 */ 589 for (i = 0; i < smp_cpus; i++) { 590 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 591 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 592 int irq; 593 /* Mapping from the output timer irq lines from the CPU to the 594 * GIC PPI inputs we use for the virt board. 595 */ 596 const int timer_irq[] = { 597 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 598 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 599 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 600 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 601 }; 602 603 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 604 qdev_connect_gpio_out(cpudev, irq, 605 qdev_get_gpio_in(gicdev, 606 ppibase + timer_irq[irq])); 607 } 608 609 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 610 sysbus_connect_irq(gicbusdev, i + smp_cpus, 611 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 612 } 613 614 for (i = 0; i < NUM_IRQS; i++) { 615 pic[i] = qdev_get_gpio_in(gicdev, i); 616 } 617 618 fdt_add_gic_node(vbi, type); 619 620 if (type == 3 && !no_its) { 621 create_its(vbi, gicdev); 622 } else if (type == 2) { 623 create_v2m(vbi, pic); 624 } 625 } 626 627 static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic, int uart, 628 MemoryRegion *mem, CharDriverState *chr) 629 { 630 char *nodename; 631 hwaddr base = vbi->memmap[uart].base; 632 hwaddr size = vbi->memmap[uart].size; 633 int irq = vbi->irqmap[uart]; 634 const char compat[] = "arm,pl011\0arm,primecell"; 635 const char clocknames[] = "uartclk\0apb_pclk"; 636 DeviceState *dev = qdev_create(NULL, "pl011"); 637 SysBusDevice *s = SYS_BUS_DEVICE(dev); 638 639 qdev_prop_set_chr(dev, "chardev", chr); 640 qdev_init_nofail(dev); 641 memory_region_add_subregion(mem, base, 642 sysbus_mmio_get_region(s, 0)); 643 sysbus_connect_irq(s, 0, pic[irq]); 644 645 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 646 qemu_fdt_add_subnode(vbi->fdt, nodename); 647 /* Note that we can't use setprop_string because of the embedded NUL */ 648 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", 649 compat, sizeof(compat)); 650 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 651 2, base, 2, size); 652 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 653 GIC_FDT_IRQ_TYPE_SPI, irq, 654 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 655 qemu_fdt_setprop_cells(vbi->fdt, nodename, "clocks", 656 vbi->clock_phandle, vbi->clock_phandle); 657 qemu_fdt_setprop(vbi->fdt, nodename, "clock-names", 658 clocknames, sizeof(clocknames)); 659 660 if (uart == VIRT_UART) { 661 qemu_fdt_setprop_string(vbi->fdt, "/chosen", "stdout-path", nodename); 662 } else { 663 /* Mark as not usable by the normal world */ 664 qemu_fdt_setprop_string(vbi->fdt, nodename, "status", "disabled"); 665 qemu_fdt_setprop_string(vbi->fdt, nodename, "secure-status", "okay"); 666 } 667 668 g_free(nodename); 669 } 670 671 static void create_rtc(const VirtBoardInfo *vbi, qemu_irq *pic) 672 { 673 char *nodename; 674 hwaddr base = vbi->memmap[VIRT_RTC].base; 675 hwaddr size = vbi->memmap[VIRT_RTC].size; 676 int irq = vbi->irqmap[VIRT_RTC]; 677 const char compat[] = "arm,pl031\0arm,primecell"; 678 679 sysbus_create_simple("pl031", base, pic[irq]); 680 681 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 682 qemu_fdt_add_subnode(vbi->fdt, nodename); 683 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat)); 684 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 685 2, base, 2, size); 686 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 687 GIC_FDT_IRQ_TYPE_SPI, irq, 688 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 689 qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle); 690 qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk"); 691 g_free(nodename); 692 } 693 694 static DeviceState *gpio_key_dev; 695 static void virt_powerdown_req(Notifier *n, void *opaque) 696 { 697 /* use gpio Pin 3 for power button event */ 698 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 699 } 700 701 static Notifier virt_system_powerdown_notifier = { 702 .notify = virt_powerdown_req 703 }; 704 705 static void create_gpio(const VirtBoardInfo *vbi, qemu_irq *pic) 706 { 707 char *nodename; 708 DeviceState *pl061_dev; 709 hwaddr base = vbi->memmap[VIRT_GPIO].base; 710 hwaddr size = vbi->memmap[VIRT_GPIO].size; 711 int irq = vbi->irqmap[VIRT_GPIO]; 712 const char compat[] = "arm,pl061\0arm,primecell"; 713 714 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); 715 716 uint32_t phandle = qemu_fdt_alloc_phandle(vbi->fdt); 717 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 718 qemu_fdt_add_subnode(vbi->fdt, nodename); 719 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 720 2, base, 2, size); 721 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat)); 722 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#gpio-cells", 2); 723 qemu_fdt_setprop(vbi->fdt, nodename, "gpio-controller", NULL, 0); 724 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 725 GIC_FDT_IRQ_TYPE_SPI, irq, 726 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 727 qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle); 728 qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk"); 729 qemu_fdt_setprop_cell(vbi->fdt, nodename, "phandle", phandle); 730 731 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 732 qdev_get_gpio_in(pl061_dev, 3)); 733 qemu_fdt_add_subnode(vbi->fdt, "/gpio-keys"); 734 qemu_fdt_setprop_string(vbi->fdt, "/gpio-keys", "compatible", "gpio-keys"); 735 qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys", "#size-cells", 0); 736 qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys", "#address-cells", 1); 737 738 qemu_fdt_add_subnode(vbi->fdt, "/gpio-keys/poweroff"); 739 qemu_fdt_setprop_string(vbi->fdt, "/gpio-keys/poweroff", 740 "label", "GPIO Key Poweroff"); 741 qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys/poweroff", "linux,code", 742 KEY_POWER); 743 qemu_fdt_setprop_cells(vbi->fdt, "/gpio-keys/poweroff", 744 "gpios", phandle, 3, 0); 745 746 /* connect powerdown request */ 747 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier); 748 749 g_free(nodename); 750 } 751 752 static void create_virtio_devices(const VirtBoardInfo *vbi, qemu_irq *pic) 753 { 754 int i; 755 hwaddr size = vbi->memmap[VIRT_MMIO].size; 756 757 /* We create the transports in forwards order. Since qbus_realize() 758 * prepends (not appends) new child buses, the incrementing loop below will 759 * create a list of virtio-mmio buses with decreasing base addresses. 760 * 761 * When a -device option is processed from the command line, 762 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 763 * order. The upshot is that -device options in increasing command line 764 * order are mapped to virtio-mmio buses with decreasing base addresses. 765 * 766 * When this code was originally written, that arrangement ensured that the 767 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 768 * the first -device on the command line. (The end-to-end order is a 769 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 770 * guest kernel's name-to-address assignment strategy.) 771 * 772 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 773 * the message, if not necessarily the code, of commit 70161ff336. 774 * Therefore the loop now establishes the inverse of the original intent. 775 * 776 * Unfortunately, we can't counteract the kernel change by reversing the 777 * loop; it would break existing command lines. 778 * 779 * In any case, the kernel makes no guarantee about the stability of 780 * enumeration order of virtio devices (as demonstrated by it changing 781 * between kernel versions). For reliable and stable identification 782 * of disks users must use UUIDs or similar mechanisms. 783 */ 784 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 785 int irq = vbi->irqmap[VIRT_MMIO] + i; 786 hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size; 787 788 sysbus_create_simple("virtio-mmio", base, pic[irq]); 789 } 790 791 /* We add dtb nodes in reverse order so that they appear in the finished 792 * device tree lowest address first. 793 * 794 * Note that this mapping is independent of the loop above. The previous 795 * loop influences virtio device to virtio transport assignment, whereas 796 * this loop controls how virtio transports are laid out in the dtb. 797 */ 798 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 799 char *nodename; 800 int irq = vbi->irqmap[VIRT_MMIO] + i; 801 hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size; 802 803 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 804 qemu_fdt_add_subnode(vbi->fdt, nodename); 805 qemu_fdt_setprop_string(vbi->fdt, nodename, 806 "compatible", "virtio,mmio"); 807 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 808 2, base, 2, size); 809 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 810 GIC_FDT_IRQ_TYPE_SPI, irq, 811 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 812 g_free(nodename); 813 } 814 } 815 816 static void create_one_flash(const char *name, hwaddr flashbase, 817 hwaddr flashsize, const char *file, 818 MemoryRegion *sysmem) 819 { 820 /* Create and map a single flash device. We use the same 821 * parameters as the flash devices on the Versatile Express board. 822 */ 823 DriveInfo *dinfo = drive_get_next(IF_PFLASH); 824 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 825 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 826 const uint64_t sectorlength = 256 * 1024; 827 828 if (dinfo) { 829 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 830 &error_abort); 831 } 832 833 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); 834 qdev_prop_set_uint64(dev, "sector-length", sectorlength); 835 qdev_prop_set_uint8(dev, "width", 4); 836 qdev_prop_set_uint8(dev, "device-width", 2); 837 qdev_prop_set_bit(dev, "big-endian", false); 838 qdev_prop_set_uint16(dev, "id0", 0x89); 839 qdev_prop_set_uint16(dev, "id1", 0x18); 840 qdev_prop_set_uint16(dev, "id2", 0x00); 841 qdev_prop_set_uint16(dev, "id3", 0x00); 842 qdev_prop_set_string(dev, "name", name); 843 qdev_init_nofail(dev); 844 845 memory_region_add_subregion(sysmem, flashbase, 846 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 847 848 if (file) { 849 char *fn; 850 int image_size; 851 852 if (drive_get(IF_PFLASH, 0, 0)) { 853 error_report("The contents of the first flash device may be " 854 "specified with -bios or with -drive if=pflash... " 855 "but you cannot use both options at once"); 856 exit(1); 857 } 858 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file); 859 if (!fn) { 860 error_report("Could not find ROM image '%s'", file); 861 exit(1); 862 } 863 image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0)); 864 g_free(fn); 865 if (image_size < 0) { 866 error_report("Could not load ROM image '%s'", file); 867 exit(1); 868 } 869 } 870 } 871 872 static void create_flash(const VirtBoardInfo *vbi, 873 MemoryRegion *sysmem, 874 MemoryRegion *secure_sysmem) 875 { 876 /* Create two flash devices to fill the VIRT_FLASH space in the memmap. 877 * Any file passed via -bios goes in the first of these. 878 * sysmem is the system memory space. secure_sysmem is the secure view 879 * of the system, and the first flash device should be made visible only 880 * there. The second flash device is visible to both secure and nonsecure. 881 * If sysmem == secure_sysmem this means there is no separate Secure 882 * address space and both flash devices are generally visible. 883 */ 884 hwaddr flashsize = vbi->memmap[VIRT_FLASH].size / 2; 885 hwaddr flashbase = vbi->memmap[VIRT_FLASH].base; 886 char *nodename; 887 888 create_one_flash("virt.flash0", flashbase, flashsize, 889 bios_name, secure_sysmem); 890 create_one_flash("virt.flash1", flashbase + flashsize, flashsize, 891 NULL, sysmem); 892 893 if (sysmem == secure_sysmem) { 894 /* Report both flash devices as a single node in the DT */ 895 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 896 qemu_fdt_add_subnode(vbi->fdt, nodename); 897 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash"); 898 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 899 2, flashbase, 2, flashsize, 900 2, flashbase + flashsize, 2, flashsize); 901 qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4); 902 g_free(nodename); 903 } else { 904 /* Report the devices as separate nodes so we can mark one as 905 * only visible to the secure world. 906 */ 907 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 908 qemu_fdt_add_subnode(vbi->fdt, nodename); 909 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash"); 910 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 911 2, flashbase, 2, flashsize); 912 qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4); 913 qemu_fdt_setprop_string(vbi->fdt, nodename, "status", "disabled"); 914 qemu_fdt_setprop_string(vbi->fdt, nodename, "secure-status", "okay"); 915 g_free(nodename); 916 917 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 918 qemu_fdt_add_subnode(vbi->fdt, nodename); 919 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash"); 920 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 921 2, flashbase + flashsize, 2, flashsize); 922 qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4); 923 g_free(nodename); 924 } 925 } 926 927 static void create_fw_cfg(const VirtBoardInfo *vbi, AddressSpace *as) 928 { 929 hwaddr base = vbi->memmap[VIRT_FW_CFG].base; 930 hwaddr size = vbi->memmap[VIRT_FW_CFG].size; 931 char *nodename; 932 933 fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 934 935 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 936 qemu_fdt_add_subnode(vbi->fdt, nodename); 937 qemu_fdt_setprop_string(vbi->fdt, nodename, 938 "compatible", "qemu,fw-cfg-mmio"); 939 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 940 2, base, 2, size); 941 g_free(nodename); 942 } 943 944 static void create_pcie_irq_map(const VirtBoardInfo *vbi, uint32_t gic_phandle, 945 int first_irq, const char *nodename) 946 { 947 int devfn, pin; 948 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 949 uint32_t *irq_map = full_irq_map; 950 951 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 952 for (pin = 0; pin < 4; pin++) { 953 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 954 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 955 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 956 int i; 957 958 uint32_t map[] = { 959 devfn << 8, 0, 0, /* devfn */ 960 pin + 1, /* PCI pin */ 961 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 962 963 /* Convert map to big endian */ 964 for (i = 0; i < 10; i++) { 965 irq_map[i] = cpu_to_be32(map[i]); 966 } 967 irq_map += 10; 968 } 969 } 970 971 qemu_fdt_setprop(vbi->fdt, nodename, "interrupt-map", 972 full_irq_map, sizeof(full_irq_map)); 973 974 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupt-map-mask", 975 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 976 0x7 /* PCI irq */); 977 } 978 979 static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic, 980 bool use_highmem) 981 { 982 hwaddr base_mmio = vbi->memmap[VIRT_PCIE_MMIO].base; 983 hwaddr size_mmio = vbi->memmap[VIRT_PCIE_MMIO].size; 984 hwaddr base_mmio_high = vbi->memmap[VIRT_PCIE_MMIO_HIGH].base; 985 hwaddr size_mmio_high = vbi->memmap[VIRT_PCIE_MMIO_HIGH].size; 986 hwaddr base_pio = vbi->memmap[VIRT_PCIE_PIO].base; 987 hwaddr size_pio = vbi->memmap[VIRT_PCIE_PIO].size; 988 hwaddr base_ecam = vbi->memmap[VIRT_PCIE_ECAM].base; 989 hwaddr size_ecam = vbi->memmap[VIRT_PCIE_ECAM].size; 990 hwaddr base = base_mmio; 991 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 992 int irq = vbi->irqmap[VIRT_PCIE]; 993 MemoryRegion *mmio_alias; 994 MemoryRegion *mmio_reg; 995 MemoryRegion *ecam_alias; 996 MemoryRegion *ecam_reg; 997 DeviceState *dev; 998 char *nodename; 999 int i; 1000 PCIHostState *pci; 1001 1002 dev = qdev_create(NULL, TYPE_GPEX_HOST); 1003 qdev_init_nofail(dev); 1004 1005 /* Map only the first size_ecam bytes of ECAM space */ 1006 ecam_alias = g_new0(MemoryRegion, 1); 1007 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1008 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1009 ecam_reg, 0, size_ecam); 1010 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1011 1012 /* Map the MMIO window into system address space so as to expose 1013 * the section of PCI MMIO space which starts at the same base address 1014 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1015 * the window). 1016 */ 1017 mmio_alias = g_new0(MemoryRegion, 1); 1018 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1019 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1020 mmio_reg, base_mmio, size_mmio); 1021 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1022 1023 if (use_highmem) { 1024 /* Map high MMIO space */ 1025 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1026 1027 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1028 mmio_reg, base_mmio_high, size_mmio_high); 1029 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1030 high_mmio_alias); 1031 } 1032 1033 /* Map IO port space */ 1034 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1035 1036 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1037 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 1038 } 1039 1040 pci = PCI_HOST_BRIDGE(dev); 1041 if (pci->bus) { 1042 for (i = 0; i < nb_nics; i++) { 1043 NICInfo *nd = &nd_table[i]; 1044 1045 if (!nd->model) { 1046 nd->model = g_strdup("virtio"); 1047 } 1048 1049 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1050 } 1051 } 1052 1053 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1054 qemu_fdt_add_subnode(vbi->fdt, nodename); 1055 qemu_fdt_setprop_string(vbi->fdt, nodename, 1056 "compatible", "pci-host-ecam-generic"); 1057 qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "pci"); 1058 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#address-cells", 3); 1059 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#size-cells", 2); 1060 qemu_fdt_setprop_cells(vbi->fdt, nodename, "bus-range", 0, 1061 nr_pcie_buses - 1); 1062 qemu_fdt_setprop(vbi->fdt, nodename, "dma-coherent", NULL, 0); 1063 1064 if (vbi->msi_phandle) { 1065 qemu_fdt_setprop_cells(vbi->fdt, nodename, "msi-parent", 1066 vbi->msi_phandle); 1067 } 1068 1069 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 1070 2, base_ecam, 2, size_ecam); 1071 1072 if (use_highmem) { 1073 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges", 1074 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1075 2, base_pio, 2, size_pio, 1076 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1077 2, base_mmio, 2, size_mmio, 1078 1, FDT_PCI_RANGE_MMIO_64BIT, 1079 2, base_mmio_high, 1080 2, base_mmio_high, 2, size_mmio_high); 1081 } else { 1082 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges", 1083 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1084 2, base_pio, 2, size_pio, 1085 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1086 2, base_mmio, 2, size_mmio); 1087 } 1088 1089 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#interrupt-cells", 1); 1090 create_pcie_irq_map(vbi, vbi->gic_phandle, irq, nodename); 1091 1092 g_free(nodename); 1093 } 1094 1095 static void create_platform_bus(VirtBoardInfo *vbi, qemu_irq *pic) 1096 { 1097 DeviceState *dev; 1098 SysBusDevice *s; 1099 int i; 1100 ARMPlatformBusFDTParams *fdt_params = g_new(ARMPlatformBusFDTParams, 1); 1101 MemoryRegion *sysmem = get_system_memory(); 1102 1103 platform_bus_params.platform_bus_base = vbi->memmap[VIRT_PLATFORM_BUS].base; 1104 platform_bus_params.platform_bus_size = vbi->memmap[VIRT_PLATFORM_BUS].size; 1105 platform_bus_params.platform_bus_first_irq = vbi->irqmap[VIRT_PLATFORM_BUS]; 1106 platform_bus_params.platform_bus_num_irqs = PLATFORM_BUS_NUM_IRQS; 1107 1108 fdt_params->system_params = &platform_bus_params; 1109 fdt_params->binfo = &vbi->bootinfo; 1110 fdt_params->intc = "/intc"; 1111 /* 1112 * register a machine init done notifier that creates the device tree 1113 * nodes of the platform bus and its children dynamic sysbus devices 1114 */ 1115 arm_register_platform_bus_fdt_creator(fdt_params); 1116 1117 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1118 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1119 qdev_prop_set_uint32(dev, "num_irqs", 1120 platform_bus_params.platform_bus_num_irqs); 1121 qdev_prop_set_uint32(dev, "mmio_size", 1122 platform_bus_params.platform_bus_size); 1123 qdev_init_nofail(dev); 1124 s = SYS_BUS_DEVICE(dev); 1125 1126 for (i = 0; i < platform_bus_params.platform_bus_num_irqs; i++) { 1127 int irqn = platform_bus_params.platform_bus_first_irq + i; 1128 sysbus_connect_irq(s, i, pic[irqn]); 1129 } 1130 1131 memory_region_add_subregion(sysmem, 1132 platform_bus_params.platform_bus_base, 1133 sysbus_mmio_get_region(s, 0)); 1134 } 1135 1136 static void create_secure_ram(VirtBoardInfo *vbi, MemoryRegion *secure_sysmem) 1137 { 1138 MemoryRegion *secram = g_new(MemoryRegion, 1); 1139 char *nodename; 1140 hwaddr base = vbi->memmap[VIRT_SECURE_MEM].base; 1141 hwaddr size = vbi->memmap[VIRT_SECURE_MEM].size; 1142 1143 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, &error_fatal); 1144 vmstate_register_ram_global(secram); 1145 memory_region_add_subregion(secure_sysmem, base, secram); 1146 1147 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1148 qemu_fdt_add_subnode(vbi->fdt, nodename); 1149 qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "memory"); 1150 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 2, base, 2, size); 1151 qemu_fdt_setprop_string(vbi->fdt, nodename, "status", "disabled"); 1152 qemu_fdt_setprop_string(vbi->fdt, nodename, "secure-status", "okay"); 1153 1154 g_free(nodename); 1155 } 1156 1157 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1158 { 1159 const VirtBoardInfo *board = (const VirtBoardInfo *)binfo; 1160 1161 *fdt_size = board->fdt_size; 1162 return board->fdt; 1163 } 1164 1165 static void virt_build_smbios(VirtGuestInfo *guest_info) 1166 { 1167 FWCfgState *fw_cfg = guest_info->fw_cfg; 1168 uint8_t *smbios_tables, *smbios_anchor; 1169 size_t smbios_tables_len, smbios_anchor_len; 1170 const char *product = "QEMU Virtual Machine"; 1171 1172 if (!fw_cfg) { 1173 return; 1174 } 1175 1176 if (kvm_enabled()) { 1177 product = "KVM Virtual Machine"; 1178 } 1179 1180 smbios_set_defaults("QEMU", product, 1181 "1.0", false, true, SMBIOS_ENTRY_POINT_30); 1182 1183 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, 1184 &smbios_anchor, &smbios_anchor_len); 1185 1186 if (smbios_anchor) { 1187 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 1188 smbios_tables, smbios_tables_len); 1189 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 1190 smbios_anchor, smbios_anchor_len); 1191 } 1192 } 1193 1194 static 1195 void virt_guest_info_machine_done(Notifier *notifier, void *data) 1196 { 1197 VirtGuestInfoState *guest_info_state = container_of(notifier, 1198 VirtGuestInfoState, machine_done); 1199 virt_acpi_setup(&guest_info_state->info); 1200 virt_build_smbios(&guest_info_state->info); 1201 } 1202 1203 static void machvirt_init(MachineState *machine) 1204 { 1205 VirtMachineState *vms = VIRT_MACHINE(machine); 1206 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1207 qemu_irq pic[NUM_IRQS]; 1208 MemoryRegion *sysmem = get_system_memory(); 1209 MemoryRegion *secure_sysmem = NULL; 1210 int gic_version = vms->gic_version; 1211 int n, virt_max_cpus; 1212 MemoryRegion *ram = g_new(MemoryRegion, 1); 1213 const char *cpu_model = machine->cpu_model; 1214 VirtBoardInfo *vbi; 1215 VirtGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1216 VirtGuestInfo *guest_info = &guest_info_state->info; 1217 char **cpustr; 1218 ObjectClass *oc; 1219 const char *typename; 1220 CPUClass *cc; 1221 Error *err = NULL; 1222 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); 1223 uint8_t clustersz; 1224 1225 if (!cpu_model) { 1226 cpu_model = "cortex-a15"; 1227 } 1228 1229 /* We can probe only here because during property set 1230 * KVM is not available yet 1231 */ 1232 if (!gic_version) { 1233 if (!kvm_enabled()) { 1234 error_report("gic-version=host requires KVM"); 1235 exit(1); 1236 } 1237 1238 gic_version = kvm_arm_vgic_probe(); 1239 if (!gic_version) { 1240 error_report("Unable to determine GIC version supported by host"); 1241 exit(1); 1242 } 1243 } 1244 1245 /* Separate the actual CPU model name from any appended features */ 1246 cpustr = g_strsplit(cpu_model, ",", 2); 1247 1248 vbi = find_machine_info(cpustr[0]); 1249 1250 if (!vbi) { 1251 error_report("mach-virt: CPU %s not supported", cpustr[0]); 1252 exit(1); 1253 } 1254 1255 /* If we have an EL3 boot ROM then the assumption is that it will 1256 * implement PSCI itself, so disable QEMU's internal implementation 1257 * so it doesn't get in the way. Instead of starting secondary 1258 * CPUs in PSCI powerdown state we will start them all running and 1259 * let the boot ROM sort them out. 1260 * The usual case is that we do use QEMU's PSCI implementation. 1261 */ 1262 vbi->using_psci = !(vms->secure && firmware_loaded); 1263 1264 /* The maximum number of CPUs depends on the GIC version, or on how 1265 * many redistributors we can fit into the memory map. 1266 */ 1267 if (gic_version == 3) { 1268 virt_max_cpus = vbi->memmap[VIRT_GIC_REDIST].size / 0x20000; 1269 clustersz = GICV3_TARGETLIST_BITS; 1270 } else { 1271 virt_max_cpus = GIC_NCPU; 1272 clustersz = GIC_TARGETLIST_BITS; 1273 } 1274 1275 if (max_cpus > virt_max_cpus) { 1276 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1277 "supported by machine 'mach-virt' (%d)", 1278 max_cpus, virt_max_cpus); 1279 exit(1); 1280 } 1281 1282 vbi->smp_cpus = smp_cpus; 1283 1284 if (machine->ram_size > vbi->memmap[VIRT_MEM].size) { 1285 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB); 1286 exit(1); 1287 } 1288 1289 if (vms->secure) { 1290 if (kvm_enabled()) { 1291 error_report("mach-virt: KVM does not support Security extensions"); 1292 exit(1); 1293 } 1294 1295 /* The Secure view of the world is the same as the NonSecure, 1296 * but with a few extra devices. Create it as a container region 1297 * containing the system memory at low priority; any secure-only 1298 * devices go in at higher priority and take precedence. 1299 */ 1300 secure_sysmem = g_new(MemoryRegion, 1); 1301 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1302 UINT64_MAX); 1303 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1304 } 1305 1306 create_fdt(vbi); 1307 1308 oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); 1309 if (!oc) { 1310 error_report("Unable to find CPU definition"); 1311 exit(1); 1312 } 1313 typename = object_class_get_name(oc); 1314 1315 /* convert -smp CPU options specified by the user into global props */ 1316 cc = CPU_CLASS(oc); 1317 cc->parse_features(typename, cpustr[1], &err); 1318 g_strfreev(cpustr); 1319 if (err) { 1320 error_report_err(err); 1321 exit(1); 1322 } 1323 1324 for (n = 0; n < smp_cpus; n++) { 1325 Object *cpuobj = object_new(typename); 1326 if (!vmc->disallow_affinity_adjustment) { 1327 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1328 * GIC's target-list limitations. 32-bit KVM hosts currently 1329 * always create clusters of 4 CPUs, but that is expected to 1330 * change when they gain support for gicv3. When KVM is enabled 1331 * it will override the changes we make here, therefore our 1332 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1333 * and to improve SGI efficiency. 1334 */ 1335 uint8_t aff1 = n / clustersz; 1336 uint8_t aff0 = n % clustersz; 1337 object_property_set_int(cpuobj, (aff1 << ARM_AFF1_SHIFT) | aff0, 1338 "mp-affinity", NULL); 1339 } 1340 1341 if (!vms->secure) { 1342 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1343 } 1344 1345 if (vbi->using_psci) { 1346 object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_HVC, 1347 "psci-conduit", NULL); 1348 1349 /* Secondary CPUs start in PSCI powered-down state */ 1350 if (n > 0) { 1351 object_property_set_bool(cpuobj, true, 1352 "start-powered-off", NULL); 1353 } 1354 } 1355 1356 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1357 object_property_set_int(cpuobj, vbi->memmap[VIRT_CPUPERIPHS].base, 1358 "reset-cbar", &error_abort); 1359 } 1360 1361 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1362 &error_abort); 1363 if (vms->secure) { 1364 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1365 "secure-memory", &error_abort); 1366 } 1367 1368 object_property_set_bool(cpuobj, true, "realized", NULL); 1369 } 1370 fdt_add_timer_nodes(vbi, gic_version); 1371 fdt_add_cpu_nodes(vbi); 1372 fdt_add_psci_node(vbi); 1373 1374 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", 1375 machine->ram_size); 1376 memory_region_add_subregion(sysmem, vbi->memmap[VIRT_MEM].base, ram); 1377 1378 create_flash(vbi, sysmem, secure_sysmem ? secure_sysmem : sysmem); 1379 1380 create_gic(vbi, pic, gic_version, vms->secure, vmc->no_its); 1381 1382 fdt_add_pmu_nodes(vbi, gic_version); 1383 1384 create_uart(vbi, pic, VIRT_UART, sysmem, serial_hds[0]); 1385 1386 if (vms->secure) { 1387 create_secure_ram(vbi, secure_sysmem); 1388 create_uart(vbi, pic, VIRT_SECURE_UART, secure_sysmem, serial_hds[1]); 1389 } 1390 1391 create_rtc(vbi, pic); 1392 1393 create_pcie(vbi, pic, vms->highmem); 1394 1395 create_gpio(vbi, pic); 1396 1397 /* Create mmio transports, so the user can create virtio backends 1398 * (which will be automatically plugged in to the transports). If 1399 * no backend is created the transport will just sit harmlessly idle. 1400 */ 1401 create_virtio_devices(vbi, pic); 1402 1403 create_fw_cfg(vbi, &address_space_memory); 1404 rom_set_fw(fw_cfg_find()); 1405 1406 guest_info->smp_cpus = smp_cpus; 1407 guest_info->fw_cfg = fw_cfg_find(); 1408 guest_info->memmap = vbi->memmap; 1409 guest_info->irqmap = vbi->irqmap; 1410 guest_info->use_highmem = vms->highmem; 1411 guest_info->gic_version = gic_version; 1412 guest_info->no_its = vmc->no_its; 1413 guest_info_state->machine_done.notify = virt_guest_info_machine_done; 1414 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1415 1416 vbi->bootinfo.ram_size = machine->ram_size; 1417 vbi->bootinfo.kernel_filename = machine->kernel_filename; 1418 vbi->bootinfo.kernel_cmdline = machine->kernel_cmdline; 1419 vbi->bootinfo.initrd_filename = machine->initrd_filename; 1420 vbi->bootinfo.nb_cpus = smp_cpus; 1421 vbi->bootinfo.board_id = -1; 1422 vbi->bootinfo.loader_start = vbi->memmap[VIRT_MEM].base; 1423 vbi->bootinfo.get_dtb = machvirt_dtb; 1424 vbi->bootinfo.firmware_loaded = firmware_loaded; 1425 arm_load_kernel(ARM_CPU(first_cpu), &vbi->bootinfo); 1426 1427 /* 1428 * arm_load_kernel machine init done notifier registration must 1429 * happen before the platform_bus_create call. In this latter, 1430 * another notifier is registered which adds platform bus nodes. 1431 * Notifiers are executed in registration reverse order. 1432 */ 1433 create_platform_bus(vbi, pic); 1434 } 1435 1436 static bool virt_get_secure(Object *obj, Error **errp) 1437 { 1438 VirtMachineState *vms = VIRT_MACHINE(obj); 1439 1440 return vms->secure; 1441 } 1442 1443 static void virt_set_secure(Object *obj, bool value, Error **errp) 1444 { 1445 VirtMachineState *vms = VIRT_MACHINE(obj); 1446 1447 vms->secure = value; 1448 } 1449 1450 static bool virt_get_highmem(Object *obj, Error **errp) 1451 { 1452 VirtMachineState *vms = VIRT_MACHINE(obj); 1453 1454 return vms->highmem; 1455 } 1456 1457 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1458 { 1459 VirtMachineState *vms = VIRT_MACHINE(obj); 1460 1461 vms->highmem = value; 1462 } 1463 1464 static char *virt_get_gic_version(Object *obj, Error **errp) 1465 { 1466 VirtMachineState *vms = VIRT_MACHINE(obj); 1467 const char *val = vms->gic_version == 3 ? "3" : "2"; 1468 1469 return g_strdup(val); 1470 } 1471 1472 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 1473 { 1474 VirtMachineState *vms = VIRT_MACHINE(obj); 1475 1476 if (!strcmp(value, "3")) { 1477 vms->gic_version = 3; 1478 } else if (!strcmp(value, "2")) { 1479 vms->gic_version = 2; 1480 } else if (!strcmp(value, "host")) { 1481 vms->gic_version = 0; /* Will probe later */ 1482 } else { 1483 error_setg(errp, "Invalid gic-version value"); 1484 error_append_hint(errp, "Valid values are 3, 2, host.\n"); 1485 } 1486 } 1487 1488 static void virt_machine_class_init(ObjectClass *oc, void *data) 1489 { 1490 MachineClass *mc = MACHINE_CLASS(oc); 1491 1492 mc->init = machvirt_init; 1493 /* Start max_cpus at the maximum QEMU supports. We'll further restrict 1494 * it later in machvirt_init, where we have more information about the 1495 * configuration of the particular instance. 1496 */ 1497 mc->max_cpus = MAX_CPUMASK_BITS; 1498 mc->has_dynamic_sysbus = true; 1499 mc->block_default_type = IF_VIRTIO; 1500 mc->no_cdrom = 1; 1501 mc->pci_allow_0_address = true; 1502 } 1503 1504 static const TypeInfo virt_machine_info = { 1505 .name = TYPE_VIRT_MACHINE, 1506 .parent = TYPE_MACHINE, 1507 .abstract = true, 1508 .instance_size = sizeof(VirtMachineState), 1509 .class_size = sizeof(VirtMachineClass), 1510 .class_init = virt_machine_class_init, 1511 }; 1512 1513 static void machvirt_machine_init(void) 1514 { 1515 type_register_static(&virt_machine_info); 1516 } 1517 type_init(machvirt_machine_init); 1518 1519 static void virt_2_8_instance_init(Object *obj) 1520 { 1521 VirtMachineState *vms = VIRT_MACHINE(obj); 1522 1523 /* EL3 is disabled by default on virt: this makes us consistent 1524 * between KVM and TCG for this board, and it also allows us to 1525 * boot UEFI blobs which assume no TrustZone support. 1526 */ 1527 vms->secure = false; 1528 object_property_add_bool(obj, "secure", virt_get_secure, 1529 virt_set_secure, NULL); 1530 object_property_set_description(obj, "secure", 1531 "Set on/off to enable/disable the ARM " 1532 "Security Extensions (TrustZone)", 1533 NULL); 1534 1535 /* High memory is enabled by default */ 1536 vms->highmem = true; 1537 object_property_add_bool(obj, "highmem", virt_get_highmem, 1538 virt_set_highmem, NULL); 1539 object_property_set_description(obj, "highmem", 1540 "Set on/off to enable/disable using " 1541 "physical address space above 32 bits", 1542 NULL); 1543 /* Default GIC type is v2 */ 1544 vms->gic_version = 2; 1545 object_property_add_str(obj, "gic-version", virt_get_gic_version, 1546 virt_set_gic_version, NULL); 1547 object_property_set_description(obj, "gic-version", 1548 "Set GIC version. " 1549 "Valid values are 2, 3 and host", NULL); 1550 } 1551 1552 static void virt_machine_2_8_options(MachineClass *mc) 1553 { 1554 } 1555 DEFINE_VIRT_MACHINE_AS_LATEST(2, 8) 1556 1557 #define VIRT_COMPAT_2_7 \ 1558 HW_COMPAT_2_7 1559 1560 static void virt_2_7_instance_init(Object *obj) 1561 { 1562 virt_2_8_instance_init(obj); 1563 } 1564 1565 static void virt_machine_2_7_options(MachineClass *mc) 1566 { 1567 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1568 1569 virt_machine_2_8_options(mc); 1570 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_7); 1571 /* ITS was introduced with 2.8 */ 1572 vmc->no_its = true; 1573 } 1574 DEFINE_VIRT_MACHINE(2, 7) 1575 1576 #define VIRT_COMPAT_2_6 \ 1577 HW_COMPAT_2_6 1578 1579 static void virt_2_6_instance_init(Object *obj) 1580 { 1581 virt_2_7_instance_init(obj); 1582 } 1583 1584 static void virt_machine_2_6_options(MachineClass *mc) 1585 { 1586 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1587 1588 virt_machine_2_7_options(mc); 1589 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6); 1590 vmc->disallow_affinity_adjustment = true; 1591 } 1592 DEFINE_VIRT_MACHINE(2, 6) 1593