1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/datadir.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "hw/sysbus.h" 37 #include "hw/arm/boot.h" 38 #include "hw/arm/primecell.h" 39 #include "hw/arm/virt.h" 40 #include "hw/block/flash.h" 41 #include "hw/vfio/vfio-calxeda-xgmac.h" 42 #include "hw/vfio/vfio-amd-xgbe.h" 43 #include "hw/display/ramfb.h" 44 #include "net/net.h" 45 #include "system/device_tree.h" 46 #include "system/numa.h" 47 #include "system/runstate.h" 48 #include "system/tpm.h" 49 #include "system/tcg.h" 50 #include "system/kvm.h" 51 #include "system/hvf.h" 52 #include "system/qtest.h" 53 #include "hw/loader.h" 54 #include "qapi/error.h" 55 #include "qemu/bitops.h" 56 #include "qemu/cutils.h" 57 #include "qemu/error-report.h" 58 #include "qemu/module.h" 59 #include "hw/pci-host/gpex.h" 60 #include "hw/pci-bridge/pci_expander_bridge.h" 61 #include "hw/virtio/virtio-pci.h" 62 #include "hw/core/sysbus-fdt.h" 63 #include "hw/platform-bus.h" 64 #include "hw/qdev-properties.h" 65 #include "hw/arm/fdt.h" 66 #include "hw/intc/arm_gic.h" 67 #include "hw/intc/arm_gicv3_common.h" 68 #include "hw/intc/arm_gicv3_its_common.h" 69 #include "hw/irq.h" 70 #include "kvm_arm.h" 71 #include "hvf_arm.h" 72 #include "hw/firmware/smbios.h" 73 #include "qapi/visitor.h" 74 #include "qapi/qapi-visit-common.h" 75 #include "qobject/qlist.h" 76 #include "standard-headers/linux/input.h" 77 #include "hw/arm/smmuv3.h" 78 #include "hw/acpi/acpi.h" 79 #include "target/arm/cpu-qom.h" 80 #include "target/arm/internals.h" 81 #include "target/arm/multiprocessing.h" 82 #include "target/arm/gtimer.h" 83 #include "hw/mem/pc-dimm.h" 84 #include "hw/mem/nvdimm.h" 85 #include "hw/acpi/generic_event_device.h" 86 #include "hw/uefi/var-service-api.h" 87 #include "hw/virtio/virtio-md-pci.h" 88 #include "hw/virtio/virtio-iommu.h" 89 #include "hw/char/pl011.h" 90 #include "hw/cxl/cxl.h" 91 #include "hw/cxl/cxl_host.h" 92 #include "qemu/guest-random.h" 93 94 static GlobalProperty arm_virt_compat[] = { 95 { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "48" }, 96 }; 97 static const size_t arm_virt_compat_len = G_N_ELEMENTS(arm_virt_compat); 98 99 /* 100 * This cannot be called from the virt_machine_class_init() because 101 * TYPE_VIRT_MACHINE is abstract and mc->compat_props g_ptr_array_new() 102 * only is called on virt non abstract class init. 103 */ 104 static void arm_virt_compat_set(MachineClass *mc) 105 { 106 compat_props_add(mc->compat_props, arm_virt_compat, 107 arm_virt_compat_len); 108 } 109 110 #define DEFINE_VIRT_MACHINE_IMPL(latest, ...) \ 111 static void MACHINE_VER_SYM(class_init, virt, __VA_ARGS__)( \ 112 ObjectClass *oc, \ 113 const void *data) \ 114 { \ 115 MachineClass *mc = MACHINE_CLASS(oc); \ 116 arm_virt_compat_set(mc); \ 117 MACHINE_VER_SYM(options, virt, __VA_ARGS__)(mc); \ 118 mc->desc = "QEMU " MACHINE_VER_STR(__VA_ARGS__) " ARM Virtual Machine"; \ 119 MACHINE_VER_DEPRECATION(__VA_ARGS__); \ 120 if (latest) { \ 121 mc->alias = "virt"; \ 122 } \ 123 } \ 124 static const TypeInfo MACHINE_VER_SYM(info, virt, __VA_ARGS__) = \ 125 { \ 126 .name = MACHINE_VER_TYPE_NAME("virt", __VA_ARGS__), \ 127 .parent = TYPE_VIRT_MACHINE, \ 128 .class_init = MACHINE_VER_SYM(class_init, virt, __VA_ARGS__), \ 129 }; \ 130 static void MACHINE_VER_SYM(register, virt, __VA_ARGS__)(void) \ 131 { \ 132 MACHINE_VER_DELETION(__VA_ARGS__); \ 133 type_register_static(&MACHINE_VER_SYM(info, virt, __VA_ARGS__)); \ 134 } \ 135 type_init(MACHINE_VER_SYM(register, virt, __VA_ARGS__)); 136 137 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 138 DEFINE_VIRT_MACHINE_IMPL(true, major, minor) 139 #define DEFINE_VIRT_MACHINE(major, minor) \ 140 DEFINE_VIRT_MACHINE_IMPL(false, major, minor) 141 142 143 /* Number of external interrupt lines to configure the GIC with */ 144 #define NUM_IRQS 256 145 146 #define PLATFORM_BUS_NUM_IRQS 64 147 148 /* Legacy RAM limit in GB (< version 4.0) */ 149 #define LEGACY_RAMLIMIT_GB 255 150 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 151 152 /* Addresses and sizes of our components. 153 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 154 * 128MB..256MB is used for miscellaneous device I/O. 155 * 256MB..1GB is reserved for possible future PCI support (ie where the 156 * PCI memory window will go if we add a PCI host controller). 157 * 1GB and up is RAM (which may happily spill over into the 158 * high memory region beyond 4GB). 159 * This represents a compromise between how much RAM can be given to 160 * a 32 bit VM and leaving space for expansion and in particular for PCI. 161 * Note that devices should generally be placed at multiples of 0x10000, 162 * to accommodate guests using 64K pages. 163 */ 164 static const MemMapEntry base_memmap[] = { 165 /* Space up to 0x8000000 is reserved for a boot ROM */ 166 [VIRT_FLASH] = { 0, 0x08000000 }, 167 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 168 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 169 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 170 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 171 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 172 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 173 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 174 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 175 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 176 /* This redistributor space allows up to 2*64kB*123 CPUs */ 177 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 178 [VIRT_UART0] = { 0x09000000, 0x00001000 }, 179 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 180 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 181 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 182 [VIRT_UART1] = { 0x09040000, 0x00001000 }, 183 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 184 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 185 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 186 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 187 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, 188 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, 189 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 190 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 191 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 192 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 193 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 194 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 195 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 196 /* Actual RAM size depends on initial RAM and device memory settings */ 197 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 198 }; 199 200 /* Update the docs for highmem-mmio-size when changing this default */ 201 #define DEFAULT_HIGH_PCIE_MMIO_SIZE_GB 512 202 #define DEFAULT_HIGH_PCIE_MMIO_SIZE (DEFAULT_HIGH_PCIE_MMIO_SIZE_GB * GiB) 203 204 /* 205 * Highmem IO Regions: This memory map is floating, located after the RAM. 206 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 207 * top of the RAM, so that its base get the same alignment as the size, 208 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 209 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 210 * Note the extended_memmap is sized so that it eventually also includes the 211 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 212 * index of base_memmap). 213 * 214 * The memory map for these Highmem IO Regions can be in legacy or compact 215 * layout, depending on 'compact-highmem' property. With legacy layout, the 216 * PA space for one specific region is always reserved, even if the region 217 * has been disabled or doesn't fit into the PA space. However, the PA space 218 * for the region won't be reserved in these circumstances with compact layout. 219 * 220 * Note that the highmem-mmio-size property will update the high PCIE MMIO size 221 * field in this array. 222 */ 223 static MemMapEntry extended_memmap[] = { 224 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 225 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 226 [VIRT_CXL_HOST] = { 0x0, 64 * KiB * 16 }, /* 16 UID */ 227 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 228 /* Second PCIe window */ 229 [VIRT_HIGH_PCIE_MMIO] = { 0x0, DEFAULT_HIGH_PCIE_MMIO_SIZE }, 230 /* Any CXL Fixed memory windows come here */ 231 }; 232 233 static const int a15irqmap[] = { 234 [VIRT_UART0] = 1, 235 [VIRT_RTC] = 2, 236 [VIRT_PCIE] = 3, /* ... to 6 */ 237 [VIRT_GPIO] = 7, 238 [VIRT_UART1] = 8, 239 [VIRT_ACPI_GED] = 9, 240 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 241 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 242 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 243 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 244 }; 245 246 static void create_randomness(MachineState *ms, const char *node) 247 { 248 struct { 249 uint64_t kaslr; 250 uint8_t rng[32]; 251 } seed; 252 253 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { 254 return; 255 } 256 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr); 257 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); 258 } 259 260 /* 261 * The CPU object always exposes the NS EL2 virt timer IRQ line, 262 * but we don't want to advertise it to the guest in the dtb or ACPI 263 * table unless it's really going to do something. 264 */ 265 static bool ns_el2_virt_timer_present(void) 266 { 267 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0)); 268 CPUARMState *env = &cpu->env; 269 270 return arm_feature(env, ARM_FEATURE_AARCH64) && 271 arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu); 272 } 273 274 static void create_fdt(VirtMachineState *vms) 275 { 276 MachineState *ms = MACHINE(vms); 277 int nb_numa_nodes = ms->numa_state->num_nodes; 278 void *fdt = create_device_tree(&vms->fdt_size); 279 280 if (!fdt) { 281 error_report("create_device_tree() failed"); 282 exit(1); 283 } 284 285 ms->fdt = fdt; 286 287 /* Header */ 288 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 289 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 290 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 291 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt"); 292 293 /* 294 * For QEMU, all DMA is coherent. Advertising this in the root node 295 * has two benefits: 296 * 297 * - It avoids potential bugs where we forget to mark a DMA 298 * capable device as being dma-coherent 299 * - It avoids spurious warnings from the Linux kernel about 300 * devices which can't do DMA at all 301 */ 302 qemu_fdt_setprop(fdt, "/", "dma-coherent", NULL, 0); 303 304 /* /chosen must exist for load_dtb to fill in necessary properties later */ 305 qemu_fdt_add_subnode(fdt, "/chosen"); 306 if (vms->dtb_randomness) { 307 create_randomness(ms, "/chosen"); 308 } 309 310 if (vms->secure) { 311 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 312 if (vms->dtb_randomness) { 313 create_randomness(ms, "/secure-chosen"); 314 } 315 } 316 317 qemu_fdt_add_subnode(fdt, "/aliases"); 318 319 /* Clock node, for the benefit of the UART. The kernel device tree 320 * binding documentation claims the PL011 node clock properties are 321 * optional but in practice if you omit them the kernel refuses to 322 * probe for the device. 323 */ 324 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 325 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 326 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 327 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 328 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 329 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 330 "clk24mhz"); 331 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 332 333 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 334 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 335 uint32_t *matrix = g_malloc0(size); 336 int idx, i, j; 337 338 for (i = 0; i < nb_numa_nodes; i++) { 339 for (j = 0; j < nb_numa_nodes; j++) { 340 idx = (i * nb_numa_nodes + j) * 3; 341 matrix[idx + 0] = cpu_to_be32(i); 342 matrix[idx + 1] = cpu_to_be32(j); 343 matrix[idx + 2] = 344 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 345 } 346 } 347 348 qemu_fdt_add_subnode(fdt, "/distance-map"); 349 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 350 "numa-distance-map-v1"); 351 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 352 matrix, size); 353 g_free(matrix); 354 } 355 } 356 357 static void fdt_add_timer_nodes(const VirtMachineState *vms) 358 { 359 /* On real hardware these interrupts are level-triggered. 360 * On KVM they were edge-triggered before host kernel version 4.4, 361 * and level-triggered afterwards. 362 * On emulated QEMU they are level-triggered. 363 * 364 * Getting the DTB info about them wrong is awkward for some 365 * guest kernels: 366 * pre-4.8 ignore the DT and leave the interrupt configured 367 * with whatever the GIC reset value (or the bootloader) left it at 368 * 4.8 before rc6 honour the incorrect data by programming it back 369 * into the GIC, causing problems 370 * 4.8rc6 and later ignore the DT and always write "level triggered" 371 * into the GIC 372 * 373 * For backwards-compatibility, virt-2.8 and earlier will continue 374 * to say these are edge-triggered, but later machines will report 375 * the correct information. 376 */ 377 ARMCPU *armcpu; 378 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 379 MachineState *ms = MACHINE(vms); 380 381 if (vms->gic_version == VIRT_GIC_VERSION_2) { 382 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 383 GIC_FDT_IRQ_PPI_CPU_WIDTH, 384 (1 << MACHINE(vms)->smp.cpus) - 1); 385 } 386 387 qemu_fdt_add_subnode(ms->fdt, "/timer"); 388 389 armcpu = ARM_CPU(qemu_get_cpu(0)); 390 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 391 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 392 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", 393 compat, sizeof(compat)); 394 } else { 395 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", 396 "arm,armv7-timer"); 397 } 398 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); 399 if (vms->ns_el2_virt_timer_irq) { 400 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 401 GIC_FDT_IRQ_TYPE_PPI, 402 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, 403 GIC_FDT_IRQ_TYPE_PPI, 404 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, 405 GIC_FDT_IRQ_TYPE_PPI, 406 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, 407 GIC_FDT_IRQ_TYPE_PPI, 408 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags, 409 GIC_FDT_IRQ_TYPE_PPI, 410 INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags); 411 } else { 412 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 413 GIC_FDT_IRQ_TYPE_PPI, 414 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, 415 GIC_FDT_IRQ_TYPE_PPI, 416 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, 417 GIC_FDT_IRQ_TYPE_PPI, 418 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, 419 GIC_FDT_IRQ_TYPE_PPI, 420 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags); 421 } 422 } 423 424 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 425 { 426 int cpu; 427 int addr_cells = 1; 428 const MachineState *ms = MACHINE(vms); 429 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 430 int smp_cpus = ms->smp.cpus; 431 432 /* 433 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml 434 * On ARM v8 64-bit systems value should be set to 2, 435 * that corresponds to the MPIDR_EL1 register size. 436 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 437 * in the system, #address-cells can be set to 1, since 438 * MPIDR_EL1[63:32] bits are not used for CPUs 439 * identification. 440 * 441 * Here we actually don't know whether our system is 32- or 64-bit one. 442 * The simplest way to go is to examine affinity IDs of all our CPUs. If 443 * at least one of them has Aff3 populated, we set #address-cells to 2. 444 */ 445 for (cpu = 0; cpu < smp_cpus; cpu++) { 446 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 447 448 if (arm_cpu_mp_affinity(armcpu) & ARM_AFF3_MASK) { 449 addr_cells = 2; 450 break; 451 } 452 } 453 454 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 455 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); 456 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 457 458 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 459 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 460 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 461 CPUState *cs = CPU(armcpu); 462 463 qemu_fdt_add_subnode(ms->fdt, nodename); 464 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 465 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 466 armcpu->dtb_compatible); 467 468 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { 469 qemu_fdt_setprop_string(ms->fdt, nodename, 470 "enable-method", "psci"); 471 } 472 473 if (addr_cells == 2) { 474 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", 475 arm_cpu_mp_affinity(armcpu)); 476 } else { 477 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", 478 arm_cpu_mp_affinity(armcpu)); 479 } 480 481 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 482 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 483 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 484 } 485 486 if (!vmc->no_cpu_topology) { 487 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 488 qemu_fdt_alloc_phandle(ms->fdt)); 489 } 490 491 g_free(nodename); 492 } 493 494 if (!vmc->no_cpu_topology) { 495 /* 496 * Add vCPU topology description through fdt node cpu-map. 497 * 498 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt 499 * In a SMP system, the hierarchy of CPUs can be defined through 500 * four entities that are used to describe the layout of CPUs in 501 * the system: socket/cluster/core/thread. 502 * 503 * A socket node represents the boundary of system physical package 504 * and its child nodes must be one or more cluster nodes. A system 505 * can contain several layers of clustering within a single physical 506 * package and cluster nodes can be contained in parent cluster nodes. 507 * 508 * Note: currently we only support one layer of clustering within 509 * each physical package. 510 */ 511 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 512 513 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 514 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); 515 char *map_path; 516 517 if (ms->smp.threads > 1) { 518 map_path = g_strdup_printf( 519 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", 520 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), 521 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, 522 (cpu / ms->smp.threads) % ms->smp.cores, 523 cpu % ms->smp.threads); 524 } else { 525 map_path = g_strdup_printf( 526 "/cpus/cpu-map/socket%d/cluster%d/core%d", 527 cpu / (ms->smp.clusters * ms->smp.cores), 528 (cpu / ms->smp.cores) % ms->smp.clusters, 529 cpu % ms->smp.cores); 530 } 531 qemu_fdt_add_path(ms->fdt, map_path); 532 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 533 534 g_free(map_path); 535 g_free(cpu_path); 536 } 537 } 538 } 539 540 static void fdt_add_its_gic_node(VirtMachineState *vms) 541 { 542 char *nodename; 543 MachineState *ms = MACHINE(vms); 544 545 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 546 nodename = g_strdup_printf("/intc/its@%" PRIx64, 547 vms->memmap[VIRT_GIC_ITS].base); 548 qemu_fdt_add_subnode(ms->fdt, nodename); 549 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 550 "arm,gic-v3-its"); 551 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 552 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1); 553 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 554 2, vms->memmap[VIRT_GIC_ITS].base, 555 2, vms->memmap[VIRT_GIC_ITS].size); 556 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 557 g_free(nodename); 558 } 559 560 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 561 { 562 MachineState *ms = MACHINE(vms); 563 char *nodename; 564 565 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 566 vms->memmap[VIRT_GIC_V2M].base); 567 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 568 qemu_fdt_add_subnode(ms->fdt, nodename); 569 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 570 "arm,gic-v2m-frame"); 571 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 572 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 573 2, vms->memmap[VIRT_GIC_V2M].base, 574 2, vms->memmap[VIRT_GIC_V2M].size); 575 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 576 g_free(nodename); 577 } 578 579 static void fdt_add_gic_node(VirtMachineState *vms) 580 { 581 MachineState *ms = MACHINE(vms); 582 char *nodename; 583 584 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 585 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); 586 587 nodename = g_strdup_printf("/intc@%" PRIx64, 588 vms->memmap[VIRT_GIC_DIST].base); 589 qemu_fdt_add_subnode(ms->fdt, nodename); 590 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 591 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 592 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 593 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 594 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 595 if (vms->gic_version != VIRT_GIC_VERSION_2) { 596 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 597 598 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 599 "arm,gic-v3"); 600 601 qemu_fdt_setprop_cell(ms->fdt, nodename, 602 "#redistributor-regions", nb_redist_regions); 603 604 if (nb_redist_regions == 1) { 605 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 606 2, vms->memmap[VIRT_GIC_DIST].base, 607 2, vms->memmap[VIRT_GIC_DIST].size, 608 2, vms->memmap[VIRT_GIC_REDIST].base, 609 2, vms->memmap[VIRT_GIC_REDIST].size); 610 } else { 611 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 612 2, vms->memmap[VIRT_GIC_DIST].base, 613 2, vms->memmap[VIRT_GIC_DIST].size, 614 2, vms->memmap[VIRT_GIC_REDIST].base, 615 2, vms->memmap[VIRT_GIC_REDIST].size, 616 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 617 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 618 } 619 620 if (vms->virt) { 621 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 622 GIC_FDT_IRQ_TYPE_PPI, 623 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), 624 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 625 } 626 } else { 627 /* 'cortex-a15-gic' means 'GIC v2' */ 628 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 629 "arm,cortex-a15-gic"); 630 if (!vms->virt) { 631 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 632 2, vms->memmap[VIRT_GIC_DIST].base, 633 2, vms->memmap[VIRT_GIC_DIST].size, 634 2, vms->memmap[VIRT_GIC_CPU].base, 635 2, vms->memmap[VIRT_GIC_CPU].size); 636 } else { 637 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 638 2, vms->memmap[VIRT_GIC_DIST].base, 639 2, vms->memmap[VIRT_GIC_DIST].size, 640 2, vms->memmap[VIRT_GIC_CPU].base, 641 2, vms->memmap[VIRT_GIC_CPU].size, 642 2, vms->memmap[VIRT_GIC_HYP].base, 643 2, vms->memmap[VIRT_GIC_HYP].size, 644 2, vms->memmap[VIRT_GIC_VCPU].base, 645 2, vms->memmap[VIRT_GIC_VCPU].size); 646 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 647 GIC_FDT_IRQ_TYPE_PPI, 648 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), 649 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 650 } 651 } 652 653 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); 654 g_free(nodename); 655 } 656 657 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 658 { 659 ARMCPU *armcpu = ARM_CPU(first_cpu); 660 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 661 MachineState *ms = MACHINE(vms); 662 663 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 664 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); 665 return; 666 } 667 668 if (vms->gic_version == VIRT_GIC_VERSION_2) { 669 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 670 GIC_FDT_IRQ_PPI_CPU_WIDTH, 671 (1 << MACHINE(vms)->smp.cpus) - 1); 672 } 673 674 qemu_fdt_add_subnode(ms->fdt, "/pmu"); 675 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 676 const char compat[] = "arm,armv8-pmuv3"; 677 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", 678 compat, sizeof(compat)); 679 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", 680 GIC_FDT_IRQ_TYPE_PPI, 681 INTID_TO_PPI(VIRTUAL_PMU_IRQ), irqflags); 682 } 683 } 684 685 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 686 { 687 DeviceState *dev; 688 MachineState *ms = MACHINE(vms); 689 int irq = vms->irqmap[VIRT_ACPI_GED]; 690 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 691 692 if (ms->ram_slots) { 693 event |= ACPI_GED_MEM_HOTPLUG_EVT; 694 } 695 696 if (ms->nvdimms_state->is_enabled) { 697 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 698 } 699 700 dev = qdev_new(TYPE_ACPI_GED); 701 qdev_prop_set_uint32(dev, "ged-event", event); 702 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 703 704 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 705 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 706 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 707 708 return dev; 709 } 710 711 static void create_its(VirtMachineState *vms) 712 { 713 DeviceState *dev; 714 715 assert(vms->its); 716 if (!kvm_irqchip_in_kernel() && !vms->tcg_its) { 717 /* 718 * Do nothing if ITS is neither supported by the host nor emulated by 719 * the machine. 720 */ 721 return; 722 } 723 724 dev = qdev_new(its_class_name()); 725 726 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 727 &error_abort); 728 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 729 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 730 731 fdt_add_its_gic_node(vms); 732 vms->msi_controller = VIRT_MSI_CTRL_ITS; 733 } 734 735 static void create_v2m(VirtMachineState *vms) 736 { 737 int i; 738 int irq = vms->irqmap[VIRT_GIC_V2M]; 739 DeviceState *dev; 740 741 dev = qdev_new("arm-gicv2m"); 742 qdev_prop_set_uint32(dev, "base-spi", irq); 743 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 744 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 745 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 746 747 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 748 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 749 qdev_get_gpio_in(vms->gic, irq + i)); 750 } 751 752 fdt_add_v2m_gic_node(vms); 753 vms->msi_controller = VIRT_MSI_CTRL_GICV2M; 754 } 755 756 /* 757 * If the CPU has FEAT_NMI, then turn on the NMI support in the GICv3 too. 758 * It's permitted to have a configuration with NMI in the CPU (and thus the 759 * GICv3 CPU interface) but not in the distributor/redistributors, but it's 760 * not very useful. 761 */ 762 static bool gicv3_nmi_present(VirtMachineState *vms) 763 { 764 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0)); 765 766 return tcg_enabled() && cpu_isar_feature(aa64_nmi, cpu) && 767 (vms->gic_version != VIRT_GIC_VERSION_2); 768 } 769 770 static void create_gic(VirtMachineState *vms, MemoryRegion *mem) 771 { 772 MachineState *ms = MACHINE(vms); 773 /* We create a standalone GIC */ 774 SysBusDevice *gicbusdev; 775 const char *gictype; 776 int i; 777 unsigned int smp_cpus = ms->smp.cpus; 778 uint32_t nb_redist_regions = 0; 779 int revision; 780 781 if (vms->gic_version == VIRT_GIC_VERSION_2) { 782 gictype = gic_class_name(); 783 } else { 784 gictype = gicv3_class_name(); 785 } 786 787 switch (vms->gic_version) { 788 case VIRT_GIC_VERSION_2: 789 revision = 2; 790 break; 791 case VIRT_GIC_VERSION_3: 792 revision = 3; 793 break; 794 case VIRT_GIC_VERSION_4: 795 revision = 4; 796 break; 797 default: 798 g_assert_not_reached(); 799 } 800 vms->gic = qdev_new(gictype); 801 qdev_prop_set_uint32(vms->gic, "revision", revision); 802 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 803 /* Note that the num-irq property counts both internal and external 804 * interrupts; there are always 32 of the former (mandated by GIC spec). 805 */ 806 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 807 if (!kvm_irqchip_in_kernel()) { 808 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 809 } 810 811 if (vms->gic_version != VIRT_GIC_VERSION_2) { 812 QList *redist_region_count; 813 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); 814 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 815 816 nb_redist_regions = virt_gicv3_redist_region_count(vms); 817 818 redist_region_count = qlist_new(); 819 qlist_append_int(redist_region_count, redist0_count); 820 if (nb_redist_regions == 2) { 821 uint32_t redist1_capacity = 822 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 823 824 qlist_append_int(redist_region_count, 825 MIN(smp_cpus - redist0_count, redist1_capacity)); 826 } 827 qdev_prop_set_array(vms->gic, "redist-region-count", 828 redist_region_count); 829 830 if (!kvm_irqchip_in_kernel()) { 831 if (vms->tcg_its) { 832 object_property_set_link(OBJECT(vms->gic), "sysmem", 833 OBJECT(mem), &error_fatal); 834 qdev_prop_set_bit(vms->gic, "has-lpi", true); 835 } 836 } 837 } else { 838 if (!kvm_irqchip_in_kernel()) { 839 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 840 vms->virt); 841 } 842 } 843 844 if (gicv3_nmi_present(vms)) { 845 qdev_prop_set_bit(vms->gic, "has-nmi", true); 846 } 847 848 gicbusdev = SYS_BUS_DEVICE(vms->gic); 849 sysbus_realize_and_unref(gicbusdev, &error_fatal); 850 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 851 if (vms->gic_version != VIRT_GIC_VERSION_2) { 852 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 853 if (nb_redist_regions == 2) { 854 sysbus_mmio_map(gicbusdev, 2, 855 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 856 } 857 } else { 858 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 859 if (vms->virt) { 860 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 861 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 862 } 863 } 864 865 /* Wire the outputs from each CPU's generic timer and the GICv3 866 * maintenance interrupt signal to the appropriate GIC PPI inputs, 867 * and the GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to the 868 * CPU's inputs. 869 */ 870 for (i = 0; i < smp_cpus; i++) { 871 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 872 int intidbase = NUM_IRQS + i * GIC_INTERNAL; 873 /* Mapping from the output timer irq lines from the CPU to the 874 * GIC PPI inputs we use for the virt board. 875 */ 876 const int timer_irq[] = { 877 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 878 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 879 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 880 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 881 [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, 882 [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ, 883 [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ, 884 }; 885 886 for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 887 qdev_connect_gpio_out(cpudev, irq, 888 qdev_get_gpio_in(vms->gic, 889 intidbase + timer_irq[irq])); 890 } 891 892 if (vms->gic_version != VIRT_GIC_VERSION_2) { 893 qemu_irq irq = qdev_get_gpio_in(vms->gic, 894 intidbase + ARCH_GIC_MAINT_IRQ); 895 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 896 0, irq); 897 } else if (vms->virt) { 898 qemu_irq irq = qdev_get_gpio_in(vms->gic, 899 intidbase + ARCH_GIC_MAINT_IRQ); 900 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 901 } 902 903 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 904 qdev_get_gpio_in(vms->gic, intidbase 905 + VIRTUAL_PMU_IRQ)); 906 907 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 908 sysbus_connect_irq(gicbusdev, i + smp_cpus, 909 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 910 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 911 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 912 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 913 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 914 915 if (vms->gic_version != VIRT_GIC_VERSION_2) { 916 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, 917 qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); 918 sysbus_connect_irq(gicbusdev, i + 5 * smp_cpus, 919 qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); 920 } 921 } 922 923 fdt_add_gic_node(vms); 924 925 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) { 926 create_its(vms); 927 } else if (vms->gic_version == VIRT_GIC_VERSION_2) { 928 create_v2m(vms); 929 } 930 } 931 932 static void create_uart(const VirtMachineState *vms, int uart, 933 MemoryRegion *mem, Chardev *chr, bool secure) 934 { 935 char *nodename; 936 hwaddr base = vms->memmap[uart].base; 937 hwaddr size = vms->memmap[uart].size; 938 int irq = vms->irqmap[uart]; 939 const char compat[] = "arm,pl011\0arm,primecell"; 940 const char clocknames[] = "uartclk\0apb_pclk"; 941 DeviceState *dev = qdev_new(TYPE_PL011); 942 SysBusDevice *s = SYS_BUS_DEVICE(dev); 943 MachineState *ms = MACHINE(vms); 944 945 qdev_prop_set_chr(dev, "chardev", chr); 946 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 947 memory_region_add_subregion(mem, base, 948 sysbus_mmio_get_region(s, 0)); 949 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 950 951 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 952 qemu_fdt_add_subnode(ms->fdt, nodename); 953 /* Note that we can't use setprop_string because of the embedded NUL */ 954 qemu_fdt_setprop(ms->fdt, nodename, "compatible", 955 compat, sizeof(compat)); 956 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 957 2, base, 2, size); 958 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 959 GIC_FDT_IRQ_TYPE_SPI, irq, 960 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 961 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", 962 vms->clock_phandle, vms->clock_phandle); 963 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", 964 clocknames, sizeof(clocknames)); 965 966 if (uart == VIRT_UART0) { 967 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 968 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", nodename); 969 } else { 970 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial1", nodename); 971 } 972 if (secure) { 973 /* Mark as not usable by the normal world */ 974 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 975 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 976 977 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", 978 nodename); 979 } 980 981 g_free(nodename); 982 } 983 984 static void create_rtc(const VirtMachineState *vms) 985 { 986 char *nodename; 987 hwaddr base = vms->memmap[VIRT_RTC].base; 988 hwaddr size = vms->memmap[VIRT_RTC].size; 989 int irq = vms->irqmap[VIRT_RTC]; 990 const char compat[] = "arm,pl031\0arm,primecell"; 991 MachineState *ms = MACHINE(vms); 992 993 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 994 995 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 996 qemu_fdt_add_subnode(ms->fdt, nodename); 997 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 998 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 999 2, base, 2, size); 1000 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1001 GIC_FDT_IRQ_TYPE_SPI, irq, 1002 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1003 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1004 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1005 g_free(nodename); 1006 } 1007 1008 static DeviceState *gpio_key_dev; 1009 static void virt_powerdown_req(Notifier *n, void *opaque) 1010 { 1011 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 1012 1013 if (s->acpi_dev) { 1014 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 1015 } else { 1016 /* use gpio Pin for power button event */ 1017 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 1018 } 1019 } 1020 1021 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, 1022 uint32_t phandle) 1023 { 1024 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 1025 qdev_get_gpio_in(pl061_dev, 1026 GPIO_PIN_POWER_BUTTON)); 1027 1028 qemu_fdt_add_subnode(fdt, "/gpio-keys"); 1029 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); 1030 1031 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); 1032 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", 1033 "label", "GPIO Key Poweroff"); 1034 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", 1035 KEY_POWER); 1036 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", 1037 "gpios", phandle, GPIO_PIN_POWER_BUTTON, 0); 1038 } 1039 1040 #define SECURE_GPIO_POWEROFF 0 1041 #define SECURE_GPIO_RESET 1 1042 1043 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, 1044 uint32_t phandle) 1045 { 1046 DeviceState *gpio_pwr_dev; 1047 1048 /* gpio-pwr */ 1049 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); 1050 1051 /* connect secure pl061 to gpio-pwr */ 1052 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, 1053 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); 1054 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, 1055 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); 1056 1057 qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); 1058 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", 1059 "gpio-poweroff"); 1060 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", 1061 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); 1062 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); 1063 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", 1064 "okay"); 1065 1066 qemu_fdt_add_subnode(fdt, "/gpio-restart"); 1067 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", 1068 "gpio-restart"); 1069 qemu_fdt_setprop_cells(fdt, "/gpio-restart", 1070 "gpios", phandle, SECURE_GPIO_RESET, 0); 1071 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); 1072 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", 1073 "okay"); 1074 } 1075 1076 static void create_gpio_devices(const VirtMachineState *vms, int gpio, 1077 MemoryRegion *mem) 1078 { 1079 char *nodename; 1080 DeviceState *pl061_dev; 1081 hwaddr base = vms->memmap[gpio].base; 1082 hwaddr size = vms->memmap[gpio].size; 1083 int irq = vms->irqmap[gpio]; 1084 const char compat[] = "arm,pl061\0arm,primecell"; 1085 SysBusDevice *s; 1086 MachineState *ms = MACHINE(vms); 1087 1088 pl061_dev = qdev_new("pl061"); 1089 /* Pull lines down to 0 if not driven by the PL061 */ 1090 qdev_prop_set_uint32(pl061_dev, "pullups", 0); 1091 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); 1092 s = SYS_BUS_DEVICE(pl061_dev); 1093 sysbus_realize_and_unref(s, &error_fatal); 1094 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); 1095 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 1096 1097 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); 1098 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 1099 qemu_fdt_add_subnode(ms->fdt, nodename); 1100 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1101 2, base, 2, size); 1102 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 1103 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); 1104 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); 1105 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1106 GIC_FDT_IRQ_TYPE_SPI, irq, 1107 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1108 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1109 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1110 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); 1111 1112 if (gpio != VIRT_GPIO) { 1113 /* Mark as not usable by the normal world */ 1114 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1115 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1116 } 1117 g_free(nodename); 1118 1119 /* Child gpio devices */ 1120 if (gpio == VIRT_GPIO) { 1121 create_gpio_keys(ms->fdt, pl061_dev, phandle); 1122 } else { 1123 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); 1124 } 1125 } 1126 1127 static void create_virtio_devices(const VirtMachineState *vms) 1128 { 1129 int i; 1130 hwaddr size = vms->memmap[VIRT_MMIO].size; 1131 MachineState *ms = MACHINE(vms); 1132 1133 /* We create the transports in forwards order. Since qbus_realize() 1134 * prepends (not appends) new child buses, the incrementing loop below will 1135 * create a list of virtio-mmio buses with decreasing base addresses. 1136 * 1137 * When a -device option is processed from the command line, 1138 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 1139 * order. The upshot is that -device options in increasing command line 1140 * order are mapped to virtio-mmio buses with decreasing base addresses. 1141 * 1142 * When this code was originally written, that arrangement ensured that the 1143 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 1144 * the first -device on the command line. (The end-to-end order is a 1145 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 1146 * guest kernel's name-to-address assignment strategy.) 1147 * 1148 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 1149 * the message, if not necessarily the code, of commit 70161ff336. 1150 * Therefore the loop now establishes the inverse of the original intent. 1151 * 1152 * Unfortunately, we can't counteract the kernel change by reversing the 1153 * loop; it would break existing command lines. 1154 * 1155 * In any case, the kernel makes no guarantee about the stability of 1156 * enumeration order of virtio devices (as demonstrated by it changing 1157 * between kernel versions). For reliable and stable identification 1158 * of disks users must use UUIDs or similar mechanisms. 1159 */ 1160 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 1161 int irq = vms->irqmap[VIRT_MMIO] + i; 1162 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1163 1164 sysbus_create_simple("virtio-mmio", base, 1165 qdev_get_gpio_in(vms->gic, irq)); 1166 } 1167 1168 /* We add dtb nodes in reverse order so that they appear in the finished 1169 * device tree lowest address first. 1170 * 1171 * Note that this mapping is independent of the loop above. The previous 1172 * loop influences virtio device to virtio transport assignment, whereas 1173 * this loop controls how virtio transports are laid out in the dtb. 1174 */ 1175 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 1176 char *nodename; 1177 int irq = vms->irqmap[VIRT_MMIO] + i; 1178 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1179 1180 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 1181 qemu_fdt_add_subnode(ms->fdt, nodename); 1182 qemu_fdt_setprop_string(ms->fdt, nodename, 1183 "compatible", "virtio,mmio"); 1184 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1185 2, base, 2, size); 1186 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1187 GIC_FDT_IRQ_TYPE_SPI, irq, 1188 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1189 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1190 g_free(nodename); 1191 } 1192 } 1193 1194 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 1195 1196 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 1197 const char *name, 1198 const char *alias_prop_name) 1199 { 1200 /* 1201 * Create a single flash device. We use the same parameters as 1202 * the flash devices on the Versatile Express board. 1203 */ 1204 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 1205 1206 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 1207 qdev_prop_set_uint8(dev, "width", 4); 1208 qdev_prop_set_uint8(dev, "device-width", 2); 1209 qdev_prop_set_bit(dev, "big-endian", false); 1210 qdev_prop_set_uint16(dev, "id0", 0x89); 1211 qdev_prop_set_uint16(dev, "id1", 0x18); 1212 qdev_prop_set_uint16(dev, "id2", 0x00); 1213 qdev_prop_set_uint16(dev, "id3", 0x00); 1214 qdev_prop_set_string(dev, "name", name); 1215 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 1216 object_property_add_alias(OBJECT(vms), alias_prop_name, 1217 OBJECT(dev), "drive"); 1218 return PFLASH_CFI01(dev); 1219 } 1220 1221 static void virt_flash_create(VirtMachineState *vms) 1222 { 1223 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 1224 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 1225 } 1226 1227 static void virt_flash_map1(PFlashCFI01 *flash, 1228 hwaddr base, hwaddr size, 1229 MemoryRegion *sysmem) 1230 { 1231 DeviceState *dev = DEVICE(flash); 1232 1233 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 1234 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 1235 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 1236 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1237 1238 memory_region_add_subregion(sysmem, base, 1239 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1240 0)); 1241 } 1242 1243 static void virt_flash_map(VirtMachineState *vms, 1244 MemoryRegion *sysmem, 1245 MemoryRegion *secure_sysmem) 1246 { 1247 /* 1248 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 1249 * sysmem is the system memory space. secure_sysmem is the secure view 1250 * of the system, and the first flash device should be made visible only 1251 * there. The second flash device is visible to both secure and nonsecure. 1252 * If sysmem == secure_sysmem this means there is no separate Secure 1253 * address space and both flash devices are generally visible. 1254 */ 1255 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1256 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1257 1258 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1259 secure_sysmem); 1260 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1261 sysmem); 1262 } 1263 1264 static void virt_flash_fdt(VirtMachineState *vms, 1265 MemoryRegion *sysmem, 1266 MemoryRegion *secure_sysmem) 1267 { 1268 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1269 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1270 MachineState *ms = MACHINE(vms); 1271 char *nodename; 1272 1273 if (sysmem == secure_sysmem) { 1274 /* Report both flash devices as a single node in the DT */ 1275 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1276 qemu_fdt_add_subnode(ms->fdt, nodename); 1277 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1278 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1279 2, flashbase, 2, flashsize, 1280 2, flashbase + flashsize, 2, flashsize); 1281 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1282 g_free(nodename); 1283 } else { 1284 /* 1285 * Report the devices as separate nodes so we can mark one as 1286 * only visible to the secure world. 1287 */ 1288 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1289 qemu_fdt_add_subnode(ms->fdt, nodename); 1290 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1291 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1292 2, flashbase, 2, flashsize); 1293 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1294 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1295 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1296 g_free(nodename); 1297 1298 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize); 1299 qemu_fdt_add_subnode(ms->fdt, nodename); 1300 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1301 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1302 2, flashbase + flashsize, 2, flashsize); 1303 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1304 g_free(nodename); 1305 } 1306 } 1307 1308 static bool virt_firmware_init(VirtMachineState *vms, 1309 MemoryRegion *sysmem, 1310 MemoryRegion *secure_sysmem) 1311 { 1312 int i; 1313 const char *bios_name; 1314 BlockBackend *pflash_blk0; 1315 1316 /* Map legacy -drive if=pflash to machine properties */ 1317 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1318 pflash_cfi01_legacy_drive(vms->flash[i], 1319 drive_get(IF_PFLASH, 0, i)); 1320 } 1321 1322 virt_flash_map(vms, sysmem, secure_sysmem); 1323 1324 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1325 1326 bios_name = MACHINE(vms)->firmware; 1327 if (bios_name) { 1328 char *fname; 1329 MemoryRegion *mr; 1330 int image_size; 1331 1332 if (pflash_blk0) { 1333 error_report("The contents of the first flash device may be " 1334 "specified with -bios or with -drive if=pflash... " 1335 "but you cannot use both options at once"); 1336 exit(1); 1337 } 1338 1339 /* Fall back to -bios */ 1340 1341 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1342 if (!fname) { 1343 error_report("Could not find ROM image '%s'", bios_name); 1344 exit(1); 1345 } 1346 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1347 image_size = load_image_mr(fname, mr); 1348 g_free(fname); 1349 if (image_size < 0) { 1350 error_report("Could not load ROM image '%s'", bios_name); 1351 exit(1); 1352 } 1353 } 1354 1355 return pflash_blk0 || bios_name; 1356 } 1357 1358 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1359 { 1360 MachineState *ms = MACHINE(vms); 1361 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1362 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1363 FWCfgState *fw_cfg; 1364 char *nodename; 1365 1366 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1367 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1368 1369 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1370 qemu_fdt_add_subnode(ms->fdt, nodename); 1371 qemu_fdt_setprop_string(ms->fdt, nodename, 1372 "compatible", "qemu,fw-cfg-mmio"); 1373 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1374 2, base, 2, size); 1375 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1376 g_free(nodename); 1377 return fw_cfg; 1378 } 1379 1380 static void create_pcie_irq_map(const MachineState *ms, 1381 uint32_t gic_phandle, 1382 int first_irq, const char *nodename) 1383 { 1384 int devfn, pin; 1385 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1386 uint32_t *irq_map = full_irq_map; 1387 1388 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1389 for (pin = 0; pin < 4; pin++) { 1390 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1391 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1392 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1393 int i; 1394 1395 uint32_t map[] = { 1396 devfn << 8, 0, 0, /* devfn */ 1397 pin + 1, /* PCI pin */ 1398 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1399 1400 /* Convert map to big endian */ 1401 for (i = 0; i < 10; i++) { 1402 irq_map[i] = cpu_to_be32(map[i]); 1403 } 1404 irq_map += 10; 1405 } 1406 } 1407 1408 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", 1409 full_irq_map, sizeof(full_irq_map)); 1410 1411 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 1412 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ 1413 0, 0, 1414 0x7 /* PCI irq */); 1415 } 1416 1417 static void create_smmu(const VirtMachineState *vms, 1418 PCIBus *bus) 1419 { 1420 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1421 char *node; 1422 const char compat[] = "arm,smmu-v3"; 1423 int irq = vms->irqmap[VIRT_SMMU]; 1424 int i; 1425 hwaddr base = vms->memmap[VIRT_SMMU].base; 1426 hwaddr size = vms->memmap[VIRT_SMMU].size; 1427 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1428 DeviceState *dev; 1429 MachineState *ms = MACHINE(vms); 1430 1431 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1432 return; 1433 } 1434 1435 dev = qdev_new(TYPE_ARM_SMMUV3); 1436 1437 if (!vmc->no_nested_smmu) { 1438 object_property_set_str(OBJECT(dev), "stage", "nested", &error_fatal); 1439 } 1440 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1441 &error_abort); 1442 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1443 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1444 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1445 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1446 qdev_get_gpio_in(vms->gic, irq + i)); 1447 } 1448 1449 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1450 qemu_fdt_add_subnode(ms->fdt, node); 1451 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1452 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); 1453 1454 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", 1455 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1456 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1457 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1458 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1459 1460 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, 1461 sizeof(irq_names)); 1462 1463 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); 1464 1465 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1466 1467 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1468 g_free(node); 1469 } 1470 1471 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1472 { 1473 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1474 uint16_t bdf = vms->virtio_iommu_bdf; 1475 MachineState *ms = MACHINE(vms); 1476 char *node; 1477 1478 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1479 1480 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename, 1481 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1482 qemu_fdt_add_subnode(ms->fdt, node); 1483 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1484 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 1485 1, bdf << 8, 1, 0, 1, 0, 1486 1, 0, 1, 0); 1487 1488 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1489 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1490 g_free(node); 1491 1492 if (!vms->default_bus_bypass_iommu) { 1493 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", 1494 0x0, vms->iommu_phandle, 0x0, bdf, 1495 bdf + 1, vms->iommu_phandle, bdf + 1, 1496 0xffff - bdf); 1497 } 1498 } 1499 1500 static void create_pcie(VirtMachineState *vms) 1501 { 1502 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1503 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1504 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1505 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1506 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1507 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1508 hwaddr base_ecam, size_ecam; 1509 hwaddr base = base_mmio; 1510 int nr_pcie_buses; 1511 int irq = vms->irqmap[VIRT_PCIE]; 1512 MemoryRegion *mmio_alias; 1513 MemoryRegion *mmio_reg; 1514 MemoryRegion *ecam_alias; 1515 MemoryRegion *ecam_reg; 1516 DeviceState *dev; 1517 char *nodename; 1518 int i, ecam_id; 1519 PCIHostState *pci; 1520 MachineState *ms = MACHINE(vms); 1521 MachineClass *mc = MACHINE_GET_CLASS(ms); 1522 1523 dev = qdev_new(TYPE_GPEX_HOST); 1524 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1525 1526 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1527 base_ecam = vms->memmap[ecam_id].base; 1528 size_ecam = vms->memmap[ecam_id].size; 1529 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1530 /* Map only the first size_ecam bytes of ECAM space */ 1531 ecam_alias = g_new0(MemoryRegion, 1); 1532 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1533 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1534 ecam_reg, 0, size_ecam); 1535 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1536 1537 /* Map the MMIO window into system address space so as to expose 1538 * the section of PCI MMIO space which starts at the same base address 1539 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1540 * the window). 1541 */ 1542 mmio_alias = g_new0(MemoryRegion, 1); 1543 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1544 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1545 mmio_reg, base_mmio, size_mmio); 1546 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1547 1548 if (vms->highmem_mmio) { 1549 /* Map high MMIO space */ 1550 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1551 1552 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1553 mmio_reg, base_mmio_high, size_mmio_high); 1554 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1555 high_mmio_alias); 1556 } 1557 1558 /* Map IO port space */ 1559 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1560 1561 for (i = 0; i < PCI_NUM_PINS; i++) { 1562 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1563 qdev_get_gpio_in(vms->gic, irq + i)); 1564 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1565 } 1566 1567 pci = PCI_HOST_BRIDGE(dev); 1568 pci->bypass_iommu = vms->default_bus_bypass_iommu; 1569 vms->bus = pci->bus; 1570 if (vms->bus) { 1571 pci_init_nic_devices(pci->bus, mc->default_nic); 1572 } 1573 1574 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1575 qemu_fdt_add_subnode(ms->fdt, nodename); 1576 qemu_fdt_setprop_string(ms->fdt, nodename, 1577 "compatible", "pci-host-ecam-generic"); 1578 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 1579 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 1580 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 1581 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 1582 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 1583 nr_pcie_buses - 1); 1584 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1585 1586 if (vms->msi_phandle) { 1587 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 1588 0, vms->msi_phandle, 0, 0x10000); 1589 } 1590 1591 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1592 2, base_ecam, 2, size_ecam); 1593 1594 if (vms->highmem_mmio) { 1595 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1596 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1597 2, base_pio, 2, size_pio, 1598 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1599 2, base_mmio, 2, size_mmio, 1600 1, FDT_PCI_RANGE_MMIO_64BIT, 1601 2, base_mmio_high, 1602 2, base_mmio_high, 2, size_mmio_high); 1603 } else { 1604 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1605 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1606 2, base_pio, 2, size_pio, 1607 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1608 2, base_mmio, 2, size_mmio); 1609 } 1610 1611 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 1612 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); 1613 1614 if (vms->iommu) { 1615 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1616 1617 switch (vms->iommu) { 1618 case VIRT_IOMMU_SMMUV3: 1619 create_smmu(vms, vms->bus); 1620 if (!vms->default_bus_bypass_iommu) { 1621 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 1622 0x0, vms->iommu_phandle, 0x0, 0x10000); 1623 } 1624 break; 1625 default: 1626 g_assert_not_reached(); 1627 } 1628 } 1629 } 1630 1631 static void create_cxl_host_reg_region(VirtMachineState *vms) 1632 { 1633 MemoryRegion *sysmem = get_system_memory(); 1634 MemoryRegion *mr = &vms->cxl_devices_state.host_mr; 1635 1636 memory_region_init(mr, OBJECT(vms), "cxl_host_reg", 1637 vms->memmap[VIRT_CXL_HOST].size); 1638 memory_region_add_subregion(sysmem, vms->memmap[VIRT_CXL_HOST].base, mr); 1639 vms->highmem_cxl = true; 1640 } 1641 1642 static void create_platform_bus(VirtMachineState *vms) 1643 { 1644 DeviceState *dev; 1645 SysBusDevice *s; 1646 int i; 1647 MemoryRegion *sysmem = get_system_memory(); 1648 1649 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1650 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1651 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1652 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1653 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1654 vms->platform_bus_dev = dev; 1655 1656 s = SYS_BUS_DEVICE(dev); 1657 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1658 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1659 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1660 } 1661 1662 memory_region_add_subregion(sysmem, 1663 vms->memmap[VIRT_PLATFORM_BUS].base, 1664 sysbus_mmio_get_region(s, 0)); 1665 } 1666 1667 static void create_tag_ram(MemoryRegion *tag_sysmem, 1668 hwaddr base, hwaddr size, 1669 const char *name) 1670 { 1671 MemoryRegion *tagram = g_new(MemoryRegion, 1); 1672 1673 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); 1674 memory_region_add_subregion(tag_sysmem, base / 32, tagram); 1675 } 1676 1677 static void create_secure_ram(VirtMachineState *vms, 1678 MemoryRegion *secure_sysmem, 1679 MemoryRegion *secure_tag_sysmem) 1680 { 1681 MemoryRegion *secram = g_new(MemoryRegion, 1); 1682 char *nodename; 1683 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1684 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1685 MachineState *ms = MACHINE(vms); 1686 1687 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1688 &error_fatal); 1689 memory_region_add_subregion(secure_sysmem, base, secram); 1690 1691 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1692 qemu_fdt_add_subnode(ms->fdt, nodename); 1693 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 1694 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 1695 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1696 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1697 1698 if (secure_tag_sysmem) { 1699 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); 1700 } 1701 1702 g_free(nodename); 1703 } 1704 1705 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1706 { 1707 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1708 bootinfo); 1709 MachineState *ms = MACHINE(board); 1710 1711 1712 *fdt_size = board->fdt_size; 1713 return ms->fdt; 1714 } 1715 1716 static void virt_build_smbios(VirtMachineState *vms) 1717 { 1718 MachineClass *mc = MACHINE_GET_CLASS(vms); 1719 MachineState *ms = MACHINE(vms); 1720 uint8_t *smbios_tables, *smbios_anchor; 1721 size_t smbios_tables_len, smbios_anchor_len; 1722 struct smbios_phys_mem_area mem_array; 1723 const char *product = "QEMU Virtual Machine"; 1724 1725 if (kvm_enabled()) { 1726 product = "KVM Virtual Machine"; 1727 } 1728 1729 smbios_set_defaults("QEMU", product, mc->name); 1730 1731 /* build the array of physical mem area from base_memmap */ 1732 mem_array.address = vms->memmap[VIRT_MEM].base; 1733 mem_array.length = ms->ram_size; 1734 1735 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, &mem_array, 1, 1736 &smbios_tables, &smbios_tables_len, 1737 &smbios_anchor, &smbios_anchor_len, 1738 &error_fatal); 1739 1740 if (smbios_anchor) { 1741 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1742 smbios_tables, smbios_tables_len); 1743 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1744 smbios_anchor, smbios_anchor_len); 1745 } 1746 } 1747 1748 static 1749 void virt_machine_done(Notifier *notifier, void *data) 1750 { 1751 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1752 machine_done); 1753 MachineState *ms = MACHINE(vms); 1754 ARMCPU *cpu = ARM_CPU(first_cpu); 1755 struct arm_boot_info *info = &vms->bootinfo; 1756 AddressSpace *as = arm_boot_address_space(cpu, info); 1757 1758 cxl_hook_up_pxb_registers(vms->bus, &vms->cxl_devices_state, 1759 &error_fatal); 1760 1761 if (vms->cxl_devices_state.is_enabled) { 1762 cxl_fmws_link_targets(&error_fatal); 1763 } 1764 /* 1765 * If the user provided a dtb, we assume the dynamic sysbus nodes 1766 * already are integrated there. This corresponds to a use case where 1767 * the dynamic sysbus nodes are complex and their generation is not yet 1768 * supported. In that case the user can take charge of the guest dt 1769 * while qemu takes charge of the qom stuff. 1770 */ 1771 if (info->dtb_filename == NULL) { 1772 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", 1773 vms->memmap[VIRT_PLATFORM_BUS].base, 1774 vms->memmap[VIRT_PLATFORM_BUS].size, 1775 vms->irqmap[VIRT_PLATFORM_BUS]); 1776 } 1777 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms, cpu) < 0) { 1778 exit(1); 1779 } 1780 1781 pci_bus_add_fw_cfg_extra_pci_roots(vms->fw_cfg, vms->bus, 1782 &error_abort); 1783 1784 virt_acpi_setup(vms); 1785 virt_build_smbios(vms); 1786 } 1787 1788 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1789 { 1790 uint8_t clustersz; 1791 1792 /* 1793 * Adjust MPIDR to make TCG consistent (with 64-bit KVM hosts) 1794 * and to improve SGI efficiency. 1795 */ 1796 if (vms->gic_version == VIRT_GIC_VERSION_2) { 1797 clustersz = GIC_TARGETLIST_BITS; 1798 } else { 1799 clustersz = GICV3_TARGETLIST_BITS; 1800 } 1801 1802 return arm_build_mp_affinity(idx, clustersz); 1803 } 1804 1805 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, 1806 int index) 1807 { 1808 bool *enabled_array[] = { 1809 &vms->highmem_redists, 1810 &vms->highmem_cxl, 1811 &vms->highmem_ecam, 1812 &vms->highmem_mmio, 1813 }; 1814 1815 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST == 1816 ARRAY_SIZE(enabled_array)); 1817 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array)); 1818 1819 return enabled_array[index - VIRT_LOWMEMMAP_LAST]; 1820 } 1821 1822 static void virt_set_high_memmap(VirtMachineState *vms, 1823 hwaddr base, int pa_bits) 1824 { 1825 hwaddr region_base, region_size; 1826 bool *region_enabled, fits; 1827 int i; 1828 1829 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1830 region_enabled = virt_get_high_memmap_enabled(vms, i); 1831 region_base = ROUND_UP(base, extended_memmap[i].size); 1832 region_size = extended_memmap[i].size; 1833 1834 vms->memmap[i].base = region_base; 1835 vms->memmap[i].size = region_size; 1836 1837 /* 1838 * Check each device to see if it fits in the PA space, 1839 * moving highest_gpa as we go. For compatibility, move 1840 * highest_gpa for disabled fitting devices as well, if 1841 * the compact layout has been disabled. 1842 * 1843 * For each device that doesn't fit, disable it. 1844 */ 1845 fits = (region_base + region_size) <= BIT_ULL(pa_bits); 1846 *region_enabled &= fits; 1847 if (vms->highmem_compact && !*region_enabled) { 1848 continue; 1849 } 1850 1851 base = region_base + region_size; 1852 if (fits) { 1853 vms->highest_gpa = base - 1; 1854 } 1855 } 1856 } 1857 1858 static void virt_set_memmap(VirtMachineState *vms, int pa_bits) 1859 { 1860 MachineState *ms = MACHINE(vms); 1861 hwaddr base, device_memory_base, device_memory_size, memtop; 1862 int i; 1863 1864 vms->memmap = extended_memmap; 1865 1866 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1867 vms->memmap[i] = base_memmap[i]; 1868 } 1869 1870 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1871 error_report("unsupported number of memory slots: %"PRIu64, 1872 ms->ram_slots); 1873 exit(EXIT_FAILURE); 1874 } 1875 1876 /* 1877 * !highmem is exactly the same as limiting the PA space to 32bit, 1878 * irrespective of the underlying capabilities of the HW. 1879 */ 1880 if (!vms->highmem) { 1881 pa_bits = 32; 1882 } 1883 1884 /* 1885 * We compute the base of the high IO region depending on the 1886 * amount of initial and device memory. The device memory start/size 1887 * is aligned on 1GiB. We never put the high IO region below 256GiB 1888 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1889 * The device region size assumes 1GiB page max alignment per slot. 1890 */ 1891 device_memory_base = 1892 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1893 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1894 1895 /* Base address of the high IO region */ 1896 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1897 if (memtop > BIT_ULL(pa_bits)) { 1898 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes", 1899 pa_bits, memtop - BIT_ULL(pa_bits)); 1900 exit(EXIT_FAILURE); 1901 } 1902 if (base < device_memory_base) { 1903 error_report("maxmem/slots too huge"); 1904 exit(EXIT_FAILURE); 1905 } 1906 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1907 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1908 } 1909 1910 /* We know for sure that at least the memory fits in the PA space */ 1911 vms->highest_gpa = memtop - 1; 1912 1913 virt_set_high_memmap(vms, base, pa_bits); 1914 1915 if (device_memory_size > 0) { 1916 machine_memory_devices_init(ms, device_memory_base, device_memory_size); 1917 } 1918 vms->highest_gpa = cxl_fmws_set_memmap(ROUND_UP(vms->highest_gpa + 1, 1919 256 * MiB), 1920 BIT_ULL(pa_bits)) - 1; 1921 } 1922 1923 static VirtGICType finalize_gic_version_do(const char *accel_name, 1924 VirtGICType gic_version, 1925 int gics_supported, 1926 unsigned int max_cpus) 1927 { 1928 /* Convert host/max/nosel to GIC version number */ 1929 switch (gic_version) { 1930 case VIRT_GIC_VERSION_HOST: 1931 if (!kvm_enabled()) { 1932 error_report("gic-version=host requires KVM"); 1933 exit(1); 1934 } 1935 1936 /* For KVM, gic-version=host means gic-version=max */ 1937 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX, 1938 gics_supported, max_cpus); 1939 case VIRT_GIC_VERSION_MAX: 1940 if (gics_supported & VIRT_GIC_VERSION_4_MASK) { 1941 gic_version = VIRT_GIC_VERSION_4; 1942 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1943 gic_version = VIRT_GIC_VERSION_3; 1944 } else { 1945 gic_version = VIRT_GIC_VERSION_2; 1946 } 1947 break; 1948 case VIRT_GIC_VERSION_NOSEL: 1949 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) && 1950 max_cpus <= GIC_NCPU) { 1951 gic_version = VIRT_GIC_VERSION_2; 1952 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1953 /* 1954 * in case the host does not support v2 emulation or 1955 * the end-user requested more than 8 VCPUs we now default 1956 * to v3. In any case defaulting to v2 would be broken. 1957 */ 1958 gic_version = VIRT_GIC_VERSION_3; 1959 } else if (max_cpus > GIC_NCPU) { 1960 error_report("%s only supports GICv2 emulation but more than 8 " 1961 "vcpus are requested", accel_name); 1962 exit(1); 1963 } 1964 break; 1965 case VIRT_GIC_VERSION_2: 1966 case VIRT_GIC_VERSION_3: 1967 case VIRT_GIC_VERSION_4: 1968 break; 1969 } 1970 1971 /* Check chosen version is effectively supported */ 1972 switch (gic_version) { 1973 case VIRT_GIC_VERSION_2: 1974 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) { 1975 error_report("%s does not support GICv2 emulation", accel_name); 1976 exit(1); 1977 } 1978 break; 1979 case VIRT_GIC_VERSION_3: 1980 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) { 1981 error_report("%s does not support GICv3 emulation", accel_name); 1982 exit(1); 1983 } 1984 break; 1985 case VIRT_GIC_VERSION_4: 1986 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) { 1987 error_report("%s does not support GICv4 emulation, is virtualization=on?", 1988 accel_name); 1989 exit(1); 1990 } 1991 break; 1992 default: 1993 error_report("logic error in finalize_gic_version"); 1994 exit(1); 1995 break; 1996 } 1997 1998 return gic_version; 1999 } 2000 2001 /* 2002 * finalize_gic_version - Determines the final gic_version 2003 * according to the gic-version property 2004 * 2005 * Default GIC type is v2 2006 */ 2007 static void finalize_gic_version(VirtMachineState *vms) 2008 { 2009 const char *accel_name = current_accel_name(); 2010 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 2011 int gics_supported = 0; 2012 2013 /* Determine which GIC versions the current environment supports */ 2014 if (kvm_enabled() && kvm_irqchip_in_kernel()) { 2015 int probe_bitmap = kvm_arm_vgic_probe(); 2016 2017 if (!probe_bitmap) { 2018 error_report("Unable to determine GIC version supported by host"); 2019 exit(1); 2020 } 2021 2022 if (probe_bitmap & KVM_ARM_VGIC_V2) { 2023 gics_supported |= VIRT_GIC_VERSION_2_MASK; 2024 } 2025 if (probe_bitmap & KVM_ARM_VGIC_V3) { 2026 gics_supported |= VIRT_GIC_VERSION_3_MASK; 2027 } 2028 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) { 2029 /* KVM w/o kernel irqchip can only deal with GICv2 */ 2030 gics_supported |= VIRT_GIC_VERSION_2_MASK; 2031 accel_name = "KVM with kernel-irqchip=off"; 2032 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { 2033 gics_supported |= VIRT_GIC_VERSION_2_MASK; 2034 if (module_object_class_by_name("arm-gicv3")) { 2035 gics_supported |= VIRT_GIC_VERSION_3_MASK; 2036 if (vms->virt) { 2037 /* GICv4 only makes sense if CPU has EL2 */ 2038 gics_supported |= VIRT_GIC_VERSION_4_MASK; 2039 } 2040 } 2041 } else { 2042 error_report("Unsupported accelerator, can not determine GIC support"); 2043 exit(1); 2044 } 2045 2046 /* 2047 * Then convert helpers like host/max to concrete GIC versions and ensure 2048 * the desired version is supported 2049 */ 2050 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version, 2051 gics_supported, max_cpus); 2052 } 2053 2054 /* 2055 * virt_post_cpus_gic_realized() must be called after the CPUs and 2056 * the GIC have both been realized. 2057 */ 2058 static void virt_post_cpus_gic_realized(VirtMachineState *vms, 2059 MemoryRegion *sysmem) 2060 { 2061 int max_cpus = MACHINE(vms)->smp.max_cpus; 2062 bool aarch64, pmu, steal_time; 2063 CPUState *cpu; 2064 2065 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); 2066 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); 2067 steal_time = object_property_get_bool(OBJECT(first_cpu), 2068 "kvm-steal-time", NULL); 2069 2070 if (kvm_enabled()) { 2071 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; 2072 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; 2073 2074 if (steal_time) { 2075 MemoryRegion *pvtime = g_new(MemoryRegion, 1); 2076 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; 2077 2078 /* The memory region size must be a multiple of host page size. */ 2079 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); 2080 2081 if (pvtime_size > pvtime_reg_size) { 2082 error_report("pvtime requires a %" HWADDR_PRId 2083 " byte memory region for %d CPUs," 2084 " but only %" HWADDR_PRId " has been reserved", 2085 pvtime_size, max_cpus, pvtime_reg_size); 2086 exit(1); 2087 } 2088 2089 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); 2090 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); 2091 } 2092 2093 CPU_FOREACH(cpu) { 2094 if (pmu) { 2095 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); 2096 if (kvm_irqchip_in_kernel()) { 2097 kvm_arm_pmu_set_irq(ARM_CPU(cpu), VIRTUAL_PMU_IRQ); 2098 } 2099 kvm_arm_pmu_init(ARM_CPU(cpu)); 2100 } 2101 if (steal_time) { 2102 kvm_arm_pvtime_init(ARM_CPU(cpu), pvtime_reg_base 2103 + cpu->cpu_index 2104 * PVTIME_SIZE_PER_CPU); 2105 } 2106 } 2107 } else { 2108 if (aarch64 && vms->highmem) { 2109 int requested_pa_size = 64 - clz64(vms->highest_gpa); 2110 int pamax = arm_pamax(ARM_CPU(first_cpu)); 2111 2112 if (pamax < requested_pa_size) { 2113 error_report("VCPU supports less PA bits (%d) than " 2114 "requested by the memory map (%d)", 2115 pamax, requested_pa_size); 2116 exit(1); 2117 } 2118 } 2119 } 2120 } 2121 2122 static void machvirt_init(MachineState *machine) 2123 { 2124 VirtMachineState *vms = VIRT_MACHINE(machine); 2125 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 2126 MachineClass *mc = MACHINE_GET_CLASS(machine); 2127 const CPUArchIdList *possible_cpus; 2128 MemoryRegion *sysmem = get_system_memory(); 2129 MemoryRegion *secure_sysmem = NULL; 2130 MemoryRegion *tag_sysmem = NULL; 2131 MemoryRegion *secure_tag_sysmem = NULL; 2132 int n, virt_max_cpus; 2133 bool firmware_loaded; 2134 bool aarch64 = true; 2135 bool has_ged = !vmc->no_ged; 2136 unsigned int smp_cpus = machine->smp.cpus; 2137 unsigned int max_cpus = machine->smp.max_cpus; 2138 2139 possible_cpus = mc->possible_cpu_arch_ids(machine); 2140 2141 /* 2142 * In accelerated mode, the memory map is computed earlier in kvm_type() 2143 * for Linux, or hvf_get_physical_address_range() for macOS to create a 2144 * VM with the right number of IPA bits. 2145 */ 2146 if (!vms->memmap) { 2147 Object *cpuobj; 2148 ARMCPU *armcpu; 2149 int pa_bits; 2150 2151 /* 2152 * Instantiate a temporary CPU object to find out about what 2153 * we are about to deal with. Once this is done, get rid of 2154 * the object. 2155 */ 2156 cpuobj = object_new(possible_cpus->cpus[0].type); 2157 armcpu = ARM_CPU(cpuobj); 2158 2159 pa_bits = arm_pamax(armcpu); 2160 2161 object_unref(cpuobj); 2162 2163 virt_set_memmap(vms, pa_bits); 2164 } 2165 2166 /* We can probe only here because during property set 2167 * KVM is not available yet 2168 */ 2169 finalize_gic_version(vms); 2170 2171 if (vms->secure) { 2172 /* 2173 * The Secure view of the world is the same as the NonSecure, 2174 * but with a few extra devices. Create it as a container region 2175 * containing the system memory at low priority; any secure-only 2176 * devices go in at higher priority and take precedence. 2177 */ 2178 secure_sysmem = g_new(MemoryRegion, 1); 2179 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 2180 UINT64_MAX); 2181 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 2182 } 2183 2184 firmware_loaded = virt_firmware_init(vms, sysmem, 2185 secure_sysmem ?: sysmem); 2186 2187 /* If we have an EL3 boot ROM then the assumption is that it will 2188 * implement PSCI itself, so disable QEMU's internal implementation 2189 * so it doesn't get in the way. Instead of starting secondary 2190 * CPUs in PSCI powerdown state we will start them all running and 2191 * let the boot ROM sort them out. 2192 * The usual case is that we do use QEMU's PSCI implementation; 2193 * if the guest has EL2 then we will use SMC as the conduit, 2194 * and otherwise we will use HVC (for backwards compatibility and 2195 * because if we're using KVM then we must use HVC). 2196 */ 2197 if (vms->secure && firmware_loaded) { 2198 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 2199 } else if (vms->virt) { 2200 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 2201 } else { 2202 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 2203 } 2204 2205 /* 2206 * The maximum number of CPUs depends on the GIC version, or on how 2207 * many redistributors we can fit into the memory map (which in turn 2208 * depends on whether this is a GICv3 or v4). 2209 */ 2210 if (vms->gic_version == VIRT_GIC_VERSION_2) { 2211 virt_max_cpus = GIC_NCPU; 2212 } else { 2213 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST); 2214 if (vms->highmem_redists) { 2215 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 2216 } 2217 } 2218 2219 if (max_cpus > virt_max_cpus) { 2220 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 2221 "supported by machine 'mach-virt' (%d)", 2222 max_cpus, virt_max_cpus); 2223 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) { 2224 error_printf("Try 'highmem-redists=on' for more CPUs\n"); 2225 } 2226 2227 exit(1); 2228 } 2229 2230 if (vms->secure && !tcg_enabled() && !qtest_enabled()) { 2231 error_report("mach-virt: %s does not support providing " 2232 "Security extensions (TrustZone) to the guest CPU", 2233 current_accel_name()); 2234 exit(1); 2235 } 2236 2237 if (vms->virt && !tcg_enabled() && !qtest_enabled()) { 2238 error_report("mach-virt: %s does not support providing " 2239 "Virtualization extensions to the guest CPU", 2240 current_accel_name()); 2241 exit(1); 2242 } 2243 2244 if (vms->mte && hvf_enabled()) { 2245 error_report("mach-virt: %s does not support providing " 2246 "MTE to the guest CPU", 2247 current_accel_name()); 2248 exit(1); 2249 } 2250 2251 create_fdt(vms); 2252 2253 assert(possible_cpus->len == max_cpus); 2254 for (n = 0; n < possible_cpus->len; n++) { 2255 Object *cpuobj; 2256 CPUState *cs; 2257 2258 if (n >= smp_cpus) { 2259 break; 2260 } 2261 2262 cpuobj = object_new(possible_cpus->cpus[n].type); 2263 object_property_set_int(cpuobj, "mp-affinity", 2264 possible_cpus->cpus[n].arch_id, NULL); 2265 2266 cs = CPU(cpuobj); 2267 cs->cpu_index = n; 2268 2269 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 2270 &error_fatal); 2271 2272 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 2273 2274 if (!vms->secure) { 2275 object_property_set_bool(cpuobj, "has_el3", false, NULL); 2276 } 2277 2278 if (!vms->virt && object_property_find(cpuobj, "has_el2")) { 2279 object_property_set_bool(cpuobj, "has_el2", false, NULL); 2280 } 2281 2282 if (vmc->kvm_no_adjvtime && 2283 object_property_find(cpuobj, "kvm-no-adjvtime")) { 2284 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 2285 } 2286 2287 if (vmc->no_kvm_steal_time && 2288 object_property_find(cpuobj, "kvm-steal-time")) { 2289 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); 2290 } 2291 2292 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { 2293 object_property_set_bool(cpuobj, "lpa2", false, NULL); 2294 } 2295 2296 if (object_property_find(cpuobj, "reset-cbar")) { 2297 object_property_set_int(cpuobj, "reset-cbar", 2298 vms->memmap[VIRT_CPUPERIPHS].base, 2299 &error_abort); 2300 } 2301 2302 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 2303 &error_abort); 2304 if (vms->secure) { 2305 object_property_set_link(cpuobj, "secure-memory", 2306 OBJECT(secure_sysmem), &error_abort); 2307 } 2308 2309 if (vms->mte) { 2310 if (tcg_enabled()) { 2311 /* Create the memory region only once, but link to all cpus. */ 2312 if (!tag_sysmem) { 2313 /* 2314 * The property exists only if MemTag is supported. 2315 * If it is, we must allocate the ram to back that up. 2316 */ 2317 if (!object_property_find(cpuobj, "tag-memory")) { 2318 error_report("MTE requested, but not supported " 2319 "by the guest CPU"); 2320 exit(1); 2321 } 2322 2323 tag_sysmem = g_new(MemoryRegion, 1); 2324 memory_region_init(tag_sysmem, OBJECT(machine), 2325 "tag-memory", UINT64_MAX / 32); 2326 2327 if (vms->secure) { 2328 secure_tag_sysmem = g_new(MemoryRegion, 1); 2329 memory_region_init(secure_tag_sysmem, OBJECT(machine), 2330 "secure-tag-memory", 2331 UINT64_MAX / 32); 2332 2333 /* As with ram, secure-tag takes precedence over tag. */ 2334 memory_region_add_subregion_overlap(secure_tag_sysmem, 2335 0, tag_sysmem, -1); 2336 } 2337 } 2338 2339 object_property_set_link(cpuobj, "tag-memory", 2340 OBJECT(tag_sysmem), &error_abort); 2341 if (vms->secure) { 2342 object_property_set_link(cpuobj, "secure-tag-memory", 2343 OBJECT(secure_tag_sysmem), 2344 &error_abort); 2345 } 2346 } else if (kvm_enabled()) { 2347 if (!kvm_arm_mte_supported()) { 2348 error_report("MTE requested, but not supported by KVM"); 2349 exit(1); 2350 } 2351 kvm_arm_enable_mte(cpuobj, &error_abort); 2352 } else { 2353 error_report("MTE requested, but not supported "); 2354 exit(1); 2355 } 2356 } 2357 2358 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 2359 object_unref(cpuobj); 2360 } 2361 2362 /* Now we've created the CPUs we can see if they have the hypvirt timer */ 2363 vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() && 2364 !vmc->no_ns_el2_virt_timer_irq; 2365 2366 fdt_add_timer_nodes(vms); 2367 fdt_add_cpu_nodes(vms); 2368 2369 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 2370 machine->ram); 2371 2372 cxl_fmws_update_mmio(); 2373 2374 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 2375 2376 create_gic(vms, sysmem); 2377 2378 virt_post_cpus_gic_realized(vms, sysmem); 2379 2380 fdt_add_pmu_nodes(vms); 2381 2382 /* 2383 * The first UART always exists. If the security extensions are 2384 * enabled, the second UART also always exists. Otherwise, it only exists 2385 * if a backend is configured explicitly via '-serial <backend>'. 2386 * This avoids potentially breaking existing user setups that expect 2387 * only one NonSecure UART to be present (for instance, older EDK2 2388 * binaries). 2389 * 2390 * The nodes end up in the DTB in reverse order of creation, so we must 2391 * create UART0 last to ensure it appears as the first node in the DTB, 2392 * for compatibility with guest software that just iterates through the 2393 * DTB to find the first UART, as older versions of EDK2 do. 2394 * DTB readers that follow the spec, as Linux does, should honour the 2395 * aliases node information and /chosen/stdout-path regardless of 2396 * the order that nodes appear in the DTB. 2397 * 2398 * For similar back-compatibility reasons, if UART1 is the secure UART 2399 * we create it second (and so it appears first in the DTB), because 2400 * that's what QEMU has always done. 2401 */ 2402 if (!vms->secure) { 2403 Chardev *serial1 = serial_hd(1); 2404 2405 if (serial1) { 2406 vms->second_ns_uart_present = true; 2407 create_uart(vms, VIRT_UART1, sysmem, serial1, false); 2408 } 2409 } 2410 create_uart(vms, VIRT_UART0, sysmem, serial_hd(0), false); 2411 if (vms->secure) { 2412 create_uart(vms, VIRT_UART1, secure_sysmem, serial_hd(1), true); 2413 } 2414 2415 if (vms->secure) { 2416 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); 2417 } 2418 2419 if (tag_sysmem) { 2420 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, 2421 machine->ram_size, "mach-virt.tag"); 2422 } 2423 2424 vms->highmem_ecam &= (!firmware_loaded || aarch64); 2425 2426 create_rtc(vms); 2427 2428 create_pcie(vms); 2429 create_cxl_host_reg_region(vms); 2430 2431 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 2432 vms->acpi_dev = create_acpi_ged(vms); 2433 } else { 2434 create_gpio_devices(vms, VIRT_GPIO, sysmem); 2435 } 2436 2437 if (vms->secure && !vmc->no_secure_gpio) { 2438 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); 2439 } 2440 2441 /* connect powerdown request */ 2442 vms->powerdown_notifier.notify = virt_powerdown_req; 2443 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 2444 2445 /* Create mmio transports, so the user can create virtio backends 2446 * (which will be automatically plugged in to the transports). If 2447 * no backend is created the transport will just sit harmlessly idle. 2448 */ 2449 create_virtio_devices(vms); 2450 2451 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 2452 rom_set_fw(vms->fw_cfg); 2453 2454 create_platform_bus(vms); 2455 2456 if (machine->nvdimms_state->is_enabled) { 2457 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 2458 .space_id = AML_AS_SYSTEM_MEMORY, 2459 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 2460 .bit_width = NVDIMM_ACPI_IO_LEN << 3 2461 }; 2462 2463 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 2464 arm_virt_nvdimm_acpi_dsmio, 2465 vms->fw_cfg, OBJECT(vms)); 2466 } 2467 2468 vms->bootinfo.ram_size = machine->ram_size; 2469 vms->bootinfo.board_id = -1; 2470 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 2471 vms->bootinfo.get_dtb = machvirt_dtb; 2472 vms->bootinfo.skip_dtb_autoload = true; 2473 vms->bootinfo.firmware_loaded = firmware_loaded; 2474 vms->bootinfo.psci_conduit = vms->psci_conduit; 2475 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 2476 2477 vms->machine_done.notify = virt_machine_done; 2478 qemu_add_machine_init_done_notifier(&vms->machine_done); 2479 } 2480 2481 static bool virt_get_secure(Object *obj, Error **errp) 2482 { 2483 VirtMachineState *vms = VIRT_MACHINE(obj); 2484 2485 return vms->secure; 2486 } 2487 2488 static void virt_set_secure(Object *obj, bool value, Error **errp) 2489 { 2490 VirtMachineState *vms = VIRT_MACHINE(obj); 2491 2492 vms->secure = value; 2493 } 2494 2495 static bool virt_get_virt(Object *obj, Error **errp) 2496 { 2497 VirtMachineState *vms = VIRT_MACHINE(obj); 2498 2499 return vms->virt; 2500 } 2501 2502 static void virt_set_virt(Object *obj, bool value, Error **errp) 2503 { 2504 VirtMachineState *vms = VIRT_MACHINE(obj); 2505 2506 vms->virt = value; 2507 } 2508 2509 static bool virt_get_highmem(Object *obj, Error **errp) 2510 { 2511 VirtMachineState *vms = VIRT_MACHINE(obj); 2512 2513 return vms->highmem; 2514 } 2515 2516 static void virt_set_highmem(Object *obj, bool value, Error **errp) 2517 { 2518 VirtMachineState *vms = VIRT_MACHINE(obj); 2519 2520 vms->highmem = value; 2521 } 2522 2523 static bool virt_get_compact_highmem(Object *obj, Error **errp) 2524 { 2525 VirtMachineState *vms = VIRT_MACHINE(obj); 2526 2527 return vms->highmem_compact; 2528 } 2529 2530 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp) 2531 { 2532 VirtMachineState *vms = VIRT_MACHINE(obj); 2533 2534 vms->highmem_compact = value; 2535 } 2536 2537 static bool virt_get_highmem_redists(Object *obj, Error **errp) 2538 { 2539 VirtMachineState *vms = VIRT_MACHINE(obj); 2540 2541 return vms->highmem_redists; 2542 } 2543 2544 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp) 2545 { 2546 VirtMachineState *vms = VIRT_MACHINE(obj); 2547 2548 vms->highmem_redists = value; 2549 } 2550 2551 static bool virt_get_highmem_ecam(Object *obj, Error **errp) 2552 { 2553 VirtMachineState *vms = VIRT_MACHINE(obj); 2554 2555 return vms->highmem_ecam; 2556 } 2557 2558 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp) 2559 { 2560 VirtMachineState *vms = VIRT_MACHINE(obj); 2561 2562 vms->highmem_ecam = value; 2563 } 2564 2565 static bool virt_get_highmem_mmio(Object *obj, Error **errp) 2566 { 2567 VirtMachineState *vms = VIRT_MACHINE(obj); 2568 2569 return vms->highmem_mmio; 2570 } 2571 2572 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp) 2573 { 2574 VirtMachineState *vms = VIRT_MACHINE(obj); 2575 2576 vms->highmem_mmio = value; 2577 } 2578 2579 static void virt_get_highmem_mmio_size(Object *obj, Visitor *v, 2580 const char *name, void *opaque, 2581 Error **errp) 2582 { 2583 uint64_t size = extended_memmap[VIRT_HIGH_PCIE_MMIO].size; 2584 2585 visit_type_size(v, name, &size, errp); 2586 } 2587 2588 static void virt_set_highmem_mmio_size(Object *obj, Visitor *v, 2589 const char *name, void *opaque, 2590 Error **errp) 2591 { 2592 uint64_t size; 2593 2594 if (!visit_type_size(v, name, &size, errp)) { 2595 return; 2596 } 2597 2598 if (!is_power_of_2(size)) { 2599 error_setg(errp, "highmem-mmio-size is not a power of 2"); 2600 return; 2601 } 2602 2603 if (size < DEFAULT_HIGH_PCIE_MMIO_SIZE) { 2604 char *sz = size_to_str(DEFAULT_HIGH_PCIE_MMIO_SIZE); 2605 error_setg(errp, "highmem-mmio-size cannot be set to a lower value " 2606 "than the default (%s)", sz); 2607 g_free(sz); 2608 return; 2609 } 2610 2611 extended_memmap[VIRT_HIGH_PCIE_MMIO].size = size; 2612 } 2613 2614 static bool virt_get_its(Object *obj, Error **errp) 2615 { 2616 VirtMachineState *vms = VIRT_MACHINE(obj); 2617 2618 return vms->its; 2619 } 2620 2621 static void virt_set_its(Object *obj, bool value, Error **errp) 2622 { 2623 VirtMachineState *vms = VIRT_MACHINE(obj); 2624 2625 vms->its = value; 2626 } 2627 2628 static bool virt_get_dtb_randomness(Object *obj, Error **errp) 2629 { 2630 VirtMachineState *vms = VIRT_MACHINE(obj); 2631 2632 return vms->dtb_randomness; 2633 } 2634 2635 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp) 2636 { 2637 VirtMachineState *vms = VIRT_MACHINE(obj); 2638 2639 vms->dtb_randomness = value; 2640 } 2641 2642 static char *virt_get_oem_id(Object *obj, Error **errp) 2643 { 2644 VirtMachineState *vms = VIRT_MACHINE(obj); 2645 2646 return g_strdup(vms->oem_id); 2647 } 2648 2649 static void virt_set_oem_id(Object *obj, const char *value, Error **errp) 2650 { 2651 VirtMachineState *vms = VIRT_MACHINE(obj); 2652 size_t len = strlen(value); 2653 2654 if (len > 6) { 2655 error_setg(errp, 2656 "User specified oem-id value is bigger than 6 bytes in size"); 2657 return; 2658 } 2659 2660 strncpy(vms->oem_id, value, 6); 2661 } 2662 2663 static char *virt_get_oem_table_id(Object *obj, Error **errp) 2664 { 2665 VirtMachineState *vms = VIRT_MACHINE(obj); 2666 2667 return g_strdup(vms->oem_table_id); 2668 } 2669 2670 static void virt_set_oem_table_id(Object *obj, const char *value, 2671 Error **errp) 2672 { 2673 VirtMachineState *vms = VIRT_MACHINE(obj); 2674 size_t len = strlen(value); 2675 2676 if (len > 8) { 2677 error_setg(errp, 2678 "User specified oem-table-id value is bigger than 8 bytes in size"); 2679 return; 2680 } 2681 strncpy(vms->oem_table_id, value, 8); 2682 } 2683 2684 2685 bool virt_is_acpi_enabled(VirtMachineState *vms) 2686 { 2687 if (vms->acpi == ON_OFF_AUTO_OFF) { 2688 return false; 2689 } 2690 return true; 2691 } 2692 2693 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 2694 void *opaque, Error **errp) 2695 { 2696 VirtMachineState *vms = VIRT_MACHINE(obj); 2697 OnOffAuto acpi = vms->acpi; 2698 2699 visit_type_OnOffAuto(v, name, &acpi, errp); 2700 } 2701 2702 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 2703 void *opaque, Error **errp) 2704 { 2705 VirtMachineState *vms = VIRT_MACHINE(obj); 2706 2707 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 2708 } 2709 2710 static bool virt_get_ras(Object *obj, Error **errp) 2711 { 2712 VirtMachineState *vms = VIRT_MACHINE(obj); 2713 2714 return vms->ras; 2715 } 2716 2717 static void virt_set_ras(Object *obj, bool value, Error **errp) 2718 { 2719 VirtMachineState *vms = VIRT_MACHINE(obj); 2720 2721 vms->ras = value; 2722 } 2723 2724 static bool virt_get_mte(Object *obj, Error **errp) 2725 { 2726 VirtMachineState *vms = VIRT_MACHINE(obj); 2727 2728 return vms->mte; 2729 } 2730 2731 static void virt_set_mte(Object *obj, bool value, Error **errp) 2732 { 2733 VirtMachineState *vms = VIRT_MACHINE(obj); 2734 2735 vms->mte = value; 2736 } 2737 2738 static char *virt_get_gic_version(Object *obj, Error **errp) 2739 { 2740 VirtMachineState *vms = VIRT_MACHINE(obj); 2741 const char *val; 2742 2743 switch (vms->gic_version) { 2744 case VIRT_GIC_VERSION_4: 2745 val = "4"; 2746 break; 2747 case VIRT_GIC_VERSION_3: 2748 val = "3"; 2749 break; 2750 default: 2751 val = "2"; 2752 break; 2753 } 2754 return g_strdup(val); 2755 } 2756 2757 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2758 { 2759 VirtMachineState *vms = VIRT_MACHINE(obj); 2760 2761 if (!strcmp(value, "4")) { 2762 vms->gic_version = VIRT_GIC_VERSION_4; 2763 } else if (!strcmp(value, "3")) { 2764 vms->gic_version = VIRT_GIC_VERSION_3; 2765 } else if (!strcmp(value, "2")) { 2766 vms->gic_version = VIRT_GIC_VERSION_2; 2767 } else if (!strcmp(value, "host")) { 2768 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2769 } else if (!strcmp(value, "max")) { 2770 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2771 } else { 2772 error_setg(errp, "Invalid gic-version value"); 2773 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2774 } 2775 } 2776 2777 static char *virt_get_iommu(Object *obj, Error **errp) 2778 { 2779 VirtMachineState *vms = VIRT_MACHINE(obj); 2780 2781 switch (vms->iommu) { 2782 case VIRT_IOMMU_NONE: 2783 return g_strdup("none"); 2784 case VIRT_IOMMU_SMMUV3: 2785 return g_strdup("smmuv3"); 2786 default: 2787 g_assert_not_reached(); 2788 } 2789 } 2790 2791 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2792 { 2793 VirtMachineState *vms = VIRT_MACHINE(obj); 2794 2795 if (!strcmp(value, "smmuv3")) { 2796 vms->iommu = VIRT_IOMMU_SMMUV3; 2797 } else if (!strcmp(value, "none")) { 2798 vms->iommu = VIRT_IOMMU_NONE; 2799 } else { 2800 error_setg(errp, "Invalid iommu value"); 2801 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2802 } 2803 } 2804 2805 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp) 2806 { 2807 VirtMachineState *vms = VIRT_MACHINE(obj); 2808 2809 return vms->default_bus_bypass_iommu; 2810 } 2811 2812 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value, 2813 Error **errp) 2814 { 2815 VirtMachineState *vms = VIRT_MACHINE(obj); 2816 2817 vms->default_bus_bypass_iommu = value; 2818 } 2819 2820 static CpuInstanceProperties 2821 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2822 { 2823 MachineClass *mc = MACHINE_GET_CLASS(ms); 2824 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2825 2826 assert(cpu_index < possible_cpus->len); 2827 return possible_cpus->cpus[cpu_index].props; 2828 } 2829 2830 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2831 { 2832 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 2833 2834 return socket_id % ms->numa_state->num_nodes; 2835 } 2836 2837 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2838 { 2839 int n; 2840 unsigned int max_cpus = ms->smp.max_cpus; 2841 VirtMachineState *vms = VIRT_MACHINE(ms); 2842 MachineClass *mc = MACHINE_GET_CLASS(vms); 2843 2844 if (ms->possible_cpus) { 2845 assert(ms->possible_cpus->len == max_cpus); 2846 return ms->possible_cpus; 2847 } 2848 2849 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2850 sizeof(CPUArchId) * max_cpus); 2851 ms->possible_cpus->len = max_cpus; 2852 for (n = 0; n < ms->possible_cpus->len; n++) { 2853 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2854 ms->possible_cpus->cpus[n].arch_id = 2855 virt_cpu_mp_affinity(vms, n); 2856 2857 assert(!mc->smp_props.dies_supported); 2858 ms->possible_cpus->cpus[n].props.has_socket_id = true; 2859 ms->possible_cpus->cpus[n].props.socket_id = 2860 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); 2861 ms->possible_cpus->cpus[n].props.has_cluster_id = true; 2862 ms->possible_cpus->cpus[n].props.cluster_id = 2863 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; 2864 ms->possible_cpus->cpus[n].props.has_core_id = true; 2865 ms->possible_cpus->cpus[n].props.core_id = 2866 (n / ms->smp.threads) % ms->smp.cores; 2867 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2868 ms->possible_cpus->cpus[n].props.thread_id = 2869 n % ms->smp.threads; 2870 } 2871 return ms->possible_cpus; 2872 } 2873 2874 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2875 Error **errp) 2876 { 2877 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2878 const MachineState *ms = MACHINE(hotplug_dev); 2879 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2880 2881 if (!vms->acpi_dev) { 2882 error_setg(errp, 2883 "memory hotplug is not enabled: missing acpi-ged device"); 2884 return; 2885 } 2886 2887 if (vms->mte) { 2888 error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); 2889 return; 2890 } 2891 2892 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2893 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2894 return; 2895 } 2896 2897 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp); 2898 } 2899 2900 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2901 DeviceState *dev, Error **errp) 2902 { 2903 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2904 MachineState *ms = MACHINE(hotplug_dev); 2905 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2906 2907 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); 2908 2909 if (is_nvdimm) { 2910 nvdimm_plug(ms->nvdimms_state); 2911 } 2912 2913 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2914 dev, &error_abort); 2915 } 2916 2917 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2918 DeviceState *dev, Error **errp) 2919 { 2920 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2921 2922 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2923 virt_memory_pre_plug(hotplug_dev, dev, errp); 2924 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2925 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2926 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2927 hwaddr db_start = 0, db_end = 0; 2928 QList *reserved_regions; 2929 char *resv_prop_str; 2930 2931 if (vms->iommu != VIRT_IOMMU_NONE) { 2932 error_setg(errp, "virt machine does not support multiple IOMMUs"); 2933 return; 2934 } 2935 2936 switch (vms->msi_controller) { 2937 case VIRT_MSI_CTRL_NONE: 2938 return; 2939 case VIRT_MSI_CTRL_ITS: 2940 /* GITS_TRANSLATER page */ 2941 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; 2942 db_end = base_memmap[VIRT_GIC_ITS].base + 2943 base_memmap[VIRT_GIC_ITS].size - 1; 2944 break; 2945 case VIRT_MSI_CTRL_GICV2M: 2946 /* MSI_SETSPI_NS page */ 2947 db_start = base_memmap[VIRT_GIC_V2M].base; 2948 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; 2949 break; 2950 } 2951 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", 2952 db_start, db_end, 2953 VIRTIO_IOMMU_RESV_MEM_T_MSI); 2954 2955 reserved_regions = qlist_new(); 2956 qlist_append_str(reserved_regions, resv_prop_str); 2957 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 2958 g_free(resv_prop_str); 2959 } 2960 } 2961 2962 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2963 DeviceState *dev, Error **errp) 2964 { 2965 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2966 2967 if (vms->platform_bus_dev) { 2968 MachineClass *mc = MACHINE_GET_CLASS(vms); 2969 2970 if (device_is_dynamic_sysbus(mc, dev)) { 2971 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2972 SYS_BUS_DEVICE(dev)); 2973 } 2974 } 2975 2976 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2977 virt_memory_plug(hotplug_dev, dev, errp); 2978 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2979 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2980 } 2981 2982 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2983 PCIDevice *pdev = PCI_DEVICE(dev); 2984 2985 vms->iommu = VIRT_IOMMU_VIRTIO; 2986 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2987 create_virtio_iommu_dt_bindings(vms); 2988 } 2989 } 2990 2991 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, 2992 DeviceState *dev, Error **errp) 2993 { 2994 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2995 2996 if (!vms->acpi_dev) { 2997 error_setg(errp, 2998 "memory hotplug is not enabled: missing acpi-ged device"); 2999 return; 3000 } 3001 3002 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3003 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3004 return; 3005 } 3006 3007 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, 3008 errp); 3009 } 3010 3011 static void virt_dimm_unplug(HotplugHandler *hotplug_dev, 3012 DeviceState *dev, Error **errp) 3013 { 3014 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 3015 Error *local_err = NULL; 3016 3017 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); 3018 if (local_err) { 3019 goto out; 3020 } 3021 3022 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); 3023 qdev_unrealize(dev); 3024 3025 out: 3026 error_propagate(errp, local_err); 3027 } 3028 3029 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 3030 DeviceState *dev, Error **errp) 3031 { 3032 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3033 virt_dimm_unplug_request(hotplug_dev, dev, errp); 3034 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 3035 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 3036 errp); 3037 } else { 3038 error_setg(errp, "device unplug request for unsupported device" 3039 " type: %s", object_get_typename(OBJECT(dev))); 3040 } 3041 } 3042 3043 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 3044 DeviceState *dev, Error **errp) 3045 { 3046 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3047 virt_dimm_unplug(hotplug_dev, dev, errp); 3048 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 3049 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 3050 } else { 3051 error_setg(errp, "virt: device unplug for unsupported device" 3052 " type: %s", object_get_typename(OBJECT(dev))); 3053 } 3054 } 3055 3056 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 3057 DeviceState *dev) 3058 { 3059 MachineClass *mc = MACHINE_GET_CLASS(machine); 3060 3061 if (device_is_dynamic_sysbus(mc, dev) || 3062 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3063 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 3064 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 3065 return HOTPLUG_HANDLER(machine); 3066 } 3067 return NULL; 3068 } 3069 3070 /* 3071 * for arm64 kvm_type [7-0] encodes the requested number of bits 3072 * in the IPA address space 3073 */ 3074 static int virt_kvm_type(MachineState *ms, const char *type_str) 3075 { 3076 VirtMachineState *vms = VIRT_MACHINE(ms); 3077 int max_vm_pa_size, requested_pa_size; 3078 bool fixed_ipa; 3079 3080 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 3081 3082 /* we freeze the memory map to compute the highest gpa */ 3083 virt_set_memmap(vms, max_vm_pa_size); 3084 3085 requested_pa_size = 64 - clz64(vms->highest_gpa); 3086 3087 /* 3088 * KVM requires the IPA size to be at least 32 bits. 3089 */ 3090 if (requested_pa_size < 32) { 3091 requested_pa_size = 32; 3092 } 3093 3094 if (requested_pa_size > max_vm_pa_size) { 3095 error_report("-m and ,maxmem option values " 3096 "require an IPA range (%d bits) larger than " 3097 "the one supported by the host (%d bits)", 3098 requested_pa_size, max_vm_pa_size); 3099 return -1; 3100 } 3101 /* 3102 * We return the requested PA log size, unless KVM only supports 3103 * the implicit legacy 40b IPA setting, in which case the kvm_type 3104 * must be 0. 3105 */ 3106 return fixed_ipa ? 0 : requested_pa_size; 3107 } 3108 3109 static int virt_hvf_get_physical_address_range(MachineState *ms) 3110 { 3111 VirtMachineState *vms = VIRT_MACHINE(ms); 3112 3113 int default_ipa_size = hvf_arm_get_default_ipa_bit_size(); 3114 int max_ipa_size = hvf_arm_get_max_ipa_bit_size(); 3115 3116 /* We freeze the memory map to compute the highest gpa */ 3117 virt_set_memmap(vms, max_ipa_size); 3118 3119 int requested_ipa_size = 64 - clz64(vms->highest_gpa); 3120 3121 /* 3122 * If we're <= the default IPA size just use the default. 3123 * If we're above the default but below the maximum, round up to 3124 * the maximum. hvf_arm_get_max_ipa_bit_size() conveniently only 3125 * returns values that are valid ARM PARange values. 3126 */ 3127 if (requested_ipa_size <= default_ipa_size) { 3128 requested_ipa_size = default_ipa_size; 3129 } else if (requested_ipa_size <= max_ipa_size) { 3130 requested_ipa_size = max_ipa_size; 3131 } else { 3132 error_report("-m and ,maxmem option values " 3133 "require an IPA range (%d bits) larger than " 3134 "the one supported by the host (%d bits)", 3135 requested_ipa_size, max_ipa_size); 3136 return -1; 3137 } 3138 3139 return requested_ipa_size; 3140 } 3141 3142 static void virt_machine_class_init(ObjectClass *oc, const void *data) 3143 { 3144 MachineClass *mc = MACHINE_CLASS(oc); 3145 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3146 static const char * const valid_cpu_types[] = { 3147 #ifdef CONFIG_TCG 3148 ARM_CPU_TYPE_NAME("cortex-a7"), 3149 ARM_CPU_TYPE_NAME("cortex-a15"), 3150 #ifdef TARGET_AARCH64 3151 ARM_CPU_TYPE_NAME("cortex-a35"), 3152 ARM_CPU_TYPE_NAME("cortex-a55"), 3153 ARM_CPU_TYPE_NAME("cortex-a72"), 3154 ARM_CPU_TYPE_NAME("cortex-a76"), 3155 ARM_CPU_TYPE_NAME("cortex-a710"), 3156 ARM_CPU_TYPE_NAME("a64fx"), 3157 ARM_CPU_TYPE_NAME("neoverse-n1"), 3158 ARM_CPU_TYPE_NAME("neoverse-v1"), 3159 ARM_CPU_TYPE_NAME("neoverse-n2"), 3160 #endif /* TARGET_AARCH64 */ 3161 #endif /* CONFIG_TCG */ 3162 #ifdef TARGET_AARCH64 3163 ARM_CPU_TYPE_NAME("cortex-a53"), 3164 ARM_CPU_TYPE_NAME("cortex-a57"), 3165 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 3166 ARM_CPU_TYPE_NAME("host"), 3167 #endif /* CONFIG_KVM || CONFIG_HVF */ 3168 #endif /* TARGET_AARCH64 */ 3169 ARM_CPU_TYPE_NAME("max"), 3170 NULL 3171 }; 3172 3173 mc->init = machvirt_init; 3174 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 3175 * The value may be reduced later when we have more information about the 3176 * configuration of the particular instance. 3177 */ 3178 mc->max_cpus = 512; 3179 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 3180 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 3181 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 3182 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 3183 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS); 3184 #ifdef CONFIG_TPM 3185 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 3186 #endif 3187 mc->block_default_type = IF_VIRTIO; 3188 mc->no_cdrom = 1; 3189 mc->pci_allow_0_address = true; 3190 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 3191 mc->minimum_page_bits = 12; 3192 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 3193 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 3194 #ifdef CONFIG_TCG 3195 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 3196 #else 3197 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); 3198 #endif 3199 mc->valid_cpu_types = valid_cpu_types; 3200 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 3201 mc->kvm_type = virt_kvm_type; 3202 mc->hvf_get_physical_address_range = virt_hvf_get_physical_address_range; 3203 assert(!mc->get_hotplug_handler); 3204 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 3205 hc->pre_plug = virt_machine_device_pre_plug_cb; 3206 hc->plug = virt_machine_device_plug_cb; 3207 hc->unplug_request = virt_machine_device_unplug_request_cb; 3208 hc->unplug = virt_machine_device_unplug_cb; 3209 mc->nvdimm_supported = true; 3210 mc->smp_props.clusters_supported = true; 3211 mc->auto_enable_numa_with_memhp = true; 3212 mc->auto_enable_numa_with_memdev = true; 3213 /* platform instead of architectural choice */ 3214 mc->cpu_cluster_has_numa_boundary = true; 3215 mc->default_ram_id = "mach-virt.ram"; 3216 mc->default_nic = "virtio-net-pci"; 3217 3218 object_class_property_add(oc, "acpi", "OnOffAuto", 3219 virt_get_acpi, virt_set_acpi, 3220 NULL, NULL); 3221 object_class_property_set_description(oc, "acpi", 3222 "Enable ACPI"); 3223 object_class_property_add_bool(oc, "secure", virt_get_secure, 3224 virt_set_secure); 3225 object_class_property_set_description(oc, "secure", 3226 "Set on/off to enable/disable the ARM " 3227 "Security Extensions (TrustZone)"); 3228 3229 object_class_property_add_bool(oc, "virtualization", virt_get_virt, 3230 virt_set_virt); 3231 object_class_property_set_description(oc, "virtualization", 3232 "Set on/off to enable/disable emulating a " 3233 "guest CPU which implements the ARM " 3234 "Virtualization Extensions"); 3235 3236 object_class_property_add_bool(oc, "highmem", virt_get_highmem, 3237 virt_set_highmem); 3238 object_class_property_set_description(oc, "highmem", 3239 "Set on/off to enable/disable using " 3240 "physical address space above 32 bits"); 3241 3242 object_class_property_add_bool(oc, "compact-highmem", 3243 virt_get_compact_highmem, 3244 virt_set_compact_highmem); 3245 object_class_property_set_description(oc, "compact-highmem", 3246 "Set on/off to enable/disable compact " 3247 "layout for high memory regions"); 3248 3249 object_class_property_add_bool(oc, "highmem-redists", 3250 virt_get_highmem_redists, 3251 virt_set_highmem_redists); 3252 object_class_property_set_description(oc, "highmem-redists", 3253 "Set on/off to enable/disable high " 3254 "memory region for GICv3 or GICv4 " 3255 "redistributor"); 3256 3257 object_class_property_add_bool(oc, "highmem-ecam", 3258 virt_get_highmem_ecam, 3259 virt_set_highmem_ecam); 3260 object_class_property_set_description(oc, "highmem-ecam", 3261 "Set on/off to enable/disable high " 3262 "memory region for PCI ECAM"); 3263 3264 object_class_property_add_bool(oc, "highmem-mmio", 3265 virt_get_highmem_mmio, 3266 virt_set_highmem_mmio); 3267 object_class_property_set_description(oc, "highmem-mmio", 3268 "Set on/off to enable/disable high " 3269 "memory region for PCI MMIO"); 3270 3271 object_class_property_add(oc, "highmem-mmio-size", "size", 3272 virt_get_highmem_mmio_size, 3273 virt_set_highmem_mmio_size, 3274 NULL, NULL); 3275 object_class_property_set_description(oc, "highmem-mmio-size", 3276 "Set the high memory region size " 3277 "for PCI MMIO"); 3278 3279 object_class_property_add_str(oc, "gic-version", virt_get_gic_version, 3280 virt_set_gic_version); 3281 object_class_property_set_description(oc, "gic-version", 3282 "Set GIC version. " 3283 "Valid values are 2, 3, 4, host and max"); 3284 3285 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); 3286 object_class_property_set_description(oc, "iommu", 3287 "Set the IOMMU type. " 3288 "Valid values are none and smmuv3"); 3289 3290 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 3291 virt_get_default_bus_bypass_iommu, 3292 virt_set_default_bus_bypass_iommu); 3293 object_class_property_set_description(oc, "default-bus-bypass-iommu", 3294 "Set on/off to enable/disable " 3295 "bypass_iommu for default root bus"); 3296 3297 object_class_property_add_bool(oc, "ras", virt_get_ras, 3298 virt_set_ras); 3299 object_class_property_set_description(oc, "ras", 3300 "Set on/off to enable/disable reporting host memory errors " 3301 "to a KVM guest using ACPI and guest external abort exceptions"); 3302 3303 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); 3304 object_class_property_set_description(oc, "mte", 3305 "Set on/off to enable/disable emulating a " 3306 "guest CPU which implements the ARM " 3307 "Memory Tagging Extension"); 3308 3309 object_class_property_add_bool(oc, "its", virt_get_its, 3310 virt_set_its); 3311 object_class_property_set_description(oc, "its", 3312 "Set on/off to enable/disable " 3313 "ITS instantiation"); 3314 3315 object_class_property_add_bool(oc, "dtb-randomness", 3316 virt_get_dtb_randomness, 3317 virt_set_dtb_randomness); 3318 object_class_property_set_description(oc, "dtb-randomness", 3319 "Set off to disable passing random or " 3320 "non-deterministic dtb nodes to guest"); 3321 3322 object_class_property_add_bool(oc, "dtb-kaslr-seed", 3323 virt_get_dtb_randomness, 3324 virt_set_dtb_randomness); 3325 object_class_property_set_description(oc, "dtb-kaslr-seed", 3326 "Deprecated synonym of dtb-randomness"); 3327 3328 object_class_property_add_str(oc, "x-oem-id", 3329 virt_get_oem_id, 3330 virt_set_oem_id); 3331 object_class_property_set_description(oc, "x-oem-id", 3332 "Override the default value of field OEMID " 3333 "in ACPI table header." 3334 "The string may be up to 6 bytes in size"); 3335 3336 3337 object_class_property_add_str(oc, "x-oem-table-id", 3338 virt_get_oem_table_id, 3339 virt_set_oem_table_id); 3340 object_class_property_set_description(oc, "x-oem-table-id", 3341 "Override the default value of field OEM Table ID " 3342 "in ACPI table header." 3343 "The string may be up to 8 bytes in size"); 3344 3345 } 3346 3347 static void virt_instance_init(Object *obj) 3348 { 3349 VirtMachineState *vms = VIRT_MACHINE(obj); 3350 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 3351 3352 /* EL3 is disabled by default on virt: this makes us consistent 3353 * between KVM and TCG for this board, and it also allows us to 3354 * boot UEFI blobs which assume no TrustZone support. 3355 */ 3356 vms->secure = false; 3357 3358 /* EL2 is also disabled by default, for similar reasons */ 3359 vms->virt = false; 3360 3361 /* High memory is enabled by default */ 3362 vms->highmem = true; 3363 vms->highmem_compact = !vmc->no_highmem_compact; 3364 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 3365 3366 vms->highmem_ecam = true; 3367 vms->highmem_mmio = true; 3368 vms->highmem_redists = true; 3369 3370 /* Default allows ITS instantiation */ 3371 vms->its = true; 3372 /* Allow ITS emulation if the machine version supports it */ 3373 vms->tcg_its = !vmc->no_tcg_its; 3374 3375 /* Default disallows iommu instantiation */ 3376 vms->iommu = VIRT_IOMMU_NONE; 3377 3378 /* The default root bus is attached to iommu by default */ 3379 vms->default_bus_bypass_iommu = false; 3380 3381 /* Default disallows RAS instantiation */ 3382 vms->ras = false; 3383 3384 /* MTE is disabled by default. */ 3385 vms->mte = false; 3386 3387 /* Supply kaslr-seed and rng-seed by default */ 3388 vms->dtb_randomness = true; 3389 3390 vms->irqmap = a15irqmap; 3391 3392 virt_flash_create(vms); 3393 3394 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 3395 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 3396 cxl_machine_init(obj, &vms->cxl_devices_state); 3397 } 3398 3399 static const TypeInfo virt_machine_info = { 3400 .name = TYPE_VIRT_MACHINE, 3401 .parent = TYPE_MACHINE, 3402 .abstract = true, 3403 .instance_size = sizeof(VirtMachineState), 3404 .class_size = sizeof(VirtMachineClass), 3405 .class_init = virt_machine_class_init, 3406 .instance_init = virt_instance_init, 3407 .interfaces = (const InterfaceInfo[]) { 3408 { TYPE_HOTPLUG_HANDLER }, 3409 { } 3410 }, 3411 }; 3412 3413 static void machvirt_machine_init(void) 3414 { 3415 type_register_static(&virt_machine_info); 3416 } 3417 type_init(machvirt_machine_init); 3418 3419 static void virt_machine_10_1_options(MachineClass *mc) 3420 { 3421 } 3422 DEFINE_VIRT_MACHINE_AS_LATEST(10, 1) 3423 3424 static void virt_machine_10_0_options(MachineClass *mc) 3425 { 3426 virt_machine_10_1_options(mc); 3427 compat_props_add(mc->compat_props, hw_compat_10_0, hw_compat_10_0_len); 3428 } 3429 DEFINE_VIRT_MACHINE(10, 0) 3430 3431 static void virt_machine_9_2_options(MachineClass *mc) 3432 { 3433 virt_machine_10_0_options(mc); 3434 compat_props_add(mc->compat_props, hw_compat_9_2, hw_compat_9_2_len); 3435 } 3436 DEFINE_VIRT_MACHINE(9, 2) 3437 3438 static void virt_machine_9_1_options(MachineClass *mc) 3439 { 3440 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3441 3442 virt_machine_9_2_options(mc); 3443 compat_props_add(mc->compat_props, hw_compat_9_1, hw_compat_9_1_len); 3444 /* 9.1 and earlier have only a stage-1 SMMU, not a nested s1+2 one */ 3445 vmc->no_nested_smmu = true; 3446 } 3447 DEFINE_VIRT_MACHINE(9, 1) 3448 3449 static void virt_machine_9_0_options(MachineClass *mc) 3450 { 3451 virt_machine_9_1_options(mc); 3452 mc->smbios_memory_device_size = 16 * GiB; 3453 compat_props_add(mc->compat_props, hw_compat_9_0, hw_compat_9_0_len); 3454 } 3455 DEFINE_VIRT_MACHINE(9, 0) 3456 3457 static void virt_machine_8_2_options(MachineClass *mc) 3458 { 3459 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3460 3461 virt_machine_9_0_options(mc); 3462 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len); 3463 /* 3464 * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and 3465 * earlier machines. (Exposing it tickles a bug in older EDK2 3466 * guest BIOS binaries.) 3467 */ 3468 vmc->no_ns_el2_virt_timer_irq = true; 3469 } 3470 DEFINE_VIRT_MACHINE(8, 2) 3471 3472 static void virt_machine_8_1_options(MachineClass *mc) 3473 { 3474 virt_machine_8_2_options(mc); 3475 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len); 3476 } 3477 DEFINE_VIRT_MACHINE(8, 1) 3478 3479 static void virt_machine_8_0_options(MachineClass *mc) 3480 { 3481 virt_machine_8_1_options(mc); 3482 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 3483 } 3484 DEFINE_VIRT_MACHINE(8, 0) 3485 3486 static void virt_machine_7_2_options(MachineClass *mc) 3487 { 3488 virt_machine_8_0_options(mc); 3489 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 3490 } 3491 DEFINE_VIRT_MACHINE(7, 2) 3492 3493 static void virt_machine_7_1_options(MachineClass *mc) 3494 { 3495 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3496 3497 virt_machine_7_2_options(mc); 3498 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 3499 /* Compact layout for high memory regions was introduced with 7.2 */ 3500 vmc->no_highmem_compact = true; 3501 } 3502 DEFINE_VIRT_MACHINE(7, 1) 3503 3504 static void virt_machine_7_0_options(MachineClass *mc) 3505 { 3506 virt_machine_7_1_options(mc); 3507 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 3508 } 3509 DEFINE_VIRT_MACHINE(7, 0) 3510 3511 static void virt_machine_6_2_options(MachineClass *mc) 3512 { 3513 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3514 3515 virt_machine_7_0_options(mc); 3516 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 3517 vmc->no_tcg_lpa2 = true; 3518 } 3519 DEFINE_VIRT_MACHINE(6, 2) 3520 3521 static void virt_machine_6_1_options(MachineClass *mc) 3522 { 3523 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3524 3525 virt_machine_6_2_options(mc); 3526 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 3527 mc->smp_props.prefer_sockets = true; 3528 vmc->no_cpu_topology = true; 3529 3530 /* qemu ITS was introduced with 6.2 */ 3531 vmc->no_tcg_its = true; 3532 } 3533 DEFINE_VIRT_MACHINE(6, 1) 3534 3535 static void virt_machine_6_0_options(MachineClass *mc) 3536 { 3537 virt_machine_6_1_options(mc); 3538 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 3539 } 3540 DEFINE_VIRT_MACHINE(6, 0) 3541 3542 static void virt_machine_5_2_options(MachineClass *mc) 3543 { 3544 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3545 3546 virt_machine_6_0_options(mc); 3547 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 3548 vmc->no_secure_gpio = true; 3549 } 3550 DEFINE_VIRT_MACHINE(5, 2) 3551 3552 static void virt_machine_5_1_options(MachineClass *mc) 3553 { 3554 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3555 3556 virt_machine_5_2_options(mc); 3557 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 3558 vmc->no_kvm_steal_time = true; 3559 } 3560 DEFINE_VIRT_MACHINE(5, 1) 3561 3562 static void virt_machine_5_0_options(MachineClass *mc) 3563 { 3564 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3565 3566 virt_machine_5_1_options(mc); 3567 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 3568 mc->numa_mem_supported = true; 3569 vmc->acpi_expose_flash = true; 3570 mc->auto_enable_numa_with_memdev = false; 3571 } 3572 DEFINE_VIRT_MACHINE(5, 0) 3573 3574 static void virt_machine_4_2_options(MachineClass *mc) 3575 { 3576 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3577 3578 virt_machine_5_0_options(mc); 3579 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 3580 vmc->kvm_no_adjvtime = true; 3581 } 3582 DEFINE_VIRT_MACHINE(4, 2) 3583 3584 static void virt_machine_4_1_options(MachineClass *mc) 3585 { 3586 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3587 3588 virt_machine_4_2_options(mc); 3589 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 3590 vmc->no_ged = true; 3591 mc->auto_enable_numa_with_memhp = false; 3592 } 3593 DEFINE_VIRT_MACHINE(4, 1) 3594