xref: /openbmc/qemu/hw/arm/virt.c (revision 1e575b66643a4311b9a6cbf0744f7f5aeba5e181)
1 /*
2  * ARM mach-virt emulation
3  *
4  * Copyright (c) 2013 Linaro Limited
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2 or later, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program.  If not, see <http://www.gnu.org/licenses/>.
17  *
18  * Emulate a virtual board which works by passing Linux all the information
19  * it needs about what devices are present via the device tree.
20  * There are some restrictions about what we can do here:
21  *  + we can only present devices whose Linux drivers will work based
22  *    purely on the device tree with no platform data at all
23  *  + we want to present a very stripped-down minimalist platform,
24  *    both because this reduces the security attack surface from the guest
25  *    and also because it reduces our exposure to being broken when
26  *    the kernel updates its device tree bindings and requires further
27  *    information in a device binding that we aren't providing.
28  * This is essentially the same approach kvmtool uses.
29  */
30 
31 #include "qemu/osdep.h"
32 #include "qapi/error.h"
33 #include "hw/sysbus.h"
34 #include "hw/arm/arm.h"
35 #include "hw/arm/primecell.h"
36 #include "hw/arm/virt.h"
37 #include "hw/vfio/vfio-calxeda-xgmac.h"
38 #include "hw/vfio/vfio-amd-xgbe.h"
39 #include "hw/display/ramfb.h"
40 #include "hw/devices.h"
41 #include "net/net.h"
42 #include "sysemu/device_tree.h"
43 #include "sysemu/numa.h"
44 #include "sysemu/sysemu.h"
45 #include "sysemu/kvm.h"
46 #include "hw/compat.h"
47 #include "hw/loader.h"
48 #include "exec/address-spaces.h"
49 #include "qemu/bitops.h"
50 #include "qemu/error-report.h"
51 #include "hw/pci-host/gpex.h"
52 #include "hw/arm/sysbus-fdt.h"
53 #include "hw/platform-bus.h"
54 #include "hw/arm/fdt.h"
55 #include "hw/intc/arm_gic.h"
56 #include "hw/intc/arm_gicv3_common.h"
57 #include "kvm_arm.h"
58 #include "hw/smbios/smbios.h"
59 #include "qapi/visitor.h"
60 #include "standard-headers/linux/input.h"
61 #include "hw/arm/smmuv3.h"
62 
63 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
64     static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
65                                                     void *data) \
66     { \
67         MachineClass *mc = MACHINE_CLASS(oc); \
68         virt_machine_##major##_##minor##_options(mc); \
69         mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
70         if (latest) { \
71             mc->alias = "virt"; \
72         } \
73     } \
74     static const TypeInfo machvirt_##major##_##minor##_info = { \
75         .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
76         .parent = TYPE_VIRT_MACHINE, \
77         .instance_init = virt_##major##_##minor##_instance_init, \
78         .class_init = virt_##major##_##minor##_class_init, \
79     }; \
80     static void machvirt_machine_##major##_##minor##_init(void) \
81     { \
82         type_register_static(&machvirt_##major##_##minor##_info); \
83     } \
84     type_init(machvirt_machine_##major##_##minor##_init);
85 
86 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
87     DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
88 #define DEFINE_VIRT_MACHINE(major, minor) \
89     DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
90 
91 
92 /* Number of external interrupt lines to configure the GIC with */
93 #define NUM_IRQS 256
94 
95 #define PLATFORM_BUS_NUM_IRQS 64
96 
97 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means
98  * RAM can go up to the 256GB mark, leaving 256GB of the physical
99  * address space unallocated and free for future use between 256G and 512G.
100  * If we need to provide more RAM to VMs in the future then we need to:
101  *  * allocate a second bank of RAM starting at 2TB and working up
102  *  * fix the DT and ACPI table generation code in QEMU to correctly
103  *    report two split lumps of RAM to the guest
104  *  * fix KVM in the host kernel to allow guests with >40 bit address spaces
105  * (We don't want to fill all the way up to 512GB with RAM because
106  * we might want it for non-RAM purposes later. Conversely it seems
107  * reasonable to assume that anybody configuring a VM with a quarter
108  * of a terabyte of RAM will be doing it on a host with more than a
109  * terabyte of physical address space.)
110  */
111 #define RAMLIMIT_GB 255
112 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)
113 
114 /* Addresses and sizes of our components.
115  * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
116  * 128MB..256MB is used for miscellaneous device I/O.
117  * 256MB..1GB is reserved for possible future PCI support (ie where the
118  * PCI memory window will go if we add a PCI host controller).
119  * 1GB and up is RAM (which may happily spill over into the
120  * high memory region beyond 4GB).
121  * This represents a compromise between how much RAM can be given to
122  * a 32 bit VM and leaving space for expansion and in particular for PCI.
123  * Note that devices should generally be placed at multiples of 0x10000,
124  * to accommodate guests using 64K pages.
125  */
126 static const MemMapEntry a15memmap[] = {
127     /* Space up to 0x8000000 is reserved for a boot ROM */
128     [VIRT_FLASH] =              {          0, 0x08000000 },
129     [VIRT_CPUPERIPHS] =         { 0x08000000, 0x00020000 },
130     /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
131     [VIRT_GIC_DIST] =           { 0x08000000, 0x00010000 },
132     [VIRT_GIC_CPU] =            { 0x08010000, 0x00010000 },
133     [VIRT_GIC_V2M] =            { 0x08020000, 0x00001000 },
134     /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
135     [VIRT_GIC_ITS] =            { 0x08080000, 0x00020000 },
136     /* This redistributor space allows up to 2*64kB*123 CPUs */
137     [VIRT_GIC_REDIST] =         { 0x080A0000, 0x00F60000 },
138     [VIRT_UART] =               { 0x09000000, 0x00001000 },
139     [VIRT_RTC] =                { 0x09010000, 0x00001000 },
140     [VIRT_FW_CFG] =             { 0x09020000, 0x00000018 },
141     [VIRT_GPIO] =               { 0x09030000, 0x00001000 },
142     [VIRT_SECURE_UART] =        { 0x09040000, 0x00001000 },
143     [VIRT_SMMU] =               { 0x09050000, 0x00020000 },
144     [VIRT_MMIO] =               { 0x0a000000, 0x00000200 },
145     /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
146     [VIRT_PLATFORM_BUS] =       { 0x0c000000, 0x02000000 },
147     [VIRT_SECURE_MEM] =         { 0x0e000000, 0x01000000 },
148     [VIRT_PCIE_MMIO] =          { 0x10000000, 0x2eff0000 },
149     [VIRT_PCIE_PIO] =           { 0x3eff0000, 0x00010000 },
150     [VIRT_PCIE_ECAM] =          { 0x3f000000, 0x01000000 },
151     [VIRT_MEM] =                { 0x40000000, RAMLIMIT_BYTES },
152     /* Second PCIe window, 512GB wide at the 512GB boundary */
153     [VIRT_PCIE_MMIO_HIGH] =   { 0x8000000000ULL, 0x8000000000ULL },
154 };
155 
156 static const int a15irqmap[] = {
157     [VIRT_UART] = 1,
158     [VIRT_RTC] = 2,
159     [VIRT_PCIE] = 3, /* ... to 6 */
160     [VIRT_GPIO] = 7,
161     [VIRT_SECURE_UART] = 8,
162     [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
163     [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
164     [VIRT_SMMU] = 74,    /* ...to 74 + NUM_SMMU_IRQS - 1 */
165     [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
166 };
167 
168 static const char *valid_cpus[] = {
169     ARM_CPU_TYPE_NAME("cortex-a15"),
170     ARM_CPU_TYPE_NAME("cortex-a53"),
171     ARM_CPU_TYPE_NAME("cortex-a57"),
172     ARM_CPU_TYPE_NAME("host"),
173     ARM_CPU_TYPE_NAME("max"),
174 };
175 
176 static bool cpu_type_valid(const char *cpu)
177 {
178     int i;
179 
180     for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
181         if (strcmp(cpu, valid_cpus[i]) == 0) {
182             return true;
183         }
184     }
185     return false;
186 }
187 
188 static void create_fdt(VirtMachineState *vms)
189 {
190     void *fdt = create_device_tree(&vms->fdt_size);
191 
192     if (!fdt) {
193         error_report("create_device_tree() failed");
194         exit(1);
195     }
196 
197     vms->fdt = fdt;
198 
199     /* Header */
200     qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
201     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
202     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
203 
204     /*
205      * /chosen and /memory nodes must exist for load_dtb
206      * to fill in necessary properties later
207      */
208     qemu_fdt_add_subnode(fdt, "/chosen");
209     qemu_fdt_add_subnode(fdt, "/memory");
210     qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");
211 
212     /* Clock node, for the benefit of the UART. The kernel device tree
213      * binding documentation claims the PL011 node clock properties are
214      * optional but in practice if you omit them the kernel refuses to
215      * probe for the device.
216      */
217     vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
218     qemu_fdt_add_subnode(fdt, "/apb-pclk");
219     qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
220     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
221     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
222     qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
223                                 "clk24mhz");
224     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
225 
226     if (have_numa_distance) {
227         int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
228         uint32_t *matrix = g_malloc0(size);
229         int idx, i, j;
230 
231         for (i = 0; i < nb_numa_nodes; i++) {
232             for (j = 0; j < nb_numa_nodes; j++) {
233                 idx = (i * nb_numa_nodes + j) * 3;
234                 matrix[idx + 0] = cpu_to_be32(i);
235                 matrix[idx + 1] = cpu_to_be32(j);
236                 matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]);
237             }
238         }
239 
240         qemu_fdt_add_subnode(fdt, "/distance-map");
241         qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
242                                 "numa-distance-map-v1");
243         qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
244                          matrix, size);
245         g_free(matrix);
246     }
247 }
248 
249 static void fdt_add_timer_nodes(const VirtMachineState *vms)
250 {
251     /* On real hardware these interrupts are level-triggered.
252      * On KVM they were edge-triggered before host kernel version 4.4,
253      * and level-triggered afterwards.
254      * On emulated QEMU they are level-triggered.
255      *
256      * Getting the DTB info about them wrong is awkward for some
257      * guest kernels:
258      *  pre-4.8 ignore the DT and leave the interrupt configured
259      *   with whatever the GIC reset value (or the bootloader) left it at
260      *  4.8 before rc6 honour the incorrect data by programming it back
261      *   into the GIC, causing problems
262      *  4.8rc6 and later ignore the DT and always write "level triggered"
263      *   into the GIC
264      *
265      * For backwards-compatibility, virt-2.8 and earlier will continue
266      * to say these are edge-triggered, but later machines will report
267      * the correct information.
268      */
269     ARMCPU *armcpu;
270     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
271     uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
272 
273     if (vmc->claim_edge_triggered_timers) {
274         irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
275     }
276 
277     if (vms->gic_version == 2) {
278         irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
279                              GIC_FDT_IRQ_PPI_CPU_WIDTH,
280                              (1 << vms->smp_cpus) - 1);
281     }
282 
283     qemu_fdt_add_subnode(vms->fdt, "/timer");
284 
285     armcpu = ARM_CPU(qemu_get_cpu(0));
286     if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
287         const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
288         qemu_fdt_setprop(vms->fdt, "/timer", "compatible",
289                          compat, sizeof(compat));
290     } else {
291         qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible",
292                                 "arm,armv7-timer");
293     }
294     qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0);
295     qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts",
296                        GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
297                        GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
298                        GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
299                        GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
300 }
301 
302 static void fdt_add_cpu_nodes(const VirtMachineState *vms)
303 {
304     int cpu;
305     int addr_cells = 1;
306     const MachineState *ms = MACHINE(vms);
307 
308     /*
309      * From Documentation/devicetree/bindings/arm/cpus.txt
310      *  On ARM v8 64-bit systems value should be set to 2,
311      *  that corresponds to the MPIDR_EL1 register size.
312      *  If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
313      *  in the system, #address-cells can be set to 1, since
314      *  MPIDR_EL1[63:32] bits are not used for CPUs
315      *  identification.
316      *
317      *  Here we actually don't know whether our system is 32- or 64-bit one.
318      *  The simplest way to go is to examine affinity IDs of all our CPUs. If
319      *  at least one of them has Aff3 populated, we set #address-cells to 2.
320      */
321     for (cpu = 0; cpu < vms->smp_cpus; cpu++) {
322         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
323 
324         if (armcpu->mp_affinity & ARM_AFF3_MASK) {
325             addr_cells = 2;
326             break;
327         }
328     }
329 
330     qemu_fdt_add_subnode(vms->fdt, "/cpus");
331     qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells);
332     qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0);
333 
334     for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) {
335         char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
336         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
337         CPUState *cs = CPU(armcpu);
338 
339         qemu_fdt_add_subnode(vms->fdt, nodename);
340         qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu");
341         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
342                                     armcpu->dtb_compatible);
343 
344         if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED
345             && vms->smp_cpus > 1) {
346             qemu_fdt_setprop_string(vms->fdt, nodename,
347                                         "enable-method", "psci");
348         }
349 
350         if (addr_cells == 2) {
351             qemu_fdt_setprop_u64(vms->fdt, nodename, "reg",
352                                  armcpu->mp_affinity);
353         } else {
354             qemu_fdt_setprop_cell(vms->fdt, nodename, "reg",
355                                   armcpu->mp_affinity);
356         }
357 
358         if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
359             qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id",
360                 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
361         }
362 
363         g_free(nodename);
364     }
365 }
366 
367 static void fdt_add_its_gic_node(VirtMachineState *vms)
368 {
369     vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
370     qemu_fdt_add_subnode(vms->fdt, "/intc/its");
371     qemu_fdt_setprop_string(vms->fdt, "/intc/its", "compatible",
372                             "arm,gic-v3-its");
373     qemu_fdt_setprop(vms->fdt, "/intc/its", "msi-controller", NULL, 0);
374     qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/its", "reg",
375                                  2, vms->memmap[VIRT_GIC_ITS].base,
376                                  2, vms->memmap[VIRT_GIC_ITS].size);
377     qemu_fdt_setprop_cell(vms->fdt, "/intc/its", "phandle", vms->msi_phandle);
378 }
379 
380 static void fdt_add_v2m_gic_node(VirtMachineState *vms)
381 {
382     vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
383     qemu_fdt_add_subnode(vms->fdt, "/intc/v2m");
384     qemu_fdt_setprop_string(vms->fdt, "/intc/v2m", "compatible",
385                             "arm,gic-v2m-frame");
386     qemu_fdt_setprop(vms->fdt, "/intc/v2m", "msi-controller", NULL, 0);
387     qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/v2m", "reg",
388                                  2, vms->memmap[VIRT_GIC_V2M].base,
389                                  2, vms->memmap[VIRT_GIC_V2M].size);
390     qemu_fdt_setprop_cell(vms->fdt, "/intc/v2m", "phandle", vms->msi_phandle);
391 }
392 
393 static void fdt_add_gic_node(VirtMachineState *vms)
394 {
395     vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt);
396     qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle);
397 
398     qemu_fdt_add_subnode(vms->fdt, "/intc");
399     qemu_fdt_setprop_cell(vms->fdt, "/intc", "#interrupt-cells", 3);
400     qemu_fdt_setprop(vms->fdt, "/intc", "interrupt-controller", NULL, 0);
401     qemu_fdt_setprop_cell(vms->fdt, "/intc", "#address-cells", 0x2);
402     qemu_fdt_setprop_cell(vms->fdt, "/intc", "#size-cells", 0x2);
403     qemu_fdt_setprop(vms->fdt, "/intc", "ranges", NULL, 0);
404     if (vms->gic_version == 3) {
405         qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible",
406                                 "arm,gic-v3");
407         qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg",
408                                      2, vms->memmap[VIRT_GIC_DIST].base,
409                                      2, vms->memmap[VIRT_GIC_DIST].size,
410                                      2, vms->memmap[VIRT_GIC_REDIST].base,
411                                      2, vms->memmap[VIRT_GIC_REDIST].size);
412         if (vms->virt) {
413             qemu_fdt_setprop_cells(vms->fdt, "/intc", "interrupts",
414                                    GIC_FDT_IRQ_TYPE_PPI, ARCH_GICV3_MAINT_IRQ,
415                                    GIC_FDT_IRQ_FLAGS_LEVEL_HI);
416         }
417     } else {
418         /* 'cortex-a15-gic' means 'GIC v2' */
419         qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible",
420                                 "arm,cortex-a15-gic");
421         qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg",
422                                       2, vms->memmap[VIRT_GIC_DIST].base,
423                                       2, vms->memmap[VIRT_GIC_DIST].size,
424                                       2, vms->memmap[VIRT_GIC_CPU].base,
425                                       2, vms->memmap[VIRT_GIC_CPU].size);
426     }
427 
428     qemu_fdt_setprop_cell(vms->fdt, "/intc", "phandle", vms->gic_phandle);
429 }
430 
431 static void fdt_add_pmu_nodes(const VirtMachineState *vms)
432 {
433     CPUState *cpu;
434     ARMCPU *armcpu;
435     uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
436 
437     CPU_FOREACH(cpu) {
438         armcpu = ARM_CPU(cpu);
439         if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
440             return;
441         }
442         if (kvm_enabled()) {
443             if (kvm_irqchip_in_kernel()) {
444                 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
445             }
446             kvm_arm_pmu_init(cpu);
447         }
448     }
449 
450     if (vms->gic_version == 2) {
451         irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
452                              GIC_FDT_IRQ_PPI_CPU_WIDTH,
453                              (1 << vms->smp_cpus) - 1);
454     }
455 
456     armcpu = ARM_CPU(qemu_get_cpu(0));
457     qemu_fdt_add_subnode(vms->fdt, "/pmu");
458     if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
459         const char compat[] = "arm,armv8-pmuv3";
460         qemu_fdt_setprop(vms->fdt, "/pmu", "compatible",
461                          compat, sizeof(compat));
462         qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts",
463                                GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
464     }
465 }
466 
467 static void create_its(VirtMachineState *vms, DeviceState *gicdev)
468 {
469     const char *itsclass = its_class_name();
470     DeviceState *dev;
471 
472     if (!itsclass) {
473         /* Do nothing if not supported */
474         return;
475     }
476 
477     dev = qdev_create(NULL, itsclass);
478 
479     object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3",
480                              &error_abort);
481     qdev_init_nofail(dev);
482     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
483 
484     fdt_add_its_gic_node(vms);
485 }
486 
487 static void create_v2m(VirtMachineState *vms, qemu_irq *pic)
488 {
489     int i;
490     int irq = vms->irqmap[VIRT_GIC_V2M];
491     DeviceState *dev;
492 
493     dev = qdev_create(NULL, "arm-gicv2m");
494     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
495     qdev_prop_set_uint32(dev, "base-spi", irq);
496     qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
497     qdev_init_nofail(dev);
498 
499     for (i = 0; i < NUM_GICV2M_SPIS; i++) {
500         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
501     }
502 
503     fdt_add_v2m_gic_node(vms);
504 }
505 
506 static void create_gic(VirtMachineState *vms, qemu_irq *pic)
507 {
508     /* We create a standalone GIC */
509     DeviceState *gicdev;
510     SysBusDevice *gicbusdev;
511     const char *gictype;
512     int type = vms->gic_version, i;
513 
514     gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
515 
516     gicdev = qdev_create(NULL, gictype);
517     qdev_prop_set_uint32(gicdev, "revision", type);
518     qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus);
519     /* Note that the num-irq property counts both internal and external
520      * interrupts; there are always 32 of the former (mandated by GIC spec).
521      */
522     qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32);
523     if (!kvm_irqchip_in_kernel()) {
524         qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure);
525     }
526 
527     if (type == 3) {
528         uint32_t redist0_capacity =
529                     vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
530         uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
531 
532         qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1);
533         qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count);
534     }
535     qdev_init_nofail(gicdev);
536     gicbusdev = SYS_BUS_DEVICE(gicdev);
537     sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
538     if (type == 3) {
539         sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
540     } else {
541         sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
542     }
543 
544     /* Wire the outputs from each CPU's generic timer and the GICv3
545      * maintenance interrupt signal to the appropriate GIC PPI inputs,
546      * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
547      */
548     for (i = 0; i < smp_cpus; i++) {
549         DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
550         int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
551         int irq;
552         /* Mapping from the output timer irq lines from the CPU to the
553          * GIC PPI inputs we use for the virt board.
554          */
555         const int timer_irq[] = {
556             [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
557             [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
558             [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
559             [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,
560         };
561 
562         for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
563             qdev_connect_gpio_out(cpudev, irq,
564                                   qdev_get_gpio_in(gicdev,
565                                                    ppibase + timer_irq[irq]));
566         }
567 
568         qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
569                                     qdev_get_gpio_in(gicdev, ppibase
570                                                      + ARCH_GICV3_MAINT_IRQ));
571         qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
572                                     qdev_get_gpio_in(gicdev, ppibase
573                                                      + VIRTUAL_PMU_IRQ));
574 
575         sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
576         sysbus_connect_irq(gicbusdev, i + smp_cpus,
577                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
578         sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
579                            qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
580         sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
581                            qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
582     }
583 
584     for (i = 0; i < NUM_IRQS; i++) {
585         pic[i] = qdev_get_gpio_in(gicdev, i);
586     }
587 
588     fdt_add_gic_node(vms);
589 
590     if (type == 3 && vms->its) {
591         create_its(vms, gicdev);
592     } else if (type == 2) {
593         create_v2m(vms, pic);
594     }
595 }
596 
597 static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart,
598                         MemoryRegion *mem, Chardev *chr)
599 {
600     char *nodename;
601     hwaddr base = vms->memmap[uart].base;
602     hwaddr size = vms->memmap[uart].size;
603     int irq = vms->irqmap[uart];
604     const char compat[] = "arm,pl011\0arm,primecell";
605     const char clocknames[] = "uartclk\0apb_pclk";
606     DeviceState *dev = qdev_create(NULL, "pl011");
607     SysBusDevice *s = SYS_BUS_DEVICE(dev);
608 
609     qdev_prop_set_chr(dev, "chardev", chr);
610     qdev_init_nofail(dev);
611     memory_region_add_subregion(mem, base,
612                                 sysbus_mmio_get_region(s, 0));
613     sysbus_connect_irq(s, 0, pic[irq]);
614 
615     nodename = g_strdup_printf("/pl011@%" PRIx64, base);
616     qemu_fdt_add_subnode(vms->fdt, nodename);
617     /* Note that we can't use setprop_string because of the embedded NUL */
618     qemu_fdt_setprop(vms->fdt, nodename, "compatible",
619                          compat, sizeof(compat));
620     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
621                                      2, base, 2, size);
622     qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
623                                GIC_FDT_IRQ_TYPE_SPI, irq,
624                                GIC_FDT_IRQ_FLAGS_LEVEL_HI);
625     qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks",
626                                vms->clock_phandle, vms->clock_phandle);
627     qemu_fdt_setprop(vms->fdt, nodename, "clock-names",
628                          clocknames, sizeof(clocknames));
629 
630     if (uart == VIRT_UART) {
631         qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename);
632     } else {
633         /* Mark as not usable by the normal world */
634         qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
635         qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
636     }
637 
638     g_free(nodename);
639 }
640 
641 static void create_rtc(const VirtMachineState *vms, qemu_irq *pic)
642 {
643     char *nodename;
644     hwaddr base = vms->memmap[VIRT_RTC].base;
645     hwaddr size = vms->memmap[VIRT_RTC].size;
646     int irq = vms->irqmap[VIRT_RTC];
647     const char compat[] = "arm,pl031\0arm,primecell";
648 
649     sysbus_create_simple("pl031", base, pic[irq]);
650 
651     nodename = g_strdup_printf("/pl031@%" PRIx64, base);
652     qemu_fdt_add_subnode(vms->fdt, nodename);
653     qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
654     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
655                                  2, base, 2, size);
656     qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
657                            GIC_FDT_IRQ_TYPE_SPI, irq,
658                            GIC_FDT_IRQ_FLAGS_LEVEL_HI);
659     qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
660     qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
661     g_free(nodename);
662 }
663 
664 static DeviceState *gpio_key_dev;
665 static void virt_powerdown_req(Notifier *n, void *opaque)
666 {
667     /* use gpio Pin 3 for power button event */
668     qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
669 }
670 
671 static Notifier virt_system_powerdown_notifier = {
672     .notify = virt_powerdown_req
673 };
674 
675 static void create_gpio(const VirtMachineState *vms, qemu_irq *pic)
676 {
677     char *nodename;
678     DeviceState *pl061_dev;
679     hwaddr base = vms->memmap[VIRT_GPIO].base;
680     hwaddr size = vms->memmap[VIRT_GPIO].size;
681     int irq = vms->irqmap[VIRT_GPIO];
682     const char compat[] = "arm,pl061\0arm,primecell";
683 
684     pl061_dev = sysbus_create_simple("pl061", base, pic[irq]);
685 
686     uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt);
687     nodename = g_strdup_printf("/pl061@%" PRIx64, base);
688     qemu_fdt_add_subnode(vms->fdt, nodename);
689     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
690                                  2, base, 2, size);
691     qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
692     qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2);
693     qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0);
694     qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
695                            GIC_FDT_IRQ_TYPE_SPI, irq,
696                            GIC_FDT_IRQ_FLAGS_LEVEL_HI);
697     qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
698     qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
699     qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle);
700 
701     gpio_key_dev = sysbus_create_simple("gpio-key", -1,
702                                         qdev_get_gpio_in(pl061_dev, 3));
703     qemu_fdt_add_subnode(vms->fdt, "/gpio-keys");
704     qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys");
705     qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0);
706     qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1);
707 
708     qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff");
709     qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff",
710                             "label", "GPIO Key Poweroff");
711     qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code",
712                           KEY_POWER);
713     qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff",
714                            "gpios", phandle, 3, 0);
715 
716     /* connect powerdown request */
717     qemu_register_powerdown_notifier(&virt_system_powerdown_notifier);
718 
719     g_free(nodename);
720 }
721 
722 static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic)
723 {
724     int i;
725     hwaddr size = vms->memmap[VIRT_MMIO].size;
726 
727     /* We create the transports in forwards order. Since qbus_realize()
728      * prepends (not appends) new child buses, the incrementing loop below will
729      * create a list of virtio-mmio buses with decreasing base addresses.
730      *
731      * When a -device option is processed from the command line,
732      * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
733      * order. The upshot is that -device options in increasing command line
734      * order are mapped to virtio-mmio buses with decreasing base addresses.
735      *
736      * When this code was originally written, that arrangement ensured that the
737      * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
738      * the first -device on the command line. (The end-to-end order is a
739      * function of this loop, qbus_realize(), qbus_find_recursive(), and the
740      * guest kernel's name-to-address assignment strategy.)
741      *
742      * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
743      * the message, if not necessarily the code, of commit 70161ff336.
744      * Therefore the loop now establishes the inverse of the original intent.
745      *
746      * Unfortunately, we can't counteract the kernel change by reversing the
747      * loop; it would break existing command lines.
748      *
749      * In any case, the kernel makes no guarantee about the stability of
750      * enumeration order of virtio devices (as demonstrated by it changing
751      * between kernel versions). For reliable and stable identification
752      * of disks users must use UUIDs or similar mechanisms.
753      */
754     for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
755         int irq = vms->irqmap[VIRT_MMIO] + i;
756         hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
757 
758         sysbus_create_simple("virtio-mmio", base, pic[irq]);
759     }
760 
761     /* We add dtb nodes in reverse order so that they appear in the finished
762      * device tree lowest address first.
763      *
764      * Note that this mapping is independent of the loop above. The previous
765      * loop influences virtio device to virtio transport assignment, whereas
766      * this loop controls how virtio transports are laid out in the dtb.
767      */
768     for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
769         char *nodename;
770         int irq = vms->irqmap[VIRT_MMIO] + i;
771         hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
772 
773         nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
774         qemu_fdt_add_subnode(vms->fdt, nodename);
775         qemu_fdt_setprop_string(vms->fdt, nodename,
776                                 "compatible", "virtio,mmio");
777         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
778                                      2, base, 2, size);
779         qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
780                                GIC_FDT_IRQ_TYPE_SPI, irq,
781                                GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
782         qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
783         g_free(nodename);
784     }
785 }
786 
787 static void create_one_flash(const char *name, hwaddr flashbase,
788                              hwaddr flashsize, const char *file,
789                              MemoryRegion *sysmem)
790 {
791     /* Create and map a single flash device. We use the same
792      * parameters as the flash devices on the Versatile Express board.
793      */
794     DriveInfo *dinfo = drive_get_next(IF_PFLASH);
795     DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
796     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
797     const uint64_t sectorlength = 256 * 1024;
798 
799     if (dinfo) {
800         qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
801                             &error_abort);
802     }
803 
804     qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength);
805     qdev_prop_set_uint64(dev, "sector-length", sectorlength);
806     qdev_prop_set_uint8(dev, "width", 4);
807     qdev_prop_set_uint8(dev, "device-width", 2);
808     qdev_prop_set_bit(dev, "big-endian", false);
809     qdev_prop_set_uint16(dev, "id0", 0x89);
810     qdev_prop_set_uint16(dev, "id1", 0x18);
811     qdev_prop_set_uint16(dev, "id2", 0x00);
812     qdev_prop_set_uint16(dev, "id3", 0x00);
813     qdev_prop_set_string(dev, "name", name);
814     qdev_init_nofail(dev);
815 
816     memory_region_add_subregion(sysmem, flashbase,
817                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
818 
819     if (file) {
820         char *fn;
821         int image_size;
822 
823         if (drive_get(IF_PFLASH, 0, 0)) {
824             error_report("The contents of the first flash device may be "
825                          "specified with -bios or with -drive if=pflash... "
826                          "but you cannot use both options at once");
827             exit(1);
828         }
829         fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file);
830         if (!fn) {
831             error_report("Could not find ROM image '%s'", file);
832             exit(1);
833         }
834         image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0));
835         g_free(fn);
836         if (image_size < 0) {
837             error_report("Could not load ROM image '%s'", file);
838             exit(1);
839         }
840     }
841 }
842 
843 static void create_flash(const VirtMachineState *vms,
844                          MemoryRegion *sysmem,
845                          MemoryRegion *secure_sysmem)
846 {
847     /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
848      * Any file passed via -bios goes in the first of these.
849      * sysmem is the system memory space. secure_sysmem is the secure view
850      * of the system, and the first flash device should be made visible only
851      * there. The second flash device is visible to both secure and nonsecure.
852      * If sysmem == secure_sysmem this means there is no separate Secure
853      * address space and both flash devices are generally visible.
854      */
855     hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
856     hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
857     char *nodename;
858 
859     create_one_flash("virt.flash0", flashbase, flashsize,
860                      bios_name, secure_sysmem);
861     create_one_flash("virt.flash1", flashbase + flashsize, flashsize,
862                      NULL, sysmem);
863 
864     if (sysmem == secure_sysmem) {
865         /* Report both flash devices as a single node in the DT */
866         nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
867         qemu_fdt_add_subnode(vms->fdt, nodename);
868         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
869         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
870                                      2, flashbase, 2, flashsize,
871                                      2, flashbase + flashsize, 2, flashsize);
872         qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
873         g_free(nodename);
874     } else {
875         /* Report the devices as separate nodes so we can mark one as
876          * only visible to the secure world.
877          */
878         nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
879         qemu_fdt_add_subnode(vms->fdt, nodename);
880         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
881         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
882                                      2, flashbase, 2, flashsize);
883         qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
884         qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
885         qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
886         g_free(nodename);
887 
888         nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
889         qemu_fdt_add_subnode(vms->fdt, nodename);
890         qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
891         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
892                                      2, flashbase + flashsize, 2, flashsize);
893         qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
894         g_free(nodename);
895     }
896 }
897 
898 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
899 {
900     hwaddr base = vms->memmap[VIRT_FW_CFG].base;
901     hwaddr size = vms->memmap[VIRT_FW_CFG].size;
902     FWCfgState *fw_cfg;
903     char *nodename;
904 
905     fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
906     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
907 
908     nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
909     qemu_fdt_add_subnode(vms->fdt, nodename);
910     qemu_fdt_setprop_string(vms->fdt, nodename,
911                             "compatible", "qemu,fw-cfg-mmio");
912     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
913                                  2, base, 2, size);
914     qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
915     g_free(nodename);
916     return fw_cfg;
917 }
918 
919 static void create_pcie_irq_map(const VirtMachineState *vms,
920                                 uint32_t gic_phandle,
921                                 int first_irq, const char *nodename)
922 {
923     int devfn, pin;
924     uint32_t full_irq_map[4 * 4 * 10] = { 0 };
925     uint32_t *irq_map = full_irq_map;
926 
927     for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
928         for (pin = 0; pin < 4; pin++) {
929             int irq_type = GIC_FDT_IRQ_TYPE_SPI;
930             int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
931             int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
932             int i;
933 
934             uint32_t map[] = {
935                 devfn << 8, 0, 0,                           /* devfn */
936                 pin + 1,                                    /* PCI pin */
937                 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */
938 
939             /* Convert map to big endian */
940             for (i = 0; i < 10; i++) {
941                 irq_map[i] = cpu_to_be32(map[i]);
942             }
943             irq_map += 10;
944         }
945     }
946 
947     qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map",
948                      full_irq_map, sizeof(full_irq_map));
949 
950     qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask",
951                            0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
952                            0x7           /* PCI irq */);
953 }
954 
955 static void create_smmu(const VirtMachineState *vms, qemu_irq *pic,
956                         PCIBus *bus)
957 {
958     char *node;
959     const char compat[] = "arm,smmu-v3";
960     int irq =  vms->irqmap[VIRT_SMMU];
961     int i;
962     hwaddr base = vms->memmap[VIRT_SMMU].base;
963     hwaddr size = vms->memmap[VIRT_SMMU].size;
964     const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
965     DeviceState *dev;
966 
967     if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
968         return;
969     }
970 
971     dev = qdev_create(NULL, "arm-smmuv3");
972 
973     object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
974                              &error_abort);
975     qdev_init_nofail(dev);
976     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
977     for (i = 0; i < NUM_SMMU_IRQS; i++) {
978         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
979     }
980 
981     node = g_strdup_printf("/smmuv3@%" PRIx64, base);
982     qemu_fdt_add_subnode(vms->fdt, node);
983     qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat));
984     qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size);
985 
986     qemu_fdt_setprop_cells(vms->fdt, node, "interrupts",
987             GIC_FDT_IRQ_TYPE_SPI, irq    , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
988             GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
989             GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
990             GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
991 
992     qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names,
993                      sizeof(irq_names));
994 
995     qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle);
996     qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk");
997     qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0);
998 
999     qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1);
1000 
1001     qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle);
1002     g_free(node);
1003 }
1004 
1005 static void create_pcie(VirtMachineState *vms, qemu_irq *pic)
1006 {
1007     hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1008     hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1009     hwaddr base_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].base;
1010     hwaddr size_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].size;
1011     hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1012     hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1013     hwaddr base_ecam = vms->memmap[VIRT_PCIE_ECAM].base;
1014     hwaddr size_ecam = vms->memmap[VIRT_PCIE_ECAM].size;
1015     hwaddr base = base_mmio;
1016     int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1017     int irq = vms->irqmap[VIRT_PCIE];
1018     MemoryRegion *mmio_alias;
1019     MemoryRegion *mmio_reg;
1020     MemoryRegion *ecam_alias;
1021     MemoryRegion *ecam_reg;
1022     DeviceState *dev;
1023     char *nodename;
1024     int i;
1025     PCIHostState *pci;
1026 
1027     dev = qdev_create(NULL, TYPE_GPEX_HOST);
1028     qdev_init_nofail(dev);
1029 
1030     /* Map only the first size_ecam bytes of ECAM space */
1031     ecam_alias = g_new0(MemoryRegion, 1);
1032     ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1033     memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1034                              ecam_reg, 0, size_ecam);
1035     memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1036 
1037     /* Map the MMIO window into system address space so as to expose
1038      * the section of PCI MMIO space which starts at the same base address
1039      * (ie 1:1 mapping for that part of PCI MMIO space visible through
1040      * the window).
1041      */
1042     mmio_alias = g_new0(MemoryRegion, 1);
1043     mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1044     memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1045                              mmio_reg, base_mmio, size_mmio);
1046     memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1047 
1048     if (vms->highmem) {
1049         /* Map high MMIO space */
1050         MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1051 
1052         memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1053                                  mmio_reg, base_mmio_high, size_mmio_high);
1054         memory_region_add_subregion(get_system_memory(), base_mmio_high,
1055                                     high_mmio_alias);
1056     }
1057 
1058     /* Map IO port space */
1059     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1060 
1061     for (i = 0; i < GPEX_NUM_IRQS; i++) {
1062         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
1063         gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1064     }
1065 
1066     pci = PCI_HOST_BRIDGE(dev);
1067     if (pci->bus) {
1068         for (i = 0; i < nb_nics; i++) {
1069             NICInfo *nd = &nd_table[i];
1070 
1071             if (!nd->model) {
1072                 nd->model = g_strdup("virtio");
1073             }
1074 
1075             pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
1076         }
1077     }
1078 
1079     nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1080     qemu_fdt_add_subnode(vms->fdt, nodename);
1081     qemu_fdt_setprop_string(vms->fdt, nodename,
1082                             "compatible", "pci-host-ecam-generic");
1083     qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci");
1084     qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3);
1085     qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2);
1086     qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0);
1087     qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0,
1088                            nr_pcie_buses - 1);
1089     qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
1090 
1091     if (vms->msi_phandle) {
1092         qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent",
1093                                vms->msi_phandle);
1094     }
1095 
1096     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
1097                                  2, base_ecam, 2, size_ecam);
1098 
1099     if (vms->highmem) {
1100         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
1101                                      1, FDT_PCI_RANGE_IOPORT, 2, 0,
1102                                      2, base_pio, 2, size_pio,
1103                                      1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1104                                      2, base_mmio, 2, size_mmio,
1105                                      1, FDT_PCI_RANGE_MMIO_64BIT,
1106                                      2, base_mmio_high,
1107                                      2, base_mmio_high, 2, size_mmio_high);
1108     } else {
1109         qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
1110                                      1, FDT_PCI_RANGE_IOPORT, 2, 0,
1111                                      2, base_pio, 2, size_pio,
1112                                      1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1113                                      2, base_mmio, 2, size_mmio);
1114     }
1115 
1116     qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1);
1117     create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename);
1118 
1119     if (vms->iommu) {
1120         vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt);
1121 
1122         create_smmu(vms, pic, pci->bus);
1123 
1124         qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map",
1125                                0x0, vms->iommu_phandle, 0x0, 0x10000);
1126     }
1127 
1128     g_free(nodename);
1129 }
1130 
1131 static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic)
1132 {
1133     DeviceState *dev;
1134     SysBusDevice *s;
1135     int i;
1136     MemoryRegion *sysmem = get_system_memory();
1137 
1138     dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
1139     dev->id = TYPE_PLATFORM_BUS_DEVICE;
1140     qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1141     qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1142     qdev_init_nofail(dev);
1143     vms->platform_bus_dev = dev;
1144 
1145     s = SYS_BUS_DEVICE(dev);
1146     for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1147         int irqn = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1148         sysbus_connect_irq(s, i, pic[irqn]);
1149     }
1150 
1151     memory_region_add_subregion(sysmem,
1152                                 vms->memmap[VIRT_PLATFORM_BUS].base,
1153                                 sysbus_mmio_get_region(s, 0));
1154 }
1155 
1156 static void create_secure_ram(VirtMachineState *vms,
1157                               MemoryRegion *secure_sysmem)
1158 {
1159     MemoryRegion *secram = g_new(MemoryRegion, 1);
1160     char *nodename;
1161     hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1162     hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1163 
1164     memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1165                            &error_fatal);
1166     memory_region_add_subregion(secure_sysmem, base, secram);
1167 
1168     nodename = g_strdup_printf("/secram@%" PRIx64, base);
1169     qemu_fdt_add_subnode(vms->fdt, nodename);
1170     qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory");
1171     qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size);
1172     qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
1173     qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
1174 
1175     g_free(nodename);
1176 }
1177 
1178 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1179 {
1180     const VirtMachineState *board = container_of(binfo, VirtMachineState,
1181                                                  bootinfo);
1182 
1183     *fdt_size = board->fdt_size;
1184     return board->fdt;
1185 }
1186 
1187 static void virt_build_smbios(VirtMachineState *vms)
1188 {
1189     MachineClass *mc = MACHINE_GET_CLASS(vms);
1190     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1191     uint8_t *smbios_tables, *smbios_anchor;
1192     size_t smbios_tables_len, smbios_anchor_len;
1193     const char *product = "QEMU Virtual Machine";
1194 
1195     if (!vms->fw_cfg) {
1196         return;
1197     }
1198 
1199     if (kvm_enabled()) {
1200         product = "KVM Virtual Machine";
1201     }
1202 
1203     smbios_set_defaults("QEMU", product,
1204                         vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
1205                         true, SMBIOS_ENTRY_POINT_30);
1206 
1207     smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len,
1208                       &smbios_anchor, &smbios_anchor_len);
1209 
1210     if (smbios_anchor) {
1211         fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1212                         smbios_tables, smbios_tables_len);
1213         fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1214                         smbios_anchor, smbios_anchor_len);
1215     }
1216 }
1217 
1218 static
1219 void virt_machine_done(Notifier *notifier, void *data)
1220 {
1221     VirtMachineState *vms = container_of(notifier, VirtMachineState,
1222                                          machine_done);
1223     ARMCPU *cpu = ARM_CPU(first_cpu);
1224     struct arm_boot_info *info = &vms->bootinfo;
1225     AddressSpace *as = arm_boot_address_space(cpu, info);
1226 
1227     /*
1228      * If the user provided a dtb, we assume the dynamic sysbus nodes
1229      * already are integrated there. This corresponds to a use case where
1230      * the dynamic sysbus nodes are complex and their generation is not yet
1231      * supported. In that case the user can take charge of the guest dt
1232      * while qemu takes charge of the qom stuff.
1233      */
1234     if (info->dtb_filename == NULL) {
1235         platform_bus_add_all_fdt_nodes(vms->fdt, "/intc",
1236                                        vms->memmap[VIRT_PLATFORM_BUS].base,
1237                                        vms->memmap[VIRT_PLATFORM_BUS].size,
1238                                        vms->irqmap[VIRT_PLATFORM_BUS]);
1239     }
1240     if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
1241         exit(1);
1242     }
1243 
1244     virt_acpi_setup(vms);
1245     virt_build_smbios(vms);
1246 }
1247 
1248 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1249 {
1250     uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1251     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1252 
1253     if (!vmc->disallow_affinity_adjustment) {
1254         /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1255          * GIC's target-list limitations. 32-bit KVM hosts currently
1256          * always create clusters of 4 CPUs, but that is expected to
1257          * change when they gain support for gicv3. When KVM is enabled
1258          * it will override the changes we make here, therefore our
1259          * purposes are to make TCG consistent (with 64-bit KVM hosts)
1260          * and to improve SGI efficiency.
1261          */
1262         if (vms->gic_version == 3) {
1263             clustersz = GICV3_TARGETLIST_BITS;
1264         } else {
1265             clustersz = GIC_TARGETLIST_BITS;
1266         }
1267     }
1268     return arm_cpu_mp_affinity(idx, clustersz);
1269 }
1270 
1271 static void machvirt_init(MachineState *machine)
1272 {
1273     VirtMachineState *vms = VIRT_MACHINE(machine);
1274     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
1275     MachineClass *mc = MACHINE_GET_CLASS(machine);
1276     const CPUArchIdList *possible_cpus;
1277     qemu_irq pic[NUM_IRQS];
1278     MemoryRegion *sysmem = get_system_memory();
1279     MemoryRegion *secure_sysmem = NULL;
1280     int n, virt_max_cpus;
1281     MemoryRegion *ram = g_new(MemoryRegion, 1);
1282     bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);
1283 
1284     /* We can probe only here because during property set
1285      * KVM is not available yet
1286      */
1287     if (vms->gic_version <= 0) {
1288         /* "host" or "max" */
1289         if (!kvm_enabled()) {
1290             if (vms->gic_version == 0) {
1291                 error_report("gic-version=host requires KVM");
1292                 exit(1);
1293             } else {
1294                 /* "max": currently means 3 for TCG */
1295                 vms->gic_version = 3;
1296             }
1297         } else {
1298             vms->gic_version = kvm_arm_vgic_probe();
1299             if (!vms->gic_version) {
1300                 error_report(
1301                     "Unable to determine GIC version supported by host");
1302                 exit(1);
1303             }
1304         }
1305     }
1306 
1307     if (!cpu_type_valid(machine->cpu_type)) {
1308         error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
1309         exit(1);
1310     }
1311 
1312     /* If we have an EL3 boot ROM then the assumption is that it will
1313      * implement PSCI itself, so disable QEMU's internal implementation
1314      * so it doesn't get in the way. Instead of starting secondary
1315      * CPUs in PSCI powerdown state we will start them all running and
1316      * let the boot ROM sort them out.
1317      * The usual case is that we do use QEMU's PSCI implementation;
1318      * if the guest has EL2 then we will use SMC as the conduit,
1319      * and otherwise we will use HVC (for backwards compatibility and
1320      * because if we're using KVM then we must use HVC).
1321      */
1322     if (vms->secure && firmware_loaded) {
1323         vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
1324     } else if (vms->virt) {
1325         vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
1326     } else {
1327         vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
1328     }
1329 
1330     /* The maximum number of CPUs depends on the GIC version, or on how
1331      * many redistributors we can fit into the memory map.
1332      */
1333     if (vms->gic_version == 3) {
1334         virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
1335     } else {
1336         virt_max_cpus = GIC_NCPU;
1337     }
1338 
1339     if (max_cpus > virt_max_cpus) {
1340         error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1341                      "supported by machine 'mach-virt' (%d)",
1342                      max_cpus, virt_max_cpus);
1343         exit(1);
1344     }
1345 
1346     vms->smp_cpus = smp_cpus;
1347 
1348     if (machine->ram_size > vms->memmap[VIRT_MEM].size) {
1349         error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB);
1350         exit(1);
1351     }
1352 
1353     if (vms->virt && kvm_enabled()) {
1354         error_report("mach-virt: KVM does not support providing "
1355                      "Virtualization extensions to the guest CPU");
1356         exit(1);
1357     }
1358 
1359     if (vms->secure) {
1360         if (kvm_enabled()) {
1361             error_report("mach-virt: KVM does not support Security extensions");
1362             exit(1);
1363         }
1364 
1365         /* The Secure view of the world is the same as the NonSecure,
1366          * but with a few extra devices. Create it as a container region
1367          * containing the system memory at low priority; any secure-only
1368          * devices go in at higher priority and take precedence.
1369          */
1370         secure_sysmem = g_new(MemoryRegion, 1);
1371         memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
1372                            UINT64_MAX);
1373         memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
1374     }
1375 
1376     create_fdt(vms);
1377 
1378     possible_cpus = mc->possible_cpu_arch_ids(machine);
1379     for (n = 0; n < possible_cpus->len; n++) {
1380         Object *cpuobj;
1381         CPUState *cs;
1382 
1383         if (n >= smp_cpus) {
1384             break;
1385         }
1386 
1387         cpuobj = object_new(possible_cpus->cpus[n].type);
1388         object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,
1389                                 "mp-affinity", NULL);
1390 
1391         cs = CPU(cpuobj);
1392         cs->cpu_index = n;
1393 
1394         numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
1395                           &error_fatal);
1396 
1397         if (!vms->secure) {
1398             object_property_set_bool(cpuobj, false, "has_el3", NULL);
1399         }
1400 
1401         if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) {
1402             object_property_set_bool(cpuobj, false, "has_el2", NULL);
1403         }
1404 
1405         if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
1406             object_property_set_int(cpuobj, vms->psci_conduit,
1407                                     "psci-conduit", NULL);
1408 
1409             /* Secondary CPUs start in PSCI powered-down state */
1410             if (n > 0) {
1411                 object_property_set_bool(cpuobj, true,
1412                                          "start-powered-off", NULL);
1413             }
1414         }
1415 
1416         if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) {
1417             object_property_set_bool(cpuobj, false, "pmu", NULL);
1418         }
1419 
1420         if (object_property_find(cpuobj, "reset-cbar", NULL)) {
1421             object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base,
1422                                     "reset-cbar", &error_abort);
1423         }
1424 
1425         object_property_set_link(cpuobj, OBJECT(sysmem), "memory",
1426                                  &error_abort);
1427         if (vms->secure) {
1428             object_property_set_link(cpuobj, OBJECT(secure_sysmem),
1429                                      "secure-memory", &error_abort);
1430         }
1431 
1432         object_property_set_bool(cpuobj, true, "realized", &error_fatal);
1433         object_unref(cpuobj);
1434     }
1435     fdt_add_timer_nodes(vms);
1436     fdt_add_cpu_nodes(vms);
1437 
1438     memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram",
1439                                          machine->ram_size);
1440     memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram);
1441 
1442     create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem);
1443 
1444     create_gic(vms, pic);
1445 
1446     fdt_add_pmu_nodes(vms);
1447 
1448     create_uart(vms, pic, VIRT_UART, sysmem, serial_hd(0));
1449 
1450     if (vms->secure) {
1451         create_secure_ram(vms, secure_sysmem);
1452         create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
1453     }
1454 
1455     create_rtc(vms, pic);
1456 
1457     create_pcie(vms, pic);
1458 
1459     create_gpio(vms, pic);
1460 
1461     /* Create mmio transports, so the user can create virtio backends
1462      * (which will be automatically plugged in to the transports). If
1463      * no backend is created the transport will just sit harmlessly idle.
1464      */
1465     create_virtio_devices(vms, pic);
1466 
1467     vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
1468     rom_set_fw(vms->fw_cfg);
1469 
1470     create_platform_bus(vms, pic);
1471 
1472     vms->bootinfo.ram_size = machine->ram_size;
1473     vms->bootinfo.kernel_filename = machine->kernel_filename;
1474     vms->bootinfo.kernel_cmdline = machine->kernel_cmdline;
1475     vms->bootinfo.initrd_filename = machine->initrd_filename;
1476     vms->bootinfo.nb_cpus = smp_cpus;
1477     vms->bootinfo.board_id = -1;
1478     vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
1479     vms->bootinfo.get_dtb = machvirt_dtb;
1480     vms->bootinfo.skip_dtb_autoload = true;
1481     vms->bootinfo.firmware_loaded = firmware_loaded;
1482     arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo);
1483 
1484     vms->machine_done.notify = virt_machine_done;
1485     qemu_add_machine_init_done_notifier(&vms->machine_done);
1486 }
1487 
1488 static bool virt_get_secure(Object *obj, Error **errp)
1489 {
1490     VirtMachineState *vms = VIRT_MACHINE(obj);
1491 
1492     return vms->secure;
1493 }
1494 
1495 static void virt_set_secure(Object *obj, bool value, Error **errp)
1496 {
1497     VirtMachineState *vms = VIRT_MACHINE(obj);
1498 
1499     vms->secure = value;
1500 }
1501 
1502 static bool virt_get_virt(Object *obj, Error **errp)
1503 {
1504     VirtMachineState *vms = VIRT_MACHINE(obj);
1505 
1506     return vms->virt;
1507 }
1508 
1509 static void virt_set_virt(Object *obj, bool value, Error **errp)
1510 {
1511     VirtMachineState *vms = VIRT_MACHINE(obj);
1512 
1513     vms->virt = value;
1514 }
1515 
1516 static bool virt_get_highmem(Object *obj, Error **errp)
1517 {
1518     VirtMachineState *vms = VIRT_MACHINE(obj);
1519 
1520     return vms->highmem;
1521 }
1522 
1523 static void virt_set_highmem(Object *obj, bool value, Error **errp)
1524 {
1525     VirtMachineState *vms = VIRT_MACHINE(obj);
1526 
1527     vms->highmem = value;
1528 }
1529 
1530 static bool virt_get_its(Object *obj, Error **errp)
1531 {
1532     VirtMachineState *vms = VIRT_MACHINE(obj);
1533 
1534     return vms->its;
1535 }
1536 
1537 static void virt_set_its(Object *obj, bool value, Error **errp)
1538 {
1539     VirtMachineState *vms = VIRT_MACHINE(obj);
1540 
1541     vms->its = value;
1542 }
1543 
1544 static char *virt_get_gic_version(Object *obj, Error **errp)
1545 {
1546     VirtMachineState *vms = VIRT_MACHINE(obj);
1547     const char *val = vms->gic_version == 3 ? "3" : "2";
1548 
1549     return g_strdup(val);
1550 }
1551 
1552 static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
1553 {
1554     VirtMachineState *vms = VIRT_MACHINE(obj);
1555 
1556     if (!strcmp(value, "3")) {
1557         vms->gic_version = 3;
1558     } else if (!strcmp(value, "2")) {
1559         vms->gic_version = 2;
1560     } else if (!strcmp(value, "host")) {
1561         vms->gic_version = 0; /* Will probe later */
1562     } else if (!strcmp(value, "max")) {
1563         vms->gic_version = -1; /* Will probe later */
1564     } else {
1565         error_setg(errp, "Invalid gic-version value");
1566         error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
1567     }
1568 }
1569 
1570 static char *virt_get_iommu(Object *obj, Error **errp)
1571 {
1572     VirtMachineState *vms = VIRT_MACHINE(obj);
1573 
1574     switch (vms->iommu) {
1575     case VIRT_IOMMU_NONE:
1576         return g_strdup("none");
1577     case VIRT_IOMMU_SMMUV3:
1578         return g_strdup("smmuv3");
1579     default:
1580         g_assert_not_reached();
1581     }
1582 }
1583 
1584 static void virt_set_iommu(Object *obj, const char *value, Error **errp)
1585 {
1586     VirtMachineState *vms = VIRT_MACHINE(obj);
1587 
1588     if (!strcmp(value, "smmuv3")) {
1589         vms->iommu = VIRT_IOMMU_SMMUV3;
1590     } else if (!strcmp(value, "none")) {
1591         vms->iommu = VIRT_IOMMU_NONE;
1592     } else {
1593         error_setg(errp, "Invalid iommu value");
1594         error_append_hint(errp, "Valid values are none, smmuv3.\n");
1595     }
1596 }
1597 
1598 static CpuInstanceProperties
1599 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
1600 {
1601     MachineClass *mc = MACHINE_GET_CLASS(ms);
1602     const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
1603 
1604     assert(cpu_index < possible_cpus->len);
1605     return possible_cpus->cpus[cpu_index].props;
1606 }
1607 
1608 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
1609 {
1610     return idx % nb_numa_nodes;
1611 }
1612 
1613 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
1614 {
1615     int n;
1616     VirtMachineState *vms = VIRT_MACHINE(ms);
1617 
1618     if (ms->possible_cpus) {
1619         assert(ms->possible_cpus->len == max_cpus);
1620         return ms->possible_cpus;
1621     }
1622 
1623     ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
1624                                   sizeof(CPUArchId) * max_cpus);
1625     ms->possible_cpus->len = max_cpus;
1626     for (n = 0; n < ms->possible_cpus->len; n++) {
1627         ms->possible_cpus->cpus[n].type = ms->cpu_type;
1628         ms->possible_cpus->cpus[n].arch_id =
1629             virt_cpu_mp_affinity(vms, n);
1630         ms->possible_cpus->cpus[n].props.has_thread_id = true;
1631         ms->possible_cpus->cpus[n].props.thread_id = n;
1632     }
1633     return ms->possible_cpus;
1634 }
1635 
1636 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1637                                         DeviceState *dev, Error **errp)
1638 {
1639     VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
1640 
1641     if (vms->platform_bus_dev) {
1642         if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
1643             platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
1644                                      SYS_BUS_DEVICE(dev));
1645         }
1646     }
1647 }
1648 
1649 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
1650                                                         DeviceState *dev)
1651 {
1652     if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
1653         return HOTPLUG_HANDLER(machine);
1654     }
1655 
1656     return NULL;
1657 }
1658 
1659 static void virt_machine_class_init(ObjectClass *oc, void *data)
1660 {
1661     MachineClass *mc = MACHINE_CLASS(oc);
1662     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1663 
1664     mc->init = machvirt_init;
1665     /* Start max_cpus at the maximum QEMU supports. We'll further restrict
1666      * it later in machvirt_init, where we have more information about the
1667      * configuration of the particular instance.
1668      */
1669     mc->max_cpus = 255;
1670     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
1671     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
1672     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
1673     mc->block_default_type = IF_VIRTIO;
1674     mc->no_cdrom = 1;
1675     mc->pci_allow_0_address = true;
1676     /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
1677     mc->minimum_page_bits = 12;
1678     mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
1679     mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
1680     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
1681     mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
1682     assert(!mc->get_hotplug_handler);
1683     mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
1684     hc->plug = virt_machine_device_plug_cb;
1685 }
1686 
1687 static const TypeInfo virt_machine_info = {
1688     .name          = TYPE_VIRT_MACHINE,
1689     .parent        = TYPE_MACHINE,
1690     .abstract      = true,
1691     .instance_size = sizeof(VirtMachineState),
1692     .class_size    = sizeof(VirtMachineClass),
1693     .class_init    = virt_machine_class_init,
1694     .interfaces = (InterfaceInfo[]) {
1695          { TYPE_HOTPLUG_HANDLER },
1696          { }
1697     },
1698 };
1699 
1700 static void machvirt_machine_init(void)
1701 {
1702     type_register_static(&virt_machine_info);
1703 }
1704 type_init(machvirt_machine_init);
1705 
1706 #define VIRT_COMPAT_2_12 \
1707     HW_COMPAT_2_12
1708 
1709 static void virt_2_12_instance_init(Object *obj)
1710 {
1711     VirtMachineState *vms = VIRT_MACHINE(obj);
1712     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1713 
1714     /* EL3 is disabled by default on virt: this makes us consistent
1715      * between KVM and TCG for this board, and it also allows us to
1716      * boot UEFI blobs which assume no TrustZone support.
1717      */
1718     vms->secure = false;
1719     object_property_add_bool(obj, "secure", virt_get_secure,
1720                              virt_set_secure, NULL);
1721     object_property_set_description(obj, "secure",
1722                                     "Set on/off to enable/disable the ARM "
1723                                     "Security Extensions (TrustZone)",
1724                                     NULL);
1725 
1726     /* EL2 is also disabled by default, for similar reasons */
1727     vms->virt = false;
1728     object_property_add_bool(obj, "virtualization", virt_get_virt,
1729                              virt_set_virt, NULL);
1730     object_property_set_description(obj, "virtualization",
1731                                     "Set on/off to enable/disable emulating a "
1732                                     "guest CPU which implements the ARM "
1733                                     "Virtualization Extensions",
1734                                     NULL);
1735 
1736     /* High memory is enabled by default */
1737     vms->highmem = true;
1738     object_property_add_bool(obj, "highmem", virt_get_highmem,
1739                              virt_set_highmem, NULL);
1740     object_property_set_description(obj, "highmem",
1741                                     "Set on/off to enable/disable using "
1742                                     "physical address space above 32 bits",
1743                                     NULL);
1744     /* Default GIC type is v2 */
1745     vms->gic_version = 2;
1746     object_property_add_str(obj, "gic-version", virt_get_gic_version,
1747                         virt_set_gic_version, NULL);
1748     object_property_set_description(obj, "gic-version",
1749                                     "Set GIC version. "
1750                                     "Valid values are 2, 3 and host", NULL);
1751 
1752     if (vmc->no_its) {
1753         vms->its = false;
1754     } else {
1755         /* Default allows ITS instantiation */
1756         vms->its = true;
1757         object_property_add_bool(obj, "its", virt_get_its,
1758                                  virt_set_its, NULL);
1759         object_property_set_description(obj, "its",
1760                                         "Set on/off to enable/disable "
1761                                         "ITS instantiation",
1762                                         NULL);
1763     }
1764 
1765     /* Default disallows iommu instantiation */
1766     vms->iommu = VIRT_IOMMU_NONE;
1767     object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu, NULL);
1768     object_property_set_description(obj, "iommu",
1769                                     "Set the IOMMU type. "
1770                                     "Valid values are none and smmuv3",
1771                                     NULL);
1772 
1773     vms->memmap = a15memmap;
1774     vms->irqmap = a15irqmap;
1775 }
1776 
1777 static void virt_machine_2_12_options(MachineClass *mc)
1778 {
1779     SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_12);
1780 }
1781 DEFINE_VIRT_MACHINE_AS_LATEST(2, 12)
1782 
1783 #define VIRT_COMPAT_2_11 \
1784     HW_COMPAT_2_11
1785 
1786 static void virt_2_11_instance_init(Object *obj)
1787 {
1788     virt_2_12_instance_init(obj);
1789 }
1790 
1791 static void virt_machine_2_11_options(MachineClass *mc)
1792 {
1793     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
1794 
1795     virt_machine_2_12_options(mc);
1796     SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_11);
1797     vmc->smbios_old_sys_ver = true;
1798 }
1799 DEFINE_VIRT_MACHINE(2, 11)
1800 
1801 #define VIRT_COMPAT_2_10 \
1802     HW_COMPAT_2_10
1803 
1804 static void virt_2_10_instance_init(Object *obj)
1805 {
1806     virt_2_11_instance_init(obj);
1807 }
1808 
1809 static void virt_machine_2_10_options(MachineClass *mc)
1810 {
1811     virt_machine_2_11_options(mc);
1812     SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_10);
1813 }
1814 DEFINE_VIRT_MACHINE(2, 10)
1815 
1816 #define VIRT_COMPAT_2_9 \
1817     HW_COMPAT_2_9
1818 
1819 static void virt_2_9_instance_init(Object *obj)
1820 {
1821     virt_2_10_instance_init(obj);
1822 }
1823 
1824 static void virt_machine_2_9_options(MachineClass *mc)
1825 {
1826     virt_machine_2_10_options(mc);
1827     SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_9);
1828 }
1829 DEFINE_VIRT_MACHINE(2, 9)
1830 
1831 #define VIRT_COMPAT_2_8 \
1832     HW_COMPAT_2_8
1833 
1834 static void virt_2_8_instance_init(Object *obj)
1835 {
1836     virt_2_9_instance_init(obj);
1837 }
1838 
1839 static void virt_machine_2_8_options(MachineClass *mc)
1840 {
1841     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
1842 
1843     virt_machine_2_9_options(mc);
1844     SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_8);
1845     /* For 2.8 and earlier we falsely claimed in the DT that
1846      * our timers were edge-triggered, not level-triggered.
1847      */
1848     vmc->claim_edge_triggered_timers = true;
1849 }
1850 DEFINE_VIRT_MACHINE(2, 8)
1851 
1852 #define VIRT_COMPAT_2_7 \
1853     HW_COMPAT_2_7
1854 
1855 static void virt_2_7_instance_init(Object *obj)
1856 {
1857     virt_2_8_instance_init(obj);
1858 }
1859 
1860 static void virt_machine_2_7_options(MachineClass *mc)
1861 {
1862     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
1863 
1864     virt_machine_2_8_options(mc);
1865     SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_7);
1866     /* ITS was introduced with 2.8 */
1867     vmc->no_its = true;
1868     /* Stick with 1K pages for migration compatibility */
1869     mc->minimum_page_bits = 0;
1870 }
1871 DEFINE_VIRT_MACHINE(2, 7)
1872 
1873 #define VIRT_COMPAT_2_6 \
1874     HW_COMPAT_2_6
1875 
1876 static void virt_2_6_instance_init(Object *obj)
1877 {
1878     virt_2_7_instance_init(obj);
1879 }
1880 
1881 static void virt_machine_2_6_options(MachineClass *mc)
1882 {
1883     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
1884 
1885     virt_machine_2_7_options(mc);
1886     SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6);
1887     vmc->disallow_affinity_adjustment = true;
1888     /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
1889     vmc->no_pmu = true;
1890 }
1891 DEFINE_VIRT_MACHINE(2, 6)
1892