1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu-common.h" 33 #include "qemu/datadir.h" 34 #include "qemu/units.h" 35 #include "qemu/option.h" 36 #include "monitor/qdev.h" 37 #include "qapi/error.h" 38 #include "hw/sysbus.h" 39 #include "hw/boards.h" 40 #include "hw/arm/boot.h" 41 #include "hw/arm/primecell.h" 42 #include "hw/arm/virt.h" 43 #include "hw/block/flash.h" 44 #include "hw/vfio/vfio-calxeda-xgmac.h" 45 #include "hw/vfio/vfio-amd-xgbe.h" 46 #include "hw/display/ramfb.h" 47 #include "net/net.h" 48 #include "sysemu/device_tree.h" 49 #include "sysemu/numa.h" 50 #include "sysemu/runstate.h" 51 #include "sysemu/sysemu.h" 52 #include "sysemu/tpm.h" 53 #include "sysemu/kvm.h" 54 #include "hw/loader.h" 55 #include "exec/address-spaces.h" 56 #include "qemu/bitops.h" 57 #include "qemu/error-report.h" 58 #include "qemu/module.h" 59 #include "hw/pci-host/gpex.h" 60 #include "hw/virtio/virtio-pci.h" 61 #include "hw/arm/sysbus-fdt.h" 62 #include "hw/platform-bus.h" 63 #include "hw/qdev-properties.h" 64 #include "hw/arm/fdt.h" 65 #include "hw/intc/arm_gic.h" 66 #include "hw/intc/arm_gicv3_common.h" 67 #include "hw/irq.h" 68 #include "kvm_arm.h" 69 #include "hw/firmware/smbios.h" 70 #include "qapi/visitor.h" 71 #include "qapi/qapi-visit-common.h" 72 #include "standard-headers/linux/input.h" 73 #include "hw/arm/smmuv3.h" 74 #include "hw/acpi/acpi.h" 75 #include "target/arm/internals.h" 76 #include "hw/mem/pc-dimm.h" 77 #include "hw/mem/nvdimm.h" 78 #include "hw/acpi/generic_event_device.h" 79 #include "hw/virtio/virtio-iommu.h" 80 #include "hw/char/pl011.h" 81 #include "qemu/guest-random.h" 82 83 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 84 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 85 void *data) \ 86 { \ 87 MachineClass *mc = MACHINE_CLASS(oc); \ 88 virt_machine_##major##_##minor##_options(mc); \ 89 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 90 if (latest) { \ 91 mc->alias = "virt"; \ 92 } \ 93 } \ 94 static const TypeInfo machvirt_##major##_##minor##_info = { \ 95 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 96 .parent = TYPE_VIRT_MACHINE, \ 97 .class_init = virt_##major##_##minor##_class_init, \ 98 }; \ 99 static void machvirt_machine_##major##_##minor##_init(void) \ 100 { \ 101 type_register_static(&machvirt_##major##_##minor##_info); \ 102 } \ 103 type_init(machvirt_machine_##major##_##minor##_init); 104 105 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 106 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 107 #define DEFINE_VIRT_MACHINE(major, minor) \ 108 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 109 110 111 /* Number of external interrupt lines to configure the GIC with */ 112 #define NUM_IRQS 256 113 114 #define PLATFORM_BUS_NUM_IRQS 64 115 116 /* Legacy RAM limit in GB (< version 4.0) */ 117 #define LEGACY_RAMLIMIT_GB 255 118 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 119 120 /* Addresses and sizes of our components. 121 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 122 * 128MB..256MB is used for miscellaneous device I/O. 123 * 256MB..1GB is reserved for possible future PCI support (ie where the 124 * PCI memory window will go if we add a PCI host controller). 125 * 1GB and up is RAM (which may happily spill over into the 126 * high memory region beyond 4GB). 127 * This represents a compromise between how much RAM can be given to 128 * a 32 bit VM and leaving space for expansion and in particular for PCI. 129 * Note that devices should generally be placed at multiples of 0x10000, 130 * to accommodate guests using 64K pages. 131 */ 132 static const MemMapEntry base_memmap[] = { 133 /* Space up to 0x8000000 is reserved for a boot ROM */ 134 [VIRT_FLASH] = { 0, 0x08000000 }, 135 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 136 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 137 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 138 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 139 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 140 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 141 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 142 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 143 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 144 /* This redistributor space allows up to 2*64kB*123 CPUs */ 145 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 146 [VIRT_UART] = { 0x09000000, 0x00001000 }, 147 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 148 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 149 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 150 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 151 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 152 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 153 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 154 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 155 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, 156 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, 157 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 158 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 159 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 160 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 161 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 162 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 163 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 164 /* Actual RAM size depends on initial RAM and device memory settings */ 165 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 166 }; 167 168 /* 169 * Highmem IO Regions: This memory map is floating, located after the RAM. 170 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 171 * top of the RAM, so that its base get the same alignment as the size, 172 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 173 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 174 * Note the extended_memmap is sized so that it eventually also includes the 175 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 176 * index of base_memmap). 177 */ 178 static MemMapEntry extended_memmap[] = { 179 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 180 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 181 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 182 /* Second PCIe window */ 183 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 184 }; 185 186 static const int a15irqmap[] = { 187 [VIRT_UART] = 1, 188 [VIRT_RTC] = 2, 189 [VIRT_PCIE] = 3, /* ... to 6 */ 190 [VIRT_GPIO] = 7, 191 [VIRT_SECURE_UART] = 8, 192 [VIRT_ACPI_GED] = 9, 193 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 194 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 195 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 196 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 197 }; 198 199 static const char *valid_cpus[] = { 200 ARM_CPU_TYPE_NAME("cortex-a7"), 201 ARM_CPU_TYPE_NAME("cortex-a15"), 202 ARM_CPU_TYPE_NAME("cortex-a53"), 203 ARM_CPU_TYPE_NAME("cortex-a57"), 204 ARM_CPU_TYPE_NAME("cortex-a72"), 205 ARM_CPU_TYPE_NAME("host"), 206 ARM_CPU_TYPE_NAME("max"), 207 }; 208 209 static bool cpu_type_valid(const char *cpu) 210 { 211 int i; 212 213 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 214 if (strcmp(cpu, valid_cpus[i]) == 0) { 215 return true; 216 } 217 } 218 return false; 219 } 220 221 static void create_kaslr_seed(MachineState *ms, const char *node) 222 { 223 uint64_t seed; 224 225 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { 226 return; 227 } 228 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed); 229 } 230 231 static void create_fdt(VirtMachineState *vms) 232 { 233 MachineState *ms = MACHINE(vms); 234 int nb_numa_nodes = ms->numa_state->num_nodes; 235 void *fdt = create_device_tree(&vms->fdt_size); 236 237 if (!fdt) { 238 error_report("create_device_tree() failed"); 239 exit(1); 240 } 241 242 ms->fdt = fdt; 243 244 /* Header */ 245 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 246 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 247 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 248 249 /* /chosen must exist for load_dtb to fill in necessary properties later */ 250 qemu_fdt_add_subnode(fdt, "/chosen"); 251 create_kaslr_seed(ms, "/chosen"); 252 253 if (vms->secure) { 254 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 255 create_kaslr_seed(ms, "/secure-chosen"); 256 } 257 258 /* Clock node, for the benefit of the UART. The kernel device tree 259 * binding documentation claims the PL011 node clock properties are 260 * optional but in practice if you omit them the kernel refuses to 261 * probe for the device. 262 */ 263 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 264 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 265 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 266 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 267 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 268 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 269 "clk24mhz"); 270 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 271 272 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 273 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 274 uint32_t *matrix = g_malloc0(size); 275 int idx, i, j; 276 277 for (i = 0; i < nb_numa_nodes; i++) { 278 for (j = 0; j < nb_numa_nodes; j++) { 279 idx = (i * nb_numa_nodes + j) * 3; 280 matrix[idx + 0] = cpu_to_be32(i); 281 matrix[idx + 1] = cpu_to_be32(j); 282 matrix[idx + 2] = 283 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 284 } 285 } 286 287 qemu_fdt_add_subnode(fdt, "/distance-map"); 288 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 289 "numa-distance-map-v1"); 290 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 291 matrix, size); 292 g_free(matrix); 293 } 294 } 295 296 static void fdt_add_timer_nodes(const VirtMachineState *vms) 297 { 298 /* On real hardware these interrupts are level-triggered. 299 * On KVM they were edge-triggered before host kernel version 4.4, 300 * and level-triggered afterwards. 301 * On emulated QEMU they are level-triggered. 302 * 303 * Getting the DTB info about them wrong is awkward for some 304 * guest kernels: 305 * pre-4.8 ignore the DT and leave the interrupt configured 306 * with whatever the GIC reset value (or the bootloader) left it at 307 * 4.8 before rc6 honour the incorrect data by programming it back 308 * into the GIC, causing problems 309 * 4.8rc6 and later ignore the DT and always write "level triggered" 310 * into the GIC 311 * 312 * For backwards-compatibility, virt-2.8 and earlier will continue 313 * to say these are edge-triggered, but later machines will report 314 * the correct information. 315 */ 316 ARMCPU *armcpu; 317 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 318 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 319 MachineState *ms = MACHINE(vms); 320 321 if (vmc->claim_edge_triggered_timers) { 322 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 323 } 324 325 if (vms->gic_version == VIRT_GIC_VERSION_2) { 326 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 327 GIC_FDT_IRQ_PPI_CPU_WIDTH, 328 (1 << MACHINE(vms)->smp.cpus) - 1); 329 } 330 331 qemu_fdt_add_subnode(ms->fdt, "/timer"); 332 333 armcpu = ARM_CPU(qemu_get_cpu(0)); 334 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 335 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 336 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", 337 compat, sizeof(compat)); 338 } else { 339 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", 340 "arm,armv7-timer"); 341 } 342 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); 343 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 344 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 345 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 346 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 347 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 348 } 349 350 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 351 { 352 int cpu; 353 int addr_cells = 1; 354 const MachineState *ms = MACHINE(vms); 355 int smp_cpus = ms->smp.cpus; 356 357 /* 358 * From Documentation/devicetree/bindings/arm/cpus.txt 359 * On ARM v8 64-bit systems value should be set to 2, 360 * that corresponds to the MPIDR_EL1 register size. 361 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 362 * in the system, #address-cells can be set to 1, since 363 * MPIDR_EL1[63:32] bits are not used for CPUs 364 * identification. 365 * 366 * Here we actually don't know whether our system is 32- or 64-bit one. 367 * The simplest way to go is to examine affinity IDs of all our CPUs. If 368 * at least one of them has Aff3 populated, we set #address-cells to 2. 369 */ 370 for (cpu = 0; cpu < smp_cpus; cpu++) { 371 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 372 373 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 374 addr_cells = 2; 375 break; 376 } 377 } 378 379 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 380 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); 381 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 382 383 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 384 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 385 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 386 CPUState *cs = CPU(armcpu); 387 388 qemu_fdt_add_subnode(ms->fdt, nodename); 389 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 390 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 391 armcpu->dtb_compatible); 392 393 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { 394 qemu_fdt_setprop_string(ms->fdt, nodename, 395 "enable-method", "psci"); 396 } 397 398 if (addr_cells == 2) { 399 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", 400 armcpu->mp_affinity); 401 } else { 402 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", 403 armcpu->mp_affinity); 404 } 405 406 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 407 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 408 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 409 } 410 411 g_free(nodename); 412 } 413 } 414 415 static void fdt_add_its_gic_node(VirtMachineState *vms) 416 { 417 char *nodename; 418 MachineState *ms = MACHINE(vms); 419 420 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 421 nodename = g_strdup_printf("/intc/its@%" PRIx64, 422 vms->memmap[VIRT_GIC_ITS].base); 423 qemu_fdt_add_subnode(ms->fdt, nodename); 424 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 425 "arm,gic-v3-its"); 426 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 427 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 428 2, vms->memmap[VIRT_GIC_ITS].base, 429 2, vms->memmap[VIRT_GIC_ITS].size); 430 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 431 g_free(nodename); 432 } 433 434 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 435 { 436 MachineState *ms = MACHINE(vms); 437 char *nodename; 438 439 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 440 vms->memmap[VIRT_GIC_V2M].base); 441 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 442 qemu_fdt_add_subnode(ms->fdt, nodename); 443 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 444 "arm,gic-v2m-frame"); 445 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 446 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 447 2, vms->memmap[VIRT_GIC_V2M].base, 448 2, vms->memmap[VIRT_GIC_V2M].size); 449 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 450 g_free(nodename); 451 } 452 453 static void fdt_add_gic_node(VirtMachineState *vms) 454 { 455 MachineState *ms = MACHINE(vms); 456 char *nodename; 457 458 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 459 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); 460 461 nodename = g_strdup_printf("/intc@%" PRIx64, 462 vms->memmap[VIRT_GIC_DIST].base); 463 qemu_fdt_add_subnode(ms->fdt, nodename); 464 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 465 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 466 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 467 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 468 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 469 if (vms->gic_version == VIRT_GIC_VERSION_3) { 470 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 471 472 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 473 "arm,gic-v3"); 474 475 qemu_fdt_setprop_cell(ms->fdt, nodename, 476 "#redistributor-regions", nb_redist_regions); 477 478 if (nb_redist_regions == 1) { 479 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 480 2, vms->memmap[VIRT_GIC_DIST].base, 481 2, vms->memmap[VIRT_GIC_DIST].size, 482 2, vms->memmap[VIRT_GIC_REDIST].base, 483 2, vms->memmap[VIRT_GIC_REDIST].size); 484 } else { 485 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 486 2, vms->memmap[VIRT_GIC_DIST].base, 487 2, vms->memmap[VIRT_GIC_DIST].size, 488 2, vms->memmap[VIRT_GIC_REDIST].base, 489 2, vms->memmap[VIRT_GIC_REDIST].size, 490 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 491 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 492 } 493 494 if (vms->virt) { 495 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 496 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 497 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 498 } 499 } else { 500 /* 'cortex-a15-gic' means 'GIC v2' */ 501 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 502 "arm,cortex-a15-gic"); 503 if (!vms->virt) { 504 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 505 2, vms->memmap[VIRT_GIC_DIST].base, 506 2, vms->memmap[VIRT_GIC_DIST].size, 507 2, vms->memmap[VIRT_GIC_CPU].base, 508 2, vms->memmap[VIRT_GIC_CPU].size); 509 } else { 510 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 511 2, vms->memmap[VIRT_GIC_DIST].base, 512 2, vms->memmap[VIRT_GIC_DIST].size, 513 2, vms->memmap[VIRT_GIC_CPU].base, 514 2, vms->memmap[VIRT_GIC_CPU].size, 515 2, vms->memmap[VIRT_GIC_HYP].base, 516 2, vms->memmap[VIRT_GIC_HYP].size, 517 2, vms->memmap[VIRT_GIC_VCPU].base, 518 2, vms->memmap[VIRT_GIC_VCPU].size); 519 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 520 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 521 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 522 } 523 } 524 525 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); 526 g_free(nodename); 527 } 528 529 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 530 { 531 ARMCPU *armcpu = ARM_CPU(first_cpu); 532 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 533 MachineState *ms = MACHINE(vms); 534 535 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 536 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); 537 return; 538 } 539 540 if (vms->gic_version == VIRT_GIC_VERSION_2) { 541 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 542 GIC_FDT_IRQ_PPI_CPU_WIDTH, 543 (1 << MACHINE(vms)->smp.cpus) - 1); 544 } 545 546 qemu_fdt_add_subnode(ms->fdt, "/pmu"); 547 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 548 const char compat[] = "arm,armv8-pmuv3"; 549 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", 550 compat, sizeof(compat)); 551 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", 552 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 553 } 554 } 555 556 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 557 { 558 DeviceState *dev; 559 MachineState *ms = MACHINE(vms); 560 int irq = vms->irqmap[VIRT_ACPI_GED]; 561 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 562 563 if (ms->ram_slots) { 564 event |= ACPI_GED_MEM_HOTPLUG_EVT; 565 } 566 567 if (ms->nvdimms_state->is_enabled) { 568 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 569 } 570 571 dev = qdev_new(TYPE_ACPI_GED); 572 qdev_prop_set_uint32(dev, "ged-event", event); 573 574 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 575 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 576 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 577 578 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 579 580 return dev; 581 } 582 583 static void create_its(VirtMachineState *vms) 584 { 585 const char *itsclass = its_class_name(); 586 DeviceState *dev; 587 588 if (!itsclass) { 589 /* Do nothing if not supported */ 590 return; 591 } 592 593 dev = qdev_new(itsclass); 594 595 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 596 &error_abort); 597 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 598 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 599 600 fdt_add_its_gic_node(vms); 601 vms->msi_controller = VIRT_MSI_CTRL_ITS; 602 } 603 604 static void create_v2m(VirtMachineState *vms) 605 { 606 int i; 607 int irq = vms->irqmap[VIRT_GIC_V2M]; 608 DeviceState *dev; 609 610 dev = qdev_new("arm-gicv2m"); 611 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 612 qdev_prop_set_uint32(dev, "base-spi", irq); 613 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 614 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 615 616 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 617 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 618 qdev_get_gpio_in(vms->gic, irq + i)); 619 } 620 621 fdt_add_v2m_gic_node(vms); 622 vms->msi_controller = VIRT_MSI_CTRL_GICV2M; 623 } 624 625 static void create_gic(VirtMachineState *vms) 626 { 627 MachineState *ms = MACHINE(vms); 628 /* We create a standalone GIC */ 629 SysBusDevice *gicbusdev; 630 const char *gictype; 631 int type = vms->gic_version, i; 632 unsigned int smp_cpus = ms->smp.cpus; 633 uint32_t nb_redist_regions = 0; 634 635 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 636 637 vms->gic = qdev_new(gictype); 638 qdev_prop_set_uint32(vms->gic, "revision", type); 639 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 640 /* Note that the num-irq property counts both internal and external 641 * interrupts; there are always 32 of the former (mandated by GIC spec). 642 */ 643 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 644 if (!kvm_irqchip_in_kernel()) { 645 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 646 } 647 648 if (type == 3) { 649 uint32_t redist0_capacity = 650 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 651 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 652 653 nb_redist_regions = virt_gicv3_redist_region_count(vms); 654 655 qdev_prop_set_uint32(vms->gic, "len-redist-region-count", 656 nb_redist_regions); 657 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count); 658 659 if (nb_redist_regions == 2) { 660 uint32_t redist1_capacity = 661 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; 662 663 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", 664 MIN(smp_cpus - redist0_count, redist1_capacity)); 665 } 666 } else { 667 if (!kvm_irqchip_in_kernel()) { 668 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 669 vms->virt); 670 } 671 } 672 gicbusdev = SYS_BUS_DEVICE(vms->gic); 673 sysbus_realize_and_unref(gicbusdev, &error_fatal); 674 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 675 if (type == 3) { 676 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 677 if (nb_redist_regions == 2) { 678 sysbus_mmio_map(gicbusdev, 2, 679 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 680 } 681 } else { 682 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 683 if (vms->virt) { 684 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 685 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 686 } 687 } 688 689 /* Wire the outputs from each CPU's generic timer and the GICv3 690 * maintenance interrupt signal to the appropriate GIC PPI inputs, 691 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 692 */ 693 for (i = 0; i < smp_cpus; i++) { 694 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 695 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 696 int irq; 697 /* Mapping from the output timer irq lines from the CPU to the 698 * GIC PPI inputs we use for the virt board. 699 */ 700 const int timer_irq[] = { 701 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 702 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 703 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 704 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 705 }; 706 707 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 708 qdev_connect_gpio_out(cpudev, irq, 709 qdev_get_gpio_in(vms->gic, 710 ppibase + timer_irq[irq])); 711 } 712 713 if (type == 3) { 714 qemu_irq irq = qdev_get_gpio_in(vms->gic, 715 ppibase + ARCH_GIC_MAINT_IRQ); 716 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 717 0, irq); 718 } else if (vms->virt) { 719 qemu_irq irq = qdev_get_gpio_in(vms->gic, 720 ppibase + ARCH_GIC_MAINT_IRQ); 721 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 722 } 723 724 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 725 qdev_get_gpio_in(vms->gic, ppibase 726 + VIRTUAL_PMU_IRQ)); 727 728 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 729 sysbus_connect_irq(gicbusdev, i + smp_cpus, 730 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 731 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 732 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 733 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 734 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 735 } 736 737 fdt_add_gic_node(vms); 738 739 if (type == 3 && vms->its) { 740 create_its(vms); 741 } else if (type == 2) { 742 create_v2m(vms); 743 } 744 } 745 746 static void create_uart(const VirtMachineState *vms, int uart, 747 MemoryRegion *mem, Chardev *chr) 748 { 749 char *nodename; 750 hwaddr base = vms->memmap[uart].base; 751 hwaddr size = vms->memmap[uart].size; 752 int irq = vms->irqmap[uart]; 753 const char compat[] = "arm,pl011\0arm,primecell"; 754 const char clocknames[] = "uartclk\0apb_pclk"; 755 DeviceState *dev = qdev_new(TYPE_PL011); 756 SysBusDevice *s = SYS_BUS_DEVICE(dev); 757 MachineState *ms = MACHINE(vms); 758 759 qdev_prop_set_chr(dev, "chardev", chr); 760 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 761 memory_region_add_subregion(mem, base, 762 sysbus_mmio_get_region(s, 0)); 763 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 764 765 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 766 qemu_fdt_add_subnode(ms->fdt, nodename); 767 /* Note that we can't use setprop_string because of the embedded NUL */ 768 qemu_fdt_setprop(ms->fdt, nodename, "compatible", 769 compat, sizeof(compat)); 770 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 771 2, base, 2, size); 772 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 773 GIC_FDT_IRQ_TYPE_SPI, irq, 774 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 775 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", 776 vms->clock_phandle, vms->clock_phandle); 777 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", 778 clocknames, sizeof(clocknames)); 779 780 if (uart == VIRT_UART) { 781 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 782 } else { 783 /* Mark as not usable by the normal world */ 784 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 785 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 786 787 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", 788 nodename); 789 } 790 791 g_free(nodename); 792 } 793 794 static void create_rtc(const VirtMachineState *vms) 795 { 796 char *nodename; 797 hwaddr base = vms->memmap[VIRT_RTC].base; 798 hwaddr size = vms->memmap[VIRT_RTC].size; 799 int irq = vms->irqmap[VIRT_RTC]; 800 const char compat[] = "arm,pl031\0arm,primecell"; 801 MachineState *ms = MACHINE(vms); 802 803 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 804 805 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 806 qemu_fdt_add_subnode(ms->fdt, nodename); 807 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 808 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 809 2, base, 2, size); 810 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 811 GIC_FDT_IRQ_TYPE_SPI, irq, 812 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 813 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 814 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 815 g_free(nodename); 816 } 817 818 static DeviceState *gpio_key_dev; 819 static void virt_powerdown_req(Notifier *n, void *opaque) 820 { 821 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 822 823 if (s->acpi_dev) { 824 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 825 } else { 826 /* use gpio Pin 3 for power button event */ 827 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 828 } 829 } 830 831 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, 832 uint32_t phandle) 833 { 834 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 835 qdev_get_gpio_in(pl061_dev, 3)); 836 837 qemu_fdt_add_subnode(fdt, "/gpio-keys"); 838 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); 839 qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#size-cells", 0); 840 qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#address-cells", 1); 841 842 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); 843 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", 844 "label", "GPIO Key Poweroff"); 845 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", 846 KEY_POWER); 847 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", 848 "gpios", phandle, 3, 0); 849 } 850 851 #define SECURE_GPIO_POWEROFF 0 852 #define SECURE_GPIO_RESET 1 853 854 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, 855 uint32_t phandle) 856 { 857 DeviceState *gpio_pwr_dev; 858 859 /* gpio-pwr */ 860 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); 861 862 /* connect secure pl061 to gpio-pwr */ 863 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, 864 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); 865 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, 866 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); 867 868 qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); 869 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", 870 "gpio-poweroff"); 871 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", 872 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); 873 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); 874 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", 875 "okay"); 876 877 qemu_fdt_add_subnode(fdt, "/gpio-restart"); 878 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", 879 "gpio-restart"); 880 qemu_fdt_setprop_cells(fdt, "/gpio-restart", 881 "gpios", phandle, SECURE_GPIO_RESET, 0); 882 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); 883 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", 884 "okay"); 885 } 886 887 static void create_gpio_devices(const VirtMachineState *vms, int gpio, 888 MemoryRegion *mem) 889 { 890 char *nodename; 891 DeviceState *pl061_dev; 892 hwaddr base = vms->memmap[gpio].base; 893 hwaddr size = vms->memmap[gpio].size; 894 int irq = vms->irqmap[gpio]; 895 const char compat[] = "arm,pl061\0arm,primecell"; 896 SysBusDevice *s; 897 MachineState *ms = MACHINE(vms); 898 899 pl061_dev = qdev_new("pl061"); 900 s = SYS_BUS_DEVICE(pl061_dev); 901 sysbus_realize_and_unref(s, &error_fatal); 902 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); 903 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 904 905 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); 906 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 907 qemu_fdt_add_subnode(ms->fdt, nodename); 908 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 909 2, base, 2, size); 910 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 911 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); 912 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); 913 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 914 GIC_FDT_IRQ_TYPE_SPI, irq, 915 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 916 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 917 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 918 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); 919 920 if (gpio != VIRT_GPIO) { 921 /* Mark as not usable by the normal world */ 922 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 923 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 924 } 925 g_free(nodename); 926 927 /* Child gpio devices */ 928 if (gpio == VIRT_GPIO) { 929 create_gpio_keys(ms->fdt, pl061_dev, phandle); 930 } else { 931 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); 932 } 933 } 934 935 static void create_virtio_devices(const VirtMachineState *vms) 936 { 937 int i; 938 hwaddr size = vms->memmap[VIRT_MMIO].size; 939 MachineState *ms = MACHINE(vms); 940 941 /* We create the transports in forwards order. Since qbus_realize() 942 * prepends (not appends) new child buses, the incrementing loop below will 943 * create a list of virtio-mmio buses with decreasing base addresses. 944 * 945 * When a -device option is processed from the command line, 946 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 947 * order. The upshot is that -device options in increasing command line 948 * order are mapped to virtio-mmio buses with decreasing base addresses. 949 * 950 * When this code was originally written, that arrangement ensured that the 951 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 952 * the first -device on the command line. (The end-to-end order is a 953 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 954 * guest kernel's name-to-address assignment strategy.) 955 * 956 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 957 * the message, if not necessarily the code, of commit 70161ff336. 958 * Therefore the loop now establishes the inverse of the original intent. 959 * 960 * Unfortunately, we can't counteract the kernel change by reversing the 961 * loop; it would break existing command lines. 962 * 963 * In any case, the kernel makes no guarantee about the stability of 964 * enumeration order of virtio devices (as demonstrated by it changing 965 * between kernel versions). For reliable and stable identification 966 * of disks users must use UUIDs or similar mechanisms. 967 */ 968 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 969 int irq = vms->irqmap[VIRT_MMIO] + i; 970 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 971 972 sysbus_create_simple("virtio-mmio", base, 973 qdev_get_gpio_in(vms->gic, irq)); 974 } 975 976 /* We add dtb nodes in reverse order so that they appear in the finished 977 * device tree lowest address first. 978 * 979 * Note that this mapping is independent of the loop above. The previous 980 * loop influences virtio device to virtio transport assignment, whereas 981 * this loop controls how virtio transports are laid out in the dtb. 982 */ 983 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 984 char *nodename; 985 int irq = vms->irqmap[VIRT_MMIO] + i; 986 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 987 988 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 989 qemu_fdt_add_subnode(ms->fdt, nodename); 990 qemu_fdt_setprop_string(ms->fdt, nodename, 991 "compatible", "virtio,mmio"); 992 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 993 2, base, 2, size); 994 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 995 GIC_FDT_IRQ_TYPE_SPI, irq, 996 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 997 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 998 g_free(nodename); 999 } 1000 } 1001 1002 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 1003 1004 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 1005 const char *name, 1006 const char *alias_prop_name) 1007 { 1008 /* 1009 * Create a single flash device. We use the same parameters as 1010 * the flash devices on the Versatile Express board. 1011 */ 1012 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 1013 1014 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 1015 qdev_prop_set_uint8(dev, "width", 4); 1016 qdev_prop_set_uint8(dev, "device-width", 2); 1017 qdev_prop_set_bit(dev, "big-endian", false); 1018 qdev_prop_set_uint16(dev, "id0", 0x89); 1019 qdev_prop_set_uint16(dev, "id1", 0x18); 1020 qdev_prop_set_uint16(dev, "id2", 0x00); 1021 qdev_prop_set_uint16(dev, "id3", 0x00); 1022 qdev_prop_set_string(dev, "name", name); 1023 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 1024 object_property_add_alias(OBJECT(vms), alias_prop_name, 1025 OBJECT(dev), "drive"); 1026 return PFLASH_CFI01(dev); 1027 } 1028 1029 static void virt_flash_create(VirtMachineState *vms) 1030 { 1031 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 1032 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 1033 } 1034 1035 static void virt_flash_map1(PFlashCFI01 *flash, 1036 hwaddr base, hwaddr size, 1037 MemoryRegion *sysmem) 1038 { 1039 DeviceState *dev = DEVICE(flash); 1040 1041 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 1042 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 1043 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 1044 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1045 1046 memory_region_add_subregion(sysmem, base, 1047 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1048 0)); 1049 } 1050 1051 static void virt_flash_map(VirtMachineState *vms, 1052 MemoryRegion *sysmem, 1053 MemoryRegion *secure_sysmem) 1054 { 1055 /* 1056 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 1057 * sysmem is the system memory space. secure_sysmem is the secure view 1058 * of the system, and the first flash device should be made visible only 1059 * there. The second flash device is visible to both secure and nonsecure. 1060 * If sysmem == secure_sysmem this means there is no separate Secure 1061 * address space and both flash devices are generally visible. 1062 */ 1063 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1064 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1065 1066 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1067 secure_sysmem); 1068 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1069 sysmem); 1070 } 1071 1072 static void virt_flash_fdt(VirtMachineState *vms, 1073 MemoryRegion *sysmem, 1074 MemoryRegion *secure_sysmem) 1075 { 1076 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1077 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1078 MachineState *ms = MACHINE(vms); 1079 char *nodename; 1080 1081 if (sysmem == secure_sysmem) { 1082 /* Report both flash devices as a single node in the DT */ 1083 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1084 qemu_fdt_add_subnode(ms->fdt, nodename); 1085 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1086 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1087 2, flashbase, 2, flashsize, 1088 2, flashbase + flashsize, 2, flashsize); 1089 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1090 g_free(nodename); 1091 } else { 1092 /* 1093 * Report the devices as separate nodes so we can mark one as 1094 * only visible to the secure world. 1095 */ 1096 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1097 qemu_fdt_add_subnode(ms->fdt, nodename); 1098 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1099 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1100 2, flashbase, 2, flashsize); 1101 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1102 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1103 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1104 g_free(nodename); 1105 1106 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1107 qemu_fdt_add_subnode(ms->fdt, nodename); 1108 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1109 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1110 2, flashbase + flashsize, 2, flashsize); 1111 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1112 g_free(nodename); 1113 } 1114 } 1115 1116 static bool virt_firmware_init(VirtMachineState *vms, 1117 MemoryRegion *sysmem, 1118 MemoryRegion *secure_sysmem) 1119 { 1120 int i; 1121 const char *bios_name; 1122 BlockBackend *pflash_blk0; 1123 1124 /* Map legacy -drive if=pflash to machine properties */ 1125 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1126 pflash_cfi01_legacy_drive(vms->flash[i], 1127 drive_get(IF_PFLASH, 0, i)); 1128 } 1129 1130 virt_flash_map(vms, sysmem, secure_sysmem); 1131 1132 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1133 1134 bios_name = MACHINE(vms)->firmware; 1135 if (bios_name) { 1136 char *fname; 1137 MemoryRegion *mr; 1138 int image_size; 1139 1140 if (pflash_blk0) { 1141 error_report("The contents of the first flash device may be " 1142 "specified with -bios or with -drive if=pflash... " 1143 "but you cannot use both options at once"); 1144 exit(1); 1145 } 1146 1147 /* Fall back to -bios */ 1148 1149 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1150 if (!fname) { 1151 error_report("Could not find ROM image '%s'", bios_name); 1152 exit(1); 1153 } 1154 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1155 image_size = load_image_mr(fname, mr); 1156 g_free(fname); 1157 if (image_size < 0) { 1158 error_report("Could not load ROM image '%s'", bios_name); 1159 exit(1); 1160 } 1161 } 1162 1163 return pflash_blk0 || bios_name; 1164 } 1165 1166 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1167 { 1168 MachineState *ms = MACHINE(vms); 1169 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1170 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1171 FWCfgState *fw_cfg; 1172 char *nodename; 1173 1174 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1175 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1176 1177 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1178 qemu_fdt_add_subnode(ms->fdt, nodename); 1179 qemu_fdt_setprop_string(ms->fdt, nodename, 1180 "compatible", "qemu,fw-cfg-mmio"); 1181 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1182 2, base, 2, size); 1183 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1184 g_free(nodename); 1185 return fw_cfg; 1186 } 1187 1188 static void create_pcie_irq_map(const MachineState *ms, 1189 uint32_t gic_phandle, 1190 int first_irq, const char *nodename) 1191 { 1192 int devfn, pin; 1193 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1194 uint32_t *irq_map = full_irq_map; 1195 1196 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1197 for (pin = 0; pin < 4; pin++) { 1198 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1199 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1200 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1201 int i; 1202 1203 uint32_t map[] = { 1204 devfn << 8, 0, 0, /* devfn */ 1205 pin + 1, /* PCI pin */ 1206 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1207 1208 /* Convert map to big endian */ 1209 for (i = 0; i < 10; i++) { 1210 irq_map[i] = cpu_to_be32(map[i]); 1211 } 1212 irq_map += 10; 1213 } 1214 } 1215 1216 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", 1217 full_irq_map, sizeof(full_irq_map)); 1218 1219 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 1220 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ 1221 0, 0, 1222 0x7 /* PCI irq */); 1223 } 1224 1225 static void create_smmu(const VirtMachineState *vms, 1226 PCIBus *bus) 1227 { 1228 char *node; 1229 const char compat[] = "arm,smmu-v3"; 1230 int irq = vms->irqmap[VIRT_SMMU]; 1231 int i; 1232 hwaddr base = vms->memmap[VIRT_SMMU].base; 1233 hwaddr size = vms->memmap[VIRT_SMMU].size; 1234 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1235 DeviceState *dev; 1236 MachineState *ms = MACHINE(vms); 1237 1238 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1239 return; 1240 } 1241 1242 dev = qdev_new("arm-smmuv3"); 1243 1244 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1245 &error_abort); 1246 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1247 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1248 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1249 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1250 qdev_get_gpio_in(vms->gic, irq + i)); 1251 } 1252 1253 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1254 qemu_fdt_add_subnode(ms->fdt, node); 1255 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1256 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); 1257 1258 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", 1259 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1260 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1261 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1262 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1263 1264 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, 1265 sizeof(irq_names)); 1266 1267 qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle); 1268 qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk"); 1269 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); 1270 1271 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1272 1273 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1274 g_free(node); 1275 } 1276 1277 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1278 { 1279 const char compat[] = "virtio,pci-iommu"; 1280 uint16_t bdf = vms->virtio_iommu_bdf; 1281 MachineState *ms = MACHINE(vms); 1282 char *node; 1283 1284 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1285 1286 node = g_strdup_printf("%s/virtio_iommu@%d", vms->pciehb_nodename, bdf); 1287 qemu_fdt_add_subnode(ms->fdt, node); 1288 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1289 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 1290 1, bdf << 8, 1, 0, 1, 0, 1291 1, 0, 1, 0); 1292 1293 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1294 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1295 g_free(node); 1296 1297 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", 1298 0x0, vms->iommu_phandle, 0x0, bdf, 1299 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1300 } 1301 1302 static void create_pcie(VirtMachineState *vms) 1303 { 1304 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1305 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1306 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1307 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1308 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1309 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1310 hwaddr base_ecam, size_ecam; 1311 hwaddr base = base_mmio; 1312 int nr_pcie_buses; 1313 int irq = vms->irqmap[VIRT_PCIE]; 1314 MemoryRegion *mmio_alias; 1315 MemoryRegion *mmio_reg; 1316 MemoryRegion *ecam_alias; 1317 MemoryRegion *ecam_reg; 1318 DeviceState *dev; 1319 char *nodename; 1320 int i, ecam_id; 1321 PCIHostState *pci; 1322 MachineState *ms = MACHINE(vms); 1323 1324 dev = qdev_new(TYPE_GPEX_HOST); 1325 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1326 1327 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1328 base_ecam = vms->memmap[ecam_id].base; 1329 size_ecam = vms->memmap[ecam_id].size; 1330 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1331 /* Map only the first size_ecam bytes of ECAM space */ 1332 ecam_alias = g_new0(MemoryRegion, 1); 1333 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1334 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1335 ecam_reg, 0, size_ecam); 1336 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1337 1338 /* Map the MMIO window into system address space so as to expose 1339 * the section of PCI MMIO space which starts at the same base address 1340 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1341 * the window). 1342 */ 1343 mmio_alias = g_new0(MemoryRegion, 1); 1344 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1345 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1346 mmio_reg, base_mmio, size_mmio); 1347 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1348 1349 if (vms->highmem) { 1350 /* Map high MMIO space */ 1351 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1352 1353 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1354 mmio_reg, base_mmio_high, size_mmio_high); 1355 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1356 high_mmio_alias); 1357 } 1358 1359 /* Map IO port space */ 1360 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1361 1362 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1363 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1364 qdev_get_gpio_in(vms->gic, irq + i)); 1365 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1366 } 1367 1368 pci = PCI_HOST_BRIDGE(dev); 1369 vms->bus = pci->bus; 1370 if (vms->bus) { 1371 for (i = 0; i < nb_nics; i++) { 1372 NICInfo *nd = &nd_table[i]; 1373 1374 if (!nd->model) { 1375 nd->model = g_strdup("virtio"); 1376 } 1377 1378 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1379 } 1380 } 1381 1382 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1383 qemu_fdt_add_subnode(ms->fdt, nodename); 1384 qemu_fdt_setprop_string(ms->fdt, nodename, 1385 "compatible", "pci-host-ecam-generic"); 1386 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 1387 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 1388 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 1389 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 1390 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 1391 nr_pcie_buses - 1); 1392 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1393 1394 if (vms->msi_phandle) { 1395 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent", 1396 vms->msi_phandle); 1397 } 1398 1399 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1400 2, base_ecam, 2, size_ecam); 1401 1402 if (vms->highmem) { 1403 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1404 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1405 2, base_pio, 2, size_pio, 1406 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1407 2, base_mmio, 2, size_mmio, 1408 1, FDT_PCI_RANGE_MMIO_64BIT, 1409 2, base_mmio_high, 1410 2, base_mmio_high, 2, size_mmio_high); 1411 } else { 1412 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1413 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1414 2, base_pio, 2, size_pio, 1415 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1416 2, base_mmio, 2, size_mmio); 1417 } 1418 1419 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 1420 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); 1421 1422 if (vms->iommu) { 1423 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1424 1425 switch (vms->iommu) { 1426 case VIRT_IOMMU_SMMUV3: 1427 create_smmu(vms, vms->bus); 1428 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 1429 0x0, vms->iommu_phandle, 0x0, 0x10000); 1430 break; 1431 default: 1432 g_assert_not_reached(); 1433 } 1434 } 1435 } 1436 1437 static void create_platform_bus(VirtMachineState *vms) 1438 { 1439 DeviceState *dev; 1440 SysBusDevice *s; 1441 int i; 1442 MemoryRegion *sysmem = get_system_memory(); 1443 1444 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1445 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1446 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1447 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1448 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1449 vms->platform_bus_dev = dev; 1450 1451 s = SYS_BUS_DEVICE(dev); 1452 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1453 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1454 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1455 } 1456 1457 memory_region_add_subregion(sysmem, 1458 vms->memmap[VIRT_PLATFORM_BUS].base, 1459 sysbus_mmio_get_region(s, 0)); 1460 } 1461 1462 static void create_tag_ram(MemoryRegion *tag_sysmem, 1463 hwaddr base, hwaddr size, 1464 const char *name) 1465 { 1466 MemoryRegion *tagram = g_new(MemoryRegion, 1); 1467 1468 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); 1469 memory_region_add_subregion(tag_sysmem, base / 32, tagram); 1470 } 1471 1472 static void create_secure_ram(VirtMachineState *vms, 1473 MemoryRegion *secure_sysmem, 1474 MemoryRegion *secure_tag_sysmem) 1475 { 1476 MemoryRegion *secram = g_new(MemoryRegion, 1); 1477 char *nodename; 1478 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1479 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1480 MachineState *ms = MACHINE(vms); 1481 1482 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1483 &error_fatal); 1484 memory_region_add_subregion(secure_sysmem, base, secram); 1485 1486 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1487 qemu_fdt_add_subnode(ms->fdt, nodename); 1488 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 1489 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 1490 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1491 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1492 1493 if (secure_tag_sysmem) { 1494 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); 1495 } 1496 1497 g_free(nodename); 1498 } 1499 1500 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1501 { 1502 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1503 bootinfo); 1504 MachineState *ms = MACHINE(board); 1505 1506 1507 *fdt_size = board->fdt_size; 1508 return ms->fdt; 1509 } 1510 1511 static void virt_build_smbios(VirtMachineState *vms) 1512 { 1513 MachineClass *mc = MACHINE_GET_CLASS(vms); 1514 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1515 uint8_t *smbios_tables, *smbios_anchor; 1516 size_t smbios_tables_len, smbios_anchor_len; 1517 const char *product = "QEMU Virtual Machine"; 1518 1519 if (kvm_enabled()) { 1520 product = "KVM Virtual Machine"; 1521 } 1522 1523 smbios_set_defaults("QEMU", product, 1524 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1525 true, SMBIOS_ENTRY_POINT_30); 1526 1527 smbios_get_tables(MACHINE(vms), NULL, 0, &smbios_tables, &smbios_tables_len, 1528 &smbios_anchor, &smbios_anchor_len); 1529 1530 if (smbios_anchor) { 1531 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1532 smbios_tables, smbios_tables_len); 1533 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1534 smbios_anchor, smbios_anchor_len); 1535 } 1536 } 1537 1538 static 1539 void virt_machine_done(Notifier *notifier, void *data) 1540 { 1541 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1542 machine_done); 1543 MachineState *ms = MACHINE(vms); 1544 ARMCPU *cpu = ARM_CPU(first_cpu); 1545 struct arm_boot_info *info = &vms->bootinfo; 1546 AddressSpace *as = arm_boot_address_space(cpu, info); 1547 1548 /* 1549 * If the user provided a dtb, we assume the dynamic sysbus nodes 1550 * already are integrated there. This corresponds to a use case where 1551 * the dynamic sysbus nodes are complex and their generation is not yet 1552 * supported. In that case the user can take charge of the guest dt 1553 * while qemu takes charge of the qom stuff. 1554 */ 1555 if (info->dtb_filename == NULL) { 1556 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", 1557 vms->memmap[VIRT_PLATFORM_BUS].base, 1558 vms->memmap[VIRT_PLATFORM_BUS].size, 1559 vms->irqmap[VIRT_PLATFORM_BUS]); 1560 } 1561 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1562 exit(1); 1563 } 1564 1565 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg); 1566 1567 virt_acpi_setup(vms); 1568 virt_build_smbios(vms); 1569 } 1570 1571 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1572 { 1573 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1574 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1575 1576 if (!vmc->disallow_affinity_adjustment) { 1577 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1578 * GIC's target-list limitations. 32-bit KVM hosts currently 1579 * always create clusters of 4 CPUs, but that is expected to 1580 * change when they gain support for gicv3. When KVM is enabled 1581 * it will override the changes we make here, therefore our 1582 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1583 * and to improve SGI efficiency. 1584 */ 1585 if (vms->gic_version == VIRT_GIC_VERSION_3) { 1586 clustersz = GICV3_TARGETLIST_BITS; 1587 } else { 1588 clustersz = GIC_TARGETLIST_BITS; 1589 } 1590 } 1591 return arm_cpu_mp_affinity(idx, clustersz); 1592 } 1593 1594 static void virt_set_memmap(VirtMachineState *vms) 1595 { 1596 MachineState *ms = MACHINE(vms); 1597 hwaddr base, device_memory_base, device_memory_size; 1598 int i; 1599 1600 vms->memmap = extended_memmap; 1601 1602 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1603 vms->memmap[i] = base_memmap[i]; 1604 } 1605 1606 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1607 error_report("unsupported number of memory slots: %"PRIu64, 1608 ms->ram_slots); 1609 exit(EXIT_FAILURE); 1610 } 1611 1612 /* 1613 * We compute the base of the high IO region depending on the 1614 * amount of initial and device memory. The device memory start/size 1615 * is aligned on 1GiB. We never put the high IO region below 256GiB 1616 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1617 * The device region size assumes 1GiB page max alignment per slot. 1618 */ 1619 device_memory_base = 1620 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1621 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1622 1623 /* Base address of the high IO region */ 1624 base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1625 if (base < device_memory_base) { 1626 error_report("maxmem/slots too huge"); 1627 exit(EXIT_FAILURE); 1628 } 1629 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1630 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1631 } 1632 1633 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1634 hwaddr size = extended_memmap[i].size; 1635 1636 base = ROUND_UP(base, size); 1637 vms->memmap[i].base = base; 1638 vms->memmap[i].size = size; 1639 base += size; 1640 } 1641 vms->highest_gpa = base - 1; 1642 if (device_memory_size > 0) { 1643 ms->device_memory = g_malloc0(sizeof(*ms->device_memory)); 1644 ms->device_memory->base = device_memory_base; 1645 memory_region_init(&ms->device_memory->mr, OBJECT(vms), 1646 "device-memory", device_memory_size); 1647 } 1648 } 1649 1650 /* 1651 * finalize_gic_version - Determines the final gic_version 1652 * according to the gic-version property 1653 * 1654 * Default GIC type is v2 1655 */ 1656 static void finalize_gic_version(VirtMachineState *vms) 1657 { 1658 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 1659 1660 if (kvm_enabled()) { 1661 int probe_bitmap; 1662 1663 if (!kvm_irqchip_in_kernel()) { 1664 switch (vms->gic_version) { 1665 case VIRT_GIC_VERSION_HOST: 1666 warn_report( 1667 "gic-version=host not relevant with kernel-irqchip=off " 1668 "as only userspace GICv2 is supported. Using v2 ..."); 1669 return; 1670 case VIRT_GIC_VERSION_MAX: 1671 case VIRT_GIC_VERSION_NOSEL: 1672 vms->gic_version = VIRT_GIC_VERSION_2; 1673 return; 1674 case VIRT_GIC_VERSION_2: 1675 return; 1676 case VIRT_GIC_VERSION_3: 1677 error_report( 1678 "gic-version=3 is not supported with kernel-irqchip=off"); 1679 exit(1); 1680 } 1681 } 1682 1683 probe_bitmap = kvm_arm_vgic_probe(); 1684 if (!probe_bitmap) { 1685 error_report("Unable to determine GIC version supported by host"); 1686 exit(1); 1687 } 1688 1689 switch (vms->gic_version) { 1690 case VIRT_GIC_VERSION_HOST: 1691 case VIRT_GIC_VERSION_MAX: 1692 if (probe_bitmap & KVM_ARM_VGIC_V3) { 1693 vms->gic_version = VIRT_GIC_VERSION_3; 1694 } else { 1695 vms->gic_version = VIRT_GIC_VERSION_2; 1696 } 1697 return; 1698 case VIRT_GIC_VERSION_NOSEL: 1699 if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) { 1700 vms->gic_version = VIRT_GIC_VERSION_2; 1701 } else if (probe_bitmap & KVM_ARM_VGIC_V3) { 1702 /* 1703 * in case the host does not support v2 in-kernel emulation or 1704 * the end-user requested more than 8 VCPUs we now default 1705 * to v3. In any case defaulting to v2 would be broken. 1706 */ 1707 vms->gic_version = VIRT_GIC_VERSION_3; 1708 } else if (max_cpus > GIC_NCPU) { 1709 error_report("host only supports in-kernel GICv2 emulation " 1710 "but more than 8 vcpus are requested"); 1711 exit(1); 1712 } 1713 break; 1714 case VIRT_GIC_VERSION_2: 1715 case VIRT_GIC_VERSION_3: 1716 break; 1717 } 1718 1719 /* Check chosen version is effectively supported by the host */ 1720 if (vms->gic_version == VIRT_GIC_VERSION_2 && 1721 !(probe_bitmap & KVM_ARM_VGIC_V2)) { 1722 error_report("host does not support in-kernel GICv2 emulation"); 1723 exit(1); 1724 } else if (vms->gic_version == VIRT_GIC_VERSION_3 && 1725 !(probe_bitmap & KVM_ARM_VGIC_V3)) { 1726 error_report("host does not support in-kernel GICv3 emulation"); 1727 exit(1); 1728 } 1729 return; 1730 } 1731 1732 /* TCG mode */ 1733 switch (vms->gic_version) { 1734 case VIRT_GIC_VERSION_NOSEL: 1735 vms->gic_version = VIRT_GIC_VERSION_2; 1736 break; 1737 case VIRT_GIC_VERSION_MAX: 1738 vms->gic_version = VIRT_GIC_VERSION_3; 1739 break; 1740 case VIRT_GIC_VERSION_HOST: 1741 error_report("gic-version=host requires KVM"); 1742 exit(1); 1743 case VIRT_GIC_VERSION_2: 1744 case VIRT_GIC_VERSION_3: 1745 break; 1746 } 1747 } 1748 1749 /* 1750 * virt_cpu_post_init() must be called after the CPUs have 1751 * been realized and the GIC has been created. 1752 */ 1753 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) 1754 { 1755 int max_cpus = MACHINE(vms)->smp.max_cpus; 1756 bool aarch64, pmu, steal_time; 1757 CPUState *cpu; 1758 1759 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); 1760 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); 1761 steal_time = object_property_get_bool(OBJECT(first_cpu), 1762 "kvm-steal-time", NULL); 1763 1764 if (kvm_enabled()) { 1765 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; 1766 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; 1767 1768 if (steal_time) { 1769 MemoryRegion *pvtime = g_new(MemoryRegion, 1); 1770 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; 1771 1772 /* The memory region size must be a multiple of host page size. */ 1773 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); 1774 1775 if (pvtime_size > pvtime_reg_size) { 1776 error_report("pvtime requires a %" HWADDR_PRId 1777 " byte memory region for %d CPUs," 1778 " but only %" HWADDR_PRId " has been reserved", 1779 pvtime_size, max_cpus, pvtime_reg_size); 1780 exit(1); 1781 } 1782 1783 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); 1784 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); 1785 } 1786 1787 CPU_FOREACH(cpu) { 1788 if (pmu) { 1789 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); 1790 if (kvm_irqchip_in_kernel()) { 1791 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); 1792 } 1793 kvm_arm_pmu_init(cpu); 1794 } 1795 if (steal_time) { 1796 kvm_arm_pvtime_init(cpu, pvtime_reg_base + 1797 cpu->cpu_index * PVTIME_SIZE_PER_CPU); 1798 } 1799 } 1800 } else { 1801 if (aarch64 && vms->highmem) { 1802 int requested_pa_size = 64 - clz64(vms->highest_gpa); 1803 int pamax = arm_pamax(ARM_CPU(first_cpu)); 1804 1805 if (pamax < requested_pa_size) { 1806 error_report("VCPU supports less PA bits (%d) than " 1807 "requested by the memory map (%d)", 1808 pamax, requested_pa_size); 1809 exit(1); 1810 } 1811 } 1812 } 1813 } 1814 1815 static void machvirt_init(MachineState *machine) 1816 { 1817 VirtMachineState *vms = VIRT_MACHINE(machine); 1818 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1819 MachineClass *mc = MACHINE_GET_CLASS(machine); 1820 const CPUArchIdList *possible_cpus; 1821 MemoryRegion *sysmem = get_system_memory(); 1822 MemoryRegion *secure_sysmem = NULL; 1823 MemoryRegion *tag_sysmem = NULL; 1824 MemoryRegion *secure_tag_sysmem = NULL; 1825 int n, virt_max_cpus; 1826 bool firmware_loaded; 1827 bool aarch64 = true; 1828 bool has_ged = !vmc->no_ged; 1829 unsigned int smp_cpus = machine->smp.cpus; 1830 unsigned int max_cpus = machine->smp.max_cpus; 1831 1832 /* 1833 * In accelerated mode, the memory map is computed earlier in kvm_type() 1834 * to create a VM with the right number of IPA bits. 1835 */ 1836 if (!vms->memmap) { 1837 virt_set_memmap(vms); 1838 } 1839 1840 /* We can probe only here because during property set 1841 * KVM is not available yet 1842 */ 1843 finalize_gic_version(vms); 1844 1845 if (!cpu_type_valid(machine->cpu_type)) { 1846 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 1847 exit(1); 1848 } 1849 1850 if (vms->secure) { 1851 if (kvm_enabled()) { 1852 error_report("mach-virt: KVM does not support Security extensions"); 1853 exit(1); 1854 } 1855 1856 /* 1857 * The Secure view of the world is the same as the NonSecure, 1858 * but with a few extra devices. Create it as a container region 1859 * containing the system memory at low priority; any secure-only 1860 * devices go in at higher priority and take precedence. 1861 */ 1862 secure_sysmem = g_new(MemoryRegion, 1); 1863 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1864 UINT64_MAX); 1865 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1866 } 1867 1868 firmware_loaded = virt_firmware_init(vms, sysmem, 1869 secure_sysmem ?: sysmem); 1870 1871 /* If we have an EL3 boot ROM then the assumption is that it will 1872 * implement PSCI itself, so disable QEMU's internal implementation 1873 * so it doesn't get in the way. Instead of starting secondary 1874 * CPUs in PSCI powerdown state we will start them all running and 1875 * let the boot ROM sort them out. 1876 * The usual case is that we do use QEMU's PSCI implementation; 1877 * if the guest has EL2 then we will use SMC as the conduit, 1878 * and otherwise we will use HVC (for backwards compatibility and 1879 * because if we're using KVM then we must use HVC). 1880 */ 1881 if (vms->secure && firmware_loaded) { 1882 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1883 } else if (vms->virt) { 1884 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 1885 } else { 1886 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 1887 } 1888 1889 /* The maximum number of CPUs depends on the GIC version, or on how 1890 * many redistributors we can fit into the memory map. 1891 */ 1892 if (vms->gic_version == VIRT_GIC_VERSION_3) { 1893 virt_max_cpus = 1894 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; 1895 virt_max_cpus += 1896 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; 1897 } else { 1898 virt_max_cpus = GIC_NCPU; 1899 } 1900 1901 if (max_cpus > virt_max_cpus) { 1902 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1903 "supported by machine 'mach-virt' (%d)", 1904 max_cpus, virt_max_cpus); 1905 exit(1); 1906 } 1907 1908 if (vms->virt && kvm_enabled()) { 1909 error_report("mach-virt: KVM does not support providing " 1910 "Virtualization extensions to the guest CPU"); 1911 exit(1); 1912 } 1913 1914 if (vms->mte && kvm_enabled()) { 1915 error_report("mach-virt: KVM does not support providing " 1916 "MTE to the guest CPU"); 1917 exit(1); 1918 } 1919 1920 create_fdt(vms); 1921 1922 possible_cpus = mc->possible_cpu_arch_ids(machine); 1923 assert(possible_cpus->len == max_cpus); 1924 for (n = 0; n < possible_cpus->len; n++) { 1925 Object *cpuobj; 1926 CPUState *cs; 1927 1928 if (n >= smp_cpus) { 1929 break; 1930 } 1931 1932 cpuobj = object_new(possible_cpus->cpus[n].type); 1933 object_property_set_int(cpuobj, "mp-affinity", 1934 possible_cpus->cpus[n].arch_id, NULL); 1935 1936 cs = CPU(cpuobj); 1937 cs->cpu_index = n; 1938 1939 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 1940 &error_fatal); 1941 1942 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 1943 1944 if (!vms->secure) { 1945 object_property_set_bool(cpuobj, "has_el3", false, NULL); 1946 } 1947 1948 if (!vms->virt && object_property_find(cpuobj, "has_el2")) { 1949 object_property_set_bool(cpuobj, "has_el2", false, NULL); 1950 } 1951 1952 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1953 object_property_set_int(cpuobj, "psci-conduit", vms->psci_conduit, 1954 NULL); 1955 1956 /* Secondary CPUs start in PSCI powered-down state */ 1957 if (n > 0) { 1958 object_property_set_bool(cpuobj, "start-powered-off", true, 1959 NULL); 1960 } 1961 } 1962 1963 if (vmc->kvm_no_adjvtime && 1964 object_property_find(cpuobj, "kvm-no-adjvtime")) { 1965 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 1966 } 1967 1968 if (vmc->no_kvm_steal_time && 1969 object_property_find(cpuobj, "kvm-steal-time")) { 1970 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); 1971 } 1972 1973 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { 1974 object_property_set_bool(cpuobj, "pmu", false, NULL); 1975 } 1976 1977 if (object_property_find(cpuobj, "reset-cbar")) { 1978 object_property_set_int(cpuobj, "reset-cbar", 1979 vms->memmap[VIRT_CPUPERIPHS].base, 1980 &error_abort); 1981 } 1982 1983 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 1984 &error_abort); 1985 if (vms->secure) { 1986 object_property_set_link(cpuobj, "secure-memory", 1987 OBJECT(secure_sysmem), &error_abort); 1988 } 1989 1990 if (vms->mte) { 1991 /* Create the memory region only once, but link to all cpus. */ 1992 if (!tag_sysmem) { 1993 /* 1994 * The property exists only if MemTag is supported. 1995 * If it is, we must allocate the ram to back that up. 1996 */ 1997 if (!object_property_find(cpuobj, "tag-memory")) { 1998 error_report("MTE requested, but not supported " 1999 "by the guest CPU"); 2000 exit(1); 2001 } 2002 2003 tag_sysmem = g_new(MemoryRegion, 1); 2004 memory_region_init(tag_sysmem, OBJECT(machine), 2005 "tag-memory", UINT64_MAX / 32); 2006 2007 if (vms->secure) { 2008 secure_tag_sysmem = g_new(MemoryRegion, 1); 2009 memory_region_init(secure_tag_sysmem, OBJECT(machine), 2010 "secure-tag-memory", UINT64_MAX / 32); 2011 2012 /* As with ram, secure-tag takes precedence over tag. */ 2013 memory_region_add_subregion_overlap(secure_tag_sysmem, 0, 2014 tag_sysmem, -1); 2015 } 2016 } 2017 2018 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem), 2019 &error_abort); 2020 if (vms->secure) { 2021 object_property_set_link(cpuobj, "secure-tag-memory", 2022 OBJECT(secure_tag_sysmem), 2023 &error_abort); 2024 } 2025 } 2026 2027 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 2028 object_unref(cpuobj); 2029 } 2030 fdt_add_timer_nodes(vms); 2031 fdt_add_cpu_nodes(vms); 2032 2033 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 2034 machine->ram); 2035 if (machine->device_memory) { 2036 memory_region_add_subregion(sysmem, machine->device_memory->base, 2037 &machine->device_memory->mr); 2038 } 2039 2040 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 2041 2042 create_gic(vms); 2043 2044 virt_cpu_post_init(vms, sysmem); 2045 2046 fdt_add_pmu_nodes(vms); 2047 2048 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 2049 2050 if (vms->secure) { 2051 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); 2052 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 2053 } 2054 2055 if (tag_sysmem) { 2056 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, 2057 machine->ram_size, "mach-virt.tag"); 2058 } 2059 2060 vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64); 2061 2062 create_rtc(vms); 2063 2064 create_pcie(vms); 2065 2066 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 2067 vms->acpi_dev = create_acpi_ged(vms); 2068 } else { 2069 create_gpio_devices(vms, VIRT_GPIO, sysmem); 2070 } 2071 2072 if (vms->secure && !vmc->no_secure_gpio) { 2073 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); 2074 } 2075 2076 /* connect powerdown request */ 2077 vms->powerdown_notifier.notify = virt_powerdown_req; 2078 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 2079 2080 /* Create mmio transports, so the user can create virtio backends 2081 * (which will be automatically plugged in to the transports). If 2082 * no backend is created the transport will just sit harmlessly idle. 2083 */ 2084 create_virtio_devices(vms); 2085 2086 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 2087 rom_set_fw(vms->fw_cfg); 2088 2089 create_platform_bus(vms); 2090 2091 if (machine->nvdimms_state->is_enabled) { 2092 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 2093 .space_id = AML_AS_SYSTEM_MEMORY, 2094 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 2095 .bit_width = NVDIMM_ACPI_IO_LEN << 3 2096 }; 2097 2098 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 2099 arm_virt_nvdimm_acpi_dsmio, 2100 vms->fw_cfg, OBJECT(vms)); 2101 } 2102 2103 vms->bootinfo.ram_size = machine->ram_size; 2104 vms->bootinfo.nb_cpus = smp_cpus; 2105 vms->bootinfo.board_id = -1; 2106 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 2107 vms->bootinfo.get_dtb = machvirt_dtb; 2108 vms->bootinfo.skip_dtb_autoload = true; 2109 vms->bootinfo.firmware_loaded = firmware_loaded; 2110 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 2111 2112 vms->machine_done.notify = virt_machine_done; 2113 qemu_add_machine_init_done_notifier(&vms->machine_done); 2114 } 2115 2116 static bool virt_get_secure(Object *obj, Error **errp) 2117 { 2118 VirtMachineState *vms = VIRT_MACHINE(obj); 2119 2120 return vms->secure; 2121 } 2122 2123 static void virt_set_secure(Object *obj, bool value, Error **errp) 2124 { 2125 VirtMachineState *vms = VIRT_MACHINE(obj); 2126 2127 vms->secure = value; 2128 } 2129 2130 static bool virt_get_virt(Object *obj, Error **errp) 2131 { 2132 VirtMachineState *vms = VIRT_MACHINE(obj); 2133 2134 return vms->virt; 2135 } 2136 2137 static void virt_set_virt(Object *obj, bool value, Error **errp) 2138 { 2139 VirtMachineState *vms = VIRT_MACHINE(obj); 2140 2141 vms->virt = value; 2142 } 2143 2144 static bool virt_get_highmem(Object *obj, Error **errp) 2145 { 2146 VirtMachineState *vms = VIRT_MACHINE(obj); 2147 2148 return vms->highmem; 2149 } 2150 2151 static void virt_set_highmem(Object *obj, bool value, Error **errp) 2152 { 2153 VirtMachineState *vms = VIRT_MACHINE(obj); 2154 2155 vms->highmem = value; 2156 } 2157 2158 static bool virt_get_its(Object *obj, Error **errp) 2159 { 2160 VirtMachineState *vms = VIRT_MACHINE(obj); 2161 2162 return vms->its; 2163 } 2164 2165 static void virt_set_its(Object *obj, bool value, Error **errp) 2166 { 2167 VirtMachineState *vms = VIRT_MACHINE(obj); 2168 2169 vms->its = value; 2170 } 2171 2172 static char *virt_get_oem_id(Object *obj, Error **errp) 2173 { 2174 VirtMachineState *vms = VIRT_MACHINE(obj); 2175 2176 return g_strdup(vms->oem_id); 2177 } 2178 2179 static void virt_set_oem_id(Object *obj, const char *value, Error **errp) 2180 { 2181 VirtMachineState *vms = VIRT_MACHINE(obj); 2182 size_t len = strlen(value); 2183 2184 if (len > 6) { 2185 error_setg(errp, 2186 "User specified oem-id value is bigger than 6 bytes in size"); 2187 return; 2188 } 2189 2190 strncpy(vms->oem_id, value, 6); 2191 } 2192 2193 static char *virt_get_oem_table_id(Object *obj, Error **errp) 2194 { 2195 VirtMachineState *vms = VIRT_MACHINE(obj); 2196 2197 return g_strdup(vms->oem_table_id); 2198 } 2199 2200 static void virt_set_oem_table_id(Object *obj, const char *value, 2201 Error **errp) 2202 { 2203 VirtMachineState *vms = VIRT_MACHINE(obj); 2204 size_t len = strlen(value); 2205 2206 if (len > 8) { 2207 error_setg(errp, 2208 "User specified oem-table-id value is bigger than 8 bytes in size"); 2209 return; 2210 } 2211 strncpy(vms->oem_table_id, value, 8); 2212 } 2213 2214 2215 bool virt_is_acpi_enabled(VirtMachineState *vms) 2216 { 2217 if (vms->acpi == ON_OFF_AUTO_OFF) { 2218 return false; 2219 } 2220 return true; 2221 } 2222 2223 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 2224 void *opaque, Error **errp) 2225 { 2226 VirtMachineState *vms = VIRT_MACHINE(obj); 2227 OnOffAuto acpi = vms->acpi; 2228 2229 visit_type_OnOffAuto(v, name, &acpi, errp); 2230 } 2231 2232 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 2233 void *opaque, Error **errp) 2234 { 2235 VirtMachineState *vms = VIRT_MACHINE(obj); 2236 2237 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 2238 } 2239 2240 static bool virt_get_ras(Object *obj, Error **errp) 2241 { 2242 VirtMachineState *vms = VIRT_MACHINE(obj); 2243 2244 return vms->ras; 2245 } 2246 2247 static void virt_set_ras(Object *obj, bool value, Error **errp) 2248 { 2249 VirtMachineState *vms = VIRT_MACHINE(obj); 2250 2251 vms->ras = value; 2252 } 2253 2254 static bool virt_get_mte(Object *obj, Error **errp) 2255 { 2256 VirtMachineState *vms = VIRT_MACHINE(obj); 2257 2258 return vms->mte; 2259 } 2260 2261 static void virt_set_mte(Object *obj, bool value, Error **errp) 2262 { 2263 VirtMachineState *vms = VIRT_MACHINE(obj); 2264 2265 vms->mte = value; 2266 } 2267 2268 static char *virt_get_gic_version(Object *obj, Error **errp) 2269 { 2270 VirtMachineState *vms = VIRT_MACHINE(obj); 2271 const char *val = vms->gic_version == VIRT_GIC_VERSION_3 ? "3" : "2"; 2272 2273 return g_strdup(val); 2274 } 2275 2276 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2277 { 2278 VirtMachineState *vms = VIRT_MACHINE(obj); 2279 2280 if (!strcmp(value, "3")) { 2281 vms->gic_version = VIRT_GIC_VERSION_3; 2282 } else if (!strcmp(value, "2")) { 2283 vms->gic_version = VIRT_GIC_VERSION_2; 2284 } else if (!strcmp(value, "host")) { 2285 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2286 } else if (!strcmp(value, "max")) { 2287 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2288 } else { 2289 error_setg(errp, "Invalid gic-version value"); 2290 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2291 } 2292 } 2293 2294 static char *virt_get_iommu(Object *obj, Error **errp) 2295 { 2296 VirtMachineState *vms = VIRT_MACHINE(obj); 2297 2298 switch (vms->iommu) { 2299 case VIRT_IOMMU_NONE: 2300 return g_strdup("none"); 2301 case VIRT_IOMMU_SMMUV3: 2302 return g_strdup("smmuv3"); 2303 default: 2304 g_assert_not_reached(); 2305 } 2306 } 2307 2308 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2309 { 2310 VirtMachineState *vms = VIRT_MACHINE(obj); 2311 2312 if (!strcmp(value, "smmuv3")) { 2313 vms->iommu = VIRT_IOMMU_SMMUV3; 2314 } else if (!strcmp(value, "none")) { 2315 vms->iommu = VIRT_IOMMU_NONE; 2316 } else { 2317 error_setg(errp, "Invalid iommu value"); 2318 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2319 } 2320 } 2321 2322 static CpuInstanceProperties 2323 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2324 { 2325 MachineClass *mc = MACHINE_GET_CLASS(ms); 2326 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2327 2328 assert(cpu_index < possible_cpus->len); 2329 return possible_cpus->cpus[cpu_index].props; 2330 } 2331 2332 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2333 { 2334 return idx % ms->numa_state->num_nodes; 2335 } 2336 2337 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2338 { 2339 int n; 2340 unsigned int max_cpus = ms->smp.max_cpus; 2341 VirtMachineState *vms = VIRT_MACHINE(ms); 2342 2343 if (ms->possible_cpus) { 2344 assert(ms->possible_cpus->len == max_cpus); 2345 return ms->possible_cpus; 2346 } 2347 2348 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2349 sizeof(CPUArchId) * max_cpus); 2350 ms->possible_cpus->len = max_cpus; 2351 for (n = 0; n < ms->possible_cpus->len; n++) { 2352 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2353 ms->possible_cpus->cpus[n].arch_id = 2354 virt_cpu_mp_affinity(vms, n); 2355 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2356 ms->possible_cpus->cpus[n].props.thread_id = n; 2357 } 2358 return ms->possible_cpus; 2359 } 2360 2361 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2362 Error **errp) 2363 { 2364 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2365 const MachineState *ms = MACHINE(hotplug_dev); 2366 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2367 2368 if (!vms->acpi_dev) { 2369 error_setg(errp, 2370 "memory hotplug is not enabled: missing acpi-ged device"); 2371 return; 2372 } 2373 2374 if (vms->mte) { 2375 error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); 2376 return; 2377 } 2378 2379 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2380 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2381 return; 2382 } 2383 2384 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 2385 } 2386 2387 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2388 DeviceState *dev, Error **errp) 2389 { 2390 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2391 MachineState *ms = MACHINE(hotplug_dev); 2392 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2393 2394 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); 2395 2396 if (is_nvdimm) { 2397 nvdimm_plug(ms->nvdimms_state); 2398 } 2399 2400 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2401 dev, &error_abort); 2402 } 2403 2404 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2405 DeviceState *dev, Error **errp) 2406 { 2407 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2408 2409 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2410 virt_memory_pre_plug(hotplug_dev, dev, errp); 2411 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2412 hwaddr db_start = 0, db_end = 0; 2413 char *resv_prop_str; 2414 2415 switch (vms->msi_controller) { 2416 case VIRT_MSI_CTRL_NONE: 2417 return; 2418 case VIRT_MSI_CTRL_ITS: 2419 /* GITS_TRANSLATER page */ 2420 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; 2421 db_end = base_memmap[VIRT_GIC_ITS].base + 2422 base_memmap[VIRT_GIC_ITS].size - 1; 2423 break; 2424 case VIRT_MSI_CTRL_GICV2M: 2425 /* MSI_SETSPI_NS page */ 2426 db_start = base_memmap[VIRT_GIC_V2M].base; 2427 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; 2428 break; 2429 } 2430 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", 2431 db_start, db_end, 2432 VIRTIO_IOMMU_RESV_MEM_T_MSI); 2433 2434 qdev_prop_set_uint32(dev, "len-reserved-regions", 1); 2435 qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str); 2436 g_free(resv_prop_str); 2437 } 2438 } 2439 2440 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2441 DeviceState *dev, Error **errp) 2442 { 2443 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2444 2445 if (vms->platform_bus_dev) { 2446 MachineClass *mc = MACHINE_GET_CLASS(vms); 2447 2448 if (device_is_dynamic_sysbus(mc, dev)) { 2449 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2450 SYS_BUS_DEVICE(dev)); 2451 } 2452 } 2453 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2454 virt_memory_plug(hotplug_dev, dev, errp); 2455 } 2456 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2457 PCIDevice *pdev = PCI_DEVICE(dev); 2458 2459 vms->iommu = VIRT_IOMMU_VIRTIO; 2460 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2461 create_virtio_iommu_dt_bindings(vms); 2462 } 2463 } 2464 2465 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, 2466 DeviceState *dev, Error **errp) 2467 { 2468 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2469 Error *local_err = NULL; 2470 2471 if (!vms->acpi_dev) { 2472 error_setg(&local_err, 2473 "memory hotplug is not enabled: missing acpi-ged device"); 2474 goto out; 2475 } 2476 2477 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2478 error_setg(&local_err, 2479 "nvdimm device hot unplug is not supported yet."); 2480 goto out; 2481 } 2482 2483 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, 2484 &local_err); 2485 out: 2486 error_propagate(errp, local_err); 2487 } 2488 2489 static void virt_dimm_unplug(HotplugHandler *hotplug_dev, 2490 DeviceState *dev, Error **errp) 2491 { 2492 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2493 Error *local_err = NULL; 2494 2495 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); 2496 if (local_err) { 2497 goto out; 2498 } 2499 2500 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); 2501 qdev_unrealize(dev); 2502 2503 out: 2504 error_propagate(errp, local_err); 2505 } 2506 2507 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2508 DeviceState *dev, Error **errp) 2509 { 2510 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2511 virt_dimm_unplug_request(hotplug_dev, dev, errp); 2512 } else { 2513 error_setg(errp, "device unplug request for unsupported device" 2514 " type: %s", object_get_typename(OBJECT(dev))); 2515 } 2516 } 2517 2518 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2519 DeviceState *dev, Error **errp) 2520 { 2521 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2522 virt_dimm_unplug(hotplug_dev, dev, errp); 2523 } else { 2524 error_setg(errp, "virt: device unplug for unsupported device" 2525 " type: %s", object_get_typename(OBJECT(dev))); 2526 } 2527 } 2528 2529 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2530 DeviceState *dev) 2531 { 2532 MachineClass *mc = MACHINE_GET_CLASS(machine); 2533 2534 if (device_is_dynamic_sysbus(mc, dev) || 2535 (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) { 2536 return HOTPLUG_HANDLER(machine); 2537 } 2538 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2539 VirtMachineState *vms = VIRT_MACHINE(machine); 2540 2541 if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) { 2542 return HOTPLUG_HANDLER(machine); 2543 } 2544 } 2545 return NULL; 2546 } 2547 2548 /* 2549 * for arm64 kvm_type [7-0] encodes the requested number of bits 2550 * in the IPA address space 2551 */ 2552 static int virt_kvm_type(MachineState *ms, const char *type_str) 2553 { 2554 VirtMachineState *vms = VIRT_MACHINE(ms); 2555 int max_vm_pa_size, requested_pa_size; 2556 bool fixed_ipa; 2557 2558 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 2559 2560 /* we freeze the memory map to compute the highest gpa */ 2561 virt_set_memmap(vms); 2562 2563 requested_pa_size = 64 - clz64(vms->highest_gpa); 2564 2565 /* 2566 * KVM requires the IPA size to be at least 32 bits. 2567 */ 2568 if (requested_pa_size < 32) { 2569 requested_pa_size = 32; 2570 } 2571 2572 if (requested_pa_size > max_vm_pa_size) { 2573 error_report("-m and ,maxmem option values " 2574 "require an IPA range (%d bits) larger than " 2575 "the one supported by the host (%d bits)", 2576 requested_pa_size, max_vm_pa_size); 2577 exit(1); 2578 } 2579 /* 2580 * We return the requested PA log size, unless KVM only supports 2581 * the implicit legacy 40b IPA setting, in which case the kvm_type 2582 * must be 0. 2583 */ 2584 return fixed_ipa ? 0 : requested_pa_size; 2585 } 2586 2587 static void virt_machine_class_init(ObjectClass *oc, void *data) 2588 { 2589 MachineClass *mc = MACHINE_CLASS(oc); 2590 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2591 2592 mc->init = machvirt_init; 2593 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 2594 * The value may be reduced later when we have more information about the 2595 * configuration of the particular instance. 2596 */ 2597 mc->max_cpus = 512; 2598 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 2599 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 2600 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 2601 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 2602 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 2603 mc->block_default_type = IF_VIRTIO; 2604 mc->no_cdrom = 1; 2605 mc->pci_allow_0_address = true; 2606 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 2607 mc->minimum_page_bits = 12; 2608 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 2609 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 2610 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 2611 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 2612 mc->kvm_type = virt_kvm_type; 2613 assert(!mc->get_hotplug_handler); 2614 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 2615 hc->pre_plug = virt_machine_device_pre_plug_cb; 2616 hc->plug = virt_machine_device_plug_cb; 2617 hc->unplug_request = virt_machine_device_unplug_request_cb; 2618 hc->unplug = virt_machine_device_unplug_cb; 2619 mc->nvdimm_supported = true; 2620 mc->auto_enable_numa_with_memhp = true; 2621 mc->auto_enable_numa_with_memdev = true; 2622 mc->default_ram_id = "mach-virt.ram"; 2623 2624 object_class_property_add(oc, "acpi", "OnOffAuto", 2625 virt_get_acpi, virt_set_acpi, 2626 NULL, NULL); 2627 object_class_property_set_description(oc, "acpi", 2628 "Enable ACPI"); 2629 object_class_property_add_bool(oc, "secure", virt_get_secure, 2630 virt_set_secure); 2631 object_class_property_set_description(oc, "secure", 2632 "Set on/off to enable/disable the ARM " 2633 "Security Extensions (TrustZone)"); 2634 2635 object_class_property_add_bool(oc, "virtualization", virt_get_virt, 2636 virt_set_virt); 2637 object_class_property_set_description(oc, "virtualization", 2638 "Set on/off to enable/disable emulating a " 2639 "guest CPU which implements the ARM " 2640 "Virtualization Extensions"); 2641 2642 object_class_property_add_bool(oc, "highmem", virt_get_highmem, 2643 virt_set_highmem); 2644 object_class_property_set_description(oc, "highmem", 2645 "Set on/off to enable/disable using " 2646 "physical address space above 32 bits"); 2647 2648 object_class_property_add_str(oc, "gic-version", virt_get_gic_version, 2649 virt_set_gic_version); 2650 object_class_property_set_description(oc, "gic-version", 2651 "Set GIC version. " 2652 "Valid values are 2, 3, host and max"); 2653 2654 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); 2655 object_class_property_set_description(oc, "iommu", 2656 "Set the IOMMU type. " 2657 "Valid values are none and smmuv3"); 2658 2659 object_class_property_add_bool(oc, "ras", virt_get_ras, 2660 virt_set_ras); 2661 object_class_property_set_description(oc, "ras", 2662 "Set on/off to enable/disable reporting host memory errors " 2663 "to a KVM guest using ACPI and guest external abort exceptions"); 2664 2665 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); 2666 object_class_property_set_description(oc, "mte", 2667 "Set on/off to enable/disable emulating a " 2668 "guest CPU which implements the ARM " 2669 "Memory Tagging Extension"); 2670 2671 object_class_property_add_bool(oc, "its", virt_get_its, 2672 virt_set_its); 2673 object_class_property_set_description(oc, "its", 2674 "Set on/off to enable/disable " 2675 "ITS instantiation"); 2676 2677 object_class_property_add_str(oc, "x-oem-id", 2678 virt_get_oem_id, 2679 virt_set_oem_id); 2680 object_class_property_set_description(oc, "x-oem-id", 2681 "Override the default value of field OEMID " 2682 "in ACPI table header." 2683 "The string may be up to 6 bytes in size"); 2684 2685 2686 object_class_property_add_str(oc, "x-oem-table-id", 2687 virt_get_oem_table_id, 2688 virt_set_oem_table_id); 2689 object_class_property_set_description(oc, "x-oem-table-id", 2690 "Override the default value of field OEM Table ID " 2691 "in ACPI table header." 2692 "The string may be up to 8 bytes in size"); 2693 2694 } 2695 2696 static void virt_instance_init(Object *obj) 2697 { 2698 VirtMachineState *vms = VIRT_MACHINE(obj); 2699 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 2700 2701 /* EL3 is disabled by default on virt: this makes us consistent 2702 * between KVM and TCG for this board, and it also allows us to 2703 * boot UEFI blobs which assume no TrustZone support. 2704 */ 2705 vms->secure = false; 2706 2707 /* EL2 is also disabled by default, for similar reasons */ 2708 vms->virt = false; 2709 2710 /* High memory is enabled by default */ 2711 vms->highmem = true; 2712 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 2713 2714 vms->highmem_ecam = !vmc->no_highmem_ecam; 2715 2716 if (vmc->no_its) { 2717 vms->its = false; 2718 } else { 2719 /* Default allows ITS instantiation */ 2720 vms->its = true; 2721 } 2722 2723 /* Default disallows iommu instantiation */ 2724 vms->iommu = VIRT_IOMMU_NONE; 2725 2726 /* Default disallows RAS instantiation */ 2727 vms->ras = false; 2728 2729 /* MTE is disabled by default. */ 2730 vms->mte = false; 2731 2732 vms->irqmap = a15irqmap; 2733 2734 virt_flash_create(vms); 2735 2736 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 2737 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 2738 } 2739 2740 static const TypeInfo virt_machine_info = { 2741 .name = TYPE_VIRT_MACHINE, 2742 .parent = TYPE_MACHINE, 2743 .abstract = true, 2744 .instance_size = sizeof(VirtMachineState), 2745 .class_size = sizeof(VirtMachineClass), 2746 .class_init = virt_machine_class_init, 2747 .instance_init = virt_instance_init, 2748 .interfaces = (InterfaceInfo[]) { 2749 { TYPE_HOTPLUG_HANDLER }, 2750 { } 2751 }, 2752 }; 2753 2754 static void machvirt_machine_init(void) 2755 { 2756 type_register_static(&virt_machine_info); 2757 } 2758 type_init(machvirt_machine_init); 2759 2760 static void virt_machine_6_1_options(MachineClass *mc) 2761 { 2762 } 2763 DEFINE_VIRT_MACHINE_AS_LATEST(6, 1) 2764 2765 static void virt_machine_6_0_options(MachineClass *mc) 2766 { 2767 } 2768 DEFINE_VIRT_MACHINE(6, 0) 2769 2770 static void virt_machine_5_2_options(MachineClass *mc) 2771 { 2772 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2773 2774 virt_machine_6_0_options(mc); 2775 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 2776 vmc->no_secure_gpio = true; 2777 } 2778 DEFINE_VIRT_MACHINE(5, 2) 2779 2780 static void virt_machine_5_1_options(MachineClass *mc) 2781 { 2782 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2783 2784 virt_machine_5_2_options(mc); 2785 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 2786 vmc->no_kvm_steal_time = true; 2787 } 2788 DEFINE_VIRT_MACHINE(5, 1) 2789 2790 static void virt_machine_5_0_options(MachineClass *mc) 2791 { 2792 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2793 2794 virt_machine_5_1_options(mc); 2795 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 2796 mc->numa_mem_supported = true; 2797 vmc->acpi_expose_flash = true; 2798 mc->auto_enable_numa_with_memdev = false; 2799 } 2800 DEFINE_VIRT_MACHINE(5, 0) 2801 2802 static void virt_machine_4_2_options(MachineClass *mc) 2803 { 2804 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2805 2806 virt_machine_5_0_options(mc); 2807 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 2808 vmc->kvm_no_adjvtime = true; 2809 } 2810 DEFINE_VIRT_MACHINE(4, 2) 2811 2812 static void virt_machine_4_1_options(MachineClass *mc) 2813 { 2814 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2815 2816 virt_machine_4_2_options(mc); 2817 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 2818 vmc->no_ged = true; 2819 mc->auto_enable_numa_with_memhp = false; 2820 } 2821 DEFINE_VIRT_MACHINE(4, 1) 2822 2823 static void virt_machine_4_0_options(MachineClass *mc) 2824 { 2825 virt_machine_4_1_options(mc); 2826 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 2827 } 2828 DEFINE_VIRT_MACHINE(4, 0) 2829 2830 static void virt_machine_3_1_options(MachineClass *mc) 2831 { 2832 virt_machine_4_0_options(mc); 2833 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 2834 } 2835 DEFINE_VIRT_MACHINE(3, 1) 2836 2837 static void virt_machine_3_0_options(MachineClass *mc) 2838 { 2839 virt_machine_3_1_options(mc); 2840 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 2841 } 2842 DEFINE_VIRT_MACHINE(3, 0) 2843 2844 static void virt_machine_2_12_options(MachineClass *mc) 2845 { 2846 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2847 2848 virt_machine_3_0_options(mc); 2849 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 2850 vmc->no_highmem_ecam = true; 2851 mc->max_cpus = 255; 2852 } 2853 DEFINE_VIRT_MACHINE(2, 12) 2854 2855 static void virt_machine_2_11_options(MachineClass *mc) 2856 { 2857 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2858 2859 virt_machine_2_12_options(mc); 2860 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 2861 vmc->smbios_old_sys_ver = true; 2862 } 2863 DEFINE_VIRT_MACHINE(2, 11) 2864 2865 static void virt_machine_2_10_options(MachineClass *mc) 2866 { 2867 virt_machine_2_11_options(mc); 2868 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 2869 /* before 2.11 we never faulted accesses to bad addresses */ 2870 mc->ignore_memory_transaction_failures = true; 2871 } 2872 DEFINE_VIRT_MACHINE(2, 10) 2873 2874 static void virt_machine_2_9_options(MachineClass *mc) 2875 { 2876 virt_machine_2_10_options(mc); 2877 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 2878 } 2879 DEFINE_VIRT_MACHINE(2, 9) 2880 2881 static void virt_machine_2_8_options(MachineClass *mc) 2882 { 2883 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2884 2885 virt_machine_2_9_options(mc); 2886 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 2887 /* For 2.8 and earlier we falsely claimed in the DT that 2888 * our timers were edge-triggered, not level-triggered. 2889 */ 2890 vmc->claim_edge_triggered_timers = true; 2891 } 2892 DEFINE_VIRT_MACHINE(2, 8) 2893 2894 static void virt_machine_2_7_options(MachineClass *mc) 2895 { 2896 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2897 2898 virt_machine_2_8_options(mc); 2899 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 2900 /* ITS was introduced with 2.8 */ 2901 vmc->no_its = true; 2902 /* Stick with 1K pages for migration compatibility */ 2903 mc->minimum_page_bits = 0; 2904 } 2905 DEFINE_VIRT_MACHINE(2, 7) 2906 2907 static void virt_machine_2_6_options(MachineClass *mc) 2908 { 2909 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 2910 2911 virt_machine_2_7_options(mc); 2912 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 2913 vmc->disallow_affinity_adjustment = true; 2914 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 2915 vmc->no_pmu = true; 2916 } 2917 DEFINE_VIRT_MACHINE(2, 6) 2918