1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "hw/sysbus.h" 32 #include "hw/arm/arm.h" 33 #include "hw/arm/primecell.h" 34 #include "hw/arm/virt.h" 35 #include "hw/devices.h" 36 #include "net/net.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/device_tree.h" 39 #include "sysemu/sysemu.h" 40 #include "sysemu/kvm.h" 41 #include "hw/boards.h" 42 #include "hw/loader.h" 43 #include "exec/address-spaces.h" 44 #include "qemu/bitops.h" 45 #include "qemu/error-report.h" 46 #include "hw/pci-host/gpex.h" 47 48 /* Number of external interrupt lines to configure the GIC with */ 49 #define NUM_IRQS 128 50 51 #define GIC_FDT_IRQ_TYPE_SPI 0 52 #define GIC_FDT_IRQ_TYPE_PPI 1 53 54 #define GIC_FDT_IRQ_FLAGS_EDGE_LO_HI 1 55 #define GIC_FDT_IRQ_FLAGS_EDGE_HI_LO 2 56 #define GIC_FDT_IRQ_FLAGS_LEVEL_HI 4 57 #define GIC_FDT_IRQ_FLAGS_LEVEL_LO 8 58 59 #define GIC_FDT_IRQ_PPI_CPU_START 8 60 #define GIC_FDT_IRQ_PPI_CPU_WIDTH 8 61 62 typedef struct VirtBoardInfo { 63 struct arm_boot_info bootinfo; 64 const char *cpu_model; 65 const MemMapEntry *memmap; 66 const int *irqmap; 67 int smp_cpus; 68 void *fdt; 69 int fdt_size; 70 uint32_t clock_phandle; 71 } VirtBoardInfo; 72 73 typedef struct { 74 MachineClass parent; 75 VirtBoardInfo *daughterboard; 76 } VirtMachineClass; 77 78 typedef struct { 79 MachineState parent; 80 bool secure; 81 } VirtMachineState; 82 83 #define TYPE_VIRT_MACHINE "virt" 84 #define VIRT_MACHINE(obj) \ 85 OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE) 86 #define VIRT_MACHINE_GET_CLASS(obj) \ 87 OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE) 88 #define VIRT_MACHINE_CLASS(klass) \ 89 OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE) 90 91 /* Addresses and sizes of our components. 92 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 93 * 128MB..256MB is used for miscellaneous device I/O. 94 * 256MB..1GB is reserved for possible future PCI support (ie where the 95 * PCI memory window will go if we add a PCI host controller). 96 * 1GB and up is RAM (which may happily spill over into the 97 * high memory region beyond 4GB). 98 * This represents a compromise between how much RAM can be given to 99 * a 32 bit VM and leaving space for expansion and in particular for PCI. 100 * Note that devices should generally be placed at multiples of 0x10000, 101 * to accommodate guests using 64K pages. 102 */ 103 static const MemMapEntry a15memmap[] = { 104 /* Space up to 0x8000000 is reserved for a boot ROM */ 105 [VIRT_FLASH] = { 0, 0x08000000 }, 106 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 107 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 108 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 109 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 110 [VIRT_UART] = { 0x09000000, 0x00001000 }, 111 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 112 [VIRT_FW_CFG] = { 0x09020000, 0x0000000a }, 113 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 114 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 115 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 116 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 117 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 118 [VIRT_MEM] = { 0x40000000, 30ULL * 1024 * 1024 * 1024 }, 119 }; 120 121 static const int a15irqmap[] = { 122 [VIRT_UART] = 1, 123 [VIRT_RTC] = 2, 124 [VIRT_PCIE] = 3, /* ... to 6 */ 125 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 126 }; 127 128 static VirtBoardInfo machines[] = { 129 { 130 .cpu_model = "cortex-a15", 131 .memmap = a15memmap, 132 .irqmap = a15irqmap, 133 }, 134 { 135 .cpu_model = "cortex-a57", 136 .memmap = a15memmap, 137 .irqmap = a15irqmap, 138 }, 139 { 140 .cpu_model = "host", 141 .memmap = a15memmap, 142 .irqmap = a15irqmap, 143 }, 144 }; 145 146 static VirtBoardInfo *find_machine_info(const char *cpu) 147 { 148 int i; 149 150 for (i = 0; i < ARRAY_SIZE(machines); i++) { 151 if (strcmp(cpu, machines[i].cpu_model) == 0) { 152 return &machines[i]; 153 } 154 } 155 return NULL; 156 } 157 158 static void create_fdt(VirtBoardInfo *vbi) 159 { 160 void *fdt = create_device_tree(&vbi->fdt_size); 161 162 if (!fdt) { 163 error_report("create_device_tree() failed"); 164 exit(1); 165 } 166 167 vbi->fdt = fdt; 168 169 /* Header */ 170 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 171 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 172 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 173 174 /* 175 * /chosen and /memory nodes must exist for load_dtb 176 * to fill in necessary properties later 177 */ 178 qemu_fdt_add_subnode(fdt, "/chosen"); 179 qemu_fdt_add_subnode(fdt, "/memory"); 180 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 181 182 /* Clock node, for the benefit of the UART. The kernel device tree 183 * binding documentation claims the PL011 node clock properties are 184 * optional but in practice if you omit them the kernel refuses to 185 * probe for the device. 186 */ 187 vbi->clock_phandle = qemu_fdt_alloc_phandle(fdt); 188 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 189 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 190 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 191 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 192 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 193 "clk24mhz"); 194 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vbi->clock_phandle); 195 196 } 197 198 static void fdt_add_psci_node(const VirtBoardInfo *vbi) 199 { 200 uint32_t cpu_suspend_fn; 201 uint32_t cpu_off_fn; 202 uint32_t cpu_on_fn; 203 uint32_t migrate_fn; 204 void *fdt = vbi->fdt; 205 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 206 207 qemu_fdt_add_subnode(fdt, "/psci"); 208 if (armcpu->psci_version == 2) { 209 const char comp[] = "arm,psci-0.2\0arm,psci"; 210 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 211 212 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 213 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 214 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 215 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 216 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 217 } else { 218 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 219 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 220 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 221 } 222 } else { 223 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 224 225 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 226 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 227 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 228 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 229 } 230 231 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 232 * to the instruction that should be used to invoke PSCI functions. 233 * However, the device tree binding uses 'method' instead, so that is 234 * what we should use here. 235 */ 236 qemu_fdt_setprop_string(fdt, "/psci", "method", "hvc"); 237 238 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 239 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 240 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 241 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 242 } 243 244 static void fdt_add_timer_nodes(const VirtBoardInfo *vbi) 245 { 246 /* Note that on A15 h/w these interrupts are level-triggered, 247 * but for the GIC implementation provided by both QEMU and KVM 248 * they are edge-triggered. 249 */ 250 ARMCPU *armcpu; 251 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 252 253 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 254 GIC_FDT_IRQ_PPI_CPU_WIDTH, (1 << vbi->smp_cpus) - 1); 255 256 qemu_fdt_add_subnode(vbi->fdt, "/timer"); 257 258 armcpu = ARM_CPU(qemu_get_cpu(0)); 259 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 260 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 261 qemu_fdt_setprop(vbi->fdt, "/timer", "compatible", 262 compat, sizeof(compat)); 263 } else { 264 qemu_fdt_setprop_string(vbi->fdt, "/timer", "compatible", 265 "arm,armv7-timer"); 266 } 267 qemu_fdt_setprop_cells(vbi->fdt, "/timer", "interrupts", 268 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 269 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 270 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 271 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 272 } 273 274 static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi) 275 { 276 int cpu; 277 278 qemu_fdt_add_subnode(vbi->fdt, "/cpus"); 279 qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#address-cells", 0x1); 280 qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#size-cells", 0x0); 281 282 for (cpu = vbi->smp_cpus - 1; cpu >= 0; cpu--) { 283 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 284 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 285 286 qemu_fdt_add_subnode(vbi->fdt, nodename); 287 qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "cpu"); 288 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", 289 armcpu->dtb_compatible); 290 291 if (vbi->smp_cpus > 1) { 292 qemu_fdt_setprop_string(vbi->fdt, nodename, 293 "enable-method", "psci"); 294 } 295 296 qemu_fdt_setprop_cell(vbi->fdt, nodename, "reg", cpu); 297 g_free(nodename); 298 } 299 } 300 301 static uint32_t fdt_add_gic_node(const VirtBoardInfo *vbi) 302 { 303 uint32_t gic_phandle; 304 305 gic_phandle = qemu_fdt_alloc_phandle(vbi->fdt); 306 qemu_fdt_setprop_cell(vbi->fdt, "/", "interrupt-parent", gic_phandle); 307 308 qemu_fdt_add_subnode(vbi->fdt, "/intc"); 309 /* 'cortex-a15-gic' means 'GIC v2' */ 310 qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", 311 "arm,cortex-a15-gic"); 312 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#interrupt-cells", 3); 313 qemu_fdt_setprop(vbi->fdt, "/intc", "interrupt-controller", NULL, 0); 314 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", 315 2, vbi->memmap[VIRT_GIC_DIST].base, 316 2, vbi->memmap[VIRT_GIC_DIST].size, 317 2, vbi->memmap[VIRT_GIC_CPU].base, 318 2, vbi->memmap[VIRT_GIC_CPU].size); 319 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", gic_phandle); 320 321 return gic_phandle; 322 } 323 324 static uint32_t create_gic(const VirtBoardInfo *vbi, qemu_irq *pic) 325 { 326 /* We create a standalone GIC v2 */ 327 DeviceState *gicdev; 328 SysBusDevice *gicbusdev; 329 const char *gictype = "arm_gic"; 330 int i; 331 332 if (kvm_irqchip_in_kernel()) { 333 gictype = "kvm-arm-gic"; 334 } 335 336 gicdev = qdev_create(NULL, gictype); 337 qdev_prop_set_uint32(gicdev, "revision", 2); 338 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 339 /* Note that the num-irq property counts both internal and external 340 * interrupts; there are always 32 of the former (mandated by GIC spec). 341 */ 342 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 343 qdev_init_nofail(gicdev); 344 gicbusdev = SYS_BUS_DEVICE(gicdev); 345 sysbus_mmio_map(gicbusdev, 0, vbi->memmap[VIRT_GIC_DIST].base); 346 sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base); 347 348 /* Wire the outputs from each CPU's generic timer to the 349 * appropriate GIC PPI inputs, and the GIC's IRQ output to 350 * the CPU's IRQ input. 351 */ 352 for (i = 0; i < smp_cpus; i++) { 353 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 354 int ppibase = NUM_IRQS + i * 32; 355 /* physical timer; we wire it up to the non-secure timer's ID, 356 * since a real A15 always has TrustZone but QEMU doesn't. 357 */ 358 qdev_connect_gpio_out(cpudev, 0, 359 qdev_get_gpio_in(gicdev, ppibase + 30)); 360 /* virtual timer */ 361 qdev_connect_gpio_out(cpudev, 1, 362 qdev_get_gpio_in(gicdev, ppibase + 27)); 363 364 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 365 sysbus_connect_irq(gicbusdev, i + smp_cpus, 366 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 367 } 368 369 for (i = 0; i < NUM_IRQS; i++) { 370 pic[i] = qdev_get_gpio_in(gicdev, i); 371 } 372 373 return fdt_add_gic_node(vbi); 374 } 375 376 static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic) 377 { 378 char *nodename; 379 hwaddr base = vbi->memmap[VIRT_UART].base; 380 hwaddr size = vbi->memmap[VIRT_UART].size; 381 int irq = vbi->irqmap[VIRT_UART]; 382 const char compat[] = "arm,pl011\0arm,primecell"; 383 const char clocknames[] = "uartclk\0apb_pclk"; 384 385 sysbus_create_simple("pl011", base, pic[irq]); 386 387 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 388 qemu_fdt_add_subnode(vbi->fdt, nodename); 389 /* Note that we can't use setprop_string because of the embedded NUL */ 390 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", 391 compat, sizeof(compat)); 392 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 393 2, base, 2, size); 394 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 395 GIC_FDT_IRQ_TYPE_SPI, irq, 396 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 397 qemu_fdt_setprop_cells(vbi->fdt, nodename, "clocks", 398 vbi->clock_phandle, vbi->clock_phandle); 399 qemu_fdt_setprop(vbi->fdt, nodename, "clock-names", 400 clocknames, sizeof(clocknames)); 401 402 qemu_fdt_setprop_string(vbi->fdt, "/chosen", "stdout-path", nodename); 403 g_free(nodename); 404 } 405 406 static void create_rtc(const VirtBoardInfo *vbi, qemu_irq *pic) 407 { 408 char *nodename; 409 hwaddr base = vbi->memmap[VIRT_RTC].base; 410 hwaddr size = vbi->memmap[VIRT_RTC].size; 411 int irq = vbi->irqmap[VIRT_RTC]; 412 const char compat[] = "arm,pl031\0arm,primecell"; 413 414 sysbus_create_simple("pl031", base, pic[irq]); 415 416 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 417 qemu_fdt_add_subnode(vbi->fdt, nodename); 418 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat)); 419 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 420 2, base, 2, size); 421 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 422 GIC_FDT_IRQ_TYPE_SPI, irq, 423 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 424 qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle); 425 qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk"); 426 g_free(nodename); 427 } 428 429 static void create_virtio_devices(const VirtBoardInfo *vbi, qemu_irq *pic) 430 { 431 int i; 432 hwaddr size = vbi->memmap[VIRT_MMIO].size; 433 434 /* We create the transports in forwards order. Since qbus_realize() 435 * prepends (not appends) new child buses, the incrementing loop below will 436 * create a list of virtio-mmio buses with decreasing base addresses. 437 * 438 * When a -device option is processed from the command line, 439 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 440 * order. The upshot is that -device options in increasing command line 441 * order are mapped to virtio-mmio buses with decreasing base addresses. 442 * 443 * When this code was originally written, that arrangement ensured that the 444 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 445 * the first -device on the command line. (The end-to-end order is a 446 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 447 * guest kernel's name-to-address assignment strategy.) 448 * 449 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 450 * the message, if not necessarily the code, of commit 70161ff336. 451 * Therefore the loop now establishes the inverse of the original intent. 452 * 453 * Unfortunately, we can't counteract the kernel change by reversing the 454 * loop; it would break existing command lines. 455 * 456 * In any case, the kernel makes no guarantee about the stability of 457 * enumeration order of virtio devices (as demonstrated by it changing 458 * between kernel versions). For reliable and stable identification 459 * of disks users must use UUIDs or similar mechanisms. 460 */ 461 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 462 int irq = vbi->irqmap[VIRT_MMIO] + i; 463 hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size; 464 465 sysbus_create_simple("virtio-mmio", base, pic[irq]); 466 } 467 468 /* We add dtb nodes in reverse order so that they appear in the finished 469 * device tree lowest address first. 470 * 471 * Note that this mapping is independent of the loop above. The previous 472 * loop influences virtio device to virtio transport assignment, whereas 473 * this loop controls how virtio transports are laid out in the dtb. 474 */ 475 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 476 char *nodename; 477 int irq = vbi->irqmap[VIRT_MMIO] + i; 478 hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size; 479 480 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 481 qemu_fdt_add_subnode(vbi->fdt, nodename); 482 qemu_fdt_setprop_string(vbi->fdt, nodename, 483 "compatible", "virtio,mmio"); 484 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 485 2, base, 2, size); 486 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 487 GIC_FDT_IRQ_TYPE_SPI, irq, 488 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 489 g_free(nodename); 490 } 491 } 492 493 static void create_one_flash(const char *name, hwaddr flashbase, 494 hwaddr flashsize) 495 { 496 /* Create and map a single flash device. We use the same 497 * parameters as the flash devices on the Versatile Express board. 498 */ 499 DriveInfo *dinfo = drive_get_next(IF_PFLASH); 500 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 501 const uint64_t sectorlength = 256 * 1024; 502 503 if (dinfo) { 504 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 505 &error_abort); 506 } 507 508 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); 509 qdev_prop_set_uint64(dev, "sector-length", sectorlength); 510 qdev_prop_set_uint8(dev, "width", 4); 511 qdev_prop_set_uint8(dev, "device-width", 2); 512 qdev_prop_set_uint8(dev, "big-endian", 0); 513 qdev_prop_set_uint16(dev, "id0", 0x89); 514 qdev_prop_set_uint16(dev, "id1", 0x18); 515 qdev_prop_set_uint16(dev, "id2", 0x00); 516 qdev_prop_set_uint16(dev, "id3", 0x00); 517 qdev_prop_set_string(dev, "name", name); 518 qdev_init_nofail(dev); 519 520 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, flashbase); 521 } 522 523 static void create_flash(const VirtBoardInfo *vbi) 524 { 525 /* Create two flash devices to fill the VIRT_FLASH space in the memmap. 526 * Any file passed via -bios goes in the first of these. 527 */ 528 hwaddr flashsize = vbi->memmap[VIRT_FLASH].size / 2; 529 hwaddr flashbase = vbi->memmap[VIRT_FLASH].base; 530 char *nodename; 531 532 if (bios_name) { 533 char *fn; 534 int image_size; 535 536 if (drive_get(IF_PFLASH, 0, 0)) { 537 error_report("The contents of the first flash device may be " 538 "specified with -bios or with -drive if=pflash... " 539 "but you cannot use both options at once"); 540 exit(1); 541 } 542 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 543 if (!fn) { 544 error_report("Could not find ROM image '%s'", bios_name); 545 exit(1); 546 } 547 image_size = load_image_targphys(fn, flashbase, flashsize); 548 g_free(fn); 549 if (image_size < 0) { 550 error_report("Could not load ROM image '%s'", bios_name); 551 exit(1); 552 } 553 } 554 555 create_one_flash("virt.flash0", flashbase, flashsize); 556 create_one_flash("virt.flash1", flashbase + flashsize, flashsize); 557 558 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 559 qemu_fdt_add_subnode(vbi->fdt, nodename); 560 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash"); 561 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 562 2, flashbase, 2, flashsize, 563 2, flashbase + flashsize, 2, flashsize); 564 qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4); 565 g_free(nodename); 566 } 567 568 static void create_fw_cfg(const VirtBoardInfo *vbi) 569 { 570 hwaddr base = vbi->memmap[VIRT_FW_CFG].base; 571 hwaddr size = vbi->memmap[VIRT_FW_CFG].size; 572 char *nodename; 573 574 fw_cfg_init_mem_wide(base + 8, base, 8); 575 576 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 577 qemu_fdt_add_subnode(vbi->fdt, nodename); 578 qemu_fdt_setprop_string(vbi->fdt, nodename, 579 "compatible", "qemu,fw-cfg-mmio"); 580 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 581 2, base, 2, size); 582 g_free(nodename); 583 } 584 585 static void create_pcie_irq_map(const VirtBoardInfo *vbi, uint32_t gic_phandle, 586 int first_irq, const char *nodename) 587 { 588 int devfn, pin; 589 uint32_t full_irq_map[4 * 4 * 8] = { 0 }; 590 uint32_t *irq_map = full_irq_map; 591 592 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 593 for (pin = 0; pin < 4; pin++) { 594 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 595 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 596 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 597 int i; 598 599 uint32_t map[] = { 600 devfn << 8, 0, 0, /* devfn */ 601 pin + 1, /* PCI pin */ 602 gic_phandle, irq_type, irq_nr, irq_level }; /* GIC irq */ 603 604 /* Convert map to big endian */ 605 for (i = 0; i < 8; i++) { 606 irq_map[i] = cpu_to_be32(map[i]); 607 } 608 irq_map += 8; 609 } 610 } 611 612 qemu_fdt_setprop(vbi->fdt, nodename, "interrupt-map", 613 full_irq_map, sizeof(full_irq_map)); 614 615 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupt-map-mask", 616 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 617 0x7 /* PCI irq */); 618 } 619 620 static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic, 621 uint32_t gic_phandle) 622 { 623 hwaddr base_mmio = vbi->memmap[VIRT_PCIE_MMIO].base; 624 hwaddr size_mmio = vbi->memmap[VIRT_PCIE_MMIO].size; 625 hwaddr base_pio = vbi->memmap[VIRT_PCIE_PIO].base; 626 hwaddr size_pio = vbi->memmap[VIRT_PCIE_PIO].size; 627 hwaddr base_ecam = vbi->memmap[VIRT_PCIE_ECAM].base; 628 hwaddr size_ecam = vbi->memmap[VIRT_PCIE_ECAM].size; 629 hwaddr base = base_mmio; 630 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 631 int irq = vbi->irqmap[VIRT_PCIE]; 632 MemoryRegion *mmio_alias; 633 MemoryRegion *mmio_reg; 634 MemoryRegion *ecam_alias; 635 MemoryRegion *ecam_reg; 636 DeviceState *dev; 637 char *nodename; 638 int i; 639 640 dev = qdev_create(NULL, TYPE_GPEX_HOST); 641 qdev_init_nofail(dev); 642 643 /* Map only the first size_ecam bytes of ECAM space */ 644 ecam_alias = g_new0(MemoryRegion, 1); 645 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 646 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 647 ecam_reg, 0, size_ecam); 648 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 649 650 /* Map the MMIO window into system address space so as to expose 651 * the section of PCI MMIO space which starts at the same base address 652 * (ie 1:1 mapping for that part of PCI MMIO space visible through 653 * the window). 654 */ 655 mmio_alias = g_new0(MemoryRegion, 1); 656 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 657 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 658 mmio_reg, base_mmio, size_mmio); 659 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 660 661 /* Map IO port space */ 662 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 663 664 for (i = 0; i < GPEX_NUM_IRQS; i++) { 665 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 666 } 667 668 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 669 qemu_fdt_add_subnode(vbi->fdt, nodename); 670 qemu_fdt_setprop_string(vbi->fdt, nodename, 671 "compatible", "pci-host-ecam-generic"); 672 qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "pci"); 673 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#address-cells", 3); 674 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#size-cells", 2); 675 qemu_fdt_setprop_cells(vbi->fdt, nodename, "bus-range", 0, 676 nr_pcie_buses - 1); 677 678 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 679 2, base_ecam, 2, size_ecam); 680 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges", 681 1, FDT_PCI_RANGE_IOPORT, 2, 0, 682 2, base_pio, 2, size_pio, 683 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 684 2, base_mmio, 2, size_mmio); 685 686 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#interrupt-cells", 1); 687 create_pcie_irq_map(vbi, gic_phandle, irq, nodename); 688 689 g_free(nodename); 690 } 691 692 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 693 { 694 const VirtBoardInfo *board = (const VirtBoardInfo *)binfo; 695 696 *fdt_size = board->fdt_size; 697 return board->fdt; 698 } 699 700 static void machvirt_init(MachineState *machine) 701 { 702 VirtMachineState *vms = VIRT_MACHINE(machine); 703 qemu_irq pic[NUM_IRQS]; 704 MemoryRegion *sysmem = get_system_memory(); 705 int n; 706 MemoryRegion *ram = g_new(MemoryRegion, 1); 707 const char *cpu_model = machine->cpu_model; 708 VirtBoardInfo *vbi; 709 uint32_t gic_phandle; 710 char **cpustr; 711 712 if (!cpu_model) { 713 cpu_model = "cortex-a15"; 714 } 715 716 /* Separate the actual CPU model name from any appended features */ 717 cpustr = g_strsplit(cpu_model, ",", 2); 718 719 vbi = find_machine_info(cpustr[0]); 720 721 if (!vbi) { 722 error_report("mach-virt: CPU %s not supported", cpustr[0]); 723 exit(1); 724 } 725 726 vbi->smp_cpus = smp_cpus; 727 728 if (machine->ram_size > vbi->memmap[VIRT_MEM].size) { 729 error_report("mach-virt: cannot model more than 30GB RAM"); 730 exit(1); 731 } 732 733 create_fdt(vbi); 734 735 for (n = 0; n < smp_cpus; n++) { 736 ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); 737 CPUClass *cc = CPU_CLASS(oc); 738 Object *cpuobj; 739 Error *err = NULL; 740 char *cpuopts = g_strdup(cpustr[1]); 741 742 if (!oc) { 743 fprintf(stderr, "Unable to find CPU definition\n"); 744 exit(1); 745 } 746 cpuobj = object_new(object_class_get_name(oc)); 747 748 /* Handle any CPU options specified by the user */ 749 cc->parse_features(CPU(cpuobj), cpuopts, &err); 750 g_free(cpuopts); 751 if (err) { 752 error_report_err(err); 753 exit(1); 754 } 755 756 if (!vms->secure) { 757 object_property_set_bool(cpuobj, false, "has_el3", NULL); 758 } 759 760 object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_HVC, "psci-conduit", 761 NULL); 762 763 /* Secondary CPUs start in PSCI powered-down state */ 764 if (n > 0) { 765 object_property_set_bool(cpuobj, true, "start-powered-off", NULL); 766 } 767 768 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 769 object_property_set_int(cpuobj, vbi->memmap[VIRT_CPUPERIPHS].base, 770 "reset-cbar", &error_abort); 771 } 772 773 object_property_set_bool(cpuobj, true, "realized", NULL); 774 } 775 g_strfreev(cpustr); 776 fdt_add_timer_nodes(vbi); 777 fdt_add_cpu_nodes(vbi); 778 fdt_add_psci_node(vbi); 779 780 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", 781 machine->ram_size); 782 memory_region_add_subregion(sysmem, vbi->memmap[VIRT_MEM].base, ram); 783 784 create_flash(vbi); 785 786 gic_phandle = create_gic(vbi, pic); 787 788 create_uart(vbi, pic); 789 790 create_rtc(vbi, pic); 791 792 create_pcie(vbi, pic, gic_phandle); 793 794 /* Create mmio transports, so the user can create virtio backends 795 * (which will be automatically plugged in to the transports). If 796 * no backend is created the transport will just sit harmlessly idle. 797 */ 798 create_virtio_devices(vbi, pic); 799 800 create_fw_cfg(vbi); 801 802 vbi->bootinfo.ram_size = machine->ram_size; 803 vbi->bootinfo.kernel_filename = machine->kernel_filename; 804 vbi->bootinfo.kernel_cmdline = machine->kernel_cmdline; 805 vbi->bootinfo.initrd_filename = machine->initrd_filename; 806 vbi->bootinfo.nb_cpus = smp_cpus; 807 vbi->bootinfo.board_id = -1; 808 vbi->bootinfo.loader_start = vbi->memmap[VIRT_MEM].base; 809 vbi->bootinfo.get_dtb = machvirt_dtb; 810 vbi->bootinfo.firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); 811 arm_load_kernel(ARM_CPU(first_cpu), &vbi->bootinfo); 812 } 813 814 static bool virt_get_secure(Object *obj, Error **errp) 815 { 816 VirtMachineState *vms = VIRT_MACHINE(obj); 817 818 return vms->secure; 819 } 820 821 static void virt_set_secure(Object *obj, bool value, Error **errp) 822 { 823 VirtMachineState *vms = VIRT_MACHINE(obj); 824 825 vms->secure = value; 826 } 827 828 static void virt_instance_init(Object *obj) 829 { 830 VirtMachineState *vms = VIRT_MACHINE(obj); 831 832 /* EL3 is enabled by default on virt */ 833 vms->secure = true; 834 object_property_add_bool(obj, "secure", virt_get_secure, 835 virt_set_secure, NULL); 836 object_property_set_description(obj, "secure", 837 "Set on/off to enable/disable the ARM " 838 "Security Extensions (TrustZone)", 839 NULL); 840 } 841 842 static void virt_class_init(ObjectClass *oc, void *data) 843 { 844 MachineClass *mc = MACHINE_CLASS(oc); 845 846 mc->name = TYPE_VIRT_MACHINE; 847 mc->desc = "ARM Virtual Machine", 848 mc->init = machvirt_init; 849 mc->max_cpus = 8; 850 } 851 852 static const TypeInfo machvirt_info = { 853 .name = TYPE_VIRT_MACHINE, 854 .parent = TYPE_MACHINE, 855 .instance_size = sizeof(VirtMachineState), 856 .instance_init = virt_instance_init, 857 .class_size = sizeof(VirtMachineClass), 858 .class_init = virt_class_init, 859 }; 860 861 static void machvirt_machine_init(void) 862 { 863 type_register_static(&machvirt_info); 864 } 865 866 machine_init(machvirt_machine_init); 867