1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qapi/error.h" 33 #include "hw/sysbus.h" 34 #include "hw/arm/arm.h" 35 #include "hw/arm/primecell.h" 36 #include "hw/arm/virt.h" 37 #include "hw/devices.h" 38 #include "net/net.h" 39 #include "sysemu/block-backend.h" 40 #include "sysemu/device_tree.h" 41 #include "sysemu/numa.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/kvm.h" 44 #include "hw/boards.h" 45 #include "hw/compat.h" 46 #include "hw/loader.h" 47 #include "exec/address-spaces.h" 48 #include "qemu/bitops.h" 49 #include "qemu/error-report.h" 50 #include "hw/pci-host/gpex.h" 51 #include "hw/arm/virt-acpi-build.h" 52 #include "hw/arm/sysbus-fdt.h" 53 #include "hw/platform-bus.h" 54 #include "hw/arm/fdt.h" 55 #include "hw/intc/arm_gic.h" 56 #include "hw/intc/arm_gicv3_common.h" 57 #include "kvm_arm.h" 58 #include "hw/smbios/smbios.h" 59 #include "qapi/visitor.h" 60 #include "standard-headers/linux/input.h" 61 62 /* Number of external interrupt lines to configure the GIC with */ 63 #define NUM_IRQS 256 64 65 #define PLATFORM_BUS_NUM_IRQS 64 66 67 static ARMPlatformBusSystemParams platform_bus_params; 68 69 typedef struct VirtBoardInfo { 70 struct arm_boot_info bootinfo; 71 const char *cpu_model; 72 const MemMapEntry *memmap; 73 const int *irqmap; 74 int smp_cpus; 75 void *fdt; 76 int fdt_size; 77 uint32_t clock_phandle; 78 uint32_t gic_phandle; 79 uint32_t v2m_phandle; 80 bool using_psci; 81 } VirtBoardInfo; 82 83 typedef struct { 84 MachineClass parent; 85 VirtBoardInfo *daughterboard; 86 bool disallow_affinity_adjustment; 87 } VirtMachineClass; 88 89 typedef struct { 90 MachineState parent; 91 bool secure; 92 bool highmem; 93 int32_t gic_version; 94 } VirtMachineState; 95 96 #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt") 97 #define VIRT_MACHINE(obj) \ 98 OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE) 99 #define VIRT_MACHINE_GET_CLASS(obj) \ 100 OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE) 101 #define VIRT_MACHINE_CLASS(klass) \ 102 OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE) 103 104 105 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 106 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 107 void *data) \ 108 { \ 109 MachineClass *mc = MACHINE_CLASS(oc); \ 110 virt_machine_##major##_##minor##_options(mc); \ 111 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 112 if (latest) { \ 113 mc->alias = "virt"; \ 114 } \ 115 } \ 116 static const TypeInfo machvirt_##major##_##minor##_info = { \ 117 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 118 .parent = TYPE_VIRT_MACHINE, \ 119 .instance_init = virt_##major##_##minor##_instance_init, \ 120 .class_init = virt_##major##_##minor##_class_init, \ 121 }; \ 122 static void machvirt_machine_##major##_##minor##_init(void) \ 123 { \ 124 type_register_static(&machvirt_##major##_##minor##_info); \ 125 } \ 126 type_init(machvirt_machine_##major##_##minor##_init); 127 128 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 129 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 130 #define DEFINE_VIRT_MACHINE(major, minor) \ 131 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 132 133 134 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means 135 * RAM can go up to the 256GB mark, leaving 256GB of the physical 136 * address space unallocated and free for future use between 256G and 512G. 137 * If we need to provide more RAM to VMs in the future then we need to: 138 * * allocate a second bank of RAM starting at 2TB and working up 139 * * fix the DT and ACPI table generation code in QEMU to correctly 140 * report two split lumps of RAM to the guest 141 * * fix KVM in the host kernel to allow guests with >40 bit address spaces 142 * (We don't want to fill all the way up to 512GB with RAM because 143 * we might want it for non-RAM purposes later. Conversely it seems 144 * reasonable to assume that anybody configuring a VM with a quarter 145 * of a terabyte of RAM will be doing it on a host with more than a 146 * terabyte of physical address space.) 147 */ 148 #define RAMLIMIT_GB 255 149 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) 150 151 /* Addresses and sizes of our components. 152 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 153 * 128MB..256MB is used for miscellaneous device I/O. 154 * 256MB..1GB is reserved for possible future PCI support (ie where the 155 * PCI memory window will go if we add a PCI host controller). 156 * 1GB and up is RAM (which may happily spill over into the 157 * high memory region beyond 4GB). 158 * This represents a compromise between how much RAM can be given to 159 * a 32 bit VM and leaving space for expansion and in particular for PCI. 160 * Note that devices should generally be placed at multiples of 0x10000, 161 * to accommodate guests using 64K pages. 162 */ 163 static const MemMapEntry a15memmap[] = { 164 /* Space up to 0x8000000 is reserved for a boot ROM */ 165 [VIRT_FLASH] = { 0, 0x08000000 }, 166 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 167 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 168 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 169 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 170 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 171 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 172 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 173 /* This redistributor space allows up to 2*64kB*123 CPUs */ 174 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 175 [VIRT_UART] = { 0x09000000, 0x00001000 }, 176 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 177 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 178 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 179 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 180 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 181 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 182 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 183 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 184 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 185 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 186 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 187 [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES }, 188 /* Second PCIe window, 512GB wide at the 512GB boundary */ 189 [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL }, 190 }; 191 192 static const int a15irqmap[] = { 193 [VIRT_UART] = 1, 194 [VIRT_RTC] = 2, 195 [VIRT_PCIE] = 3, /* ... to 6 */ 196 [VIRT_GPIO] = 7, 197 [VIRT_SECURE_UART] = 8, 198 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 199 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 200 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 201 }; 202 203 static VirtBoardInfo machines[] = { 204 { 205 .cpu_model = "cortex-a15", 206 .memmap = a15memmap, 207 .irqmap = a15irqmap, 208 }, 209 { 210 .cpu_model = "cortex-a53", 211 .memmap = a15memmap, 212 .irqmap = a15irqmap, 213 }, 214 { 215 .cpu_model = "cortex-a57", 216 .memmap = a15memmap, 217 .irqmap = a15irqmap, 218 }, 219 { 220 .cpu_model = "host", 221 .memmap = a15memmap, 222 .irqmap = a15irqmap, 223 }, 224 }; 225 226 static VirtBoardInfo *find_machine_info(const char *cpu) 227 { 228 int i; 229 230 for (i = 0; i < ARRAY_SIZE(machines); i++) { 231 if (strcmp(cpu, machines[i].cpu_model) == 0) { 232 return &machines[i]; 233 } 234 } 235 return NULL; 236 } 237 238 static void create_fdt(VirtBoardInfo *vbi) 239 { 240 void *fdt = create_device_tree(&vbi->fdt_size); 241 242 if (!fdt) { 243 error_report("create_device_tree() failed"); 244 exit(1); 245 } 246 247 vbi->fdt = fdt; 248 249 /* Header */ 250 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 251 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 252 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 253 254 /* 255 * /chosen and /memory nodes must exist for load_dtb 256 * to fill in necessary properties later 257 */ 258 qemu_fdt_add_subnode(fdt, "/chosen"); 259 qemu_fdt_add_subnode(fdt, "/memory"); 260 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 261 262 /* Clock node, for the benefit of the UART. The kernel device tree 263 * binding documentation claims the PL011 node clock properties are 264 * optional but in practice if you omit them the kernel refuses to 265 * probe for the device. 266 */ 267 vbi->clock_phandle = qemu_fdt_alloc_phandle(fdt); 268 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 269 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 270 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 271 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 272 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 273 "clk24mhz"); 274 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vbi->clock_phandle); 275 276 } 277 278 static void fdt_add_psci_node(const VirtBoardInfo *vbi) 279 { 280 uint32_t cpu_suspend_fn; 281 uint32_t cpu_off_fn; 282 uint32_t cpu_on_fn; 283 uint32_t migrate_fn; 284 void *fdt = vbi->fdt; 285 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); 286 287 if (!vbi->using_psci) { 288 return; 289 } 290 291 qemu_fdt_add_subnode(fdt, "/psci"); 292 if (armcpu->psci_version == 2) { 293 const char comp[] = "arm,psci-0.2\0arm,psci"; 294 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 295 296 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 297 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 298 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 299 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 300 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 301 } else { 302 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 303 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 304 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 305 } 306 } else { 307 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 308 309 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 310 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 311 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 312 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 313 } 314 315 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 316 * to the instruction that should be used to invoke PSCI functions. 317 * However, the device tree binding uses 'method' instead, so that is 318 * what we should use here. 319 */ 320 qemu_fdt_setprop_string(fdt, "/psci", "method", "hvc"); 321 322 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 323 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 324 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 325 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 326 } 327 328 static void fdt_add_timer_nodes(const VirtBoardInfo *vbi, int gictype) 329 { 330 /* Note that on A15 h/w these interrupts are level-triggered, 331 * but for the GIC implementation provided by both QEMU and KVM 332 * they are edge-triggered. 333 */ 334 ARMCPU *armcpu; 335 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 336 337 if (gictype == 2) { 338 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 339 GIC_FDT_IRQ_PPI_CPU_WIDTH, 340 (1 << vbi->smp_cpus) - 1); 341 } 342 343 qemu_fdt_add_subnode(vbi->fdt, "/timer"); 344 345 armcpu = ARM_CPU(qemu_get_cpu(0)); 346 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 347 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 348 qemu_fdt_setprop(vbi->fdt, "/timer", "compatible", 349 compat, sizeof(compat)); 350 } else { 351 qemu_fdt_setprop_string(vbi->fdt, "/timer", "compatible", 352 "arm,armv7-timer"); 353 } 354 qemu_fdt_setprop(vbi->fdt, "/timer", "always-on", NULL, 0); 355 qemu_fdt_setprop_cells(vbi->fdt, "/timer", "interrupts", 356 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, 357 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, 358 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, 359 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); 360 } 361 362 static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi) 363 { 364 int cpu; 365 int addr_cells = 1; 366 unsigned int i; 367 368 /* 369 * From Documentation/devicetree/bindings/arm/cpus.txt 370 * On ARM v8 64-bit systems value should be set to 2, 371 * that corresponds to the MPIDR_EL1 register size. 372 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 373 * in the system, #address-cells can be set to 1, since 374 * MPIDR_EL1[63:32] bits are not used for CPUs 375 * identification. 376 * 377 * Here we actually don't know whether our system is 32- or 64-bit one. 378 * The simplest way to go is to examine affinity IDs of all our CPUs. If 379 * at least one of them has Aff3 populated, we set #address-cells to 2. 380 */ 381 for (cpu = 0; cpu < vbi->smp_cpus; cpu++) { 382 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 383 384 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 385 addr_cells = 2; 386 break; 387 } 388 } 389 390 qemu_fdt_add_subnode(vbi->fdt, "/cpus"); 391 qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#address-cells", addr_cells); 392 qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#size-cells", 0x0); 393 394 for (cpu = vbi->smp_cpus - 1; cpu >= 0; cpu--) { 395 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 396 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 397 398 qemu_fdt_add_subnode(vbi->fdt, nodename); 399 qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "cpu"); 400 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", 401 armcpu->dtb_compatible); 402 403 if (vbi->using_psci && vbi->smp_cpus > 1) { 404 qemu_fdt_setprop_string(vbi->fdt, nodename, 405 "enable-method", "psci"); 406 } 407 408 if (addr_cells == 2) { 409 qemu_fdt_setprop_u64(vbi->fdt, nodename, "reg", 410 armcpu->mp_affinity); 411 } else { 412 qemu_fdt_setprop_cell(vbi->fdt, nodename, "reg", 413 armcpu->mp_affinity); 414 } 415 416 for (i = 0; i < nb_numa_nodes; i++) { 417 if (test_bit(cpu, numa_info[i].node_cpu)) { 418 qemu_fdt_setprop_cell(vbi->fdt, nodename, "numa-node-id", i); 419 } 420 } 421 422 g_free(nodename); 423 } 424 } 425 426 static void fdt_add_v2m_gic_node(VirtBoardInfo *vbi) 427 { 428 vbi->v2m_phandle = qemu_fdt_alloc_phandle(vbi->fdt); 429 qemu_fdt_add_subnode(vbi->fdt, "/intc/v2m"); 430 qemu_fdt_setprop_string(vbi->fdt, "/intc/v2m", "compatible", 431 "arm,gic-v2m-frame"); 432 qemu_fdt_setprop(vbi->fdt, "/intc/v2m", "msi-controller", NULL, 0); 433 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc/v2m", "reg", 434 2, vbi->memmap[VIRT_GIC_V2M].base, 435 2, vbi->memmap[VIRT_GIC_V2M].size); 436 qemu_fdt_setprop_cell(vbi->fdt, "/intc/v2m", "phandle", vbi->v2m_phandle); 437 } 438 439 static void fdt_add_gic_node(VirtBoardInfo *vbi, int type) 440 { 441 vbi->gic_phandle = qemu_fdt_alloc_phandle(vbi->fdt); 442 qemu_fdt_setprop_cell(vbi->fdt, "/", "interrupt-parent", vbi->gic_phandle); 443 444 qemu_fdt_add_subnode(vbi->fdt, "/intc"); 445 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#interrupt-cells", 3); 446 qemu_fdt_setprop(vbi->fdt, "/intc", "interrupt-controller", NULL, 0); 447 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#address-cells", 0x2); 448 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#size-cells", 0x2); 449 qemu_fdt_setprop(vbi->fdt, "/intc", "ranges", NULL, 0); 450 if (type == 3) { 451 qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", 452 "arm,gic-v3"); 453 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", 454 2, vbi->memmap[VIRT_GIC_DIST].base, 455 2, vbi->memmap[VIRT_GIC_DIST].size, 456 2, vbi->memmap[VIRT_GIC_REDIST].base, 457 2, vbi->memmap[VIRT_GIC_REDIST].size); 458 } else { 459 /* 'cortex-a15-gic' means 'GIC v2' */ 460 qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", 461 "arm,cortex-a15-gic"); 462 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", 463 2, vbi->memmap[VIRT_GIC_DIST].base, 464 2, vbi->memmap[VIRT_GIC_DIST].size, 465 2, vbi->memmap[VIRT_GIC_CPU].base, 466 2, vbi->memmap[VIRT_GIC_CPU].size); 467 } 468 469 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", vbi->gic_phandle); 470 } 471 472 static void fdt_add_pmu_nodes(const VirtBoardInfo *vbi, int gictype) 473 { 474 CPUState *cpu; 475 ARMCPU *armcpu; 476 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 477 478 CPU_FOREACH(cpu) { 479 armcpu = ARM_CPU(cpu); 480 if (!armcpu->has_pmu || 481 !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ))) { 482 return; 483 } 484 } 485 486 if (gictype == 2) { 487 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 488 GIC_FDT_IRQ_PPI_CPU_WIDTH, 489 (1 << vbi->smp_cpus) - 1); 490 } 491 492 armcpu = ARM_CPU(qemu_get_cpu(0)); 493 qemu_fdt_add_subnode(vbi->fdt, "/pmu"); 494 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 495 const char compat[] = "arm,armv8-pmuv3"; 496 qemu_fdt_setprop(vbi->fdt, "/pmu", "compatible", 497 compat, sizeof(compat)); 498 qemu_fdt_setprop_cells(vbi->fdt, "/pmu", "interrupts", 499 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 500 } 501 } 502 503 static void create_v2m(VirtBoardInfo *vbi, qemu_irq *pic) 504 { 505 int i; 506 int irq = vbi->irqmap[VIRT_GIC_V2M]; 507 DeviceState *dev; 508 509 dev = qdev_create(NULL, "arm-gicv2m"); 510 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vbi->memmap[VIRT_GIC_V2M].base); 511 qdev_prop_set_uint32(dev, "base-spi", irq); 512 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 513 qdev_init_nofail(dev); 514 515 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 516 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 517 } 518 519 fdt_add_v2m_gic_node(vbi); 520 } 521 522 static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic, int type, bool secure) 523 { 524 /* We create a standalone GIC */ 525 DeviceState *gicdev; 526 SysBusDevice *gicbusdev; 527 const char *gictype; 528 int i; 529 530 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 531 532 gicdev = qdev_create(NULL, gictype); 533 qdev_prop_set_uint32(gicdev, "revision", type); 534 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 535 /* Note that the num-irq property counts both internal and external 536 * interrupts; there are always 32 of the former (mandated by GIC spec). 537 */ 538 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 539 if (!kvm_irqchip_in_kernel()) { 540 qdev_prop_set_bit(gicdev, "has-security-extensions", secure); 541 } 542 qdev_init_nofail(gicdev); 543 gicbusdev = SYS_BUS_DEVICE(gicdev); 544 sysbus_mmio_map(gicbusdev, 0, vbi->memmap[VIRT_GIC_DIST].base); 545 if (type == 3) { 546 sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_REDIST].base); 547 } else { 548 sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base); 549 } 550 551 /* Wire the outputs from each CPU's generic timer to the 552 * appropriate GIC PPI inputs, and the GIC's IRQ output to 553 * the CPU's IRQ input. 554 */ 555 for (i = 0; i < smp_cpus; i++) { 556 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 557 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 558 int irq; 559 /* Mapping from the output timer irq lines from the CPU to the 560 * GIC PPI inputs we use for the virt board. 561 */ 562 const int timer_irq[] = { 563 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 564 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 565 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 566 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 567 }; 568 569 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 570 qdev_connect_gpio_out(cpudev, irq, 571 qdev_get_gpio_in(gicdev, 572 ppibase + timer_irq[irq])); 573 } 574 575 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 576 sysbus_connect_irq(gicbusdev, i + smp_cpus, 577 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 578 } 579 580 for (i = 0; i < NUM_IRQS; i++) { 581 pic[i] = qdev_get_gpio_in(gicdev, i); 582 } 583 584 fdt_add_gic_node(vbi, type); 585 586 if (type == 2) { 587 create_v2m(vbi, pic); 588 } 589 } 590 591 static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic, int uart, 592 MemoryRegion *mem, CharDriverState *chr) 593 { 594 char *nodename; 595 hwaddr base = vbi->memmap[uart].base; 596 hwaddr size = vbi->memmap[uart].size; 597 int irq = vbi->irqmap[uart]; 598 const char compat[] = "arm,pl011\0arm,primecell"; 599 const char clocknames[] = "uartclk\0apb_pclk"; 600 DeviceState *dev = qdev_create(NULL, "pl011"); 601 SysBusDevice *s = SYS_BUS_DEVICE(dev); 602 603 qdev_prop_set_chr(dev, "chardev", chr); 604 qdev_init_nofail(dev); 605 memory_region_add_subregion(mem, base, 606 sysbus_mmio_get_region(s, 0)); 607 sysbus_connect_irq(s, 0, pic[irq]); 608 609 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 610 qemu_fdt_add_subnode(vbi->fdt, nodename); 611 /* Note that we can't use setprop_string because of the embedded NUL */ 612 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", 613 compat, sizeof(compat)); 614 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 615 2, base, 2, size); 616 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 617 GIC_FDT_IRQ_TYPE_SPI, irq, 618 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 619 qemu_fdt_setprop_cells(vbi->fdt, nodename, "clocks", 620 vbi->clock_phandle, vbi->clock_phandle); 621 qemu_fdt_setprop(vbi->fdt, nodename, "clock-names", 622 clocknames, sizeof(clocknames)); 623 624 if (uart == VIRT_UART) { 625 qemu_fdt_setprop_string(vbi->fdt, "/chosen", "stdout-path", nodename); 626 } else { 627 /* Mark as not usable by the normal world */ 628 qemu_fdt_setprop_string(vbi->fdt, nodename, "status", "disabled"); 629 qemu_fdt_setprop_string(vbi->fdt, nodename, "secure-status", "okay"); 630 } 631 632 g_free(nodename); 633 } 634 635 static void create_rtc(const VirtBoardInfo *vbi, qemu_irq *pic) 636 { 637 char *nodename; 638 hwaddr base = vbi->memmap[VIRT_RTC].base; 639 hwaddr size = vbi->memmap[VIRT_RTC].size; 640 int irq = vbi->irqmap[VIRT_RTC]; 641 const char compat[] = "arm,pl031\0arm,primecell"; 642 643 sysbus_create_simple("pl031", base, pic[irq]); 644 645 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 646 qemu_fdt_add_subnode(vbi->fdt, nodename); 647 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat)); 648 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 649 2, base, 2, size); 650 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 651 GIC_FDT_IRQ_TYPE_SPI, irq, 652 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 653 qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle); 654 qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk"); 655 g_free(nodename); 656 } 657 658 static DeviceState *gpio_key_dev; 659 static void virt_powerdown_req(Notifier *n, void *opaque) 660 { 661 /* use gpio Pin 3 for power button event */ 662 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 663 } 664 665 static Notifier virt_system_powerdown_notifier = { 666 .notify = virt_powerdown_req 667 }; 668 669 static void create_gpio(const VirtBoardInfo *vbi, qemu_irq *pic) 670 { 671 char *nodename; 672 DeviceState *pl061_dev; 673 hwaddr base = vbi->memmap[VIRT_GPIO].base; 674 hwaddr size = vbi->memmap[VIRT_GPIO].size; 675 int irq = vbi->irqmap[VIRT_GPIO]; 676 const char compat[] = "arm,pl061\0arm,primecell"; 677 678 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); 679 680 uint32_t phandle = qemu_fdt_alloc_phandle(vbi->fdt); 681 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 682 qemu_fdt_add_subnode(vbi->fdt, nodename); 683 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 684 2, base, 2, size); 685 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat)); 686 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#gpio-cells", 2); 687 qemu_fdt_setprop(vbi->fdt, nodename, "gpio-controller", NULL, 0); 688 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 689 GIC_FDT_IRQ_TYPE_SPI, irq, 690 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 691 qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle); 692 qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk"); 693 qemu_fdt_setprop_cell(vbi->fdt, nodename, "phandle", phandle); 694 695 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 696 qdev_get_gpio_in(pl061_dev, 3)); 697 qemu_fdt_add_subnode(vbi->fdt, "/gpio-keys"); 698 qemu_fdt_setprop_string(vbi->fdt, "/gpio-keys", "compatible", "gpio-keys"); 699 qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys", "#size-cells", 0); 700 qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys", "#address-cells", 1); 701 702 qemu_fdt_add_subnode(vbi->fdt, "/gpio-keys/poweroff"); 703 qemu_fdt_setprop_string(vbi->fdt, "/gpio-keys/poweroff", 704 "label", "GPIO Key Poweroff"); 705 qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys/poweroff", "linux,code", 706 KEY_POWER); 707 qemu_fdt_setprop_cells(vbi->fdt, "/gpio-keys/poweroff", 708 "gpios", phandle, 3, 0); 709 710 /* connect powerdown request */ 711 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier); 712 713 g_free(nodename); 714 } 715 716 static void create_virtio_devices(const VirtBoardInfo *vbi, qemu_irq *pic) 717 { 718 int i; 719 hwaddr size = vbi->memmap[VIRT_MMIO].size; 720 721 /* We create the transports in forwards order. Since qbus_realize() 722 * prepends (not appends) new child buses, the incrementing loop below will 723 * create a list of virtio-mmio buses with decreasing base addresses. 724 * 725 * When a -device option is processed from the command line, 726 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 727 * order. The upshot is that -device options in increasing command line 728 * order are mapped to virtio-mmio buses with decreasing base addresses. 729 * 730 * When this code was originally written, that arrangement ensured that the 731 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 732 * the first -device on the command line. (The end-to-end order is a 733 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 734 * guest kernel's name-to-address assignment strategy.) 735 * 736 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 737 * the message, if not necessarily the code, of commit 70161ff336. 738 * Therefore the loop now establishes the inverse of the original intent. 739 * 740 * Unfortunately, we can't counteract the kernel change by reversing the 741 * loop; it would break existing command lines. 742 * 743 * In any case, the kernel makes no guarantee about the stability of 744 * enumeration order of virtio devices (as demonstrated by it changing 745 * between kernel versions). For reliable and stable identification 746 * of disks users must use UUIDs or similar mechanisms. 747 */ 748 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 749 int irq = vbi->irqmap[VIRT_MMIO] + i; 750 hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size; 751 752 sysbus_create_simple("virtio-mmio", base, pic[irq]); 753 } 754 755 /* We add dtb nodes in reverse order so that they appear in the finished 756 * device tree lowest address first. 757 * 758 * Note that this mapping is independent of the loop above. The previous 759 * loop influences virtio device to virtio transport assignment, whereas 760 * this loop controls how virtio transports are laid out in the dtb. 761 */ 762 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 763 char *nodename; 764 int irq = vbi->irqmap[VIRT_MMIO] + i; 765 hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size; 766 767 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 768 qemu_fdt_add_subnode(vbi->fdt, nodename); 769 qemu_fdt_setprop_string(vbi->fdt, nodename, 770 "compatible", "virtio,mmio"); 771 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 772 2, base, 2, size); 773 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", 774 GIC_FDT_IRQ_TYPE_SPI, irq, 775 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 776 g_free(nodename); 777 } 778 } 779 780 static void create_one_flash(const char *name, hwaddr flashbase, 781 hwaddr flashsize, const char *file, 782 MemoryRegion *sysmem) 783 { 784 /* Create and map a single flash device. We use the same 785 * parameters as the flash devices on the Versatile Express board. 786 */ 787 DriveInfo *dinfo = drive_get_next(IF_PFLASH); 788 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 789 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 790 const uint64_t sectorlength = 256 * 1024; 791 792 if (dinfo) { 793 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 794 &error_abort); 795 } 796 797 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); 798 qdev_prop_set_uint64(dev, "sector-length", sectorlength); 799 qdev_prop_set_uint8(dev, "width", 4); 800 qdev_prop_set_uint8(dev, "device-width", 2); 801 qdev_prop_set_bit(dev, "big-endian", false); 802 qdev_prop_set_uint16(dev, "id0", 0x89); 803 qdev_prop_set_uint16(dev, "id1", 0x18); 804 qdev_prop_set_uint16(dev, "id2", 0x00); 805 qdev_prop_set_uint16(dev, "id3", 0x00); 806 qdev_prop_set_string(dev, "name", name); 807 qdev_init_nofail(dev); 808 809 memory_region_add_subregion(sysmem, flashbase, 810 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 811 812 if (file) { 813 char *fn; 814 int image_size; 815 816 if (drive_get(IF_PFLASH, 0, 0)) { 817 error_report("The contents of the first flash device may be " 818 "specified with -bios or with -drive if=pflash... " 819 "but you cannot use both options at once"); 820 exit(1); 821 } 822 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file); 823 if (!fn) { 824 error_report("Could not find ROM image '%s'", file); 825 exit(1); 826 } 827 image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0)); 828 g_free(fn); 829 if (image_size < 0) { 830 error_report("Could not load ROM image '%s'", file); 831 exit(1); 832 } 833 } 834 } 835 836 static void create_flash(const VirtBoardInfo *vbi, 837 MemoryRegion *sysmem, 838 MemoryRegion *secure_sysmem) 839 { 840 /* Create two flash devices to fill the VIRT_FLASH space in the memmap. 841 * Any file passed via -bios goes in the first of these. 842 * sysmem is the system memory space. secure_sysmem is the secure view 843 * of the system, and the first flash device should be made visible only 844 * there. The second flash device is visible to both secure and nonsecure. 845 * If sysmem == secure_sysmem this means there is no separate Secure 846 * address space and both flash devices are generally visible. 847 */ 848 hwaddr flashsize = vbi->memmap[VIRT_FLASH].size / 2; 849 hwaddr flashbase = vbi->memmap[VIRT_FLASH].base; 850 char *nodename; 851 852 create_one_flash("virt.flash0", flashbase, flashsize, 853 bios_name, secure_sysmem); 854 create_one_flash("virt.flash1", flashbase + flashsize, flashsize, 855 NULL, sysmem); 856 857 if (sysmem == secure_sysmem) { 858 /* Report both flash devices as a single node in the DT */ 859 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 860 qemu_fdt_add_subnode(vbi->fdt, nodename); 861 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash"); 862 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 863 2, flashbase, 2, flashsize, 864 2, flashbase + flashsize, 2, flashsize); 865 qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4); 866 g_free(nodename); 867 } else { 868 /* Report the devices as separate nodes so we can mark one as 869 * only visible to the secure world. 870 */ 871 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 872 qemu_fdt_add_subnode(vbi->fdt, nodename); 873 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash"); 874 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 875 2, flashbase, 2, flashsize); 876 qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4); 877 qemu_fdt_setprop_string(vbi->fdt, nodename, "status", "disabled"); 878 qemu_fdt_setprop_string(vbi->fdt, nodename, "secure-status", "okay"); 879 g_free(nodename); 880 881 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 882 qemu_fdt_add_subnode(vbi->fdt, nodename); 883 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash"); 884 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 885 2, flashbase + flashsize, 2, flashsize); 886 qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4); 887 g_free(nodename); 888 } 889 } 890 891 static void create_fw_cfg(const VirtBoardInfo *vbi, AddressSpace *as) 892 { 893 hwaddr base = vbi->memmap[VIRT_FW_CFG].base; 894 hwaddr size = vbi->memmap[VIRT_FW_CFG].size; 895 char *nodename; 896 897 fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 898 899 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 900 qemu_fdt_add_subnode(vbi->fdt, nodename); 901 qemu_fdt_setprop_string(vbi->fdt, nodename, 902 "compatible", "qemu,fw-cfg-mmio"); 903 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 904 2, base, 2, size); 905 g_free(nodename); 906 } 907 908 static void create_pcie_irq_map(const VirtBoardInfo *vbi, uint32_t gic_phandle, 909 int first_irq, const char *nodename) 910 { 911 int devfn, pin; 912 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 913 uint32_t *irq_map = full_irq_map; 914 915 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 916 for (pin = 0; pin < 4; pin++) { 917 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 918 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 919 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 920 int i; 921 922 uint32_t map[] = { 923 devfn << 8, 0, 0, /* devfn */ 924 pin + 1, /* PCI pin */ 925 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 926 927 /* Convert map to big endian */ 928 for (i = 0; i < 10; i++) { 929 irq_map[i] = cpu_to_be32(map[i]); 930 } 931 irq_map += 10; 932 } 933 } 934 935 qemu_fdt_setprop(vbi->fdt, nodename, "interrupt-map", 936 full_irq_map, sizeof(full_irq_map)); 937 938 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupt-map-mask", 939 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 940 0x7 /* PCI irq */); 941 } 942 943 static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic, 944 bool use_highmem) 945 { 946 hwaddr base_mmio = vbi->memmap[VIRT_PCIE_MMIO].base; 947 hwaddr size_mmio = vbi->memmap[VIRT_PCIE_MMIO].size; 948 hwaddr base_mmio_high = vbi->memmap[VIRT_PCIE_MMIO_HIGH].base; 949 hwaddr size_mmio_high = vbi->memmap[VIRT_PCIE_MMIO_HIGH].size; 950 hwaddr base_pio = vbi->memmap[VIRT_PCIE_PIO].base; 951 hwaddr size_pio = vbi->memmap[VIRT_PCIE_PIO].size; 952 hwaddr base_ecam = vbi->memmap[VIRT_PCIE_ECAM].base; 953 hwaddr size_ecam = vbi->memmap[VIRT_PCIE_ECAM].size; 954 hwaddr base = base_mmio; 955 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 956 int irq = vbi->irqmap[VIRT_PCIE]; 957 MemoryRegion *mmio_alias; 958 MemoryRegion *mmio_reg; 959 MemoryRegion *ecam_alias; 960 MemoryRegion *ecam_reg; 961 DeviceState *dev; 962 char *nodename; 963 int i; 964 PCIHostState *pci; 965 966 dev = qdev_create(NULL, TYPE_GPEX_HOST); 967 qdev_init_nofail(dev); 968 969 /* Map only the first size_ecam bytes of ECAM space */ 970 ecam_alias = g_new0(MemoryRegion, 1); 971 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 972 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 973 ecam_reg, 0, size_ecam); 974 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 975 976 /* Map the MMIO window into system address space so as to expose 977 * the section of PCI MMIO space which starts at the same base address 978 * (ie 1:1 mapping for that part of PCI MMIO space visible through 979 * the window). 980 */ 981 mmio_alias = g_new0(MemoryRegion, 1); 982 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 983 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 984 mmio_reg, base_mmio, size_mmio); 985 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 986 987 if (use_highmem) { 988 /* Map high MMIO space */ 989 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 990 991 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 992 mmio_reg, base_mmio_high, size_mmio_high); 993 memory_region_add_subregion(get_system_memory(), base_mmio_high, 994 high_mmio_alias); 995 } 996 997 /* Map IO port space */ 998 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 999 1000 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1001 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 1002 } 1003 1004 pci = PCI_HOST_BRIDGE(dev); 1005 if (pci->bus) { 1006 for (i = 0; i < nb_nics; i++) { 1007 NICInfo *nd = &nd_table[i]; 1008 1009 if (!nd->model) { 1010 nd->model = g_strdup("virtio"); 1011 } 1012 1013 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 1014 } 1015 } 1016 1017 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1018 qemu_fdt_add_subnode(vbi->fdt, nodename); 1019 qemu_fdt_setprop_string(vbi->fdt, nodename, 1020 "compatible", "pci-host-ecam-generic"); 1021 qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "pci"); 1022 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#address-cells", 3); 1023 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#size-cells", 2); 1024 qemu_fdt_setprop_cells(vbi->fdt, nodename, "bus-range", 0, 1025 nr_pcie_buses - 1); 1026 qemu_fdt_setprop(vbi->fdt, nodename, "dma-coherent", NULL, 0); 1027 1028 if (vbi->v2m_phandle) { 1029 qemu_fdt_setprop_cells(vbi->fdt, nodename, "msi-parent", 1030 vbi->v2m_phandle); 1031 } 1032 1033 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 1034 2, base_ecam, 2, size_ecam); 1035 1036 if (use_highmem) { 1037 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges", 1038 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1039 2, base_pio, 2, size_pio, 1040 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1041 2, base_mmio, 2, size_mmio, 1042 1, FDT_PCI_RANGE_MMIO_64BIT, 1043 2, base_mmio_high, 1044 2, base_mmio_high, 2, size_mmio_high); 1045 } else { 1046 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges", 1047 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1048 2, base_pio, 2, size_pio, 1049 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1050 2, base_mmio, 2, size_mmio); 1051 } 1052 1053 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#interrupt-cells", 1); 1054 create_pcie_irq_map(vbi, vbi->gic_phandle, irq, nodename); 1055 1056 g_free(nodename); 1057 } 1058 1059 static void create_platform_bus(VirtBoardInfo *vbi, qemu_irq *pic) 1060 { 1061 DeviceState *dev; 1062 SysBusDevice *s; 1063 int i; 1064 ARMPlatformBusFDTParams *fdt_params = g_new(ARMPlatformBusFDTParams, 1); 1065 MemoryRegion *sysmem = get_system_memory(); 1066 1067 platform_bus_params.platform_bus_base = vbi->memmap[VIRT_PLATFORM_BUS].base; 1068 platform_bus_params.platform_bus_size = vbi->memmap[VIRT_PLATFORM_BUS].size; 1069 platform_bus_params.platform_bus_first_irq = vbi->irqmap[VIRT_PLATFORM_BUS]; 1070 platform_bus_params.platform_bus_num_irqs = PLATFORM_BUS_NUM_IRQS; 1071 1072 fdt_params->system_params = &platform_bus_params; 1073 fdt_params->binfo = &vbi->bootinfo; 1074 fdt_params->intc = "/intc"; 1075 /* 1076 * register a machine init done notifier that creates the device tree 1077 * nodes of the platform bus and its children dynamic sysbus devices 1078 */ 1079 arm_register_platform_bus_fdt_creator(fdt_params); 1080 1081 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1082 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1083 qdev_prop_set_uint32(dev, "num_irqs", 1084 platform_bus_params.platform_bus_num_irqs); 1085 qdev_prop_set_uint32(dev, "mmio_size", 1086 platform_bus_params.platform_bus_size); 1087 qdev_init_nofail(dev); 1088 s = SYS_BUS_DEVICE(dev); 1089 1090 for (i = 0; i < platform_bus_params.platform_bus_num_irqs; i++) { 1091 int irqn = platform_bus_params.platform_bus_first_irq + i; 1092 sysbus_connect_irq(s, i, pic[irqn]); 1093 } 1094 1095 memory_region_add_subregion(sysmem, 1096 platform_bus_params.platform_bus_base, 1097 sysbus_mmio_get_region(s, 0)); 1098 } 1099 1100 static void create_secure_ram(VirtBoardInfo *vbi, MemoryRegion *secure_sysmem) 1101 { 1102 MemoryRegion *secram = g_new(MemoryRegion, 1); 1103 char *nodename; 1104 hwaddr base = vbi->memmap[VIRT_SECURE_MEM].base; 1105 hwaddr size = vbi->memmap[VIRT_SECURE_MEM].size; 1106 1107 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, &error_fatal); 1108 vmstate_register_ram_global(secram); 1109 memory_region_add_subregion(secure_sysmem, base, secram); 1110 1111 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1112 qemu_fdt_add_subnode(vbi->fdt, nodename); 1113 qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "memory"); 1114 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 2, base, 2, size); 1115 qemu_fdt_setprop_string(vbi->fdt, nodename, "status", "disabled"); 1116 qemu_fdt_setprop_string(vbi->fdt, nodename, "secure-status", "okay"); 1117 1118 g_free(nodename); 1119 } 1120 1121 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1122 { 1123 const VirtBoardInfo *board = (const VirtBoardInfo *)binfo; 1124 1125 *fdt_size = board->fdt_size; 1126 return board->fdt; 1127 } 1128 1129 static void virt_build_smbios(VirtGuestInfo *guest_info) 1130 { 1131 FWCfgState *fw_cfg = guest_info->fw_cfg; 1132 uint8_t *smbios_tables, *smbios_anchor; 1133 size_t smbios_tables_len, smbios_anchor_len; 1134 const char *product = "QEMU Virtual Machine"; 1135 1136 if (!fw_cfg) { 1137 return; 1138 } 1139 1140 if (kvm_enabled()) { 1141 product = "KVM Virtual Machine"; 1142 } 1143 1144 smbios_set_defaults("QEMU", product, 1145 "1.0", false, true, SMBIOS_ENTRY_POINT_30); 1146 1147 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, 1148 &smbios_anchor, &smbios_anchor_len); 1149 1150 if (smbios_anchor) { 1151 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 1152 smbios_tables, smbios_tables_len); 1153 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 1154 smbios_anchor, smbios_anchor_len); 1155 } 1156 } 1157 1158 static 1159 void virt_guest_info_machine_done(Notifier *notifier, void *data) 1160 { 1161 VirtGuestInfoState *guest_info_state = container_of(notifier, 1162 VirtGuestInfoState, machine_done); 1163 virt_acpi_setup(&guest_info_state->info); 1164 virt_build_smbios(&guest_info_state->info); 1165 } 1166 1167 static void machvirt_init(MachineState *machine) 1168 { 1169 VirtMachineState *vms = VIRT_MACHINE(machine); 1170 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 1171 qemu_irq pic[NUM_IRQS]; 1172 MemoryRegion *sysmem = get_system_memory(); 1173 MemoryRegion *secure_sysmem = NULL; 1174 int gic_version = vms->gic_version; 1175 int n, virt_max_cpus; 1176 MemoryRegion *ram = g_new(MemoryRegion, 1); 1177 const char *cpu_model = machine->cpu_model; 1178 VirtBoardInfo *vbi; 1179 VirtGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1180 VirtGuestInfo *guest_info = &guest_info_state->info; 1181 char **cpustr; 1182 ObjectClass *oc; 1183 const char *typename; 1184 CPUClass *cc; 1185 Error *err = NULL; 1186 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); 1187 uint8_t clustersz; 1188 1189 if (!cpu_model) { 1190 cpu_model = "cortex-a15"; 1191 } 1192 1193 /* We can probe only here because during property set 1194 * KVM is not available yet 1195 */ 1196 if (!gic_version) { 1197 if (!kvm_enabled()) { 1198 error_report("gic-version=host requires KVM"); 1199 exit(1); 1200 } 1201 1202 gic_version = kvm_arm_vgic_probe(); 1203 if (!gic_version) { 1204 error_report("Unable to determine GIC version supported by host"); 1205 exit(1); 1206 } 1207 } 1208 1209 /* Separate the actual CPU model name from any appended features */ 1210 cpustr = g_strsplit(cpu_model, ",", 2); 1211 1212 vbi = find_machine_info(cpustr[0]); 1213 1214 if (!vbi) { 1215 error_report("mach-virt: CPU %s not supported", cpustr[0]); 1216 exit(1); 1217 } 1218 1219 /* If we have an EL3 boot ROM then the assumption is that it will 1220 * implement PSCI itself, so disable QEMU's internal implementation 1221 * so it doesn't get in the way. Instead of starting secondary 1222 * CPUs in PSCI powerdown state we will start them all running and 1223 * let the boot ROM sort them out. 1224 * The usual case is that we do use QEMU's PSCI implementation. 1225 */ 1226 vbi->using_psci = !(vms->secure && firmware_loaded); 1227 1228 /* The maximum number of CPUs depends on the GIC version, or on how 1229 * many redistributors we can fit into the memory map. 1230 */ 1231 if (gic_version == 3) { 1232 virt_max_cpus = vbi->memmap[VIRT_GIC_REDIST].size / 0x20000; 1233 clustersz = GICV3_TARGETLIST_BITS; 1234 } else { 1235 virt_max_cpus = GIC_NCPU; 1236 clustersz = GIC_TARGETLIST_BITS; 1237 } 1238 1239 if (max_cpus > virt_max_cpus) { 1240 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 1241 "supported by machine 'mach-virt' (%d)", 1242 max_cpus, virt_max_cpus); 1243 exit(1); 1244 } 1245 1246 vbi->smp_cpus = smp_cpus; 1247 1248 if (machine->ram_size > vbi->memmap[VIRT_MEM].size) { 1249 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB); 1250 exit(1); 1251 } 1252 1253 if (vms->secure) { 1254 if (kvm_enabled()) { 1255 error_report("mach-virt: KVM does not support Security extensions"); 1256 exit(1); 1257 } 1258 1259 /* The Secure view of the world is the same as the NonSecure, 1260 * but with a few extra devices. Create it as a container region 1261 * containing the system memory at low priority; any secure-only 1262 * devices go in at higher priority and take precedence. 1263 */ 1264 secure_sysmem = g_new(MemoryRegion, 1); 1265 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 1266 UINT64_MAX); 1267 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 1268 } 1269 1270 create_fdt(vbi); 1271 1272 oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); 1273 if (!oc) { 1274 error_report("Unable to find CPU definition"); 1275 exit(1); 1276 } 1277 typename = object_class_get_name(oc); 1278 1279 /* convert -smp CPU options specified by the user into global props */ 1280 cc = CPU_CLASS(oc); 1281 cc->parse_features(typename, cpustr[1], &err); 1282 g_strfreev(cpustr); 1283 if (err) { 1284 error_report_err(err); 1285 exit(1); 1286 } 1287 1288 for (n = 0; n < smp_cpus; n++) { 1289 Object *cpuobj = object_new(typename); 1290 if (!vmc->disallow_affinity_adjustment) { 1291 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1292 * GIC's target-list limitations. 32-bit KVM hosts currently 1293 * always create clusters of 4 CPUs, but that is expected to 1294 * change when they gain support for gicv3. When KVM is enabled 1295 * it will override the changes we make here, therefore our 1296 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1297 * and to improve SGI efficiency. 1298 */ 1299 uint8_t aff1 = n / clustersz; 1300 uint8_t aff0 = n % clustersz; 1301 object_property_set_int(cpuobj, (aff1 << ARM_AFF1_SHIFT) | aff0, 1302 "mp-affinity", NULL); 1303 } 1304 1305 if (!vms->secure) { 1306 object_property_set_bool(cpuobj, false, "has_el3", NULL); 1307 } 1308 1309 if (vbi->using_psci) { 1310 object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_HVC, 1311 "psci-conduit", NULL); 1312 1313 /* Secondary CPUs start in PSCI powered-down state */ 1314 if (n > 0) { 1315 object_property_set_bool(cpuobj, true, 1316 "start-powered-off", NULL); 1317 } 1318 } 1319 1320 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1321 object_property_set_int(cpuobj, vbi->memmap[VIRT_CPUPERIPHS].base, 1322 "reset-cbar", &error_abort); 1323 } 1324 1325 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1326 &error_abort); 1327 if (vms->secure) { 1328 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1329 "secure-memory", &error_abort); 1330 } 1331 1332 object_property_set_bool(cpuobj, true, "realized", NULL); 1333 } 1334 fdt_add_timer_nodes(vbi, gic_version); 1335 fdt_add_cpu_nodes(vbi); 1336 fdt_add_psci_node(vbi); 1337 1338 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", 1339 machine->ram_size); 1340 memory_region_add_subregion(sysmem, vbi->memmap[VIRT_MEM].base, ram); 1341 1342 create_flash(vbi, sysmem, secure_sysmem ? secure_sysmem : sysmem); 1343 1344 create_gic(vbi, pic, gic_version, vms->secure); 1345 1346 fdt_add_pmu_nodes(vbi, gic_version); 1347 1348 create_uart(vbi, pic, VIRT_UART, sysmem, serial_hds[0]); 1349 1350 if (vms->secure) { 1351 create_secure_ram(vbi, secure_sysmem); 1352 create_uart(vbi, pic, VIRT_SECURE_UART, secure_sysmem, serial_hds[1]); 1353 } 1354 1355 create_rtc(vbi, pic); 1356 1357 create_pcie(vbi, pic, vms->highmem); 1358 1359 create_gpio(vbi, pic); 1360 1361 /* Create mmio transports, so the user can create virtio backends 1362 * (which will be automatically plugged in to the transports). If 1363 * no backend is created the transport will just sit harmlessly idle. 1364 */ 1365 create_virtio_devices(vbi, pic); 1366 1367 create_fw_cfg(vbi, &address_space_memory); 1368 rom_set_fw(fw_cfg_find()); 1369 1370 guest_info->smp_cpus = smp_cpus; 1371 guest_info->fw_cfg = fw_cfg_find(); 1372 guest_info->memmap = vbi->memmap; 1373 guest_info->irqmap = vbi->irqmap; 1374 guest_info->use_highmem = vms->highmem; 1375 guest_info->gic_version = gic_version; 1376 guest_info_state->machine_done.notify = virt_guest_info_machine_done; 1377 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1378 1379 vbi->bootinfo.ram_size = machine->ram_size; 1380 vbi->bootinfo.kernel_filename = machine->kernel_filename; 1381 vbi->bootinfo.kernel_cmdline = machine->kernel_cmdline; 1382 vbi->bootinfo.initrd_filename = machine->initrd_filename; 1383 vbi->bootinfo.nb_cpus = smp_cpus; 1384 vbi->bootinfo.board_id = -1; 1385 vbi->bootinfo.loader_start = vbi->memmap[VIRT_MEM].base; 1386 vbi->bootinfo.get_dtb = machvirt_dtb; 1387 vbi->bootinfo.firmware_loaded = firmware_loaded; 1388 arm_load_kernel(ARM_CPU(first_cpu), &vbi->bootinfo); 1389 1390 /* 1391 * arm_load_kernel machine init done notifier registration must 1392 * happen before the platform_bus_create call. In this latter, 1393 * another notifier is registered which adds platform bus nodes. 1394 * Notifiers are executed in registration reverse order. 1395 */ 1396 create_platform_bus(vbi, pic); 1397 } 1398 1399 static bool virt_get_secure(Object *obj, Error **errp) 1400 { 1401 VirtMachineState *vms = VIRT_MACHINE(obj); 1402 1403 return vms->secure; 1404 } 1405 1406 static void virt_set_secure(Object *obj, bool value, Error **errp) 1407 { 1408 VirtMachineState *vms = VIRT_MACHINE(obj); 1409 1410 vms->secure = value; 1411 } 1412 1413 static bool virt_get_highmem(Object *obj, Error **errp) 1414 { 1415 VirtMachineState *vms = VIRT_MACHINE(obj); 1416 1417 return vms->highmem; 1418 } 1419 1420 static void virt_set_highmem(Object *obj, bool value, Error **errp) 1421 { 1422 VirtMachineState *vms = VIRT_MACHINE(obj); 1423 1424 vms->highmem = value; 1425 } 1426 1427 static char *virt_get_gic_version(Object *obj, Error **errp) 1428 { 1429 VirtMachineState *vms = VIRT_MACHINE(obj); 1430 const char *val = vms->gic_version == 3 ? "3" : "2"; 1431 1432 return g_strdup(val); 1433 } 1434 1435 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 1436 { 1437 VirtMachineState *vms = VIRT_MACHINE(obj); 1438 1439 if (!strcmp(value, "3")) { 1440 vms->gic_version = 3; 1441 } else if (!strcmp(value, "2")) { 1442 vms->gic_version = 2; 1443 } else if (!strcmp(value, "host")) { 1444 vms->gic_version = 0; /* Will probe later */ 1445 } else { 1446 error_setg(errp, "Invalid gic-version value"); 1447 error_append_hint(errp, "Valid values are 3, 2, host.\n"); 1448 } 1449 } 1450 1451 static void virt_machine_class_init(ObjectClass *oc, void *data) 1452 { 1453 MachineClass *mc = MACHINE_CLASS(oc); 1454 1455 mc->init = machvirt_init; 1456 /* Start max_cpus at the maximum QEMU supports. We'll further restrict 1457 * it later in machvirt_init, where we have more information about the 1458 * configuration of the particular instance. 1459 */ 1460 mc->max_cpus = MAX_CPUMASK_BITS; 1461 mc->has_dynamic_sysbus = true; 1462 mc->block_default_type = IF_VIRTIO; 1463 mc->no_cdrom = 1; 1464 mc->pci_allow_0_address = true; 1465 } 1466 1467 static const TypeInfo virt_machine_info = { 1468 .name = TYPE_VIRT_MACHINE, 1469 .parent = TYPE_MACHINE, 1470 .abstract = true, 1471 .instance_size = sizeof(VirtMachineState), 1472 .class_size = sizeof(VirtMachineClass), 1473 .class_init = virt_machine_class_init, 1474 }; 1475 1476 static void machvirt_machine_init(void) 1477 { 1478 type_register_static(&virt_machine_info); 1479 } 1480 type_init(machvirt_machine_init); 1481 1482 static void virt_2_7_instance_init(Object *obj) 1483 { 1484 VirtMachineState *vms = VIRT_MACHINE(obj); 1485 1486 /* EL3 is disabled by default on virt: this makes us consistent 1487 * between KVM and TCG for this board, and it also allows us to 1488 * boot UEFI blobs which assume no TrustZone support. 1489 */ 1490 vms->secure = false; 1491 object_property_add_bool(obj, "secure", virt_get_secure, 1492 virt_set_secure, NULL); 1493 object_property_set_description(obj, "secure", 1494 "Set on/off to enable/disable the ARM " 1495 "Security Extensions (TrustZone)", 1496 NULL); 1497 1498 /* High memory is enabled by default */ 1499 vms->highmem = true; 1500 object_property_add_bool(obj, "highmem", virt_get_highmem, 1501 virt_set_highmem, NULL); 1502 object_property_set_description(obj, "highmem", 1503 "Set on/off to enable/disable using " 1504 "physical address space above 32 bits", 1505 NULL); 1506 /* Default GIC type is v2 */ 1507 vms->gic_version = 2; 1508 object_property_add_str(obj, "gic-version", virt_get_gic_version, 1509 virt_set_gic_version, NULL); 1510 object_property_set_description(obj, "gic-version", 1511 "Set GIC version. " 1512 "Valid values are 2, 3 and host", NULL); 1513 } 1514 1515 static void virt_machine_2_7_options(MachineClass *mc) 1516 { 1517 } 1518 DEFINE_VIRT_MACHINE_AS_LATEST(2, 7) 1519 1520 #define VIRT_COMPAT_2_6 \ 1521 HW_COMPAT_2_6 1522 1523 static void virt_2_6_instance_init(Object *obj) 1524 { 1525 virt_2_7_instance_init(obj); 1526 } 1527 1528 static void virt_machine_2_6_options(MachineClass *mc) 1529 { 1530 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 1531 1532 virt_machine_2_7_options(mc); 1533 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6); 1534 vmc->disallow_affinity_adjustment = true; 1535 } 1536 DEFINE_VIRT_MACHINE(2, 6) 1537