xref: /openbmc/qemu/hw/arm/virt-acpi-build.c (revision f7ceab1e)
1 /* Support for generating ACPI tables and passing them to Guests
2  *
3  * ARM virt ACPI generation
4  *
5  * Copyright (C) 2008-2010  Kevin O'Connor <kevin@koconnor.net>
6  * Copyright (C) 2006 Fabrice Bellard
7  * Copyright (C) 2013 Red Hat Inc
8  *
9  * Author: Michael S. Tsirkin <mst@redhat.com>
10  *
11  * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
12  *
13  * Author: Shannon Zhao <zhaoshenglong@huawei.com>
14  *
15  * This program is free software; you can redistribute it and/or modify
16  * it under the terms of the GNU General Public License as published by
17  * the Free Software Foundation; either version 2 of the License, or
18  * (at your option) any later version.
19 
20  * This program is distributed in the hope that it will be useful,
21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23  * GNU General Public License for more details.
24 
25  * You should have received a copy of the GNU General Public License along
26  * with this program; if not, see <http://www.gnu.org/licenses/>.
27  */
28 
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "qemu/bitmap.h"
32 #include "qemu/error-report.h"
33 #include "trace.h"
34 #include "hw/core/cpu.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/nvram/fw_cfg_acpi.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/acpi/aml-build.h"
40 #include "hw/acpi/utils.h"
41 #include "hw/acpi/pci.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "hw/acpi/generic_event_device.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/hmat.h"
46 #include "hw/pci/pcie_host.h"
47 #include "hw/pci/pci.h"
48 #include "hw/pci/pci_bus.h"
49 #include "hw/pci-host/gpex.h"
50 #include "hw/arm/virt.h"
51 #include "hw/intc/arm_gicv3_its_common.h"
52 #include "hw/mem/nvdimm.h"
53 #include "hw/platform-bus.h"
54 #include "sysemu/numa.h"
55 #include "sysemu/reset.h"
56 #include "sysemu/tpm.h"
57 #include "migration/vmstate.h"
58 #include "hw/acpi/ghes.h"
59 #include "hw/acpi/viot.h"
60 #include "hw/virtio/virtio-acpi.h"
61 #include "target/arm/multiprocessing.h"
62 
63 #define ARM_SPI_BASE 32
64 
65 #define ACPI_BUILD_TABLE_SIZE             0x20000
66 
67 static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms)
68 {
69     MachineState *ms = MACHINE(vms);
70     uint16_t i;
71 
72     for (i = 0; i < ms->smp.cpus; i++) {
73         Aml *dev = aml_device("C%.03X", i);
74         aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
75         aml_append(dev, aml_name_decl("_UID", aml_int(i)));
76         aml_append(scope, dev);
77     }
78 }
79 
80 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
81                                uint32_t uart_irq, int uartidx)
82 {
83     Aml *dev = aml_device("COM%d", uartidx);
84     aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
85     aml_append(dev, aml_name_decl("_UID", aml_int(uartidx)));
86 
87     Aml *crs = aml_resource_template();
88     aml_append(crs, aml_memory32_fixed(uart_memmap->base,
89                                        uart_memmap->size, AML_READ_WRITE));
90     aml_append(crs,
91                aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
92                              AML_EXCLUSIVE, &uart_irq, 1));
93     aml_append(dev, aml_name_decl("_CRS", crs));
94 
95     aml_append(scope, dev);
96 }
97 
98 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
99 {
100     Aml *dev, *crs;
101     hwaddr base = flash_memmap->base;
102     hwaddr size = flash_memmap->size / 2;
103 
104     dev = aml_device("FLS0");
105     aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
106     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
107 
108     crs = aml_resource_template();
109     aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
110     aml_append(dev, aml_name_decl("_CRS", crs));
111     aml_append(scope, dev);
112 
113     dev = aml_device("FLS1");
114     aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
115     aml_append(dev, aml_name_decl("_UID", aml_int(1)));
116     crs = aml_resource_template();
117     aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE));
118     aml_append(dev, aml_name_decl("_CRS", crs));
119     aml_append(scope, dev);
120 }
121 
122 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
123                               uint32_t irq, VirtMachineState *vms)
124 {
125     int ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
126     struct GPEXConfig cfg = {
127         .mmio32 = memmap[VIRT_PCIE_MMIO],
128         .pio    = memmap[VIRT_PCIE_PIO],
129         .ecam   = memmap[ecam_id],
130         .irq    = irq,
131         .bus    = vms->bus,
132     };
133 
134     if (vms->highmem_mmio) {
135         cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO];
136     }
137 
138     acpi_dsdt_add_gpex(scope, &cfg);
139 }
140 
141 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
142                                            uint32_t gpio_irq)
143 {
144     Aml *dev = aml_device("GPO0");
145     aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061")));
146     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
147 
148     Aml *crs = aml_resource_template();
149     aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size,
150                                        AML_READ_WRITE));
151     aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
152                                   AML_EXCLUSIVE, &gpio_irq, 1));
153     aml_append(dev, aml_name_decl("_CRS", crs));
154 
155     Aml *aei = aml_resource_template();
156 
157     const uint32_t pin = GPIO_PIN_POWER_BUTTON;
158     aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH,
159                                  AML_EXCLUSIVE, AML_PULL_UP, 0, &pin, 1,
160                                  "GPO0", NULL, 0));
161     aml_append(dev, aml_name_decl("_AEI", aei));
162 
163     /* _E03 is handle for power button */
164     Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED);
165     aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE),
166                                   aml_int(0x80)));
167     aml_append(dev, method);
168     aml_append(scope, dev);
169 }
170 
171 #ifdef CONFIG_TPM
172 static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms)
173 {
174     PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
175     hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base;
176     SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find());
177     MemoryRegion *sbdev_mr;
178     hwaddr tpm_base;
179 
180     if (!sbdev) {
181         return;
182     }
183 
184     tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
185     assert(tpm_base != -1);
186 
187     tpm_base += pbus_base;
188 
189     sbdev_mr = sysbus_mmio_get_region(sbdev, 0);
190 
191     Aml *dev = aml_device("TPM0");
192     aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
193     aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device")));
194     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
195 
196     Aml *crs = aml_resource_template();
197     aml_append(crs,
198                aml_memory32_fixed(tpm_base,
199                                   (uint32_t)memory_region_size(sbdev_mr),
200                                   AML_READ_WRITE));
201     aml_append(dev, aml_name_decl("_CRS", crs));
202     aml_append(scope, dev);
203 }
204 #endif
205 
206 #define ID_MAPPING_ENTRY_SIZE 20
207 #define SMMU_V3_ENTRY_SIZE 68
208 #define ROOT_COMPLEX_ENTRY_SIZE 36
209 #define IORT_NODE_OFFSET 48
210 
211 /*
212  * Append an ID mapping entry as described by "Table 4 ID mapping format" in
213  * "IO Remapping Table System Software on ARM Platforms", Chapter 3.
214  * Document number: ARM DEN 0049E.f, Apr 2024
215  *
216  * Note that @id_count gets internally subtracted by one, following the spec.
217  */
218 static void build_iort_id_mapping(GArray *table_data, uint32_t input_base,
219                                   uint32_t id_count, uint32_t out_ref)
220 {
221     build_append_int_noprefix(table_data, input_base, 4); /* Input base */
222     /* Number of IDs - The number of IDs in the range minus one */
223     build_append_int_noprefix(table_data, id_count - 1, 4);
224     build_append_int_noprefix(table_data, input_base, 4); /* Output base */
225     build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference */
226     /* Flags */
227     build_append_int_noprefix(table_data, 0 /* Single mapping (disabled) */, 4);
228 }
229 
230 struct AcpiIortIdMapping {
231     uint32_t input_base;
232     uint32_t id_count;
233 };
234 typedef struct AcpiIortIdMapping AcpiIortIdMapping;
235 
236 /* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */
237 static int
238 iort_host_bridges(Object *obj, void *opaque)
239 {
240     GArray *idmap_blob = opaque;
241 
242     if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
243         PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
244 
245         if (bus && !pci_bus_bypass_iommu(bus)) {
246             int min_bus, max_bus;
247 
248             pci_bus_range(bus, &min_bus, &max_bus);
249 
250             AcpiIortIdMapping idmap = {
251                 .input_base = min_bus << 8,
252                 .id_count = (max_bus - min_bus + 1) << 8,
253             };
254             g_array_append_val(idmap_blob, idmap);
255         }
256     }
257 
258     return 0;
259 }
260 
261 static int iort_idmap_compare(gconstpointer a, gconstpointer b)
262 {
263     AcpiIortIdMapping *idmap_a = (AcpiIortIdMapping *)a;
264     AcpiIortIdMapping *idmap_b = (AcpiIortIdMapping *)b;
265 
266     return idmap_a->input_base - idmap_b->input_base;
267 }
268 
269 /*
270  * Input Output Remapping Table (IORT)
271  * Conforms to "IO Remapping Table System Software on ARM Platforms",
272  * Document number: ARM DEN 0049E.b, Feb 2021
273  */
274 static void
275 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
276 {
277     int i, nb_nodes, rc_mapping_count;
278     size_t node_size, smmu_offset = 0;
279     AcpiIortIdMapping *idmap;
280     uint32_t id = 0;
281     GArray *smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
282     GArray *its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
283 
284     AcpiTable table = { .sig = "IORT", .rev = 3, .oem_id = vms->oem_id,
285                         .oem_table_id = vms->oem_table_id };
286     /* Table 2 The IORT */
287     acpi_table_begin(&table, table_data);
288 
289     if (vms->iommu == VIRT_IOMMU_SMMUV3) {
290         AcpiIortIdMapping next_range = {0};
291 
292         object_child_foreach_recursive(object_get_root(),
293                                        iort_host_bridges, smmu_idmaps);
294 
295         /* Sort the smmu idmap by input_base */
296         g_array_sort(smmu_idmaps, iort_idmap_compare);
297 
298         /*
299          * Split the whole RIDs by mapping from RC to SMMU,
300          * build the ID mapping from RC to ITS directly.
301          */
302         for (i = 0; i < smmu_idmaps->len; i++) {
303             idmap = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i);
304 
305             if (next_range.input_base < idmap->input_base) {
306                 next_range.id_count = idmap->input_base - next_range.input_base;
307                 g_array_append_val(its_idmaps, next_range);
308             }
309 
310             next_range.input_base = idmap->input_base + idmap->id_count;
311         }
312 
313         /* Append the last RC -> ITS ID mapping */
314         if (next_range.input_base < 0x10000) {
315             next_range.id_count = 0x10000 - next_range.input_base;
316             g_array_append_val(its_idmaps, next_range);
317         }
318 
319         nb_nodes = 3; /* RC, ITS, SMMUv3 */
320         rc_mapping_count = smmu_idmaps->len + its_idmaps->len;
321     } else {
322         nb_nodes = 2; /* RC, ITS */
323         rc_mapping_count = 1;
324     }
325     /* Number of IORT Nodes */
326     build_append_int_noprefix(table_data, nb_nodes, 4);
327 
328     /* Offset to Array of IORT Nodes */
329     build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4);
330     build_append_int_noprefix(table_data, 0, 4); /* Reserved */
331 
332     /* Table 12 ITS Group Format */
333     build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */
334     node_size =  20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */;
335     build_append_int_noprefix(table_data, node_size, 2); /* Length */
336     build_append_int_noprefix(table_data, 1, 1); /* Revision */
337     build_append_int_noprefix(table_data, id++, 4); /* Identifier */
338     build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */
339     build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */
340     build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */
341     /* GIC ITS Identifier Array */
342     build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4);
343 
344     if (vms->iommu == VIRT_IOMMU_SMMUV3) {
345         int irq =  vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE;
346 
347         smmu_offset = table_data->len - table.table_offset;
348         /* Table 9 SMMUv3 Format */
349         build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type */
350         node_size =  SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE;
351         build_append_int_noprefix(table_data, node_size, 2); /* Length */
352         build_append_int_noprefix(table_data, 4, 1); /* Revision */
353         build_append_int_noprefix(table_data, id++, 4); /* Identifier */
354         build_append_int_noprefix(table_data, 1, 4); /* Number of ID mappings */
355         /* Reference to ID Array */
356         build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4);
357         /* Base address */
358         build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base, 8);
359         /* Flags */
360         build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4);
361         build_append_int_noprefix(table_data, 0, 4); /* Reserved */
362         build_append_int_noprefix(table_data, 0, 8); /* VATOS address */
363         /* Model */
364         build_append_int_noprefix(table_data, 0 /* Generic SMMU-v3 */, 4);
365         build_append_int_noprefix(table_data, irq, 4); /* Event */
366         build_append_int_noprefix(table_data, irq + 1, 4); /* PRI */
367         build_append_int_noprefix(table_data, irq + 3, 4); /* GERR */
368         build_append_int_noprefix(table_data, irq + 2, 4); /* Sync */
369         build_append_int_noprefix(table_data, 0, 4); /* Proximity domain */
370         /* DeviceID mapping index (ignored since interrupts are GSIV based) */
371         build_append_int_noprefix(table_data, 0, 4);
372 
373         /* output IORT node is the ITS group node (the first node) */
374         build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET);
375     }
376 
377     /* Table 17 Root Complex Node */
378     build_append_int_noprefix(table_data, 2 /* Root complex */, 1); /* Type */
379     node_size =  ROOT_COMPLEX_ENTRY_SIZE +
380                  ID_MAPPING_ENTRY_SIZE * rc_mapping_count;
381     build_append_int_noprefix(table_data, node_size, 2); /* Length */
382     build_append_int_noprefix(table_data, 3, 1); /* Revision */
383     build_append_int_noprefix(table_data, id++, 4); /* Identifier */
384     /* Number of ID mappings */
385     build_append_int_noprefix(table_data, rc_mapping_count, 4);
386     /* Reference to ID Array */
387     build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 4);
388 
389     /* Table 14 Memory access properties */
390     /* CCA: Cache Coherent Attribute */
391     build_append_int_noprefix(table_data, 1 /* fully coherent */, 4);
392     build_append_int_noprefix(table_data, 0, 1); /* AH: Note Allocation Hints */
393     build_append_int_noprefix(table_data, 0, 2); /* Reserved */
394     /* Table 15 Memory Access Flags */
395     build_append_int_noprefix(table_data, 0x3 /* CCA = CPM = DACS = 1 */, 1);
396 
397     build_append_int_noprefix(table_data, 0, 4); /* ATS Attribute */
398     /* MCFG pci_segment */
399     build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */
400 
401     /* Memory address size limit */
402     build_append_int_noprefix(table_data, 64, 1);
403 
404     build_append_int_noprefix(table_data, 0, 3); /* Reserved */
405 
406     /* Output Reference */
407     if (vms->iommu == VIRT_IOMMU_SMMUV3) {
408         AcpiIortIdMapping *range;
409 
410         /* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */
411         for (i = 0; i < smmu_idmaps->len; i++) {
412             range = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i);
413             /* output IORT node is the smmuv3 node */
414             build_iort_id_mapping(table_data, range->input_base,
415                                   range->id_count, smmu_offset);
416         }
417 
418         /* bypassed RIDs connect to ITS group node directly: RC -> ITS */
419         for (i = 0; i < its_idmaps->len; i++) {
420             range = &g_array_index(its_idmaps, AcpiIortIdMapping, i);
421             /* output IORT node is the ITS group node (the first node) */
422             build_iort_id_mapping(table_data, range->input_base,
423                                   range->id_count, IORT_NODE_OFFSET);
424         }
425     } else {
426         /* output IORT node is the ITS group node (the first node) */
427         build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET);
428     }
429 
430     acpi_table_end(linker, &table);
431     g_array_free(smmu_idmaps, true);
432     g_array_free(its_idmaps, true);
433 }
434 
435 /*
436  * Serial Port Console Redirection Table (SPCR)
437  * Rev: 1.07
438  */
439 static void
440 spcr_setup(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
441 {
442     AcpiSpcrData serial = {
443         .interface_type = 3,       /* ARM PL011 UART */
444         .base_addr.id = AML_AS_SYSTEM_MEMORY,
445         .base_addr.width = 32,
446         .base_addr.offset = 0,
447         .base_addr.size = 3,
448         .base_addr.addr = vms->memmap[VIRT_UART0].base,
449         .interrupt_type = (1 << 3),/* Bit[3] ARMH GIC interrupt*/
450         .pc_interrupt = 0,         /* IRQ */
451         .interrupt = (vms->irqmap[VIRT_UART0] + ARM_SPI_BASE),
452         .baud_rate = 3,            /* 9600 */
453         .parity = 0,               /* No Parity */
454         .stop_bits = 1,            /* 1 Stop bit */
455         .flow_control = 1 << 1,    /* RTS/CTS hardware flow control */
456         .terminal_type = 0,        /* VT100 */
457         .language = 0,             /* Language */
458         .pci_device_id = 0xffff,   /* not a PCI device*/
459         .pci_vendor_id = 0xffff,   /* not a PCI device*/
460         .pci_bus = 0,
461         .pci_device = 0,
462         .pci_function = 0,
463         .pci_flags = 0,
464         .pci_segment = 0,
465     };
466 
467     build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id);
468 }
469 
470 /*
471  * ACPI spec, Revision 5.1
472  * 5.2.16 System Resource Affinity Table (SRAT)
473  */
474 static void
475 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
476 {
477     int i;
478     uint64_t mem_base;
479     MachineClass *mc = MACHINE_GET_CLASS(vms);
480     MachineState *ms = MACHINE(vms);
481     const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms);
482     AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id,
483                         .oem_table_id = vms->oem_table_id };
484 
485     acpi_table_begin(&table, table_data);
486     build_append_int_noprefix(table_data, 1, 4); /* Reserved */
487     build_append_int_noprefix(table_data, 0, 8); /* Reserved */
488 
489     for (i = 0; i < cpu_list->len; ++i) {
490         uint32_t nodeid = cpu_list->cpus[i].props.node_id;
491         /*
492          * 5.2.16.4 GICC Affinity Structure
493          */
494         build_append_int_noprefix(table_data, 3, 1);      /* Type */
495         build_append_int_noprefix(table_data, 18, 1);     /* Length */
496         build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */
497         build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
498         /* Flags, Table 5-76 */
499         build_append_int_noprefix(table_data, 1 /* Enabled */, 4);
500         build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
501     }
502 
503     mem_base = vms->memmap[VIRT_MEM].base;
504     for (i = 0; i < ms->numa_state->num_nodes; ++i) {
505         if (ms->numa_state->nodes[i].node_mem > 0) {
506             build_srat_memory(table_data, mem_base,
507                               ms->numa_state->nodes[i].node_mem, i,
508                               MEM_AFFINITY_ENABLED);
509             mem_base += ms->numa_state->nodes[i].node_mem;
510         }
511     }
512 
513     build_srat_generic_affinity_structures(table_data);
514 
515     if (ms->nvdimms_state->is_enabled) {
516         nvdimm_build_srat(table_data);
517     }
518 
519     if (ms->device_memory) {
520         build_srat_memory(table_data, ms->device_memory->base,
521                           memory_region_size(&ms->device_memory->mr),
522                           ms->numa_state->num_nodes - 1,
523                           MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
524     }
525 
526     acpi_table_end(linker, &table);
527 }
528 
529 /*
530  * ACPI spec, Revision 6.5
531  * 5.2.25 Generic Timer Description Table (GTDT)
532  */
533 static void
534 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
535 {
536     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
537     /*
538      * Table 5-117 Flag Definitions
539      * set only "Timer interrupt Mode" and assume "Timer Interrupt
540      * polarity" bit as '0: Interrupt is Active high'
541      */
542     uint32_t irqflags = vmc->claim_edge_triggered_timers ?
543         1 : /* Interrupt is Edge triggered */
544         0;  /* Interrupt is Level triggered  */
545     AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id,
546                         .oem_table_id = vms->oem_table_id };
547 
548     acpi_table_begin(&table, table_data);
549 
550     /* CntControlBase Physical Address */
551     build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8);
552     build_append_int_noprefix(table_data, 0, 4); /* Reserved */
553     /*
554      * FIXME: clarify comment:
555      * The interrupt values are the same with the device tree when adding 16
556      */
557     /* Secure EL1 timer GSIV */
558     build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ, 4);
559     /* Secure EL1 timer Flags */
560     build_append_int_noprefix(table_data, irqflags, 4);
561     /* Non-Secure EL1 timer GSIV */
562     build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ, 4);
563     /* Non-Secure EL1 timer Flags */
564     build_append_int_noprefix(table_data, irqflags |
565                               1UL << 2, /* Always-on Capability */
566                               4);
567     /* Virtual timer GSIV */
568     build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ, 4);
569     /* Virtual Timer Flags */
570     build_append_int_noprefix(table_data, irqflags, 4);
571     /* Non-Secure EL2 timer GSIV */
572     build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ, 4);
573     /* Non-Secure EL2 timer Flags */
574     build_append_int_noprefix(table_data, irqflags, 4);
575     /* CntReadBase Physical address */
576     build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8);
577     /* Platform Timer Count */
578     build_append_int_noprefix(table_data, 0, 4);
579     /* Platform Timer Offset */
580     build_append_int_noprefix(table_data, 0, 4);
581     if (vms->ns_el2_virt_timer_irq) {
582         /* Virtual EL2 Timer GSIV */
583         build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, 4);
584         /* Virtual EL2 Timer Flags */
585         build_append_int_noprefix(table_data, irqflags, 4);
586     } else {
587         build_append_int_noprefix(table_data, 0, 4);
588         build_append_int_noprefix(table_data, 0, 4);
589     }
590     acpi_table_end(linker, &table);
591 }
592 
593 /* Debug Port Table 2 (DBG2) */
594 static void
595 build_dbg2(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
596 {
597     AcpiTable table = { .sig = "DBG2", .rev = 0, .oem_id = vms->oem_id,
598                         .oem_table_id = vms->oem_table_id };
599     int dbg2devicelength;
600     const char name[] = "COM0";
601     const int namespace_length = sizeof(name);
602 
603     acpi_table_begin(&table, table_data);
604 
605     dbg2devicelength = 22 + /* BaseAddressRegister[] offset */
606                        12 + /* BaseAddressRegister[] */
607                        4 + /* AddressSize[] */
608                        namespace_length /* NamespaceString[] */;
609 
610     /* OffsetDbgDeviceInfo */
611     build_append_int_noprefix(table_data, 44, 4);
612     /* NumberDbgDeviceInfo */
613     build_append_int_noprefix(table_data, 1, 4);
614 
615     /* Table 2. Debug Device Information structure format */
616     build_append_int_noprefix(table_data, 0, 1); /* Revision */
617     build_append_int_noprefix(table_data, dbg2devicelength, 2); /* Length */
618     /* NumberofGenericAddressRegisters */
619     build_append_int_noprefix(table_data, 1, 1);
620     /* NameSpaceStringLength */
621     build_append_int_noprefix(table_data, namespace_length, 2);
622     build_append_int_noprefix(table_data, 38, 2); /* NameSpaceStringOffset */
623     build_append_int_noprefix(table_data, 0, 2); /* OemDataLength */
624     /* OemDataOffset (0 means no OEM data) */
625     build_append_int_noprefix(table_data, 0, 2);
626 
627     /* Port Type */
628     build_append_int_noprefix(table_data, 0x8000 /* Serial */, 2);
629     /* Port Subtype */
630     build_append_int_noprefix(table_data, 0x3 /* ARM PL011 UART */, 2);
631     build_append_int_noprefix(table_data, 0, 2); /* Reserved */
632     /* BaseAddressRegisterOffset */
633     build_append_int_noprefix(table_data, 22, 2);
634     /* AddressSizeOffset */
635     build_append_int_noprefix(table_data, 34, 2);
636 
637     /* BaseAddressRegister[] */
638     build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3,
639                      vms->memmap[VIRT_UART0].base);
640 
641     /* AddressSize[] */
642     build_append_int_noprefix(table_data,
643                               vms->memmap[VIRT_UART0].size, 4);
644 
645     /* NamespaceString[] */
646     g_array_append_vals(table_data, name, namespace_length);
647 
648     acpi_table_end(linker, &table);
649 };
650 
651 /*
652  * ACPI spec, Revision 6.0 Errata A
653  * 5.2.12 Multiple APIC Description Table (MADT)
654  */
655 static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size)
656 {
657     build_append_int_noprefix(table_data, 0xE, 1);  /* Type */
658     build_append_int_noprefix(table_data, 16, 1);   /* Length */
659     build_append_int_noprefix(table_data, 0, 2);    /* Reserved */
660     /* Discovery Range Base Address */
661     build_append_int_noprefix(table_data, base, 8);
662     build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */
663 }
664 
665 static void
666 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
667 {
668     int i;
669     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
670     const MemMapEntry *memmap = vms->memmap;
671     AcpiTable table = { .sig = "APIC", .rev = 4, .oem_id = vms->oem_id,
672                         .oem_table_id = vms->oem_table_id };
673 
674     acpi_table_begin(&table, table_data);
675     /* Local Interrupt Controller Address */
676     build_append_int_noprefix(table_data, 0, 4);
677     build_append_int_noprefix(table_data, 0, 4);   /* Flags */
678 
679     /* 5.2.12.15 GIC Distributor Structure */
680     build_append_int_noprefix(table_data, 0xC, 1); /* Type */
681     build_append_int_noprefix(table_data, 24, 1);  /* Length */
682     build_append_int_noprefix(table_data, 0, 2);   /* Reserved */
683     build_append_int_noprefix(table_data, 0, 4);   /* GIC ID */
684     /* Physical Base Address */
685     build_append_int_noprefix(table_data, memmap[VIRT_GIC_DIST].base, 8);
686     build_append_int_noprefix(table_data, 0, 4);   /* System Vector Base */
687     /* GIC version */
688     build_append_int_noprefix(table_data, vms->gic_version, 1);
689     build_append_int_noprefix(table_data, 0, 3);   /* Reserved */
690 
691     for (i = 0; i < MACHINE(vms)->smp.cpus; i++) {
692         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
693         uint64_t physical_base_address = 0, gich = 0, gicv = 0;
694         uint32_t vgic_interrupt = vms->virt ? ARCH_GIC_MAINT_IRQ : 0;
695         uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
696                                              VIRTUAL_PMU_IRQ : 0;
697 
698         if (vms->gic_version == VIRT_GIC_VERSION_2) {
699             physical_base_address = memmap[VIRT_GIC_CPU].base;
700             gicv = memmap[VIRT_GIC_VCPU].base;
701             gich = memmap[VIRT_GIC_HYP].base;
702         }
703 
704         /* 5.2.12.14 GIC Structure */
705         build_append_int_noprefix(table_data, 0xB, 1);  /* Type */
706         build_append_int_noprefix(table_data, 80, 1);   /* Length */
707         build_append_int_noprefix(table_data, 0, 2);    /* Reserved */
708         build_append_int_noprefix(table_data, i, 4);    /* GIC ID */
709         build_append_int_noprefix(table_data, i, 4);    /* ACPI Processor UID */
710         /* Flags */
711         build_append_int_noprefix(table_data, 1, 4);    /* Enabled */
712         /* Parking Protocol Version */
713         build_append_int_noprefix(table_data, 0, 4);
714         /* Performance Interrupt GSIV */
715         build_append_int_noprefix(table_data, pmu_interrupt, 4);
716         build_append_int_noprefix(table_data, 0, 8); /* Parked Address */
717         /* Physical Base Address */
718         build_append_int_noprefix(table_data, physical_base_address, 8);
719         build_append_int_noprefix(table_data, gicv, 8); /* GICV */
720         build_append_int_noprefix(table_data, gich, 8); /* GICH */
721         /* VGIC Maintenance interrupt */
722         build_append_int_noprefix(table_data, vgic_interrupt, 4);
723         build_append_int_noprefix(table_data, 0, 8);    /* GICR Base Address*/
724         /* MPIDR */
725         build_append_int_noprefix(table_data, arm_cpu_mp_affinity(armcpu), 8);
726         /* Processor Power Efficiency Class */
727         build_append_int_noprefix(table_data, 0, 1);
728         /* Reserved */
729         build_append_int_noprefix(table_data, 0, 3);
730     }
731 
732     if (vms->gic_version != VIRT_GIC_VERSION_2) {
733         build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base,
734                                       memmap[VIRT_GIC_REDIST].size);
735         if (virt_gicv3_redist_region_count(vms) == 2) {
736             build_append_gicr(table_data, memmap[VIRT_HIGH_GIC_REDIST2].base,
737                                           memmap[VIRT_HIGH_GIC_REDIST2].size);
738         }
739 
740         if (its_class_name() && !vmc->no_its) {
741             /*
742              * ACPI spec, Revision 6.0 Errata A
743              * (original 6.0 definition has invalid Length)
744              * 5.2.12.18 GIC ITS Structure
745              */
746             build_append_int_noprefix(table_data, 0xF, 1);  /* Type */
747             build_append_int_noprefix(table_data, 20, 1);   /* Length */
748             build_append_int_noprefix(table_data, 0, 2);    /* Reserved */
749             build_append_int_noprefix(table_data, 0, 4);    /* GIC ITS ID */
750             /* Physical Base Address */
751             build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].base, 8);
752             build_append_int_noprefix(table_data, 0, 4);    /* Reserved */
753         }
754     } else {
755         const uint16_t spi_base = vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE;
756 
757         /* 5.2.12.16 GIC MSI Frame Structure */
758         build_append_int_noprefix(table_data, 0xD, 1);  /* Type */
759         build_append_int_noprefix(table_data, 24, 1);   /* Length */
760         build_append_int_noprefix(table_data, 0, 2);    /* Reserved */
761         build_append_int_noprefix(table_data, 0, 4);    /* GIC MSI Frame ID */
762         /* Physical Base Address */
763         build_append_int_noprefix(table_data, memmap[VIRT_GIC_V2M].base, 8);
764         build_append_int_noprefix(table_data, 1, 4);    /* Flags */
765         /* SPI Count */
766         build_append_int_noprefix(table_data, NUM_GICV2M_SPIS, 2);
767         build_append_int_noprefix(table_data, spi_base, 2); /* SPI Base */
768     }
769     acpi_table_end(linker, &table);
770 }
771 
772 /* FADT */
773 static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker,
774                             VirtMachineState *vms, unsigned dsdt_tbl_offset)
775 {
776     /* ACPI v6.3 */
777     AcpiFadtData fadt = {
778         .rev = 6,
779         .minor_ver = 3,
780         .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
781         .xdsdt_tbl_offset = &dsdt_tbl_offset,
782     };
783 
784     switch (vms->psci_conduit) {
785     case QEMU_PSCI_CONDUIT_DISABLED:
786         fadt.arm_boot_arch = 0;
787         break;
788     case QEMU_PSCI_CONDUIT_HVC:
789         fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT |
790                              ACPI_FADT_ARM_PSCI_USE_HVC;
791         break;
792     case QEMU_PSCI_CONDUIT_SMC:
793         fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT;
794         break;
795     default:
796         g_assert_not_reached();
797     }
798 
799     build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id);
800 }
801 
802 /* DSDT */
803 static void
804 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
805 {
806     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
807     Aml *scope, *dsdt;
808     MachineState *ms = MACHINE(vms);
809     const MemMapEntry *memmap = vms->memmap;
810     const int *irqmap = vms->irqmap;
811     AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = vms->oem_id,
812                         .oem_table_id = vms->oem_table_id };
813 
814     acpi_table_begin(&table, table_data);
815     dsdt = init_aml_allocator();
816 
817     /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware.
818      * While UEFI can use libfdt to disable the RTC device node in the DTB that
819      * it passes to the OS, it cannot modify AML. Therefore, we won't generate
820      * the RTC ACPI device at all when using UEFI.
821      */
822     scope = aml_scope("\\_SB");
823     acpi_dsdt_add_cpus(scope, vms);
824     acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0],
825                        (irqmap[VIRT_UART0] + ARM_SPI_BASE), 0);
826     if (vms->second_ns_uart_present) {
827         acpi_dsdt_add_uart(scope, &memmap[VIRT_UART1],
828                            (irqmap[VIRT_UART1] + ARM_SPI_BASE), 1);
829     }
830     if (vmc->acpi_expose_flash) {
831         acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
832     }
833     fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]);
834     virtio_acpi_dsdt_add(scope, memmap[VIRT_MMIO].base, memmap[VIRT_MMIO].size,
835                          (irqmap[VIRT_MMIO] + ARM_SPI_BASE),
836                          0, NUM_VIRTIO_TRANSPORTS);
837     acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms);
838     if (vms->acpi_dev) {
839         build_ged_aml(scope, "\\_SB."GED_DEVICE,
840                       HOTPLUG_HANDLER(vms->acpi_dev),
841                       irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY,
842                       memmap[VIRT_ACPI_GED].base);
843     } else {
844         acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO],
845                            (irqmap[VIRT_GPIO] + ARM_SPI_BASE));
846     }
847 
848     if (vms->acpi_dev) {
849         uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev),
850                                                   "ged-event", &error_abort);
851 
852         if (event & ACPI_GED_MEM_HOTPLUG_EVT) {
853             build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL,
854                                      AML_SYSTEM_MEMORY,
855                                      memmap[VIRT_PCDIMM_ACPI].base);
856         }
857     }
858 
859     acpi_dsdt_add_power_button(scope);
860 #ifdef CONFIG_TPM
861     acpi_dsdt_add_tpm(scope, vms);
862 #endif
863 
864     aml_append(dsdt, scope);
865 
866     /* copy AML table into ACPI tables blob */
867     g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
868 
869     acpi_table_end(linker, &table);
870     free_aml_allocator();
871 }
872 
873 typedef
874 struct AcpiBuildState {
875     /* Copy of table in RAM (for patching). */
876     MemoryRegion *table_mr;
877     MemoryRegion *rsdp_mr;
878     MemoryRegion *linker_mr;
879     /* Is table patched? */
880     bool patched;
881 } AcpiBuildState;
882 
883 static void acpi_align_size(GArray *blob, unsigned align)
884 {
885     /*
886      * Align size to multiple of given size. This reduces the chance
887      * we need to change size in the future (breaking cross version migration).
888      */
889     g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
890 }
891 
892 static
893 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
894 {
895     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
896     GArray *table_offsets;
897     unsigned dsdt, xsdt;
898     GArray *tables_blob = tables->table_data;
899     MachineState *ms = MACHINE(vms);
900 
901     table_offsets = g_array_new(false, true /* clear */,
902                                         sizeof(uint32_t));
903 
904     bios_linker_loader_alloc(tables->linker,
905                              ACPI_BUILD_TABLE_FILE, tables_blob,
906                              64, false /* high memory */);
907 
908     /* DSDT is pointed to by FADT */
909     dsdt = tables_blob->len;
910     build_dsdt(tables_blob, tables->linker, vms);
911 
912     /* FADT MADT PPTT GTDT MCFG SPCR DBG2 pointed to by RSDT */
913     acpi_add_table(table_offsets, tables_blob);
914     build_fadt_rev6(tables_blob, tables->linker, vms, dsdt);
915 
916     acpi_add_table(table_offsets, tables_blob);
917     build_madt(tables_blob, tables->linker, vms);
918 
919     if (!vmc->no_cpu_topology) {
920         acpi_add_table(table_offsets, tables_blob);
921         build_pptt(tables_blob, tables->linker, ms,
922                    vms->oem_id, vms->oem_table_id);
923     }
924 
925     acpi_add_table(table_offsets, tables_blob);
926     build_gtdt(tables_blob, tables->linker, vms);
927 
928     acpi_add_table(table_offsets, tables_blob);
929     {
930         AcpiMcfgInfo mcfg = {
931            .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base,
932            .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size,
933         };
934         build_mcfg(tables_blob, tables->linker, &mcfg, vms->oem_id,
935                    vms->oem_table_id);
936     }
937 
938     acpi_add_table(table_offsets, tables_blob);
939     spcr_setup(tables_blob, tables->linker, vms);
940 
941     acpi_add_table(table_offsets, tables_blob);
942     build_dbg2(tables_blob, tables->linker, vms);
943 
944     if (vms->ras) {
945         build_ghes_error_table(tables->hardware_errors, tables->linker);
946         acpi_add_table(table_offsets, tables_blob);
947         acpi_build_hest(tables_blob, tables->linker, vms->oem_id,
948                         vms->oem_table_id);
949     }
950 
951     if (ms->numa_state->num_nodes > 0) {
952         acpi_add_table(table_offsets, tables_blob);
953         build_srat(tables_blob, tables->linker, vms);
954         if (ms->numa_state->have_numa_distance) {
955             acpi_add_table(table_offsets, tables_blob);
956             build_slit(tables_blob, tables->linker, ms, vms->oem_id,
957                        vms->oem_table_id);
958         }
959 
960         if (ms->numa_state->hmat_enabled) {
961             acpi_add_table(table_offsets, tables_blob);
962             build_hmat(tables_blob, tables->linker, ms->numa_state,
963                        vms->oem_id, vms->oem_table_id);
964         }
965     }
966 
967     if (ms->nvdimms_state->is_enabled) {
968         nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
969                           ms->nvdimms_state, ms->ram_slots, vms->oem_id,
970                           vms->oem_table_id);
971     }
972 
973     if (its_class_name() && !vmc->no_its) {
974         acpi_add_table(table_offsets, tables_blob);
975         build_iort(tables_blob, tables->linker, vms);
976     }
977 
978 #ifdef CONFIG_TPM
979     if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {
980         acpi_add_table(table_offsets, tables_blob);
981         build_tpm2(tables_blob, tables->linker, tables->tcpalog, vms->oem_id,
982                    vms->oem_table_id);
983     }
984 #endif
985 
986     if (vms->iommu == VIRT_IOMMU_VIRTIO) {
987         acpi_add_table(table_offsets, tables_blob);
988         build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf,
989                    vms->oem_id, vms->oem_table_id);
990     }
991 
992     /* XSDT is pointed to by RSDP */
993     xsdt = tables_blob->len;
994     build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id,
995                vms->oem_table_id);
996 
997     /* RSDP is in FSEG memory, so allocate it separately */
998     {
999         AcpiRsdpData rsdp_data = {
1000             .revision = 2,
1001             .oem_id = vms->oem_id,
1002             .xsdt_tbl_offset = &xsdt,
1003             .rsdt_tbl_offset = NULL,
1004         };
1005         build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
1006     }
1007 
1008     /*
1009      * The align size is 128, warn if 64k is not enough therefore
1010      * the align size could be resized.
1011      */
1012     if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
1013         warn_report("ACPI table size %u exceeds %d bytes,"
1014                     " migration may not work",
1015                     tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
1016         error_printf("Try removing CPUs, NUMA nodes, memory slots"
1017                      " or PCI bridges.\n");
1018     }
1019     acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
1020 
1021 
1022     /* Cleanup memory that's no longer used. */
1023     g_array_free(table_offsets, true);
1024 }
1025 
1026 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
1027 {
1028     uint32_t size = acpi_data_len(data);
1029 
1030     /* Make sure RAM size is correct - in case it got changed
1031      * e.g. by migration */
1032     memory_region_ram_resize(mr, size, &error_abort);
1033 
1034     memcpy(memory_region_get_ram_ptr(mr), data->data, size);
1035     memory_region_set_dirty(mr, 0, size);
1036 }
1037 
1038 static void virt_acpi_build_update(void *build_opaque)
1039 {
1040     AcpiBuildState *build_state = build_opaque;
1041     AcpiBuildTables tables;
1042 
1043     /* No state to update or already patched? Nothing to do. */
1044     if (!build_state || build_state->patched) {
1045         return;
1046     }
1047     build_state->patched = true;
1048 
1049     acpi_build_tables_init(&tables);
1050 
1051     virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables);
1052 
1053     acpi_ram_update(build_state->table_mr, tables.table_data);
1054     acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
1055     acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
1056 
1057     acpi_build_tables_cleanup(&tables, true);
1058 }
1059 
1060 static void virt_acpi_build_reset(void *build_opaque)
1061 {
1062     AcpiBuildState *build_state = build_opaque;
1063     build_state->patched = false;
1064 }
1065 
1066 static const VMStateDescription vmstate_virt_acpi_build = {
1067     .name = "virt_acpi_build",
1068     .version_id = 1,
1069     .minimum_version_id = 1,
1070     .fields = (const VMStateField[]) {
1071         VMSTATE_BOOL(patched, AcpiBuildState),
1072         VMSTATE_END_OF_LIST()
1073     },
1074 };
1075 
1076 void virt_acpi_setup(VirtMachineState *vms)
1077 {
1078     AcpiBuildTables tables;
1079     AcpiBuildState *build_state;
1080     AcpiGedState *acpi_ged_state;
1081 
1082     if (!vms->fw_cfg) {
1083         trace_virt_acpi_setup();
1084         return;
1085     }
1086 
1087     if (!virt_is_acpi_enabled(vms)) {
1088         trace_virt_acpi_setup();
1089         return;
1090     }
1091 
1092     build_state = g_malloc0(sizeof *build_state);
1093 
1094     acpi_build_tables_init(&tables);
1095     virt_acpi_build(vms, &tables);
1096 
1097     /* Now expose it all to Guest */
1098     build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update,
1099                                               build_state, tables.table_data,
1100                                               ACPI_BUILD_TABLE_FILE);
1101     assert(build_state->table_mr != NULL);
1102 
1103     build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update,
1104                                                build_state,
1105                                                tables.linker->cmd_blob,
1106                                                ACPI_BUILD_LOADER_FILE);
1107 
1108     fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
1109                     acpi_data_len(tables.tcpalog));
1110 
1111     if (vms->ras) {
1112         assert(vms->acpi_dev);
1113         acpi_ged_state = ACPI_GED(vms->acpi_dev);
1114         acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state,
1115                              vms->fw_cfg, tables.hardware_errors);
1116     }
1117 
1118     build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update,
1119                                              build_state, tables.rsdp,
1120                                              ACPI_BUILD_RSDP_FILE);
1121 
1122     qemu_register_reset(virt_acpi_build_reset, build_state);
1123     virt_acpi_build_reset(build_state);
1124     vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
1125 
1126     /* Cleanup tables but don't free the memory: we track it
1127      * in build_state.
1128      */
1129     acpi_build_tables_cleanup(&tables, false);
1130 }
1131