1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * ARM virt ACPI generation 4 * 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 6 * Copyright (C) 2006 Fabrice Bellard 7 * Copyright (C) 2013 Red Hat Inc 8 * 9 * Author: Michael S. Tsirkin <mst@redhat.com> 10 * 11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 12 * 13 * Author: Shannon Zhao <zhaoshenglong@huawei.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu-common.h" 30 #include "hw/arm/virt-acpi-build.h" 31 #include "qemu/bitmap.h" 32 #include "trace.h" 33 #include "qom/cpu.h" 34 #include "target-arm/cpu.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/loader.h" 40 #include "hw/hw.h" 41 #include "hw/acpi/aml-build.h" 42 #include "hw/pci/pcie_host.h" 43 #include "hw/pci/pci.h" 44 45 #define ARM_SPI_BASE 32 46 47 typedef struct VirtAcpiCpuInfo { 48 DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT); 49 } VirtAcpiCpuInfo; 50 51 static void virt_acpi_get_cpu_info(VirtAcpiCpuInfo *cpuinfo) 52 { 53 CPUState *cpu; 54 55 memset(cpuinfo->found_cpus, 0, sizeof cpuinfo->found_cpus); 56 CPU_FOREACH(cpu) { 57 set_bit(cpu->cpu_index, cpuinfo->found_cpus); 58 } 59 } 60 61 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) 62 { 63 uint16_t i; 64 65 for (i = 0; i < smp_cpus; i++) { 66 Aml *dev = aml_device("C%03x", i); 67 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 68 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 69 aml_append(scope, dev); 70 } 71 } 72 73 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 74 int uart_irq) 75 { 76 Aml *dev = aml_device("COM0"); 77 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); 78 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 79 80 Aml *crs = aml_resource_template(); 81 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 82 uart_memmap->size, AML_READ_WRITE)); 83 aml_append(crs, 84 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 85 AML_EXCLUSIVE, uart_irq)); 86 aml_append(dev, aml_name_decl("_CRS", crs)); 87 88 /* The _ADR entry is used to link this device to the UART described 89 * in the SPCR table, i.e. SPCR.base_address.address == _ADR. 90 */ 91 aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base))); 92 93 aml_append(scope, dev); 94 } 95 96 static void acpi_dsdt_add_rtc(Aml *scope, const MemMapEntry *rtc_memmap, 97 int rtc_irq) 98 { 99 Aml *dev = aml_device("RTC0"); 100 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0013"))); 101 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 102 103 Aml *crs = aml_resource_template(); 104 aml_append(crs, aml_memory32_fixed(rtc_memmap->base, 105 rtc_memmap->size, AML_READ_WRITE)); 106 aml_append(crs, 107 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 108 AML_EXCLUSIVE, rtc_irq)); 109 aml_append(dev, aml_name_decl("_CRS", crs)); 110 aml_append(scope, dev); 111 } 112 113 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) 114 { 115 Aml *dev, *crs; 116 hwaddr base = flash_memmap->base; 117 hwaddr size = flash_memmap->size / 2; 118 119 dev = aml_device("FLS0"); 120 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 121 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 122 123 crs = aml_resource_template(); 124 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 125 aml_append(dev, aml_name_decl("_CRS", crs)); 126 aml_append(scope, dev); 127 128 dev = aml_device("FLS1"); 129 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 130 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 131 crs = aml_resource_template(); 132 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); 133 aml_append(dev, aml_name_decl("_CRS", crs)); 134 aml_append(scope, dev); 135 } 136 137 static void acpi_dsdt_add_virtio(Aml *scope, 138 const MemMapEntry *virtio_mmio_memmap, 139 int mmio_irq, int num) 140 { 141 hwaddr base = virtio_mmio_memmap->base; 142 hwaddr size = virtio_mmio_memmap->size; 143 int irq = mmio_irq; 144 int i; 145 146 for (i = 0; i < num; i++) { 147 Aml *dev = aml_device("VR%02u", i); 148 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); 149 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 150 151 Aml *crs = aml_resource_template(); 152 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 153 aml_append(crs, 154 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 155 AML_EXCLUSIVE, irq + i)); 156 aml_append(dev, aml_name_decl("_CRS", crs)); 157 aml_append(scope, dev); 158 base += size; 159 } 160 } 161 162 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, int irq, 163 bool use_highmem) 164 { 165 Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; 166 int i, bus_no; 167 hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base; 168 hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size; 169 hwaddr base_pio = memmap[VIRT_PCIE_PIO].base; 170 hwaddr size_pio = memmap[VIRT_PCIE_PIO].size; 171 hwaddr base_ecam = memmap[VIRT_PCIE_ECAM].base; 172 hwaddr size_ecam = memmap[VIRT_PCIE_ECAM].size; 173 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 174 175 Aml *dev = aml_device("%s", "PCI0"); 176 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); 177 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); 178 aml_append(dev, aml_name_decl("_SEG", aml_int(0))); 179 aml_append(dev, aml_name_decl("_BBN", aml_int(0))); 180 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 181 aml_append(dev, aml_name_decl("_UID", aml_string("PCI0"))); 182 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); 183 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 184 185 /* Declare the PCI Routing Table. */ 186 Aml *rt_pkg = aml_package(nr_pcie_buses * PCI_NUM_PINS); 187 for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) { 188 for (i = 0; i < PCI_NUM_PINS; i++) { 189 int gsi = (i + bus_no) % PCI_NUM_PINS; 190 Aml *pkg = aml_package(4); 191 aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF)); 192 aml_append(pkg, aml_int(i)); 193 aml_append(pkg, aml_name("GSI%d", gsi)); 194 aml_append(pkg, aml_int(0)); 195 aml_append(rt_pkg, pkg); 196 } 197 } 198 aml_append(dev, aml_name_decl("_PRT", rt_pkg)); 199 200 /* Create GSI link device */ 201 for (i = 0; i < PCI_NUM_PINS; i++) { 202 Aml *dev_gsi = aml_device("GSI%d", i); 203 aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); 204 aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0))); 205 crs = aml_resource_template(); 206 aml_append(crs, 207 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 208 AML_EXCLUSIVE, irq + i)); 209 aml_append(dev_gsi, aml_name_decl("_PRS", crs)); 210 crs = aml_resource_template(); 211 aml_append(crs, 212 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 213 AML_EXCLUSIVE, irq + i)); 214 aml_append(dev_gsi, aml_name_decl("_CRS", crs)); 215 method = aml_method("_SRS", 1); 216 aml_append(dev_gsi, method); 217 aml_append(dev, dev_gsi); 218 } 219 220 method = aml_method("_CBA", 0); 221 aml_append(method, aml_return(aml_int(base_ecam))); 222 aml_append(dev, method); 223 224 method = aml_method("_CRS", 0); 225 Aml *rbuf = aml_resource_template(); 226 aml_append(rbuf, 227 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 228 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, 229 nr_pcie_buses)); 230 aml_append(rbuf, 231 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 232 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio, 233 base_mmio + size_mmio - 1, 0x0000, size_mmio)); 234 aml_append(rbuf, 235 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 236 AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio, 237 size_pio)); 238 239 if (use_highmem) { 240 hwaddr base_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].base; 241 hwaddr size_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].size; 242 243 aml_append(rbuf, 244 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 245 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, 246 base_mmio_high, base_mmio_high, 0x0000, 247 size_mmio_high)); 248 } 249 250 aml_append(method, aml_name_decl("RBUF", rbuf)); 251 aml_append(method, aml_return(rbuf)); 252 aml_append(dev, method); 253 254 /* Declare an _OSC (OS Control Handoff) method */ 255 aml_append(dev, aml_name_decl("SUPP", aml_int(0))); 256 aml_append(dev, aml_name_decl("CTRL", aml_int(0))); 257 method = aml_method("_OSC", 4); 258 aml_append(method, 259 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 260 261 /* PCI Firmware Specification 3.0 262 * 4.5.1. _OSC Interface for PCI Host Bridge Devices 263 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is 264 * identified by the Universal Unique IDentifier (UUID) 265 * 33DB4D5B-1FF7-401C-9657-7441C03DD766 266 */ 267 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"); 268 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 269 aml_append(ifctx, 270 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 271 aml_append(ifctx, 272 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 273 aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); 274 aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); 275 aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D)), 276 aml_name("CTRL"))); 277 278 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); 279 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08)), 280 aml_name("CDW1"))); 281 aml_append(ifctx, ifctx1); 282 283 ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL")))); 284 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10)), 285 aml_name("CDW1"))); 286 aml_append(ifctx, ifctx1); 287 288 aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3"))); 289 aml_append(ifctx, aml_return(aml_arg(3))); 290 aml_append(method, ifctx); 291 292 elsectx = aml_else(); 293 aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4)), 294 aml_name("CDW1"))); 295 aml_append(elsectx, aml_return(aml_arg(3))); 296 aml_append(method, elsectx); 297 aml_append(dev, method); 298 299 method = aml_method("_DSM", 4); 300 301 /* PCI Firmware Specification 3.0 302 * 4.6.1. _DSM for PCI Express Slot Information 303 * The UUID in _DSM in this context is 304 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} 305 */ 306 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 307 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 308 ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0))); 309 uint8_t byte_list[1] = {1}; 310 buf = aml_buffer(1, byte_list); 311 aml_append(ifctx1, aml_return(buf)); 312 aml_append(ifctx, ifctx1); 313 aml_append(method, ifctx); 314 315 byte_list[0] = 0; 316 buf = aml_buffer(1, byte_list); 317 aml_append(method, aml_return(buf)); 318 aml_append(dev, method); 319 320 Aml *dev_rp0 = aml_device("%s", "RP0"); 321 aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0))); 322 aml_append(dev, dev_rp0); 323 aml_append(scope, dev); 324 } 325 326 /* RSDP */ 327 static GArray * 328 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) 329 { 330 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 331 332 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, 333 true /* fseg memory */); 334 335 memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature)); 336 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, sizeof(rsdp->oem_id)); 337 rsdp->length = cpu_to_le32(sizeof(*rsdp)); 338 rsdp->revision = 0x02; 339 340 /* Point to RSDT */ 341 rsdp->rsdt_physical_address = cpu_to_le32(rsdt); 342 /* Address to be filled by Guest linker */ 343 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, 344 ACPI_BUILD_TABLE_FILE, 345 rsdp_table, &rsdp->rsdt_physical_address, 346 sizeof rsdp->rsdt_physical_address); 347 rsdp->checksum = 0; 348 /* Checksum to be filled by Guest linker */ 349 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 350 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum); 351 352 return rsdp_table; 353 } 354 355 static void 356 build_spcr(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 357 { 358 AcpiSerialPortConsoleRedirection *spcr; 359 const MemMapEntry *uart_memmap = &guest_info->memmap[VIRT_UART]; 360 int irq = guest_info->irqmap[VIRT_UART] + ARM_SPI_BASE; 361 362 spcr = acpi_data_push(table_data, sizeof(*spcr)); 363 364 spcr->interface_type = 0x3; /* ARM PL011 UART */ 365 366 spcr->base_address.space_id = AML_SYSTEM_MEMORY; 367 spcr->base_address.bit_width = 8; 368 spcr->base_address.bit_offset = 0; 369 spcr->base_address.access_width = 1; 370 spcr->base_address.address = cpu_to_le64(uart_memmap->base); 371 372 spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */ 373 spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */ 374 375 spcr->baud = 3; /* Baud Rate: 3 = 9600 */ 376 spcr->parity = 0; /* No Parity */ 377 spcr->stopbits = 1; /* 1 Stop bit */ 378 spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */ 379 spcr->term_type = 0; /* Terminal Type: 0 = VT100 */ 380 381 spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */ 382 spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */ 383 384 build_header(linker, table_data, (void *)spcr, "SPCR", sizeof(*spcr), 2); 385 } 386 387 static void 388 build_mcfg(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 389 { 390 AcpiTableMcfg *mcfg; 391 const MemMapEntry *memmap = guest_info->memmap; 392 int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]); 393 394 mcfg = acpi_data_push(table_data, len); 395 mcfg->allocation[0].address = cpu_to_le64(memmap[VIRT_PCIE_ECAM].base); 396 397 /* Only a single allocation so no need to play with segments */ 398 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 399 mcfg->allocation[0].start_bus_number = 0; 400 mcfg->allocation[0].end_bus_number = (memmap[VIRT_PCIE_ECAM].size 401 / PCIE_MMCFG_SIZE_MIN) - 1; 402 403 build_header(linker, table_data, (void *)mcfg, "MCFG", len, 1); 404 } 405 406 /* GTDT */ 407 static void 408 build_gtdt(GArray *table_data, GArray *linker) 409 { 410 int gtdt_start = table_data->len; 411 AcpiGenericTimerTable *gtdt; 412 413 gtdt = acpi_data_push(table_data, sizeof *gtdt); 414 /* The interrupt values are the same with the device tree when adding 16 */ 415 gtdt->secure_el1_interrupt = ARCH_TIMER_S_EL1_IRQ + 16; 416 gtdt->secure_el1_flags = ACPI_EDGE_SENSITIVE; 417 418 gtdt->non_secure_el1_interrupt = ARCH_TIMER_NS_EL1_IRQ + 16; 419 gtdt->non_secure_el1_flags = ACPI_EDGE_SENSITIVE; 420 421 gtdt->virtual_timer_interrupt = ARCH_TIMER_VIRT_IRQ + 16; 422 gtdt->virtual_timer_flags = ACPI_EDGE_SENSITIVE; 423 424 gtdt->non_secure_el2_interrupt = ARCH_TIMER_NS_EL2_IRQ + 16; 425 gtdt->non_secure_el2_flags = ACPI_EDGE_SENSITIVE; 426 427 build_header(linker, table_data, 428 (void *)(table_data->data + gtdt_start), "GTDT", 429 table_data->len - gtdt_start, 2); 430 } 431 432 /* MADT */ 433 static void 434 build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info, 435 VirtAcpiCpuInfo *cpuinfo) 436 { 437 int madt_start = table_data->len; 438 const MemMapEntry *memmap = guest_info->memmap; 439 const int *irqmap = guest_info->irqmap; 440 AcpiMultipleApicTable *madt; 441 AcpiMadtGenericDistributor *gicd; 442 AcpiMadtGenericMsiFrame *gic_msi; 443 int i; 444 445 madt = acpi_data_push(table_data, sizeof *madt); 446 447 gicd = acpi_data_push(table_data, sizeof *gicd); 448 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR; 449 gicd->length = sizeof(*gicd); 450 gicd->base_address = memmap[VIRT_GIC_DIST].base; 451 452 for (i = 0; i < guest_info->smp_cpus; i++) { 453 AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data, 454 sizeof *gicc); 455 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 456 457 gicc->type = ACPI_APIC_GENERIC_INTERRUPT; 458 gicc->length = sizeof(*gicc); 459 if (guest_info->gic_version == 2) { 460 gicc->base_address = memmap[VIRT_GIC_CPU].base; 461 } 462 gicc->cpu_interface_number = i; 463 gicc->arm_mpidr = armcpu->mp_affinity; 464 gicc->uid = i; 465 if (test_bit(i, cpuinfo->found_cpus)) { 466 gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED); 467 } 468 } 469 470 if (guest_info->gic_version == 3) { 471 AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data, 472 sizeof *gicr); 473 474 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 475 gicr->length = sizeof(*gicr); 476 gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base); 477 gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size); 478 } else { 479 gic_msi = acpi_data_push(table_data, sizeof *gic_msi); 480 gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME; 481 gic_msi->length = sizeof(*gic_msi); 482 gic_msi->gic_msi_frame_id = 0; 483 gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base); 484 gic_msi->flags = cpu_to_le32(1); 485 gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS); 486 gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE); 487 } 488 489 build_header(linker, table_data, 490 (void *)(table_data->data + madt_start), "APIC", 491 table_data->len - madt_start, 3); 492 } 493 494 /* FADT */ 495 static void 496 build_fadt(GArray *table_data, GArray *linker, unsigned dsdt) 497 { 498 AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); 499 500 /* Hardware Reduced = 1 and use PSCI 0.2+ and with HVC */ 501 fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI); 502 fadt->arm_boot_flags = cpu_to_le16((1 << ACPI_FADT_ARM_USE_PSCI_G_0_2) | 503 (1 << ACPI_FADT_ARM_PSCI_USE_HVC)); 504 505 /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */ 506 fadt->minor_revision = 0x1; 507 508 fadt->dsdt = cpu_to_le32(dsdt); 509 /* DSDT address to be filled by Guest linker */ 510 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 511 ACPI_BUILD_TABLE_FILE, 512 table_data, &fadt->dsdt, 513 sizeof fadt->dsdt); 514 515 build_header(linker, table_data, 516 (void *)fadt, "FACP", sizeof(*fadt), 5); 517 } 518 519 /* DSDT */ 520 static void 521 build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 522 { 523 Aml *scope, *dsdt; 524 const MemMapEntry *memmap = guest_info->memmap; 525 const int *irqmap = guest_info->irqmap; 526 527 dsdt = init_aml_allocator(); 528 /* Reserve space for header */ 529 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 530 531 scope = aml_scope("\\_SB"); 532 acpi_dsdt_add_cpus(scope, guest_info->smp_cpus); 533 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], 534 (irqmap[VIRT_UART] + ARM_SPI_BASE)); 535 acpi_dsdt_add_rtc(scope, &memmap[VIRT_RTC], 536 (irqmap[VIRT_RTC] + ARM_SPI_BASE)); 537 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); 538 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], 539 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); 540 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), 541 guest_info->use_highmem); 542 543 aml_append(dsdt, scope); 544 545 /* copy AML table into ACPI tables blob and patch header there */ 546 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 547 build_header(linker, table_data, 548 (void *)(table_data->data + table_data->len - dsdt->buf->len), 549 "DSDT", dsdt->buf->len, 2); 550 free_aml_allocator(); 551 } 552 553 typedef 554 struct AcpiBuildState { 555 /* Copy of table in RAM (for patching). */ 556 MemoryRegion *table_mr; 557 MemoryRegion *rsdp_mr; 558 MemoryRegion *linker_mr; 559 /* Is table patched? */ 560 bool patched; 561 VirtGuestInfo *guest_info; 562 } AcpiBuildState; 563 564 static 565 void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables) 566 { 567 GArray *table_offsets; 568 unsigned dsdt, rsdt; 569 VirtAcpiCpuInfo cpuinfo; 570 GArray *tables_blob = tables->table_data; 571 572 virt_acpi_get_cpu_info(&cpuinfo); 573 574 table_offsets = g_array_new(false, true /* clear */, 575 sizeof(uint32_t)); 576 577 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, 578 64, false /* high memory */); 579 580 /* 581 * The ACPI v5.1 tables for Hardware-reduced ACPI platform are: 582 * RSDP 583 * RSDT 584 * FADT 585 * GTDT 586 * MADT 587 * MCFG 588 * DSDT 589 */ 590 591 /* DSDT is pointed to by FADT */ 592 dsdt = tables_blob->len; 593 build_dsdt(tables_blob, tables->linker, guest_info); 594 595 /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */ 596 acpi_add_table(table_offsets, tables_blob); 597 build_fadt(tables_blob, tables->linker, dsdt); 598 599 acpi_add_table(table_offsets, tables_blob); 600 build_madt(tables_blob, tables->linker, guest_info, &cpuinfo); 601 602 acpi_add_table(table_offsets, tables_blob); 603 build_gtdt(tables_blob, tables->linker); 604 605 acpi_add_table(table_offsets, tables_blob); 606 build_mcfg(tables_blob, tables->linker, guest_info); 607 608 acpi_add_table(table_offsets, tables_blob); 609 build_spcr(tables_blob, tables->linker, guest_info); 610 611 /* RSDT is pointed to by RSDP */ 612 rsdt = tables_blob->len; 613 build_rsdt(tables_blob, tables->linker, table_offsets); 614 615 /* RSDP is in FSEG memory, so allocate it separately */ 616 build_rsdp(tables->rsdp, tables->linker, rsdt); 617 618 /* Cleanup memory that's no longer used. */ 619 g_array_free(table_offsets, true); 620 } 621 622 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 623 { 624 uint32_t size = acpi_data_len(data); 625 626 /* Make sure RAM size is correct - in case it got changed 627 * e.g. by migration */ 628 memory_region_ram_resize(mr, size, &error_abort); 629 630 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 631 memory_region_set_dirty(mr, 0, size); 632 } 633 634 static void virt_acpi_build_update(void *build_opaque) 635 { 636 AcpiBuildState *build_state = build_opaque; 637 AcpiBuildTables tables; 638 639 /* No state to update or already patched? Nothing to do. */ 640 if (!build_state || build_state->patched) { 641 return; 642 } 643 build_state->patched = true; 644 645 acpi_build_tables_init(&tables); 646 647 virt_acpi_build(build_state->guest_info, &tables); 648 649 acpi_ram_update(build_state->table_mr, tables.table_data); 650 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 651 acpi_ram_update(build_state->linker_mr, tables.linker); 652 653 654 acpi_build_tables_cleanup(&tables, true); 655 } 656 657 static void virt_acpi_build_reset(void *build_opaque) 658 { 659 AcpiBuildState *build_state = build_opaque; 660 build_state->patched = false; 661 } 662 663 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, 664 GArray *blob, const char *name, 665 uint64_t max_size) 666 { 667 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 668 name, virt_acpi_build_update, build_state); 669 } 670 671 static const VMStateDescription vmstate_virt_acpi_build = { 672 .name = "virt_acpi_build", 673 .version_id = 1, 674 .minimum_version_id = 1, 675 .fields = (VMStateField[]) { 676 VMSTATE_BOOL(patched, AcpiBuildState), 677 VMSTATE_END_OF_LIST() 678 }, 679 }; 680 681 void virt_acpi_setup(VirtGuestInfo *guest_info) 682 { 683 AcpiBuildTables tables; 684 AcpiBuildState *build_state; 685 686 if (!guest_info->fw_cfg) { 687 trace_virt_acpi_setup(); 688 return; 689 } 690 691 if (!acpi_enabled) { 692 trace_virt_acpi_setup(); 693 return; 694 } 695 696 build_state = g_malloc0(sizeof *build_state); 697 build_state->guest_info = guest_info; 698 699 acpi_build_tables_init(&tables); 700 virt_acpi_build(build_state->guest_info, &tables); 701 702 /* Now expose it all to Guest */ 703 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, 704 ACPI_BUILD_TABLE_FILE, 705 ACPI_BUILD_TABLE_MAX_SIZE); 706 assert(build_state->table_mr != NULL); 707 708 build_state->linker_mr = 709 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); 710 711 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 712 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 713 714 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, 715 ACPI_BUILD_RSDP_FILE, 0); 716 717 qemu_register_reset(virt_acpi_build_reset, build_state); 718 virt_acpi_build_reset(build_state); 719 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 720 721 /* Cleanup tables but don't free the memory: we track it 722 * in build_state. 723 */ 724 acpi_build_tables_cleanup(&tables, false); 725 } 726