1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * ARM virt ACPI generation 4 * 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 6 * Copyright (C) 2006 Fabrice Bellard 7 * Copyright (C) 2013 Red Hat Inc 8 * 9 * Author: Michael S. Tsirkin <mst@redhat.com> 10 * 11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 12 * 13 * Author: Shannon Zhao <zhaoshenglong@huawei.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "qapi/error.h" 31 #include "qemu/bitmap.h" 32 #include "trace.h" 33 #include "hw/core/cpu.h" 34 #include "target/arm/cpu.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/acpi/aml-build.h" 40 #include "hw/acpi/utils.h" 41 #include "hw/acpi/pci.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "hw/acpi/generic_event_device.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/pci/pcie_host.h" 46 #include "hw/pci/pci.h" 47 #include "hw/pci-host/gpex.h" 48 #include "hw/arm/virt.h" 49 #include "hw/mem/nvdimm.h" 50 #include "hw/platform-bus.h" 51 #include "sysemu/numa.h" 52 #include "sysemu/reset.h" 53 #include "sysemu/tpm.h" 54 #include "kvm_arm.h" 55 #include "migration/vmstate.h" 56 #include "hw/acpi/ghes.h" 57 58 #define ARM_SPI_BASE 32 59 60 #define ACPI_BUILD_TABLE_SIZE 0x20000 61 62 static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms) 63 { 64 MachineState *ms = MACHINE(vms); 65 uint16_t i; 66 67 for (i = 0; i < ms->smp.cpus; i++) { 68 Aml *dev = aml_device("C%.03X", i); 69 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 70 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 71 aml_append(scope, dev); 72 } 73 } 74 75 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 76 uint32_t uart_irq) 77 { 78 Aml *dev = aml_device("COM0"); 79 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); 80 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 81 82 Aml *crs = aml_resource_template(); 83 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 84 uart_memmap->size, AML_READ_WRITE)); 85 aml_append(crs, 86 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 87 AML_EXCLUSIVE, &uart_irq, 1)); 88 aml_append(dev, aml_name_decl("_CRS", crs)); 89 90 aml_append(scope, dev); 91 } 92 93 static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) 94 { 95 Aml *dev = aml_device("FWCF"); 96 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 97 /* device present, functioning, decoding, not shown in UI */ 98 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 99 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 100 101 Aml *crs = aml_resource_template(); 102 aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, 103 fw_cfg_memmap->size, AML_READ_WRITE)); 104 aml_append(dev, aml_name_decl("_CRS", crs)); 105 aml_append(scope, dev); 106 } 107 108 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) 109 { 110 Aml *dev, *crs; 111 hwaddr base = flash_memmap->base; 112 hwaddr size = flash_memmap->size / 2; 113 114 dev = aml_device("FLS0"); 115 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 116 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 117 118 crs = aml_resource_template(); 119 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 120 aml_append(dev, aml_name_decl("_CRS", crs)); 121 aml_append(scope, dev); 122 123 dev = aml_device("FLS1"); 124 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 125 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 126 crs = aml_resource_template(); 127 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); 128 aml_append(dev, aml_name_decl("_CRS", crs)); 129 aml_append(scope, dev); 130 } 131 132 static void acpi_dsdt_add_virtio(Aml *scope, 133 const MemMapEntry *virtio_mmio_memmap, 134 uint32_t mmio_irq, int num) 135 { 136 hwaddr base = virtio_mmio_memmap->base; 137 hwaddr size = virtio_mmio_memmap->size; 138 int i; 139 140 for (i = 0; i < num; i++) { 141 uint32_t irq = mmio_irq + i; 142 Aml *dev = aml_device("VR%02u", i); 143 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); 144 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 145 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 146 147 Aml *crs = aml_resource_template(); 148 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 149 aml_append(crs, 150 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 151 AML_EXCLUSIVE, &irq, 1)); 152 aml_append(dev, aml_name_decl("_CRS", crs)); 153 aml_append(scope, dev); 154 base += size; 155 } 156 } 157 158 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, 159 uint32_t irq, bool use_highmem, bool highmem_ecam, 160 VirtMachineState *vms) 161 { 162 int ecam_id = VIRT_ECAM_ID(highmem_ecam); 163 struct GPEXConfig cfg = { 164 .mmio32 = memmap[VIRT_PCIE_MMIO], 165 .pio = memmap[VIRT_PCIE_PIO], 166 .ecam = memmap[ecam_id], 167 .irq = irq, 168 .bus = vms->bus, 169 }; 170 171 if (use_highmem) { 172 cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO]; 173 } 174 175 acpi_dsdt_add_gpex(scope, &cfg); 176 } 177 178 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, 179 uint32_t gpio_irq) 180 { 181 Aml *dev = aml_device("GPO0"); 182 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); 183 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 184 185 Aml *crs = aml_resource_template(); 186 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, 187 AML_READ_WRITE)); 188 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 189 AML_EXCLUSIVE, &gpio_irq, 1)); 190 aml_append(dev, aml_name_decl("_CRS", crs)); 191 192 Aml *aei = aml_resource_template(); 193 /* Pin 3 for power button */ 194 const uint32_t pin_list[1] = {3}; 195 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, 196 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, 197 "GPO0", NULL, 0)); 198 aml_append(dev, aml_name_decl("_AEI", aei)); 199 200 /* _E03 is handle for power button */ 201 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); 202 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), 203 aml_int(0x80))); 204 aml_append(dev, method); 205 aml_append(scope, dev); 206 } 207 208 static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms) 209 { 210 PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); 211 hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base; 212 SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find()); 213 MemoryRegion *sbdev_mr; 214 hwaddr tpm_base; 215 216 if (!sbdev) { 217 return; 218 } 219 220 tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); 221 assert(tpm_base != -1); 222 223 tpm_base += pbus_base; 224 225 sbdev_mr = sysbus_mmio_get_region(sbdev, 0); 226 227 Aml *dev = aml_device("TPM0"); 228 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 229 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 230 231 Aml *crs = aml_resource_template(); 232 aml_append(crs, 233 aml_memory32_fixed(tpm_base, 234 (uint32_t)memory_region_size(sbdev_mr), 235 AML_READ_WRITE)); 236 aml_append(dev, aml_name_decl("_CRS", crs)); 237 aml_append(scope, dev); 238 } 239 240 static void 241 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 242 { 243 int nb_nodes, iort_start = table_data->len; 244 AcpiIortIdMapping *idmap; 245 AcpiIortItsGroup *its; 246 AcpiIortTable *iort; 247 AcpiIortSmmu3 *smmu; 248 size_t node_size, iort_node_offset, iort_length, smmu_offset = 0; 249 AcpiIortRC *rc; 250 251 iort = acpi_data_push(table_data, sizeof(*iort)); 252 253 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 254 nb_nodes = 3; /* RC, ITS, SMMUv3 */ 255 } else { 256 nb_nodes = 2; /* RC, ITS */ 257 } 258 259 iort_length = sizeof(*iort); 260 iort->node_count = cpu_to_le32(nb_nodes); 261 /* 262 * Use a copy in case table_data->data moves during acpi_data_push 263 * operations. 264 */ 265 iort_node_offset = sizeof(*iort); 266 iort->node_offset = cpu_to_le32(iort_node_offset); 267 268 /* ITS group node */ 269 node_size = sizeof(*its) + sizeof(uint32_t); 270 iort_length += node_size; 271 its = acpi_data_push(table_data, node_size); 272 273 its->type = ACPI_IORT_NODE_ITS_GROUP; 274 its->length = cpu_to_le16(node_size); 275 its->its_count = cpu_to_le32(1); 276 its->identifiers[0] = 0; /* MADT translation_id */ 277 278 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 279 int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; 280 281 /* SMMUv3 node */ 282 smmu_offset = iort_node_offset + node_size; 283 node_size = sizeof(*smmu) + sizeof(*idmap); 284 iort_length += node_size; 285 smmu = acpi_data_push(table_data, node_size); 286 287 smmu->type = ACPI_IORT_NODE_SMMU_V3; 288 smmu->length = cpu_to_le16(node_size); 289 smmu->mapping_count = cpu_to_le32(1); 290 smmu->mapping_offset = cpu_to_le32(sizeof(*smmu)); 291 smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base); 292 smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE); 293 smmu->event_gsiv = cpu_to_le32(irq); 294 smmu->pri_gsiv = cpu_to_le32(irq + 1); 295 smmu->gerr_gsiv = cpu_to_le32(irq + 2); 296 smmu->sync_gsiv = cpu_to_le32(irq + 3); 297 298 /* Identity RID mapping covering the whole input RID range */ 299 idmap = &smmu->id_mapping_array[0]; 300 idmap->input_base = 0; 301 idmap->id_count = cpu_to_le32(0xFFFF); 302 idmap->output_base = 0; 303 /* output IORT node is the ITS group node (the first node) */ 304 idmap->output_reference = cpu_to_le32(iort_node_offset); 305 } 306 307 /* Root Complex Node */ 308 node_size = sizeof(*rc) + sizeof(*idmap); 309 iort_length += node_size; 310 rc = acpi_data_push(table_data, node_size); 311 312 rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX; 313 rc->length = cpu_to_le16(node_size); 314 rc->mapping_count = cpu_to_le32(1); 315 rc->mapping_offset = cpu_to_le32(sizeof(*rc)); 316 317 /* fully coherent device */ 318 rc->memory_properties.cache_coherency = cpu_to_le32(1); 319 rc->memory_properties.memory_flags = 0x3; /* CCA = CPM = DCAS = 1 */ 320 rc->pci_segment_number = 0; /* MCFG pci_segment */ 321 322 /* Identity RID mapping covering the whole input RID range */ 323 idmap = &rc->id_mapping_array[0]; 324 idmap->input_base = 0; 325 idmap->id_count = cpu_to_le32(0xFFFF); 326 idmap->output_base = 0; 327 328 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 329 /* output IORT node is the smmuv3 node */ 330 idmap->output_reference = cpu_to_le32(smmu_offset); 331 } else { 332 /* output IORT node is the ITS group node (the first node) */ 333 idmap->output_reference = cpu_to_le32(iort_node_offset); 334 } 335 336 /* 337 * Update the pointer address in case table_data->data moves during above 338 * acpi_data_push operations. 339 */ 340 iort = (AcpiIortTable *)(table_data->data + iort_start); 341 iort->length = cpu_to_le32(iort_length); 342 343 build_header(linker, table_data, (void *)(table_data->data + iort_start), 344 "IORT", table_data->len - iort_start, 0, NULL, NULL); 345 } 346 347 static void 348 build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 349 { 350 AcpiSerialPortConsoleRedirection *spcr; 351 const MemMapEntry *uart_memmap = &vms->memmap[VIRT_UART]; 352 int irq = vms->irqmap[VIRT_UART] + ARM_SPI_BASE; 353 int spcr_start = table_data->len; 354 355 spcr = acpi_data_push(table_data, sizeof(*spcr)); 356 357 spcr->interface_type = 0x3; /* ARM PL011 UART */ 358 359 spcr->base_address.space_id = AML_SYSTEM_MEMORY; 360 spcr->base_address.bit_width = 8; 361 spcr->base_address.bit_offset = 0; 362 spcr->base_address.access_width = 1; 363 spcr->base_address.address = cpu_to_le64(uart_memmap->base); 364 365 spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */ 366 spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */ 367 368 spcr->baud = 3; /* Baud Rate: 3 = 9600 */ 369 spcr->parity = 0; /* No Parity */ 370 spcr->stopbits = 1; /* 1 Stop bit */ 371 spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */ 372 spcr->term_type = 0; /* Terminal Type: 0 = VT100 */ 373 374 spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */ 375 spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */ 376 377 build_header(linker, table_data, (void *)(table_data->data + spcr_start), 378 "SPCR", table_data->len - spcr_start, 2, NULL, NULL); 379 } 380 381 static void 382 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 383 { 384 AcpiSystemResourceAffinityTable *srat; 385 AcpiSratProcessorGiccAffinity *core; 386 AcpiSratMemoryAffinity *numamem; 387 int i, srat_start; 388 uint64_t mem_base; 389 MachineClass *mc = MACHINE_GET_CLASS(vms); 390 MachineState *ms = MACHINE(vms); 391 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); 392 393 srat_start = table_data->len; 394 srat = acpi_data_push(table_data, sizeof(*srat)); 395 srat->reserved1 = cpu_to_le32(1); 396 397 for (i = 0; i < cpu_list->len; ++i) { 398 core = acpi_data_push(table_data, sizeof(*core)); 399 core->type = ACPI_SRAT_PROCESSOR_GICC; 400 core->length = sizeof(*core); 401 core->proximity = cpu_to_le32(cpu_list->cpus[i].props.node_id); 402 core->acpi_processor_uid = cpu_to_le32(i); 403 core->flags = cpu_to_le32(1); 404 } 405 406 mem_base = vms->memmap[VIRT_MEM].base; 407 for (i = 0; i < ms->numa_state->num_nodes; ++i) { 408 if (ms->numa_state->nodes[i].node_mem > 0) { 409 numamem = acpi_data_push(table_data, sizeof(*numamem)); 410 build_srat_memory(numamem, mem_base, 411 ms->numa_state->nodes[i].node_mem, i, 412 MEM_AFFINITY_ENABLED); 413 mem_base += ms->numa_state->nodes[i].node_mem; 414 } 415 } 416 417 if (ms->nvdimms_state->is_enabled) { 418 nvdimm_build_srat(table_data); 419 } 420 421 if (ms->device_memory) { 422 numamem = acpi_data_push(table_data, sizeof *numamem); 423 build_srat_memory(numamem, ms->device_memory->base, 424 memory_region_size(&ms->device_memory->mr), 425 ms->numa_state->num_nodes - 1, 426 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 427 } 428 429 build_header(linker, table_data, (void *)(table_data->data + srat_start), 430 "SRAT", table_data->len - srat_start, 3, NULL, NULL); 431 } 432 433 /* GTDT */ 434 static void 435 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 436 { 437 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 438 int gtdt_start = table_data->len; 439 AcpiGenericTimerTable *gtdt; 440 uint32_t irqflags; 441 442 if (vmc->claim_edge_triggered_timers) { 443 irqflags = ACPI_GTDT_INTERRUPT_MODE_EDGE; 444 } else { 445 irqflags = ACPI_GTDT_INTERRUPT_MODE_LEVEL; 446 } 447 448 gtdt = acpi_data_push(table_data, sizeof *gtdt); 449 /* The interrupt values are the same with the device tree when adding 16 */ 450 gtdt->secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_S_EL1_IRQ + 16); 451 gtdt->secure_el1_flags = cpu_to_le32(irqflags); 452 453 gtdt->non_secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ + 16); 454 gtdt->non_secure_el1_flags = cpu_to_le32(irqflags | 455 ACPI_GTDT_CAP_ALWAYS_ON); 456 457 gtdt->virtual_timer_interrupt = cpu_to_le32(ARCH_TIMER_VIRT_IRQ + 16); 458 gtdt->virtual_timer_flags = cpu_to_le32(irqflags); 459 460 gtdt->non_secure_el2_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ + 16); 461 gtdt->non_secure_el2_flags = cpu_to_le32(irqflags); 462 463 build_header(linker, table_data, 464 (void *)(table_data->data + gtdt_start), "GTDT", 465 table_data->len - gtdt_start, 2, NULL, NULL); 466 } 467 468 /* MADT */ 469 static void 470 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 471 { 472 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 473 int madt_start = table_data->len; 474 const MemMapEntry *memmap = vms->memmap; 475 const int *irqmap = vms->irqmap; 476 AcpiMadtGenericDistributor *gicd; 477 AcpiMadtGenericMsiFrame *gic_msi; 478 int i; 479 480 acpi_data_push(table_data, sizeof(AcpiMultipleApicTable)); 481 482 gicd = acpi_data_push(table_data, sizeof *gicd); 483 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR; 484 gicd->length = sizeof(*gicd); 485 gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base); 486 gicd->version = vms->gic_version; 487 488 for (i = 0; i < MACHINE(vms)->smp.cpus; i++) { 489 AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data, 490 sizeof(*gicc)); 491 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 492 493 gicc->type = ACPI_APIC_GENERIC_CPU_INTERFACE; 494 gicc->length = sizeof(*gicc); 495 if (vms->gic_version == 2) { 496 gicc->base_address = cpu_to_le64(memmap[VIRT_GIC_CPU].base); 497 gicc->gich_base_address = cpu_to_le64(memmap[VIRT_GIC_HYP].base); 498 gicc->gicv_base_address = cpu_to_le64(memmap[VIRT_GIC_VCPU].base); 499 } 500 gicc->cpu_interface_number = cpu_to_le32(i); 501 gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity); 502 gicc->uid = cpu_to_le32(i); 503 gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED); 504 505 if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 506 gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ)); 507 } 508 if (vms->virt) { 509 gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ)); 510 } 511 } 512 513 if (vms->gic_version == 3) { 514 AcpiMadtGenericTranslator *gic_its; 515 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 516 AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data, 517 sizeof *gicr); 518 519 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 520 gicr->length = sizeof(*gicr); 521 gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base); 522 gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size); 523 524 if (nb_redist_regions == 2) { 525 gicr = acpi_data_push(table_data, sizeof(*gicr)); 526 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 527 gicr->length = sizeof(*gicr); 528 gicr->base_address = 529 cpu_to_le64(memmap[VIRT_HIGH_GIC_REDIST2].base); 530 gicr->range_length = 531 cpu_to_le32(memmap[VIRT_HIGH_GIC_REDIST2].size); 532 } 533 534 if (its_class_name() && !vmc->no_its) { 535 gic_its = acpi_data_push(table_data, sizeof *gic_its); 536 gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR; 537 gic_its->length = sizeof(*gic_its); 538 gic_its->translation_id = 0; 539 gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base); 540 } 541 } else { 542 gic_msi = acpi_data_push(table_data, sizeof *gic_msi); 543 gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME; 544 gic_msi->length = sizeof(*gic_msi); 545 gic_msi->gic_msi_frame_id = 0; 546 gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base); 547 gic_msi->flags = cpu_to_le32(1); 548 gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS); 549 gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE); 550 } 551 552 build_header(linker, table_data, 553 (void *)(table_data->data + madt_start), "APIC", 554 table_data->len - madt_start, 3, NULL, NULL); 555 } 556 557 /* FADT */ 558 static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker, 559 VirtMachineState *vms, unsigned dsdt_tbl_offset) 560 { 561 /* ACPI v5.1 */ 562 AcpiFadtData fadt = { 563 .rev = 5, 564 .minor_ver = 1, 565 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, 566 .xdsdt_tbl_offset = &dsdt_tbl_offset, 567 }; 568 569 switch (vms->psci_conduit) { 570 case QEMU_PSCI_CONDUIT_DISABLED: 571 fadt.arm_boot_arch = 0; 572 break; 573 case QEMU_PSCI_CONDUIT_HVC: 574 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT | 575 ACPI_FADT_ARM_PSCI_USE_HVC; 576 break; 577 case QEMU_PSCI_CONDUIT_SMC: 578 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT; 579 break; 580 default: 581 g_assert_not_reached(); 582 } 583 584 build_fadt(table_data, linker, &fadt, NULL, NULL); 585 } 586 587 /* DSDT */ 588 static void 589 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 590 { 591 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 592 Aml *scope, *dsdt; 593 MachineState *ms = MACHINE(vms); 594 const MemMapEntry *memmap = vms->memmap; 595 const int *irqmap = vms->irqmap; 596 597 dsdt = init_aml_allocator(); 598 /* Reserve space for header */ 599 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 600 601 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. 602 * While UEFI can use libfdt to disable the RTC device node in the DTB that 603 * it passes to the OS, it cannot modify AML. Therefore, we won't generate 604 * the RTC ACPI device at all when using UEFI. 605 */ 606 scope = aml_scope("\\_SB"); 607 acpi_dsdt_add_cpus(scope, vms); 608 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], 609 (irqmap[VIRT_UART] + ARM_SPI_BASE)); 610 if (vmc->acpi_expose_flash) { 611 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); 612 } 613 acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); 614 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], 615 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); 616 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), 617 vms->highmem, vms->highmem_ecam, vms); 618 if (vms->acpi_dev) { 619 build_ged_aml(scope, "\\_SB."GED_DEVICE, 620 HOTPLUG_HANDLER(vms->acpi_dev), 621 irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY, 622 memmap[VIRT_ACPI_GED].base); 623 } else { 624 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], 625 (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); 626 } 627 628 if (vms->acpi_dev) { 629 uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev), 630 "ged-event", &error_abort); 631 632 if (event & ACPI_GED_MEM_HOTPLUG_EVT) { 633 build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL, 634 AML_SYSTEM_MEMORY, 635 memmap[VIRT_PCDIMM_ACPI].base); 636 } 637 } 638 639 acpi_dsdt_add_power_button(scope); 640 acpi_dsdt_add_tpm(scope, vms); 641 642 aml_append(dsdt, scope); 643 644 /* copy AML table into ACPI tables blob and patch header there */ 645 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 646 build_header(linker, table_data, 647 (void *)(table_data->data + table_data->len - dsdt->buf->len), 648 "DSDT", dsdt->buf->len, 2, NULL, NULL); 649 free_aml_allocator(); 650 } 651 652 typedef 653 struct AcpiBuildState { 654 /* Copy of table in RAM (for patching). */ 655 MemoryRegion *table_mr; 656 MemoryRegion *rsdp_mr; 657 MemoryRegion *linker_mr; 658 /* Is table patched? */ 659 bool patched; 660 } AcpiBuildState; 661 662 static void acpi_align_size(GArray *blob, unsigned align) 663 { 664 /* 665 * Align size to multiple of given size. This reduces the chance 666 * we need to change size in the future (breaking cross version migration). 667 */ 668 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 669 } 670 671 static 672 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) 673 { 674 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 675 GArray *table_offsets; 676 unsigned dsdt, xsdt; 677 GArray *tables_blob = tables->table_data; 678 MachineState *ms = MACHINE(vms); 679 680 table_offsets = g_array_new(false, true /* clear */, 681 sizeof(uint32_t)); 682 683 bios_linker_loader_alloc(tables->linker, 684 ACPI_BUILD_TABLE_FILE, tables_blob, 685 64, false /* high memory */); 686 687 /* DSDT is pointed to by FADT */ 688 dsdt = tables_blob->len; 689 build_dsdt(tables_blob, tables->linker, vms); 690 691 /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */ 692 acpi_add_table(table_offsets, tables_blob); 693 build_fadt_rev5(tables_blob, tables->linker, vms, dsdt); 694 695 acpi_add_table(table_offsets, tables_blob); 696 build_madt(tables_blob, tables->linker, vms); 697 698 acpi_add_table(table_offsets, tables_blob); 699 build_gtdt(tables_blob, tables->linker, vms); 700 701 acpi_add_table(table_offsets, tables_blob); 702 { 703 AcpiMcfgInfo mcfg = { 704 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, 705 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, 706 }; 707 build_mcfg(tables_blob, tables->linker, &mcfg); 708 } 709 710 acpi_add_table(table_offsets, tables_blob); 711 build_spcr(tables_blob, tables->linker, vms); 712 713 if (vms->ras) { 714 build_ghes_error_table(tables->hardware_errors, tables->linker); 715 acpi_add_table(table_offsets, tables_blob); 716 acpi_build_hest(tables_blob, tables->linker); 717 } 718 719 if (ms->numa_state->num_nodes > 0) { 720 acpi_add_table(table_offsets, tables_blob); 721 build_srat(tables_blob, tables->linker, vms); 722 if (ms->numa_state->have_numa_distance) { 723 acpi_add_table(table_offsets, tables_blob); 724 build_slit(tables_blob, tables->linker, ms); 725 } 726 } 727 728 if (ms->nvdimms_state->is_enabled) { 729 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 730 ms->nvdimms_state, ms->ram_slots); 731 } 732 733 if (its_class_name() && !vmc->no_its) { 734 acpi_add_table(table_offsets, tables_blob); 735 build_iort(tables_blob, tables->linker, vms); 736 } 737 738 if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) { 739 acpi_add_table(table_offsets, tables_blob); 740 build_tpm2(tables_blob, tables->linker, tables->tcpalog); 741 } 742 743 /* XSDT is pointed to by RSDP */ 744 xsdt = tables_blob->len; 745 build_xsdt(tables_blob, tables->linker, table_offsets, NULL, NULL); 746 747 /* RSDP is in FSEG memory, so allocate it separately */ 748 { 749 AcpiRsdpData rsdp_data = { 750 .revision = 2, 751 .oem_id = ACPI_BUILD_APPNAME6, 752 .xsdt_tbl_offset = &xsdt, 753 .rsdt_tbl_offset = NULL, 754 }; 755 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 756 } 757 758 /* 759 * The align size is 128, warn if 64k is not enough therefore 760 * the align size could be resized. 761 */ 762 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 763 warn_report("ACPI table size %u exceeds %d bytes," 764 " migration may not work", 765 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 766 error_printf("Try removing CPUs, NUMA nodes, memory slots" 767 " or PCI bridges."); 768 } 769 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 770 771 772 /* Cleanup memory that's no longer used. */ 773 g_array_free(table_offsets, true); 774 } 775 776 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 777 { 778 uint32_t size = acpi_data_len(data); 779 780 /* Make sure RAM size is correct - in case it got changed 781 * e.g. by migration */ 782 memory_region_ram_resize(mr, size, &error_abort); 783 784 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 785 memory_region_set_dirty(mr, 0, size); 786 } 787 788 static void virt_acpi_build_update(void *build_opaque) 789 { 790 AcpiBuildState *build_state = build_opaque; 791 AcpiBuildTables tables; 792 793 /* No state to update or already patched? Nothing to do. */ 794 if (!build_state || build_state->patched) { 795 return; 796 } 797 build_state->patched = true; 798 799 acpi_build_tables_init(&tables); 800 801 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables); 802 803 acpi_ram_update(build_state->table_mr, tables.table_data); 804 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 805 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 806 807 acpi_build_tables_cleanup(&tables, true); 808 } 809 810 static void virt_acpi_build_reset(void *build_opaque) 811 { 812 AcpiBuildState *build_state = build_opaque; 813 build_state->patched = false; 814 } 815 816 static const VMStateDescription vmstate_virt_acpi_build = { 817 .name = "virt_acpi_build", 818 .version_id = 1, 819 .minimum_version_id = 1, 820 .fields = (VMStateField[]) { 821 VMSTATE_BOOL(patched, AcpiBuildState), 822 VMSTATE_END_OF_LIST() 823 }, 824 }; 825 826 void virt_acpi_setup(VirtMachineState *vms) 827 { 828 AcpiBuildTables tables; 829 AcpiBuildState *build_state; 830 AcpiGedState *acpi_ged_state; 831 832 if (!vms->fw_cfg) { 833 trace_virt_acpi_setup(); 834 return; 835 } 836 837 if (!virt_is_acpi_enabled(vms)) { 838 trace_virt_acpi_setup(); 839 return; 840 } 841 842 build_state = g_malloc0(sizeof *build_state); 843 844 acpi_build_tables_init(&tables); 845 virt_acpi_build(vms, &tables); 846 847 /* Now expose it all to Guest */ 848 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, 849 build_state, tables.table_data, 850 ACPI_BUILD_TABLE_FILE, 851 ACPI_BUILD_TABLE_MAX_SIZE); 852 assert(build_state->table_mr != NULL); 853 854 build_state->linker_mr = 855 acpi_add_rom_blob(virt_acpi_build_update, build_state, 856 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0); 857 858 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, 859 acpi_data_len(tables.tcpalog)); 860 861 if (vms->ras) { 862 assert(vms->acpi_dev); 863 acpi_ged_state = ACPI_GED(vms->acpi_dev); 864 acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state, 865 vms->fw_cfg, tables.hardware_errors); 866 } 867 868 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, 869 build_state, tables.rsdp, 870 ACPI_BUILD_RSDP_FILE, 0); 871 872 qemu_register_reset(virt_acpi_build_reset, build_state); 873 virt_acpi_build_reset(build_state); 874 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 875 876 /* Cleanup tables but don't free the memory: we track it 877 * in build_state. 878 */ 879 acpi_build_tables_cleanup(&tables, false); 880 } 881