1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * ARM virt ACPI generation 4 * 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 6 * Copyright (C) 2006 Fabrice Bellard 7 * Copyright (C) 2013 Red Hat Inc 8 * 9 * Author: Michael S. Tsirkin <mst@redhat.com> 10 * 11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 12 * 13 * Author: Shannon Zhao <zhaoshenglong@huawei.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu-common.h" 30 #include "hw/arm/virt-acpi-build.h" 31 #include "qemu/bitmap.h" 32 #include "trace.h" 33 #include "qom/cpu.h" 34 #include "target-arm/cpu.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/loader.h" 40 #include "hw/hw.h" 41 #include "hw/acpi/aml-build.h" 42 #include "hw/pci/pcie_host.h" 43 #include "hw/pci/pci.h" 44 45 #define ARM_SPI_BASE 32 46 #define ACPI_POWER_BUTTON_DEVICE "PWRB" 47 48 typedef struct VirtAcpiCpuInfo { 49 DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT); 50 } VirtAcpiCpuInfo; 51 52 static void virt_acpi_get_cpu_info(VirtAcpiCpuInfo *cpuinfo) 53 { 54 CPUState *cpu; 55 56 memset(cpuinfo->found_cpus, 0, sizeof cpuinfo->found_cpus); 57 CPU_FOREACH(cpu) { 58 set_bit(cpu->cpu_index, cpuinfo->found_cpus); 59 } 60 } 61 62 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) 63 { 64 uint16_t i; 65 66 for (i = 0; i < smp_cpus; i++) { 67 Aml *dev = aml_device("C%03x", i); 68 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 69 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 70 aml_append(scope, dev); 71 } 72 } 73 74 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 75 uint32_t uart_irq) 76 { 77 Aml *dev = aml_device("COM0"); 78 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); 79 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 80 81 Aml *crs = aml_resource_template(); 82 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 83 uart_memmap->size, AML_READ_WRITE)); 84 aml_append(crs, 85 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 86 AML_EXCLUSIVE, &uart_irq, 1)); 87 aml_append(dev, aml_name_decl("_CRS", crs)); 88 89 /* The _ADR entry is used to link this device to the UART described 90 * in the SPCR table, i.e. SPCR.base_address.address == _ADR. 91 */ 92 aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base))); 93 94 aml_append(scope, dev); 95 } 96 97 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) 98 { 99 Aml *dev, *crs; 100 hwaddr base = flash_memmap->base; 101 hwaddr size = flash_memmap->size / 2; 102 103 dev = aml_device("FLS0"); 104 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 105 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 106 107 crs = aml_resource_template(); 108 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 109 aml_append(dev, aml_name_decl("_CRS", crs)); 110 aml_append(scope, dev); 111 112 dev = aml_device("FLS1"); 113 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 114 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 115 crs = aml_resource_template(); 116 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); 117 aml_append(dev, aml_name_decl("_CRS", crs)); 118 aml_append(scope, dev); 119 } 120 121 static void acpi_dsdt_add_virtio(Aml *scope, 122 const MemMapEntry *virtio_mmio_memmap, 123 uint32_t mmio_irq, int num) 124 { 125 hwaddr base = virtio_mmio_memmap->base; 126 hwaddr size = virtio_mmio_memmap->size; 127 int i; 128 129 for (i = 0; i < num; i++) { 130 uint32_t irq = mmio_irq + i; 131 Aml *dev = aml_device("VR%02u", i); 132 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); 133 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 134 135 Aml *crs = aml_resource_template(); 136 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 137 aml_append(crs, 138 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 139 AML_EXCLUSIVE, &irq, 1)); 140 aml_append(dev, aml_name_decl("_CRS", crs)); 141 aml_append(scope, dev); 142 base += size; 143 } 144 } 145 146 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, 147 uint32_t irq, bool use_highmem) 148 { 149 Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; 150 int i, bus_no; 151 hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base; 152 hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size; 153 hwaddr base_pio = memmap[VIRT_PCIE_PIO].base; 154 hwaddr size_pio = memmap[VIRT_PCIE_PIO].size; 155 hwaddr base_ecam = memmap[VIRT_PCIE_ECAM].base; 156 hwaddr size_ecam = memmap[VIRT_PCIE_ECAM].size; 157 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 158 159 Aml *dev = aml_device("%s", "PCI0"); 160 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); 161 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); 162 aml_append(dev, aml_name_decl("_SEG", aml_int(0))); 163 aml_append(dev, aml_name_decl("_BBN", aml_int(0))); 164 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 165 aml_append(dev, aml_name_decl("_UID", aml_string("PCI0"))); 166 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); 167 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 168 169 /* Declare the PCI Routing Table. */ 170 Aml *rt_pkg = aml_package(nr_pcie_buses * PCI_NUM_PINS); 171 for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) { 172 for (i = 0; i < PCI_NUM_PINS; i++) { 173 int gsi = (i + bus_no) % PCI_NUM_PINS; 174 Aml *pkg = aml_package(4); 175 aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF)); 176 aml_append(pkg, aml_int(i)); 177 aml_append(pkg, aml_name("GSI%d", gsi)); 178 aml_append(pkg, aml_int(0)); 179 aml_append(rt_pkg, pkg); 180 } 181 } 182 aml_append(dev, aml_name_decl("_PRT", rt_pkg)); 183 184 /* Create GSI link device */ 185 for (i = 0; i < PCI_NUM_PINS; i++) { 186 uint32_t irqs = irq + i; 187 Aml *dev_gsi = aml_device("GSI%d", i); 188 aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); 189 aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0))); 190 crs = aml_resource_template(); 191 aml_append(crs, 192 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 193 AML_EXCLUSIVE, &irqs, 1)); 194 aml_append(dev_gsi, aml_name_decl("_PRS", crs)); 195 crs = aml_resource_template(); 196 aml_append(crs, 197 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 198 AML_EXCLUSIVE, &irqs, 1)); 199 aml_append(dev_gsi, aml_name_decl("_CRS", crs)); 200 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 201 aml_append(dev_gsi, method); 202 aml_append(dev, dev_gsi); 203 } 204 205 method = aml_method("_CBA", 0, AML_NOTSERIALIZED); 206 aml_append(method, aml_return(aml_int(base_ecam))); 207 aml_append(dev, method); 208 209 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 210 Aml *rbuf = aml_resource_template(); 211 aml_append(rbuf, 212 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 213 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, 214 nr_pcie_buses)); 215 aml_append(rbuf, 216 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 217 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio, 218 base_mmio + size_mmio - 1, 0x0000, size_mmio)); 219 aml_append(rbuf, 220 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 221 AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio, 222 size_pio)); 223 224 if (use_highmem) { 225 hwaddr base_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].base; 226 hwaddr size_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].size; 227 228 aml_append(rbuf, 229 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 230 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, 231 base_mmio_high, base_mmio_high, 0x0000, 232 size_mmio_high)); 233 } 234 235 aml_append(method, aml_name_decl("RBUF", rbuf)); 236 aml_append(method, aml_return(rbuf)); 237 aml_append(dev, method); 238 239 /* Declare an _OSC (OS Control Handoff) method */ 240 aml_append(dev, aml_name_decl("SUPP", aml_int(0))); 241 aml_append(dev, aml_name_decl("CTRL", aml_int(0))); 242 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 243 aml_append(method, 244 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 245 246 /* PCI Firmware Specification 3.0 247 * 4.5.1. _OSC Interface for PCI Host Bridge Devices 248 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is 249 * identified by the Universal Unique IDentifier (UUID) 250 * 33DB4D5B-1FF7-401C-9657-7441C03DD766 251 */ 252 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"); 253 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 254 aml_append(ifctx, 255 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 256 aml_append(ifctx, 257 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 258 aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); 259 aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); 260 aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL), 261 aml_name("CTRL"))); 262 263 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); 264 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08), NULL), 265 aml_name("CDW1"))); 266 aml_append(ifctx, ifctx1); 267 268 ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL")))); 269 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10), NULL), 270 aml_name("CDW1"))); 271 aml_append(ifctx, ifctx1); 272 273 aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3"))); 274 aml_append(ifctx, aml_return(aml_arg(3))); 275 aml_append(method, ifctx); 276 277 elsectx = aml_else(); 278 aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4), NULL), 279 aml_name("CDW1"))); 280 aml_append(elsectx, aml_return(aml_arg(3))); 281 aml_append(method, elsectx); 282 aml_append(dev, method); 283 284 method = aml_method("_DSM", 4, AML_NOTSERIALIZED); 285 286 /* PCI Firmware Specification 3.0 287 * 4.6.1. _DSM for PCI Express Slot Information 288 * The UUID in _DSM in this context is 289 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} 290 */ 291 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 292 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 293 ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0))); 294 uint8_t byte_list[1] = {1}; 295 buf = aml_buffer(1, byte_list); 296 aml_append(ifctx1, aml_return(buf)); 297 aml_append(ifctx, ifctx1); 298 aml_append(method, ifctx); 299 300 byte_list[0] = 0; 301 buf = aml_buffer(1, byte_list); 302 aml_append(method, aml_return(buf)); 303 aml_append(dev, method); 304 305 Aml *dev_rp0 = aml_device("%s", "RP0"); 306 aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0))); 307 aml_append(dev, dev_rp0); 308 aml_append(scope, dev); 309 } 310 311 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, 312 uint32_t gpio_irq) 313 { 314 Aml *dev = aml_device("GPO0"); 315 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); 316 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 317 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 318 319 Aml *crs = aml_resource_template(); 320 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, 321 AML_READ_WRITE)); 322 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 323 AML_EXCLUSIVE, &gpio_irq, 1)); 324 aml_append(dev, aml_name_decl("_CRS", crs)); 325 326 Aml *aei = aml_resource_template(); 327 /* Pin 3 for power button */ 328 const uint32_t pin_list[1] = {3}; 329 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, 330 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, 331 "GPO0", NULL, 0)); 332 aml_append(dev, aml_name_decl("_AEI", aei)); 333 334 /* _E03 is handle for power button */ 335 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); 336 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), 337 aml_int(0x80))); 338 aml_append(dev, method); 339 aml_append(scope, dev); 340 } 341 342 static void acpi_dsdt_add_power_button(Aml *scope) 343 { 344 Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE); 345 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C"))); 346 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 347 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 348 aml_append(scope, dev); 349 } 350 351 /* RSDP */ 352 static GArray * 353 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) 354 { 355 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 356 357 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, 358 true /* fseg memory */); 359 360 memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature)); 361 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, sizeof(rsdp->oem_id)); 362 rsdp->length = cpu_to_le32(sizeof(*rsdp)); 363 rsdp->revision = 0x02; 364 365 /* Point to RSDT */ 366 rsdp->rsdt_physical_address = cpu_to_le32(rsdt); 367 /* Address to be filled by Guest linker */ 368 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, 369 ACPI_BUILD_TABLE_FILE, 370 rsdp_table, &rsdp->rsdt_physical_address, 371 sizeof rsdp->rsdt_physical_address); 372 rsdp->checksum = 0; 373 /* Checksum to be filled by Guest linker */ 374 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 375 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum); 376 377 return rsdp_table; 378 } 379 380 static void 381 build_spcr(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 382 { 383 AcpiSerialPortConsoleRedirection *spcr; 384 const MemMapEntry *uart_memmap = &guest_info->memmap[VIRT_UART]; 385 int irq = guest_info->irqmap[VIRT_UART] + ARM_SPI_BASE; 386 387 spcr = acpi_data_push(table_data, sizeof(*spcr)); 388 389 spcr->interface_type = 0x3; /* ARM PL011 UART */ 390 391 spcr->base_address.space_id = AML_SYSTEM_MEMORY; 392 spcr->base_address.bit_width = 8; 393 spcr->base_address.bit_offset = 0; 394 spcr->base_address.access_width = 1; 395 spcr->base_address.address = cpu_to_le64(uart_memmap->base); 396 397 spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */ 398 spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */ 399 400 spcr->baud = 3; /* Baud Rate: 3 = 9600 */ 401 spcr->parity = 0; /* No Parity */ 402 spcr->stopbits = 1; /* 1 Stop bit */ 403 spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */ 404 spcr->term_type = 0; /* Terminal Type: 0 = VT100 */ 405 406 spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */ 407 spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */ 408 409 build_header(linker, table_data, (void *)spcr, "SPCR", sizeof(*spcr), 2, 410 NULL); 411 } 412 413 static void 414 build_mcfg(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 415 { 416 AcpiTableMcfg *mcfg; 417 const MemMapEntry *memmap = guest_info->memmap; 418 int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]); 419 420 mcfg = acpi_data_push(table_data, len); 421 mcfg->allocation[0].address = cpu_to_le64(memmap[VIRT_PCIE_ECAM].base); 422 423 /* Only a single allocation so no need to play with segments */ 424 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 425 mcfg->allocation[0].start_bus_number = 0; 426 mcfg->allocation[0].end_bus_number = (memmap[VIRT_PCIE_ECAM].size 427 / PCIE_MMCFG_SIZE_MIN) - 1; 428 429 build_header(linker, table_data, (void *)mcfg, "MCFG", len, 1, NULL); 430 } 431 432 /* GTDT */ 433 static void 434 build_gtdt(GArray *table_data, GArray *linker) 435 { 436 int gtdt_start = table_data->len; 437 AcpiGenericTimerTable *gtdt; 438 439 gtdt = acpi_data_push(table_data, sizeof *gtdt); 440 /* The interrupt values are the same with the device tree when adding 16 */ 441 gtdt->secure_el1_interrupt = ARCH_TIMER_S_EL1_IRQ + 16; 442 gtdt->secure_el1_flags = ACPI_EDGE_SENSITIVE; 443 444 gtdt->non_secure_el1_interrupt = ARCH_TIMER_NS_EL1_IRQ + 16; 445 gtdt->non_secure_el1_flags = ACPI_EDGE_SENSITIVE; 446 447 gtdt->virtual_timer_interrupt = ARCH_TIMER_VIRT_IRQ + 16; 448 gtdt->virtual_timer_flags = ACPI_EDGE_SENSITIVE; 449 450 gtdt->non_secure_el2_interrupt = ARCH_TIMER_NS_EL2_IRQ + 16; 451 gtdt->non_secure_el2_flags = ACPI_EDGE_SENSITIVE; 452 453 build_header(linker, table_data, 454 (void *)(table_data->data + gtdt_start), "GTDT", 455 table_data->len - gtdt_start, 2, NULL); 456 } 457 458 /* MADT */ 459 static void 460 build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info, 461 VirtAcpiCpuInfo *cpuinfo) 462 { 463 int madt_start = table_data->len; 464 const MemMapEntry *memmap = guest_info->memmap; 465 const int *irqmap = guest_info->irqmap; 466 AcpiMultipleApicTable *madt; 467 AcpiMadtGenericDistributor *gicd; 468 AcpiMadtGenericMsiFrame *gic_msi; 469 int i; 470 471 madt = acpi_data_push(table_data, sizeof *madt); 472 473 gicd = acpi_data_push(table_data, sizeof *gicd); 474 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR; 475 gicd->length = sizeof(*gicd); 476 gicd->base_address = memmap[VIRT_GIC_DIST].base; 477 478 for (i = 0; i < guest_info->smp_cpus; i++) { 479 AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data, 480 sizeof *gicc); 481 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 482 483 gicc->type = ACPI_APIC_GENERIC_INTERRUPT; 484 gicc->length = sizeof(*gicc); 485 if (guest_info->gic_version == 2) { 486 gicc->base_address = memmap[VIRT_GIC_CPU].base; 487 } 488 gicc->cpu_interface_number = i; 489 gicc->arm_mpidr = armcpu->mp_affinity; 490 gicc->uid = i; 491 if (test_bit(i, cpuinfo->found_cpus)) { 492 gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED); 493 } 494 } 495 496 if (guest_info->gic_version == 3) { 497 AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data, 498 sizeof *gicr); 499 500 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 501 gicr->length = sizeof(*gicr); 502 gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base); 503 gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size); 504 } else { 505 gic_msi = acpi_data_push(table_data, sizeof *gic_msi); 506 gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME; 507 gic_msi->length = sizeof(*gic_msi); 508 gic_msi->gic_msi_frame_id = 0; 509 gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base); 510 gic_msi->flags = cpu_to_le32(1); 511 gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS); 512 gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE); 513 } 514 515 build_header(linker, table_data, 516 (void *)(table_data->data + madt_start), "APIC", 517 table_data->len - madt_start, 3, NULL); 518 } 519 520 /* FADT */ 521 static void 522 build_fadt(GArray *table_data, GArray *linker, unsigned dsdt) 523 { 524 AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); 525 526 /* Hardware Reduced = 1 and use PSCI 0.2+ and with HVC */ 527 fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI); 528 fadt->arm_boot_flags = cpu_to_le16((1 << ACPI_FADT_ARM_USE_PSCI_G_0_2) | 529 (1 << ACPI_FADT_ARM_PSCI_USE_HVC)); 530 531 /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */ 532 fadt->minor_revision = 0x1; 533 534 fadt->dsdt = cpu_to_le32(dsdt); 535 /* DSDT address to be filled by Guest linker */ 536 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 537 ACPI_BUILD_TABLE_FILE, 538 table_data, &fadt->dsdt, 539 sizeof fadt->dsdt); 540 541 build_header(linker, table_data, 542 (void *)fadt, "FACP", sizeof(*fadt), 5, NULL); 543 } 544 545 /* DSDT */ 546 static void 547 build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 548 { 549 Aml *scope, *dsdt; 550 const MemMapEntry *memmap = guest_info->memmap; 551 const int *irqmap = guest_info->irqmap; 552 553 dsdt = init_aml_allocator(); 554 /* Reserve space for header */ 555 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 556 557 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. 558 * While UEFI can use libfdt to disable the RTC device node in the DTB that 559 * it passes to the OS, it cannot modify AML. Therefore, we won't generate 560 * the RTC ACPI device at all when using UEFI. 561 */ 562 scope = aml_scope("\\_SB"); 563 acpi_dsdt_add_cpus(scope, guest_info->smp_cpus); 564 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], 565 (irqmap[VIRT_UART] + ARM_SPI_BASE)); 566 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); 567 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], 568 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); 569 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), 570 guest_info->use_highmem); 571 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], 572 (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); 573 acpi_dsdt_add_power_button(scope); 574 575 aml_append(dsdt, scope); 576 577 /* copy AML table into ACPI tables blob and patch header there */ 578 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 579 build_header(linker, table_data, 580 (void *)(table_data->data + table_data->len - dsdt->buf->len), 581 "DSDT", dsdt->buf->len, 2, NULL); 582 free_aml_allocator(); 583 } 584 585 typedef 586 struct AcpiBuildState { 587 /* Copy of table in RAM (for patching). */ 588 MemoryRegion *table_mr; 589 MemoryRegion *rsdp_mr; 590 MemoryRegion *linker_mr; 591 /* Is table patched? */ 592 bool patched; 593 VirtGuestInfo *guest_info; 594 } AcpiBuildState; 595 596 static 597 void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables) 598 { 599 GArray *table_offsets; 600 unsigned dsdt, rsdt; 601 VirtAcpiCpuInfo cpuinfo; 602 GArray *tables_blob = tables->table_data; 603 604 virt_acpi_get_cpu_info(&cpuinfo); 605 606 table_offsets = g_array_new(false, true /* clear */, 607 sizeof(uint32_t)); 608 609 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, 610 64, false /* high memory */); 611 612 /* 613 * The ACPI v5.1 tables for Hardware-reduced ACPI platform are: 614 * RSDP 615 * RSDT 616 * FADT 617 * GTDT 618 * MADT 619 * MCFG 620 * DSDT 621 */ 622 623 /* DSDT is pointed to by FADT */ 624 dsdt = tables_blob->len; 625 build_dsdt(tables_blob, tables->linker, guest_info); 626 627 /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */ 628 acpi_add_table(table_offsets, tables_blob); 629 build_fadt(tables_blob, tables->linker, dsdt); 630 631 acpi_add_table(table_offsets, tables_blob); 632 build_madt(tables_blob, tables->linker, guest_info, &cpuinfo); 633 634 acpi_add_table(table_offsets, tables_blob); 635 build_gtdt(tables_blob, tables->linker); 636 637 acpi_add_table(table_offsets, tables_blob); 638 build_mcfg(tables_blob, tables->linker, guest_info); 639 640 acpi_add_table(table_offsets, tables_blob); 641 build_spcr(tables_blob, tables->linker, guest_info); 642 643 /* RSDT is pointed to by RSDP */ 644 rsdt = tables_blob->len; 645 build_rsdt(tables_blob, tables->linker, table_offsets); 646 647 /* RSDP is in FSEG memory, so allocate it separately */ 648 build_rsdp(tables->rsdp, tables->linker, rsdt); 649 650 /* Cleanup memory that's no longer used. */ 651 g_array_free(table_offsets, true); 652 } 653 654 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 655 { 656 uint32_t size = acpi_data_len(data); 657 658 /* Make sure RAM size is correct - in case it got changed 659 * e.g. by migration */ 660 memory_region_ram_resize(mr, size, &error_abort); 661 662 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 663 memory_region_set_dirty(mr, 0, size); 664 } 665 666 static void virt_acpi_build_update(void *build_opaque) 667 { 668 AcpiBuildState *build_state = build_opaque; 669 AcpiBuildTables tables; 670 671 /* No state to update or already patched? Nothing to do. */ 672 if (!build_state || build_state->patched) { 673 return; 674 } 675 build_state->patched = true; 676 677 acpi_build_tables_init(&tables); 678 679 virt_acpi_build(build_state->guest_info, &tables); 680 681 acpi_ram_update(build_state->table_mr, tables.table_data); 682 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 683 acpi_ram_update(build_state->linker_mr, tables.linker); 684 685 686 acpi_build_tables_cleanup(&tables, true); 687 } 688 689 static void virt_acpi_build_reset(void *build_opaque) 690 { 691 AcpiBuildState *build_state = build_opaque; 692 build_state->patched = false; 693 } 694 695 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, 696 GArray *blob, const char *name, 697 uint64_t max_size) 698 { 699 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 700 name, virt_acpi_build_update, build_state); 701 } 702 703 static const VMStateDescription vmstate_virt_acpi_build = { 704 .name = "virt_acpi_build", 705 .version_id = 1, 706 .minimum_version_id = 1, 707 .fields = (VMStateField[]) { 708 VMSTATE_BOOL(patched, AcpiBuildState), 709 VMSTATE_END_OF_LIST() 710 }, 711 }; 712 713 void virt_acpi_setup(VirtGuestInfo *guest_info) 714 { 715 AcpiBuildTables tables; 716 AcpiBuildState *build_state; 717 718 if (!guest_info->fw_cfg) { 719 trace_virt_acpi_setup(); 720 return; 721 } 722 723 if (!acpi_enabled) { 724 trace_virt_acpi_setup(); 725 return; 726 } 727 728 build_state = g_malloc0(sizeof *build_state); 729 build_state->guest_info = guest_info; 730 731 acpi_build_tables_init(&tables); 732 virt_acpi_build(build_state->guest_info, &tables); 733 734 /* Now expose it all to Guest */ 735 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, 736 ACPI_BUILD_TABLE_FILE, 737 ACPI_BUILD_TABLE_MAX_SIZE); 738 assert(build_state->table_mr != NULL); 739 740 build_state->linker_mr = 741 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); 742 743 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 744 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 745 746 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, 747 ACPI_BUILD_RSDP_FILE, 0); 748 749 qemu_register_reset(virt_acpi_build_reset, build_state); 750 virt_acpi_build_reset(build_state); 751 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 752 753 /* Cleanup tables but don't free the memory: we track it 754 * in build_state. 755 */ 756 acpi_build_tables_cleanup(&tables, false); 757 } 758