1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * ARM virt ACPI generation 4 * 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 6 * Copyright (C) 2006 Fabrice Bellard 7 * Copyright (C) 2013 Red Hat Inc 8 * 9 * Author: Michael S. Tsirkin <mst@redhat.com> 10 * 11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 12 * 13 * Author: Shannon Zhao <zhaoshenglong@huawei.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "qapi/error.h" 31 #include "qemu/bitmap.h" 32 #include "trace.h" 33 #include "hw/core/cpu.h" 34 #include "target/arm/cpu.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/acpi/aml-build.h" 40 #include "hw/acpi/utils.h" 41 #include "hw/acpi/pci.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "hw/acpi/generic_event_device.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/pci/pcie_host.h" 46 #include "hw/pci/pci.h" 47 #include "hw/arm/virt.h" 48 #include "hw/mem/nvdimm.h" 49 #include "hw/platform-bus.h" 50 #include "sysemu/numa.h" 51 #include "sysemu/reset.h" 52 #include "sysemu/tpm.h" 53 #include "kvm_arm.h" 54 #include "migration/vmstate.h" 55 #include "hw/acpi/ghes.h" 56 57 #define ARM_SPI_BASE 32 58 59 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) 60 { 61 uint16_t i; 62 63 for (i = 0; i < smp_cpus; i++) { 64 Aml *dev = aml_device("C%.03X", i); 65 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 66 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 67 aml_append(scope, dev); 68 } 69 } 70 71 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 72 uint32_t uart_irq) 73 { 74 Aml *dev = aml_device("COM0"); 75 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); 76 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 77 78 Aml *crs = aml_resource_template(); 79 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 80 uart_memmap->size, AML_READ_WRITE)); 81 aml_append(crs, 82 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 83 AML_EXCLUSIVE, &uart_irq, 1)); 84 aml_append(dev, aml_name_decl("_CRS", crs)); 85 86 aml_append(scope, dev); 87 } 88 89 static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) 90 { 91 Aml *dev = aml_device("FWCF"); 92 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 93 /* device present, functioning, decoding, not shown in UI */ 94 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 95 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 96 97 Aml *crs = aml_resource_template(); 98 aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, 99 fw_cfg_memmap->size, AML_READ_WRITE)); 100 aml_append(dev, aml_name_decl("_CRS", crs)); 101 aml_append(scope, dev); 102 } 103 104 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) 105 { 106 Aml *dev, *crs; 107 hwaddr base = flash_memmap->base; 108 hwaddr size = flash_memmap->size / 2; 109 110 dev = aml_device("FLS0"); 111 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 112 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 113 114 crs = aml_resource_template(); 115 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 116 aml_append(dev, aml_name_decl("_CRS", crs)); 117 aml_append(scope, dev); 118 119 dev = aml_device("FLS1"); 120 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 121 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 122 crs = aml_resource_template(); 123 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); 124 aml_append(dev, aml_name_decl("_CRS", crs)); 125 aml_append(scope, dev); 126 } 127 128 static void acpi_dsdt_add_virtio(Aml *scope, 129 const MemMapEntry *virtio_mmio_memmap, 130 uint32_t mmio_irq, int num) 131 { 132 hwaddr base = virtio_mmio_memmap->base; 133 hwaddr size = virtio_mmio_memmap->size; 134 int i; 135 136 for (i = 0; i < num; i++) { 137 uint32_t irq = mmio_irq + i; 138 Aml *dev = aml_device("VR%02u", i); 139 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); 140 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 141 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 142 143 Aml *crs = aml_resource_template(); 144 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 145 aml_append(crs, 146 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 147 AML_EXCLUSIVE, &irq, 1)); 148 aml_append(dev, aml_name_decl("_CRS", crs)); 149 aml_append(scope, dev); 150 base += size; 151 } 152 } 153 154 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, 155 uint32_t irq, bool use_highmem, bool highmem_ecam) 156 { 157 int ecam_id = VIRT_ECAM_ID(highmem_ecam); 158 Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; 159 int i, slot_no; 160 hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base; 161 hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size; 162 hwaddr base_pio = memmap[VIRT_PCIE_PIO].base; 163 hwaddr size_pio = memmap[VIRT_PCIE_PIO].size; 164 hwaddr base_ecam = memmap[ecam_id].base; 165 hwaddr size_ecam = memmap[ecam_id].size; 166 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 167 168 Aml *dev = aml_device("%s", "PCI0"); 169 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); 170 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); 171 aml_append(dev, aml_name_decl("_SEG", aml_int(0))); 172 aml_append(dev, aml_name_decl("_BBN", aml_int(0))); 173 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 174 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); 175 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 176 177 /* Declare the PCI Routing Table. */ 178 Aml *rt_pkg = aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS); 179 for (slot_no = 0; slot_no < PCI_SLOT_MAX; slot_no++) { 180 for (i = 0; i < PCI_NUM_PINS; i++) { 181 int gsi = (i + slot_no) % PCI_NUM_PINS; 182 Aml *pkg = aml_package(4); 183 aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF)); 184 aml_append(pkg, aml_int(i)); 185 aml_append(pkg, aml_name("GSI%d", gsi)); 186 aml_append(pkg, aml_int(0)); 187 aml_append(rt_pkg, pkg); 188 } 189 } 190 aml_append(dev, aml_name_decl("_PRT", rt_pkg)); 191 192 /* Create GSI link device */ 193 for (i = 0; i < PCI_NUM_PINS; i++) { 194 uint32_t irqs = irq + i; 195 Aml *dev_gsi = aml_device("GSI%d", i); 196 aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); 197 aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i))); 198 crs = aml_resource_template(); 199 aml_append(crs, 200 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 201 AML_EXCLUSIVE, &irqs, 1)); 202 aml_append(dev_gsi, aml_name_decl("_PRS", crs)); 203 crs = aml_resource_template(); 204 aml_append(crs, 205 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 206 AML_EXCLUSIVE, &irqs, 1)); 207 aml_append(dev_gsi, aml_name_decl("_CRS", crs)); 208 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 209 aml_append(dev_gsi, method); 210 aml_append(dev, dev_gsi); 211 } 212 213 method = aml_method("_CBA", 0, AML_NOTSERIALIZED); 214 aml_append(method, aml_return(aml_int(base_ecam))); 215 aml_append(dev, method); 216 217 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 218 Aml *rbuf = aml_resource_template(); 219 aml_append(rbuf, 220 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 221 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, 222 nr_pcie_buses)); 223 aml_append(rbuf, 224 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 225 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio, 226 base_mmio + size_mmio - 1, 0x0000, size_mmio)); 227 aml_append(rbuf, 228 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 229 AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio, 230 size_pio)); 231 232 if (use_highmem) { 233 hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base; 234 hwaddr size_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].size; 235 236 aml_append(rbuf, 237 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 238 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, 239 base_mmio_high, 240 base_mmio_high + size_mmio_high - 1, 0x0000, 241 size_mmio_high)); 242 } 243 244 aml_append(method, aml_return(rbuf)); 245 aml_append(dev, method); 246 247 /* Declare an _OSC (OS Control Handoff) method */ 248 aml_append(dev, aml_name_decl("SUPP", aml_int(0))); 249 aml_append(dev, aml_name_decl("CTRL", aml_int(0))); 250 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 251 aml_append(method, 252 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 253 254 /* PCI Firmware Specification 3.0 255 * 4.5.1. _OSC Interface for PCI Host Bridge Devices 256 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is 257 * identified by the Universal Unique IDentifier (UUID) 258 * 33DB4D5B-1FF7-401C-9657-7441C03DD766 259 */ 260 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"); 261 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 262 aml_append(ifctx, 263 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 264 aml_append(ifctx, 265 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 266 aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); 267 aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); 268 269 /* 270 * Allow OS control for all 5 features: 271 * PCIeHotplug SHPCHotplug PME AER PCIeCapability. 272 */ 273 aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F), 274 aml_name("CTRL"))); 275 276 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); 277 aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08), 278 aml_name("CDW1"))); 279 aml_append(ifctx, ifctx1); 280 281 ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL")))); 282 aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10), 283 aml_name("CDW1"))); 284 aml_append(ifctx, ifctx1); 285 286 aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3"))); 287 aml_append(ifctx, aml_return(aml_arg(3))); 288 aml_append(method, ifctx); 289 290 elsectx = aml_else(); 291 aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4), 292 aml_name("CDW1"))); 293 aml_append(elsectx, aml_return(aml_arg(3))); 294 aml_append(method, elsectx); 295 aml_append(dev, method); 296 297 method = aml_method("_DSM", 4, AML_NOTSERIALIZED); 298 299 /* PCI Firmware Specification 3.0 300 * 4.6.1. _DSM for PCI Express Slot Information 301 * The UUID in _DSM in this context is 302 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} 303 */ 304 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 305 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 306 ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0))); 307 uint8_t byte_list[1] = {1}; 308 buf = aml_buffer(1, byte_list); 309 aml_append(ifctx1, aml_return(buf)); 310 aml_append(ifctx, ifctx1); 311 aml_append(method, ifctx); 312 313 byte_list[0] = 0; 314 buf = aml_buffer(1, byte_list); 315 aml_append(method, aml_return(buf)); 316 aml_append(dev, method); 317 318 Aml *dev_res0 = aml_device("%s", "RES0"); 319 aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); 320 crs = aml_resource_template(); 321 aml_append(crs, 322 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 323 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_ecam, 324 base_ecam + size_ecam - 1, 0x0000, size_ecam)); 325 aml_append(dev_res0, aml_name_decl("_CRS", crs)); 326 aml_append(dev, dev_res0); 327 aml_append(scope, dev); 328 } 329 330 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, 331 uint32_t gpio_irq) 332 { 333 Aml *dev = aml_device("GPO0"); 334 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); 335 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 336 337 Aml *crs = aml_resource_template(); 338 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, 339 AML_READ_WRITE)); 340 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 341 AML_EXCLUSIVE, &gpio_irq, 1)); 342 aml_append(dev, aml_name_decl("_CRS", crs)); 343 344 Aml *aei = aml_resource_template(); 345 /* Pin 3 for power button */ 346 const uint32_t pin_list[1] = {3}; 347 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, 348 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, 349 "GPO0", NULL, 0)); 350 aml_append(dev, aml_name_decl("_AEI", aei)); 351 352 /* _E03 is handle for power button */ 353 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); 354 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), 355 aml_int(0x80))); 356 aml_append(dev, method); 357 aml_append(scope, dev); 358 } 359 360 static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms) 361 { 362 PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); 363 hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base; 364 SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find()); 365 MemoryRegion *sbdev_mr; 366 hwaddr tpm_base; 367 368 if (!sbdev) { 369 return; 370 } 371 372 tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); 373 assert(tpm_base != -1); 374 375 tpm_base += pbus_base; 376 377 sbdev_mr = sysbus_mmio_get_region(sbdev, 0); 378 379 Aml *dev = aml_device("TPM0"); 380 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 381 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 382 383 Aml *crs = aml_resource_template(); 384 aml_append(crs, 385 aml_memory32_fixed(tpm_base, 386 (uint32_t)memory_region_size(sbdev_mr), 387 AML_READ_WRITE)); 388 aml_append(dev, aml_name_decl("_CRS", crs)); 389 aml_append(scope, dev); 390 } 391 392 static void 393 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 394 { 395 int nb_nodes, iort_start = table_data->len; 396 AcpiIortIdMapping *idmap; 397 AcpiIortItsGroup *its; 398 AcpiIortTable *iort; 399 AcpiIortSmmu3 *smmu; 400 size_t node_size, iort_node_offset, iort_length, smmu_offset = 0; 401 AcpiIortRC *rc; 402 403 iort = acpi_data_push(table_data, sizeof(*iort)); 404 405 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 406 nb_nodes = 3; /* RC, ITS, SMMUv3 */ 407 } else { 408 nb_nodes = 2; /* RC, ITS */ 409 } 410 411 iort_length = sizeof(*iort); 412 iort->node_count = cpu_to_le32(nb_nodes); 413 /* 414 * Use a copy in case table_data->data moves during acpi_data_push 415 * operations. 416 */ 417 iort_node_offset = sizeof(*iort); 418 iort->node_offset = cpu_to_le32(iort_node_offset); 419 420 /* ITS group node */ 421 node_size = sizeof(*its) + sizeof(uint32_t); 422 iort_length += node_size; 423 its = acpi_data_push(table_data, node_size); 424 425 its->type = ACPI_IORT_NODE_ITS_GROUP; 426 its->length = cpu_to_le16(node_size); 427 its->its_count = cpu_to_le32(1); 428 its->identifiers[0] = 0; /* MADT translation_id */ 429 430 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 431 int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; 432 433 /* SMMUv3 node */ 434 smmu_offset = iort_node_offset + node_size; 435 node_size = sizeof(*smmu) + sizeof(*idmap); 436 iort_length += node_size; 437 smmu = acpi_data_push(table_data, node_size); 438 439 smmu->type = ACPI_IORT_NODE_SMMU_V3; 440 smmu->length = cpu_to_le16(node_size); 441 smmu->mapping_count = cpu_to_le32(1); 442 smmu->mapping_offset = cpu_to_le32(sizeof(*smmu)); 443 smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base); 444 smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE); 445 smmu->event_gsiv = cpu_to_le32(irq); 446 smmu->pri_gsiv = cpu_to_le32(irq + 1); 447 smmu->gerr_gsiv = cpu_to_le32(irq + 2); 448 smmu->sync_gsiv = cpu_to_le32(irq + 3); 449 450 /* Identity RID mapping covering the whole input RID range */ 451 idmap = &smmu->id_mapping_array[0]; 452 idmap->input_base = 0; 453 idmap->id_count = cpu_to_le32(0xFFFF); 454 idmap->output_base = 0; 455 /* output IORT node is the ITS group node (the first node) */ 456 idmap->output_reference = cpu_to_le32(iort_node_offset); 457 } 458 459 /* Root Complex Node */ 460 node_size = sizeof(*rc) + sizeof(*idmap); 461 iort_length += node_size; 462 rc = acpi_data_push(table_data, node_size); 463 464 rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX; 465 rc->length = cpu_to_le16(node_size); 466 rc->mapping_count = cpu_to_le32(1); 467 rc->mapping_offset = cpu_to_le32(sizeof(*rc)); 468 469 /* fully coherent device */ 470 rc->memory_properties.cache_coherency = cpu_to_le32(1); 471 rc->memory_properties.memory_flags = 0x3; /* CCA = CPM = DCAS = 1 */ 472 rc->pci_segment_number = 0; /* MCFG pci_segment */ 473 474 /* Identity RID mapping covering the whole input RID range */ 475 idmap = &rc->id_mapping_array[0]; 476 idmap->input_base = 0; 477 idmap->id_count = cpu_to_le32(0xFFFF); 478 idmap->output_base = 0; 479 480 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 481 /* output IORT node is the smmuv3 node */ 482 idmap->output_reference = cpu_to_le32(smmu_offset); 483 } else { 484 /* output IORT node is the ITS group node (the first node) */ 485 idmap->output_reference = cpu_to_le32(iort_node_offset); 486 } 487 488 /* 489 * Update the pointer address in case table_data->data moves during above 490 * acpi_data_push operations. 491 */ 492 iort = (AcpiIortTable *)(table_data->data + iort_start); 493 iort->length = cpu_to_le32(iort_length); 494 495 build_header(linker, table_data, (void *)(table_data->data + iort_start), 496 "IORT", table_data->len - iort_start, 0, NULL, NULL); 497 } 498 499 static void 500 build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 501 { 502 AcpiSerialPortConsoleRedirection *spcr; 503 const MemMapEntry *uart_memmap = &vms->memmap[VIRT_UART]; 504 int irq = vms->irqmap[VIRT_UART] + ARM_SPI_BASE; 505 int spcr_start = table_data->len; 506 507 spcr = acpi_data_push(table_data, sizeof(*spcr)); 508 509 spcr->interface_type = 0x3; /* ARM PL011 UART */ 510 511 spcr->base_address.space_id = AML_SYSTEM_MEMORY; 512 spcr->base_address.bit_width = 8; 513 spcr->base_address.bit_offset = 0; 514 spcr->base_address.access_width = 1; 515 spcr->base_address.address = cpu_to_le64(uart_memmap->base); 516 517 spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */ 518 spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */ 519 520 spcr->baud = 3; /* Baud Rate: 3 = 9600 */ 521 spcr->parity = 0; /* No Parity */ 522 spcr->stopbits = 1; /* 1 Stop bit */ 523 spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */ 524 spcr->term_type = 0; /* Terminal Type: 0 = VT100 */ 525 526 spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */ 527 spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */ 528 529 build_header(linker, table_data, (void *)(table_data->data + spcr_start), 530 "SPCR", table_data->len - spcr_start, 2, NULL, NULL); 531 } 532 533 static void 534 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 535 { 536 AcpiSystemResourceAffinityTable *srat; 537 AcpiSratProcessorGiccAffinity *core; 538 AcpiSratMemoryAffinity *numamem; 539 int i, srat_start; 540 uint64_t mem_base; 541 MachineClass *mc = MACHINE_GET_CLASS(vms); 542 MachineState *ms = MACHINE(vms); 543 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); 544 545 srat_start = table_data->len; 546 srat = acpi_data_push(table_data, sizeof(*srat)); 547 srat->reserved1 = cpu_to_le32(1); 548 549 for (i = 0; i < cpu_list->len; ++i) { 550 core = acpi_data_push(table_data, sizeof(*core)); 551 core->type = ACPI_SRAT_PROCESSOR_GICC; 552 core->length = sizeof(*core); 553 core->proximity = cpu_to_le32(cpu_list->cpus[i].props.node_id); 554 core->acpi_processor_uid = cpu_to_le32(i); 555 core->flags = cpu_to_le32(1); 556 } 557 558 mem_base = vms->memmap[VIRT_MEM].base; 559 for (i = 0; i < ms->numa_state->num_nodes; ++i) { 560 if (ms->numa_state->nodes[i].node_mem > 0) { 561 numamem = acpi_data_push(table_data, sizeof(*numamem)); 562 build_srat_memory(numamem, mem_base, 563 ms->numa_state->nodes[i].node_mem, i, 564 MEM_AFFINITY_ENABLED); 565 mem_base += ms->numa_state->nodes[i].node_mem; 566 } 567 } 568 569 if (ms->nvdimms_state->is_enabled) { 570 nvdimm_build_srat(table_data); 571 } 572 573 if (ms->device_memory) { 574 numamem = acpi_data_push(table_data, sizeof *numamem); 575 build_srat_memory(numamem, ms->device_memory->base, 576 memory_region_size(&ms->device_memory->mr), 577 ms->numa_state->num_nodes - 1, 578 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 579 } 580 581 build_header(linker, table_data, (void *)(table_data->data + srat_start), 582 "SRAT", table_data->len - srat_start, 3, NULL, NULL); 583 } 584 585 /* GTDT */ 586 static void 587 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 588 { 589 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 590 int gtdt_start = table_data->len; 591 AcpiGenericTimerTable *gtdt; 592 uint32_t irqflags; 593 594 if (vmc->claim_edge_triggered_timers) { 595 irqflags = ACPI_GTDT_INTERRUPT_MODE_EDGE; 596 } else { 597 irqflags = ACPI_GTDT_INTERRUPT_MODE_LEVEL; 598 } 599 600 gtdt = acpi_data_push(table_data, sizeof *gtdt); 601 /* The interrupt values are the same with the device tree when adding 16 */ 602 gtdt->secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_S_EL1_IRQ + 16); 603 gtdt->secure_el1_flags = cpu_to_le32(irqflags); 604 605 gtdt->non_secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ + 16); 606 gtdt->non_secure_el1_flags = cpu_to_le32(irqflags | 607 ACPI_GTDT_CAP_ALWAYS_ON); 608 609 gtdt->virtual_timer_interrupt = cpu_to_le32(ARCH_TIMER_VIRT_IRQ + 16); 610 gtdt->virtual_timer_flags = cpu_to_le32(irqflags); 611 612 gtdt->non_secure_el2_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ + 16); 613 gtdt->non_secure_el2_flags = cpu_to_le32(irqflags); 614 615 build_header(linker, table_data, 616 (void *)(table_data->data + gtdt_start), "GTDT", 617 table_data->len - gtdt_start, 2, NULL, NULL); 618 } 619 620 /* MADT */ 621 static void 622 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 623 { 624 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 625 int madt_start = table_data->len; 626 const MemMapEntry *memmap = vms->memmap; 627 const int *irqmap = vms->irqmap; 628 AcpiMadtGenericDistributor *gicd; 629 AcpiMadtGenericMsiFrame *gic_msi; 630 int i; 631 632 acpi_data_push(table_data, sizeof(AcpiMultipleApicTable)); 633 634 gicd = acpi_data_push(table_data, sizeof *gicd); 635 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR; 636 gicd->length = sizeof(*gicd); 637 gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base); 638 gicd->version = vms->gic_version; 639 640 for (i = 0; i < vms->smp_cpus; i++) { 641 AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data, 642 sizeof(*gicc)); 643 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 644 645 gicc->type = ACPI_APIC_GENERIC_CPU_INTERFACE; 646 gicc->length = sizeof(*gicc); 647 if (vms->gic_version == 2) { 648 gicc->base_address = cpu_to_le64(memmap[VIRT_GIC_CPU].base); 649 gicc->gich_base_address = cpu_to_le64(memmap[VIRT_GIC_HYP].base); 650 gicc->gicv_base_address = cpu_to_le64(memmap[VIRT_GIC_VCPU].base); 651 } 652 gicc->cpu_interface_number = cpu_to_le32(i); 653 gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity); 654 gicc->uid = cpu_to_le32(i); 655 gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED); 656 657 if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 658 gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ)); 659 } 660 if (vms->virt) { 661 gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ)); 662 } 663 } 664 665 if (vms->gic_version == 3) { 666 AcpiMadtGenericTranslator *gic_its; 667 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 668 AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data, 669 sizeof *gicr); 670 671 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 672 gicr->length = sizeof(*gicr); 673 gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base); 674 gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size); 675 676 if (nb_redist_regions == 2) { 677 gicr = acpi_data_push(table_data, sizeof(*gicr)); 678 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 679 gicr->length = sizeof(*gicr); 680 gicr->base_address = 681 cpu_to_le64(memmap[VIRT_HIGH_GIC_REDIST2].base); 682 gicr->range_length = 683 cpu_to_le32(memmap[VIRT_HIGH_GIC_REDIST2].size); 684 } 685 686 if (its_class_name() && !vmc->no_its) { 687 gic_its = acpi_data_push(table_data, sizeof *gic_its); 688 gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR; 689 gic_its->length = sizeof(*gic_its); 690 gic_its->translation_id = 0; 691 gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base); 692 } 693 } else { 694 gic_msi = acpi_data_push(table_data, sizeof *gic_msi); 695 gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME; 696 gic_msi->length = sizeof(*gic_msi); 697 gic_msi->gic_msi_frame_id = 0; 698 gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base); 699 gic_msi->flags = cpu_to_le32(1); 700 gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS); 701 gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE); 702 } 703 704 build_header(linker, table_data, 705 (void *)(table_data->data + madt_start), "APIC", 706 table_data->len - madt_start, 3, NULL, NULL); 707 } 708 709 /* FADT */ 710 static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker, 711 VirtMachineState *vms, unsigned dsdt_tbl_offset) 712 { 713 /* ACPI v5.1 */ 714 AcpiFadtData fadt = { 715 .rev = 5, 716 .minor_ver = 1, 717 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, 718 .xdsdt_tbl_offset = &dsdt_tbl_offset, 719 }; 720 721 switch (vms->psci_conduit) { 722 case QEMU_PSCI_CONDUIT_DISABLED: 723 fadt.arm_boot_arch = 0; 724 break; 725 case QEMU_PSCI_CONDUIT_HVC: 726 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT | 727 ACPI_FADT_ARM_PSCI_USE_HVC; 728 break; 729 case QEMU_PSCI_CONDUIT_SMC: 730 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT; 731 break; 732 default: 733 g_assert_not_reached(); 734 } 735 736 build_fadt(table_data, linker, &fadt, NULL, NULL); 737 } 738 739 /* DSDT */ 740 static void 741 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 742 { 743 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 744 Aml *scope, *dsdt; 745 MachineState *ms = MACHINE(vms); 746 const MemMapEntry *memmap = vms->memmap; 747 const int *irqmap = vms->irqmap; 748 749 dsdt = init_aml_allocator(); 750 /* Reserve space for header */ 751 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 752 753 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. 754 * While UEFI can use libfdt to disable the RTC device node in the DTB that 755 * it passes to the OS, it cannot modify AML. Therefore, we won't generate 756 * the RTC ACPI device at all when using UEFI. 757 */ 758 scope = aml_scope("\\_SB"); 759 acpi_dsdt_add_cpus(scope, vms->smp_cpus); 760 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], 761 (irqmap[VIRT_UART] + ARM_SPI_BASE)); 762 if (vmc->acpi_expose_flash) { 763 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); 764 } 765 acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); 766 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], 767 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); 768 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), 769 vms->highmem, vms->highmem_ecam); 770 if (vms->acpi_dev) { 771 build_ged_aml(scope, "\\_SB."GED_DEVICE, 772 HOTPLUG_HANDLER(vms->acpi_dev), 773 irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY, 774 memmap[VIRT_ACPI_GED].base); 775 } else { 776 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], 777 (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); 778 } 779 780 if (vms->acpi_dev) { 781 uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev), 782 "ged-event", &error_abort); 783 784 if (event & ACPI_GED_MEM_HOTPLUG_EVT) { 785 build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL, 786 AML_SYSTEM_MEMORY, 787 memmap[VIRT_PCDIMM_ACPI].base); 788 } 789 } 790 791 acpi_dsdt_add_power_button(scope); 792 acpi_dsdt_add_tpm(scope, vms); 793 794 aml_append(dsdt, scope); 795 796 /* copy AML table into ACPI tables blob and patch header there */ 797 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 798 build_header(linker, table_data, 799 (void *)(table_data->data + table_data->len - dsdt->buf->len), 800 "DSDT", dsdt->buf->len, 2, NULL, NULL); 801 free_aml_allocator(); 802 } 803 804 typedef 805 struct AcpiBuildState { 806 /* Copy of table in RAM (for patching). */ 807 MemoryRegion *table_mr; 808 MemoryRegion *rsdp_mr; 809 MemoryRegion *linker_mr; 810 /* Is table patched? */ 811 bool patched; 812 } AcpiBuildState; 813 814 static 815 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) 816 { 817 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 818 GArray *table_offsets; 819 unsigned dsdt, xsdt; 820 GArray *tables_blob = tables->table_data; 821 MachineState *ms = MACHINE(vms); 822 823 table_offsets = g_array_new(false, true /* clear */, 824 sizeof(uint32_t)); 825 826 bios_linker_loader_alloc(tables->linker, 827 ACPI_BUILD_TABLE_FILE, tables_blob, 828 64, false /* high memory */); 829 830 /* DSDT is pointed to by FADT */ 831 dsdt = tables_blob->len; 832 build_dsdt(tables_blob, tables->linker, vms); 833 834 /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */ 835 acpi_add_table(table_offsets, tables_blob); 836 build_fadt_rev5(tables_blob, tables->linker, vms, dsdt); 837 838 acpi_add_table(table_offsets, tables_blob); 839 build_madt(tables_blob, tables->linker, vms); 840 841 acpi_add_table(table_offsets, tables_blob); 842 build_gtdt(tables_blob, tables->linker, vms); 843 844 acpi_add_table(table_offsets, tables_blob); 845 { 846 AcpiMcfgInfo mcfg = { 847 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, 848 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, 849 }; 850 build_mcfg(tables_blob, tables->linker, &mcfg); 851 } 852 853 acpi_add_table(table_offsets, tables_blob); 854 build_spcr(tables_blob, tables->linker, vms); 855 856 if (vms->ras) { 857 build_ghes_error_table(tables->hardware_errors, tables->linker); 858 acpi_add_table(table_offsets, tables_blob); 859 acpi_build_hest(tables_blob, tables->linker); 860 } 861 862 if (ms->numa_state->num_nodes > 0) { 863 acpi_add_table(table_offsets, tables_blob); 864 build_srat(tables_blob, tables->linker, vms); 865 if (ms->numa_state->have_numa_distance) { 866 acpi_add_table(table_offsets, tables_blob); 867 build_slit(tables_blob, tables->linker, ms); 868 } 869 } 870 871 if (ms->nvdimms_state->is_enabled) { 872 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 873 ms->nvdimms_state, ms->ram_slots); 874 } 875 876 if (its_class_name() && !vmc->no_its) { 877 acpi_add_table(table_offsets, tables_blob); 878 build_iort(tables_blob, tables->linker, vms); 879 } 880 881 if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) { 882 acpi_add_table(table_offsets, tables_blob); 883 build_tpm2(tables_blob, tables->linker, tables->tcpalog); 884 } 885 886 /* XSDT is pointed to by RSDP */ 887 xsdt = tables_blob->len; 888 build_xsdt(tables_blob, tables->linker, table_offsets, NULL, NULL); 889 890 /* RSDP is in FSEG memory, so allocate it separately */ 891 { 892 AcpiRsdpData rsdp_data = { 893 .revision = 2, 894 .oem_id = ACPI_BUILD_APPNAME6, 895 .xsdt_tbl_offset = &xsdt, 896 .rsdt_tbl_offset = NULL, 897 }; 898 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 899 } 900 901 /* Cleanup memory that's no longer used. */ 902 g_array_free(table_offsets, true); 903 } 904 905 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 906 { 907 uint32_t size = acpi_data_len(data); 908 909 /* Make sure RAM size is correct - in case it got changed 910 * e.g. by migration */ 911 memory_region_ram_resize(mr, size, &error_abort); 912 913 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 914 memory_region_set_dirty(mr, 0, size); 915 } 916 917 static void virt_acpi_build_update(void *build_opaque) 918 { 919 AcpiBuildState *build_state = build_opaque; 920 AcpiBuildTables tables; 921 922 /* No state to update or already patched? Nothing to do. */ 923 if (!build_state || build_state->patched) { 924 return; 925 } 926 build_state->patched = true; 927 928 acpi_build_tables_init(&tables); 929 930 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables); 931 932 acpi_ram_update(build_state->table_mr, tables.table_data); 933 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 934 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 935 936 acpi_build_tables_cleanup(&tables, true); 937 } 938 939 static void virt_acpi_build_reset(void *build_opaque) 940 { 941 AcpiBuildState *build_state = build_opaque; 942 build_state->patched = false; 943 } 944 945 static const VMStateDescription vmstate_virt_acpi_build = { 946 .name = "virt_acpi_build", 947 .version_id = 1, 948 .minimum_version_id = 1, 949 .fields = (VMStateField[]) { 950 VMSTATE_BOOL(patched, AcpiBuildState), 951 VMSTATE_END_OF_LIST() 952 }, 953 }; 954 955 void virt_acpi_setup(VirtMachineState *vms) 956 { 957 AcpiBuildTables tables; 958 AcpiBuildState *build_state; 959 AcpiGedState *acpi_ged_state; 960 961 if (!vms->fw_cfg) { 962 trace_virt_acpi_setup(); 963 return; 964 } 965 966 if (!virt_is_acpi_enabled(vms)) { 967 trace_virt_acpi_setup(); 968 return; 969 } 970 971 build_state = g_malloc0(sizeof *build_state); 972 973 acpi_build_tables_init(&tables); 974 virt_acpi_build(vms, &tables); 975 976 /* Now expose it all to Guest */ 977 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, 978 build_state, tables.table_data, 979 ACPI_BUILD_TABLE_FILE, 980 ACPI_BUILD_TABLE_MAX_SIZE); 981 assert(build_state->table_mr != NULL); 982 983 build_state->linker_mr = 984 acpi_add_rom_blob(virt_acpi_build_update, build_state, 985 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0); 986 987 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, 988 acpi_data_len(tables.tcpalog)); 989 990 if (vms->ras) { 991 assert(vms->acpi_dev); 992 acpi_ged_state = ACPI_GED(vms->acpi_dev); 993 acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state, 994 vms->fw_cfg, tables.hardware_errors); 995 } 996 997 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, 998 build_state, tables.rsdp, 999 ACPI_BUILD_RSDP_FILE, 0); 1000 1001 qemu_register_reset(virt_acpi_build_reset, build_state); 1002 virt_acpi_build_reset(build_state); 1003 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 1004 1005 /* Cleanup tables but don't free the memory: we track it 1006 * in build_state. 1007 */ 1008 acpi_build_tables_cleanup(&tables, false); 1009 } 1010