1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * ARM virt ACPI generation 4 * 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 6 * Copyright (C) 2006 Fabrice Bellard 7 * Copyright (C) 2013 Red Hat Inc 8 * 9 * Author: Michael S. Tsirkin <mst@redhat.com> 10 * 11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 12 * 13 * Author: Shannon Zhao <zhaoshenglong@huawei.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "qapi/error.h" 31 #include "qemu/bitmap.h" 32 #include "trace.h" 33 #include "hw/core/cpu.h" 34 #include "target/arm/cpu.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/acpi/aml-build.h" 40 #include "hw/acpi/utils.h" 41 #include "hw/acpi/pci.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "hw/acpi/generic_event_device.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/pci/pcie_host.h" 46 #include "hw/pci/pci.h" 47 #include "hw/pci-host/gpex.h" 48 #include "hw/arm/virt.h" 49 #include "hw/mem/nvdimm.h" 50 #include "hw/platform-bus.h" 51 #include "sysemu/numa.h" 52 #include "sysemu/reset.h" 53 #include "sysemu/tpm.h" 54 #include "kvm_arm.h" 55 #include "migration/vmstate.h" 56 #include "hw/acpi/ghes.h" 57 58 #define ARM_SPI_BASE 32 59 60 #define ACPI_BUILD_TABLE_SIZE 0x20000 61 62 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) 63 { 64 uint16_t i; 65 66 for (i = 0; i < smp_cpus; i++) { 67 Aml *dev = aml_device("C%.03X", i); 68 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 69 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 70 aml_append(scope, dev); 71 } 72 } 73 74 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 75 uint32_t uart_irq) 76 { 77 Aml *dev = aml_device("COM0"); 78 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); 79 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 80 81 Aml *crs = aml_resource_template(); 82 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 83 uart_memmap->size, AML_READ_WRITE)); 84 aml_append(crs, 85 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 86 AML_EXCLUSIVE, &uart_irq, 1)); 87 aml_append(dev, aml_name_decl("_CRS", crs)); 88 89 aml_append(scope, dev); 90 } 91 92 static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) 93 { 94 Aml *dev = aml_device("FWCF"); 95 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 96 /* device present, functioning, decoding, not shown in UI */ 97 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 98 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 99 100 Aml *crs = aml_resource_template(); 101 aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, 102 fw_cfg_memmap->size, AML_READ_WRITE)); 103 aml_append(dev, aml_name_decl("_CRS", crs)); 104 aml_append(scope, dev); 105 } 106 107 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) 108 { 109 Aml *dev, *crs; 110 hwaddr base = flash_memmap->base; 111 hwaddr size = flash_memmap->size / 2; 112 113 dev = aml_device("FLS0"); 114 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 115 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 116 117 crs = aml_resource_template(); 118 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 119 aml_append(dev, aml_name_decl("_CRS", crs)); 120 aml_append(scope, dev); 121 122 dev = aml_device("FLS1"); 123 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 124 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 125 crs = aml_resource_template(); 126 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); 127 aml_append(dev, aml_name_decl("_CRS", crs)); 128 aml_append(scope, dev); 129 } 130 131 static void acpi_dsdt_add_virtio(Aml *scope, 132 const MemMapEntry *virtio_mmio_memmap, 133 uint32_t mmio_irq, int num) 134 { 135 hwaddr base = virtio_mmio_memmap->base; 136 hwaddr size = virtio_mmio_memmap->size; 137 int i; 138 139 for (i = 0; i < num; i++) { 140 uint32_t irq = mmio_irq + i; 141 Aml *dev = aml_device("VR%02u", i); 142 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); 143 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 144 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 145 146 Aml *crs = aml_resource_template(); 147 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 148 aml_append(crs, 149 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 150 AML_EXCLUSIVE, &irq, 1)); 151 aml_append(dev, aml_name_decl("_CRS", crs)); 152 aml_append(scope, dev); 153 base += size; 154 } 155 } 156 157 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, 158 uint32_t irq, bool use_highmem, bool highmem_ecam, 159 VirtMachineState *vms) 160 { 161 int ecam_id = VIRT_ECAM_ID(highmem_ecam); 162 struct GPEXConfig cfg = { 163 .mmio32 = memmap[VIRT_PCIE_MMIO], 164 .pio = memmap[VIRT_PCIE_PIO], 165 .ecam = memmap[ecam_id], 166 .irq = irq, 167 .bus = vms->bus, 168 }; 169 170 if (use_highmem) { 171 cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO]; 172 } 173 174 acpi_dsdt_add_gpex(scope, &cfg); 175 } 176 177 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, 178 uint32_t gpio_irq) 179 { 180 Aml *dev = aml_device("GPO0"); 181 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); 182 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 183 184 Aml *crs = aml_resource_template(); 185 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, 186 AML_READ_WRITE)); 187 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 188 AML_EXCLUSIVE, &gpio_irq, 1)); 189 aml_append(dev, aml_name_decl("_CRS", crs)); 190 191 Aml *aei = aml_resource_template(); 192 /* Pin 3 for power button */ 193 const uint32_t pin_list[1] = {3}; 194 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, 195 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, 196 "GPO0", NULL, 0)); 197 aml_append(dev, aml_name_decl("_AEI", aei)); 198 199 /* _E03 is handle for power button */ 200 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); 201 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), 202 aml_int(0x80))); 203 aml_append(dev, method); 204 aml_append(scope, dev); 205 } 206 207 static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms) 208 { 209 PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); 210 hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base; 211 SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find()); 212 MemoryRegion *sbdev_mr; 213 hwaddr tpm_base; 214 215 if (!sbdev) { 216 return; 217 } 218 219 tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); 220 assert(tpm_base != -1); 221 222 tpm_base += pbus_base; 223 224 sbdev_mr = sysbus_mmio_get_region(sbdev, 0); 225 226 Aml *dev = aml_device("TPM0"); 227 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 228 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 229 230 Aml *crs = aml_resource_template(); 231 aml_append(crs, 232 aml_memory32_fixed(tpm_base, 233 (uint32_t)memory_region_size(sbdev_mr), 234 AML_READ_WRITE)); 235 aml_append(dev, aml_name_decl("_CRS", crs)); 236 aml_append(scope, dev); 237 } 238 239 static void 240 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 241 { 242 int nb_nodes, iort_start = table_data->len; 243 AcpiIortIdMapping *idmap; 244 AcpiIortItsGroup *its; 245 AcpiIortTable *iort; 246 AcpiIortSmmu3 *smmu; 247 size_t node_size, iort_node_offset, iort_length, smmu_offset = 0; 248 AcpiIortRC *rc; 249 250 iort = acpi_data_push(table_data, sizeof(*iort)); 251 252 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 253 nb_nodes = 3; /* RC, ITS, SMMUv3 */ 254 } else { 255 nb_nodes = 2; /* RC, ITS */ 256 } 257 258 iort_length = sizeof(*iort); 259 iort->node_count = cpu_to_le32(nb_nodes); 260 /* 261 * Use a copy in case table_data->data moves during acpi_data_push 262 * operations. 263 */ 264 iort_node_offset = sizeof(*iort); 265 iort->node_offset = cpu_to_le32(iort_node_offset); 266 267 /* ITS group node */ 268 node_size = sizeof(*its) + sizeof(uint32_t); 269 iort_length += node_size; 270 its = acpi_data_push(table_data, node_size); 271 272 its->type = ACPI_IORT_NODE_ITS_GROUP; 273 its->length = cpu_to_le16(node_size); 274 its->its_count = cpu_to_le32(1); 275 its->identifiers[0] = 0; /* MADT translation_id */ 276 277 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 278 int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; 279 280 /* SMMUv3 node */ 281 smmu_offset = iort_node_offset + node_size; 282 node_size = sizeof(*smmu) + sizeof(*idmap); 283 iort_length += node_size; 284 smmu = acpi_data_push(table_data, node_size); 285 286 smmu->type = ACPI_IORT_NODE_SMMU_V3; 287 smmu->length = cpu_to_le16(node_size); 288 smmu->mapping_count = cpu_to_le32(1); 289 smmu->mapping_offset = cpu_to_le32(sizeof(*smmu)); 290 smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base); 291 smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE); 292 smmu->event_gsiv = cpu_to_le32(irq); 293 smmu->pri_gsiv = cpu_to_le32(irq + 1); 294 smmu->gerr_gsiv = cpu_to_le32(irq + 2); 295 smmu->sync_gsiv = cpu_to_le32(irq + 3); 296 297 /* Identity RID mapping covering the whole input RID range */ 298 idmap = &smmu->id_mapping_array[0]; 299 idmap->input_base = 0; 300 idmap->id_count = cpu_to_le32(0xFFFF); 301 idmap->output_base = 0; 302 /* output IORT node is the ITS group node (the first node) */ 303 idmap->output_reference = cpu_to_le32(iort_node_offset); 304 } 305 306 /* Root Complex Node */ 307 node_size = sizeof(*rc) + sizeof(*idmap); 308 iort_length += node_size; 309 rc = acpi_data_push(table_data, node_size); 310 311 rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX; 312 rc->length = cpu_to_le16(node_size); 313 rc->mapping_count = cpu_to_le32(1); 314 rc->mapping_offset = cpu_to_le32(sizeof(*rc)); 315 316 /* fully coherent device */ 317 rc->memory_properties.cache_coherency = cpu_to_le32(1); 318 rc->memory_properties.memory_flags = 0x3; /* CCA = CPM = DCAS = 1 */ 319 rc->pci_segment_number = 0; /* MCFG pci_segment */ 320 321 /* Identity RID mapping covering the whole input RID range */ 322 idmap = &rc->id_mapping_array[0]; 323 idmap->input_base = 0; 324 idmap->id_count = cpu_to_le32(0xFFFF); 325 idmap->output_base = 0; 326 327 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 328 /* output IORT node is the smmuv3 node */ 329 idmap->output_reference = cpu_to_le32(smmu_offset); 330 } else { 331 /* output IORT node is the ITS group node (the first node) */ 332 idmap->output_reference = cpu_to_le32(iort_node_offset); 333 } 334 335 /* 336 * Update the pointer address in case table_data->data moves during above 337 * acpi_data_push operations. 338 */ 339 iort = (AcpiIortTable *)(table_data->data + iort_start); 340 iort->length = cpu_to_le32(iort_length); 341 342 build_header(linker, table_data, (void *)(table_data->data + iort_start), 343 "IORT", table_data->len - iort_start, 0, NULL, NULL); 344 } 345 346 static void 347 build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 348 { 349 AcpiSerialPortConsoleRedirection *spcr; 350 const MemMapEntry *uart_memmap = &vms->memmap[VIRT_UART]; 351 int irq = vms->irqmap[VIRT_UART] + ARM_SPI_BASE; 352 int spcr_start = table_data->len; 353 354 spcr = acpi_data_push(table_data, sizeof(*spcr)); 355 356 spcr->interface_type = 0x3; /* ARM PL011 UART */ 357 358 spcr->base_address.space_id = AML_SYSTEM_MEMORY; 359 spcr->base_address.bit_width = 8; 360 spcr->base_address.bit_offset = 0; 361 spcr->base_address.access_width = 1; 362 spcr->base_address.address = cpu_to_le64(uart_memmap->base); 363 364 spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */ 365 spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */ 366 367 spcr->baud = 3; /* Baud Rate: 3 = 9600 */ 368 spcr->parity = 0; /* No Parity */ 369 spcr->stopbits = 1; /* 1 Stop bit */ 370 spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */ 371 spcr->term_type = 0; /* Terminal Type: 0 = VT100 */ 372 373 spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */ 374 spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */ 375 376 build_header(linker, table_data, (void *)(table_data->data + spcr_start), 377 "SPCR", table_data->len - spcr_start, 2, NULL, NULL); 378 } 379 380 static void 381 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 382 { 383 AcpiSystemResourceAffinityTable *srat; 384 AcpiSratProcessorGiccAffinity *core; 385 AcpiSratMemoryAffinity *numamem; 386 int i, srat_start; 387 uint64_t mem_base; 388 MachineClass *mc = MACHINE_GET_CLASS(vms); 389 MachineState *ms = MACHINE(vms); 390 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); 391 392 srat_start = table_data->len; 393 srat = acpi_data_push(table_data, sizeof(*srat)); 394 srat->reserved1 = cpu_to_le32(1); 395 396 for (i = 0; i < cpu_list->len; ++i) { 397 core = acpi_data_push(table_data, sizeof(*core)); 398 core->type = ACPI_SRAT_PROCESSOR_GICC; 399 core->length = sizeof(*core); 400 core->proximity = cpu_to_le32(cpu_list->cpus[i].props.node_id); 401 core->acpi_processor_uid = cpu_to_le32(i); 402 core->flags = cpu_to_le32(1); 403 } 404 405 mem_base = vms->memmap[VIRT_MEM].base; 406 for (i = 0; i < ms->numa_state->num_nodes; ++i) { 407 if (ms->numa_state->nodes[i].node_mem > 0) { 408 numamem = acpi_data_push(table_data, sizeof(*numamem)); 409 build_srat_memory(numamem, mem_base, 410 ms->numa_state->nodes[i].node_mem, i, 411 MEM_AFFINITY_ENABLED); 412 mem_base += ms->numa_state->nodes[i].node_mem; 413 } 414 } 415 416 if (ms->nvdimms_state->is_enabled) { 417 nvdimm_build_srat(table_data); 418 } 419 420 if (ms->device_memory) { 421 numamem = acpi_data_push(table_data, sizeof *numamem); 422 build_srat_memory(numamem, ms->device_memory->base, 423 memory_region_size(&ms->device_memory->mr), 424 ms->numa_state->num_nodes - 1, 425 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 426 } 427 428 build_header(linker, table_data, (void *)(table_data->data + srat_start), 429 "SRAT", table_data->len - srat_start, 3, NULL, NULL); 430 } 431 432 /* GTDT */ 433 static void 434 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 435 { 436 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 437 int gtdt_start = table_data->len; 438 AcpiGenericTimerTable *gtdt; 439 uint32_t irqflags; 440 441 if (vmc->claim_edge_triggered_timers) { 442 irqflags = ACPI_GTDT_INTERRUPT_MODE_EDGE; 443 } else { 444 irqflags = ACPI_GTDT_INTERRUPT_MODE_LEVEL; 445 } 446 447 gtdt = acpi_data_push(table_data, sizeof *gtdt); 448 /* The interrupt values are the same with the device tree when adding 16 */ 449 gtdt->secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_S_EL1_IRQ + 16); 450 gtdt->secure_el1_flags = cpu_to_le32(irqflags); 451 452 gtdt->non_secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ + 16); 453 gtdt->non_secure_el1_flags = cpu_to_le32(irqflags | 454 ACPI_GTDT_CAP_ALWAYS_ON); 455 456 gtdt->virtual_timer_interrupt = cpu_to_le32(ARCH_TIMER_VIRT_IRQ + 16); 457 gtdt->virtual_timer_flags = cpu_to_le32(irqflags); 458 459 gtdt->non_secure_el2_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ + 16); 460 gtdt->non_secure_el2_flags = cpu_to_le32(irqflags); 461 462 build_header(linker, table_data, 463 (void *)(table_data->data + gtdt_start), "GTDT", 464 table_data->len - gtdt_start, 2, NULL, NULL); 465 } 466 467 /* MADT */ 468 static void 469 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 470 { 471 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 472 int madt_start = table_data->len; 473 const MemMapEntry *memmap = vms->memmap; 474 const int *irqmap = vms->irqmap; 475 AcpiMadtGenericDistributor *gicd; 476 AcpiMadtGenericMsiFrame *gic_msi; 477 int i; 478 479 acpi_data_push(table_data, sizeof(AcpiMultipleApicTable)); 480 481 gicd = acpi_data_push(table_data, sizeof *gicd); 482 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR; 483 gicd->length = sizeof(*gicd); 484 gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base); 485 gicd->version = vms->gic_version; 486 487 for (i = 0; i < vms->smp_cpus; i++) { 488 AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data, 489 sizeof(*gicc)); 490 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 491 492 gicc->type = ACPI_APIC_GENERIC_CPU_INTERFACE; 493 gicc->length = sizeof(*gicc); 494 if (vms->gic_version == 2) { 495 gicc->base_address = cpu_to_le64(memmap[VIRT_GIC_CPU].base); 496 gicc->gich_base_address = cpu_to_le64(memmap[VIRT_GIC_HYP].base); 497 gicc->gicv_base_address = cpu_to_le64(memmap[VIRT_GIC_VCPU].base); 498 } 499 gicc->cpu_interface_number = cpu_to_le32(i); 500 gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity); 501 gicc->uid = cpu_to_le32(i); 502 gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED); 503 504 if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 505 gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ)); 506 } 507 if (vms->virt) { 508 gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ)); 509 } 510 } 511 512 if (vms->gic_version == 3) { 513 AcpiMadtGenericTranslator *gic_its; 514 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 515 AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data, 516 sizeof *gicr); 517 518 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 519 gicr->length = sizeof(*gicr); 520 gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base); 521 gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size); 522 523 if (nb_redist_regions == 2) { 524 gicr = acpi_data_push(table_data, sizeof(*gicr)); 525 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 526 gicr->length = sizeof(*gicr); 527 gicr->base_address = 528 cpu_to_le64(memmap[VIRT_HIGH_GIC_REDIST2].base); 529 gicr->range_length = 530 cpu_to_le32(memmap[VIRT_HIGH_GIC_REDIST2].size); 531 } 532 533 if (its_class_name() && !vmc->no_its) { 534 gic_its = acpi_data_push(table_data, sizeof *gic_its); 535 gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR; 536 gic_its->length = sizeof(*gic_its); 537 gic_its->translation_id = 0; 538 gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base); 539 } 540 } else { 541 gic_msi = acpi_data_push(table_data, sizeof *gic_msi); 542 gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME; 543 gic_msi->length = sizeof(*gic_msi); 544 gic_msi->gic_msi_frame_id = 0; 545 gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base); 546 gic_msi->flags = cpu_to_le32(1); 547 gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS); 548 gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE); 549 } 550 551 build_header(linker, table_data, 552 (void *)(table_data->data + madt_start), "APIC", 553 table_data->len - madt_start, 3, NULL, NULL); 554 } 555 556 /* FADT */ 557 static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker, 558 VirtMachineState *vms, unsigned dsdt_tbl_offset) 559 { 560 /* ACPI v5.1 */ 561 AcpiFadtData fadt = { 562 .rev = 5, 563 .minor_ver = 1, 564 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, 565 .xdsdt_tbl_offset = &dsdt_tbl_offset, 566 }; 567 568 switch (vms->psci_conduit) { 569 case QEMU_PSCI_CONDUIT_DISABLED: 570 fadt.arm_boot_arch = 0; 571 break; 572 case QEMU_PSCI_CONDUIT_HVC: 573 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT | 574 ACPI_FADT_ARM_PSCI_USE_HVC; 575 break; 576 case QEMU_PSCI_CONDUIT_SMC: 577 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT; 578 break; 579 default: 580 g_assert_not_reached(); 581 } 582 583 build_fadt(table_data, linker, &fadt, NULL, NULL); 584 } 585 586 /* DSDT */ 587 static void 588 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 589 { 590 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 591 Aml *scope, *dsdt; 592 MachineState *ms = MACHINE(vms); 593 const MemMapEntry *memmap = vms->memmap; 594 const int *irqmap = vms->irqmap; 595 596 dsdt = init_aml_allocator(); 597 /* Reserve space for header */ 598 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 599 600 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. 601 * While UEFI can use libfdt to disable the RTC device node in the DTB that 602 * it passes to the OS, it cannot modify AML. Therefore, we won't generate 603 * the RTC ACPI device at all when using UEFI. 604 */ 605 scope = aml_scope("\\_SB"); 606 acpi_dsdt_add_cpus(scope, vms->smp_cpus); 607 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], 608 (irqmap[VIRT_UART] + ARM_SPI_BASE)); 609 if (vmc->acpi_expose_flash) { 610 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); 611 } 612 acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); 613 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], 614 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); 615 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), 616 vms->highmem, vms->highmem_ecam, vms); 617 if (vms->acpi_dev) { 618 build_ged_aml(scope, "\\_SB."GED_DEVICE, 619 HOTPLUG_HANDLER(vms->acpi_dev), 620 irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY, 621 memmap[VIRT_ACPI_GED].base); 622 } else { 623 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], 624 (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); 625 } 626 627 if (vms->acpi_dev) { 628 uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev), 629 "ged-event", &error_abort); 630 631 if (event & ACPI_GED_MEM_HOTPLUG_EVT) { 632 build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL, 633 AML_SYSTEM_MEMORY, 634 memmap[VIRT_PCDIMM_ACPI].base); 635 } 636 } 637 638 acpi_dsdt_add_power_button(scope); 639 acpi_dsdt_add_tpm(scope, vms); 640 641 aml_append(dsdt, scope); 642 643 /* copy AML table into ACPI tables blob and patch header there */ 644 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 645 build_header(linker, table_data, 646 (void *)(table_data->data + table_data->len - dsdt->buf->len), 647 "DSDT", dsdt->buf->len, 2, NULL, NULL); 648 free_aml_allocator(); 649 } 650 651 typedef 652 struct AcpiBuildState { 653 /* Copy of table in RAM (for patching). */ 654 MemoryRegion *table_mr; 655 MemoryRegion *rsdp_mr; 656 MemoryRegion *linker_mr; 657 /* Is table patched? */ 658 bool patched; 659 } AcpiBuildState; 660 661 static void acpi_align_size(GArray *blob, unsigned align) 662 { 663 /* 664 * Align size to multiple of given size. This reduces the chance 665 * we need to change size in the future (breaking cross version migration). 666 */ 667 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 668 } 669 670 static 671 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) 672 { 673 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 674 GArray *table_offsets; 675 unsigned dsdt, xsdt; 676 GArray *tables_blob = tables->table_data; 677 MachineState *ms = MACHINE(vms); 678 679 table_offsets = g_array_new(false, true /* clear */, 680 sizeof(uint32_t)); 681 682 bios_linker_loader_alloc(tables->linker, 683 ACPI_BUILD_TABLE_FILE, tables_blob, 684 64, false /* high memory */); 685 686 /* DSDT is pointed to by FADT */ 687 dsdt = tables_blob->len; 688 build_dsdt(tables_blob, tables->linker, vms); 689 690 /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */ 691 acpi_add_table(table_offsets, tables_blob); 692 build_fadt_rev5(tables_blob, tables->linker, vms, dsdt); 693 694 acpi_add_table(table_offsets, tables_blob); 695 build_madt(tables_blob, tables->linker, vms); 696 697 acpi_add_table(table_offsets, tables_blob); 698 build_gtdt(tables_blob, tables->linker, vms); 699 700 acpi_add_table(table_offsets, tables_blob); 701 { 702 AcpiMcfgInfo mcfg = { 703 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, 704 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, 705 }; 706 build_mcfg(tables_blob, tables->linker, &mcfg); 707 } 708 709 acpi_add_table(table_offsets, tables_blob); 710 build_spcr(tables_blob, tables->linker, vms); 711 712 if (vms->ras) { 713 build_ghes_error_table(tables->hardware_errors, tables->linker); 714 acpi_add_table(table_offsets, tables_blob); 715 acpi_build_hest(tables_blob, tables->linker); 716 } 717 718 if (ms->numa_state->num_nodes > 0) { 719 acpi_add_table(table_offsets, tables_blob); 720 build_srat(tables_blob, tables->linker, vms); 721 if (ms->numa_state->have_numa_distance) { 722 acpi_add_table(table_offsets, tables_blob); 723 build_slit(tables_blob, tables->linker, ms); 724 } 725 } 726 727 if (ms->nvdimms_state->is_enabled) { 728 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 729 ms->nvdimms_state, ms->ram_slots); 730 } 731 732 if (its_class_name() && !vmc->no_its) { 733 acpi_add_table(table_offsets, tables_blob); 734 build_iort(tables_blob, tables->linker, vms); 735 } 736 737 if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) { 738 acpi_add_table(table_offsets, tables_blob); 739 build_tpm2(tables_blob, tables->linker, tables->tcpalog); 740 } 741 742 /* XSDT is pointed to by RSDP */ 743 xsdt = tables_blob->len; 744 build_xsdt(tables_blob, tables->linker, table_offsets, NULL, NULL); 745 746 /* RSDP is in FSEG memory, so allocate it separately */ 747 { 748 AcpiRsdpData rsdp_data = { 749 .revision = 2, 750 .oem_id = ACPI_BUILD_APPNAME6, 751 .xsdt_tbl_offset = &xsdt, 752 .rsdt_tbl_offset = NULL, 753 }; 754 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 755 } 756 757 /* 758 * The align size is 128, warn if 64k is not enough therefore 759 * the align size could be resized. 760 */ 761 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 762 warn_report("ACPI table size %u exceeds %d bytes," 763 " migration may not work", 764 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 765 error_printf("Try removing CPUs, NUMA nodes, memory slots" 766 " or PCI bridges."); 767 } 768 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 769 770 771 /* Cleanup memory that's no longer used. */ 772 g_array_free(table_offsets, true); 773 } 774 775 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 776 { 777 uint32_t size = acpi_data_len(data); 778 779 /* Make sure RAM size is correct - in case it got changed 780 * e.g. by migration */ 781 memory_region_ram_resize(mr, size, &error_abort); 782 783 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 784 memory_region_set_dirty(mr, 0, size); 785 } 786 787 static void virt_acpi_build_update(void *build_opaque) 788 { 789 AcpiBuildState *build_state = build_opaque; 790 AcpiBuildTables tables; 791 792 /* No state to update or already patched? Nothing to do. */ 793 if (!build_state || build_state->patched) { 794 return; 795 } 796 build_state->patched = true; 797 798 acpi_build_tables_init(&tables); 799 800 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables); 801 802 acpi_ram_update(build_state->table_mr, tables.table_data); 803 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 804 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 805 806 acpi_build_tables_cleanup(&tables, true); 807 } 808 809 static void virt_acpi_build_reset(void *build_opaque) 810 { 811 AcpiBuildState *build_state = build_opaque; 812 build_state->patched = false; 813 } 814 815 static const VMStateDescription vmstate_virt_acpi_build = { 816 .name = "virt_acpi_build", 817 .version_id = 1, 818 .minimum_version_id = 1, 819 .fields = (VMStateField[]) { 820 VMSTATE_BOOL(patched, AcpiBuildState), 821 VMSTATE_END_OF_LIST() 822 }, 823 }; 824 825 void virt_acpi_setup(VirtMachineState *vms) 826 { 827 AcpiBuildTables tables; 828 AcpiBuildState *build_state; 829 AcpiGedState *acpi_ged_state; 830 831 if (!vms->fw_cfg) { 832 trace_virt_acpi_setup(); 833 return; 834 } 835 836 if (!virt_is_acpi_enabled(vms)) { 837 trace_virt_acpi_setup(); 838 return; 839 } 840 841 build_state = g_malloc0(sizeof *build_state); 842 843 acpi_build_tables_init(&tables); 844 virt_acpi_build(vms, &tables); 845 846 /* Now expose it all to Guest */ 847 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, 848 build_state, tables.table_data, 849 ACPI_BUILD_TABLE_FILE, 850 ACPI_BUILD_TABLE_MAX_SIZE); 851 assert(build_state->table_mr != NULL); 852 853 build_state->linker_mr = 854 acpi_add_rom_blob(virt_acpi_build_update, build_state, 855 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0); 856 857 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, 858 acpi_data_len(tables.tcpalog)); 859 860 if (vms->ras) { 861 assert(vms->acpi_dev); 862 acpi_ged_state = ACPI_GED(vms->acpi_dev); 863 acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state, 864 vms->fw_cfg, tables.hardware_errors); 865 } 866 867 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, 868 build_state, tables.rsdp, 869 ACPI_BUILD_RSDP_FILE, 0); 870 871 qemu_register_reset(virt_acpi_build_reset, build_state); 872 virt_acpi_build_reset(build_state); 873 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 874 875 /* Cleanup tables but don't free the memory: we track it 876 * in build_state. 877 */ 878 acpi_build_tables_cleanup(&tables, false); 879 } 880