1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * ARM virt ACPI generation 4 * 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 6 * Copyright (C) 2006 Fabrice Bellard 7 * Copyright (C) 2013 Red Hat Inc 8 * 9 * Author: Michael S. Tsirkin <mst@redhat.com> 10 * 11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 12 * 13 * Author: Shannon Zhao <zhaoshenglong@huawei.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu-common.h" 30 #include "hw/arm/virt-acpi-build.h" 31 #include "qemu/bitmap.h" 32 #include "trace.h" 33 #include "qom/cpu.h" 34 #include "target-arm/cpu.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/loader.h" 40 #include "hw/hw.h" 41 #include "hw/acpi/aml-build.h" 42 #include "hw/pci/pcie_host.h" 43 #include "hw/pci/pci.h" 44 45 #define ARM_SPI_BASE 32 46 47 typedef struct VirtAcpiCpuInfo { 48 DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT); 49 } VirtAcpiCpuInfo; 50 51 static void virt_acpi_get_cpu_info(VirtAcpiCpuInfo *cpuinfo) 52 { 53 CPUState *cpu; 54 55 memset(cpuinfo->found_cpus, 0, sizeof cpuinfo->found_cpus); 56 CPU_FOREACH(cpu) { 57 set_bit(cpu->cpu_index, cpuinfo->found_cpus); 58 } 59 } 60 61 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) 62 { 63 uint16_t i; 64 65 for (i = 0; i < smp_cpus; i++) { 66 Aml *dev = aml_device("C%03x", i); 67 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 68 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 69 aml_append(scope, dev); 70 } 71 } 72 73 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 74 int uart_irq) 75 { 76 Aml *dev = aml_device("COM0"); 77 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); 78 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 79 80 Aml *crs = aml_resource_template(); 81 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 82 uart_memmap->size, AML_READ_WRITE)); 83 aml_append(crs, 84 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 85 AML_EXCLUSIVE, uart_irq)); 86 aml_append(dev, aml_name_decl("_CRS", crs)); 87 88 /* The _ADR entry is used to link this device to the UART described 89 * in the SPCR table, i.e. SPCR.base_address.address == _ADR. 90 */ 91 aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base))); 92 93 aml_append(scope, dev); 94 } 95 96 static void acpi_dsdt_add_rtc(Aml *scope, const MemMapEntry *rtc_memmap, 97 int rtc_irq) 98 { 99 Aml *dev = aml_device("RTC0"); 100 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0013"))); 101 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 102 103 Aml *crs = aml_resource_template(); 104 aml_append(crs, aml_memory32_fixed(rtc_memmap->base, 105 rtc_memmap->size, AML_READ_WRITE)); 106 aml_append(crs, 107 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 108 AML_EXCLUSIVE, rtc_irq)); 109 aml_append(dev, aml_name_decl("_CRS", crs)); 110 aml_append(scope, dev); 111 } 112 113 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) 114 { 115 Aml *dev, *crs; 116 hwaddr base = flash_memmap->base; 117 hwaddr size = flash_memmap->size; 118 119 dev = aml_device("FLS0"); 120 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 121 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 122 123 crs = aml_resource_template(); 124 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 125 aml_append(dev, aml_name_decl("_CRS", crs)); 126 aml_append(scope, dev); 127 128 dev = aml_device("FLS1"); 129 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 130 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 131 crs = aml_resource_template(); 132 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); 133 aml_append(dev, aml_name_decl("_CRS", crs)); 134 aml_append(scope, dev); 135 } 136 137 static void acpi_dsdt_add_virtio(Aml *scope, 138 const MemMapEntry *virtio_mmio_memmap, 139 int mmio_irq, int num) 140 { 141 hwaddr base = virtio_mmio_memmap->base; 142 hwaddr size = virtio_mmio_memmap->size; 143 int irq = mmio_irq; 144 int i; 145 146 for (i = 0; i < num; i++) { 147 Aml *dev = aml_device("VR%02u", i); 148 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); 149 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 150 151 Aml *crs = aml_resource_template(); 152 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 153 aml_append(crs, 154 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 155 AML_EXCLUSIVE, irq + i)); 156 aml_append(dev, aml_name_decl("_CRS", crs)); 157 aml_append(scope, dev); 158 base += size; 159 } 160 } 161 162 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, int irq, 163 bool use_highmem) 164 { 165 Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; 166 int i, bus_no; 167 hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base; 168 hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size; 169 hwaddr base_pio = memmap[VIRT_PCIE_PIO].base; 170 hwaddr size_pio = memmap[VIRT_PCIE_PIO].size; 171 hwaddr base_ecam = memmap[VIRT_PCIE_ECAM].base; 172 hwaddr size_ecam = memmap[VIRT_PCIE_ECAM].size; 173 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 174 175 Aml *dev = aml_device("%s", "PCI0"); 176 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); 177 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); 178 aml_append(dev, aml_name_decl("_SEG", aml_int(0))); 179 aml_append(dev, aml_name_decl("_BBN", aml_int(0))); 180 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 181 aml_append(dev, aml_name_decl("_UID", aml_string("PCI0"))); 182 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); 183 184 /* Declare the PCI Routing Table. */ 185 Aml *rt_pkg = aml_package(nr_pcie_buses * PCI_NUM_PINS); 186 for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) { 187 for (i = 0; i < PCI_NUM_PINS; i++) { 188 int gsi = (i + bus_no) % PCI_NUM_PINS; 189 Aml *pkg = aml_package(4); 190 aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF)); 191 aml_append(pkg, aml_int(i)); 192 aml_append(pkg, aml_name("GSI%d", gsi)); 193 aml_append(pkg, aml_int(0)); 194 aml_append(rt_pkg, pkg); 195 } 196 } 197 aml_append(dev, aml_name_decl("_PRT", rt_pkg)); 198 199 /* Create GSI link device */ 200 for (i = 0; i < PCI_NUM_PINS; i++) { 201 Aml *dev_gsi = aml_device("GSI%d", i); 202 aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); 203 aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0))); 204 crs = aml_resource_template(); 205 aml_append(crs, 206 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 207 AML_EXCLUSIVE, irq + i)); 208 aml_append(dev_gsi, aml_name_decl("_PRS", crs)); 209 crs = aml_resource_template(); 210 aml_append(crs, 211 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 212 AML_EXCLUSIVE, irq + i)); 213 aml_append(dev_gsi, aml_name_decl("_CRS", crs)); 214 method = aml_method("_SRS", 1); 215 aml_append(dev_gsi, method); 216 aml_append(dev, dev_gsi); 217 } 218 219 method = aml_method("_CBA", 0); 220 aml_append(method, aml_return(aml_int(base_ecam))); 221 aml_append(dev, method); 222 223 method = aml_method("_CRS", 0); 224 Aml *rbuf = aml_resource_template(); 225 aml_append(rbuf, 226 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 227 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, 228 nr_pcie_buses)); 229 aml_append(rbuf, 230 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 231 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio, 232 base_mmio + size_mmio - 1, 0x0000, size_mmio)); 233 aml_append(rbuf, 234 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 235 AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio, 236 size_pio)); 237 238 if (use_highmem) { 239 hwaddr base_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].base; 240 hwaddr size_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].size; 241 242 aml_append(rbuf, 243 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 244 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, 245 base_mmio_high, base_mmio_high, 0x0000, 246 size_mmio_high)); 247 } 248 249 aml_append(method, aml_name_decl("RBUF", rbuf)); 250 aml_append(method, aml_return(rbuf)); 251 aml_append(dev, method); 252 253 /* Declare an _OSC (OS Control Handoff) method */ 254 aml_append(dev, aml_name_decl("SUPP", aml_int(0))); 255 aml_append(dev, aml_name_decl("CTRL", aml_int(0))); 256 method = aml_method("_OSC", 4); 257 aml_append(method, 258 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 259 260 /* PCI Firmware Specification 3.0 261 * 4.5.1. _OSC Interface for PCI Host Bridge Devices 262 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is 263 * identified by the Universal Unique IDentifier (UUID) 264 * 33DB4D5B-1FF7-401C-9657-7441C03DD766 265 */ 266 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"); 267 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 268 aml_append(ifctx, 269 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 270 aml_append(ifctx, 271 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 272 aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); 273 aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); 274 aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D)), 275 aml_name("CTRL"))); 276 277 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); 278 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08)), 279 aml_name("CDW1"))); 280 aml_append(ifctx, ifctx1); 281 282 ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL")))); 283 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10)), 284 aml_name("CDW1"))); 285 aml_append(ifctx, ifctx1); 286 287 aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3"))); 288 aml_append(ifctx, aml_return(aml_arg(3))); 289 aml_append(method, ifctx); 290 291 elsectx = aml_else(); 292 aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4)), 293 aml_name("CDW1"))); 294 aml_append(elsectx, aml_return(aml_arg(3))); 295 aml_append(method, elsectx); 296 aml_append(dev, method); 297 298 method = aml_method("_DSM", 4); 299 300 /* PCI Firmware Specification 3.0 301 * 4.6.1. _DSM for PCI Express Slot Information 302 * The UUID in _DSM in this context is 303 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} 304 */ 305 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 306 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 307 ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0))); 308 uint8_t byte_list[1] = {1}; 309 buf = aml_buffer(1, byte_list); 310 aml_append(ifctx1, aml_return(buf)); 311 aml_append(ifctx, ifctx1); 312 aml_append(method, ifctx); 313 314 byte_list[0] = 0; 315 buf = aml_buffer(1, byte_list); 316 aml_append(method, aml_return(buf)); 317 aml_append(dev, method); 318 319 Aml *dev_rp0 = aml_device("%s", "RP0"); 320 aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0))); 321 aml_append(dev, dev_rp0); 322 aml_append(scope, dev); 323 } 324 325 /* RSDP */ 326 static GArray * 327 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) 328 { 329 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 330 331 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, 332 true /* fseg memory */); 333 334 memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature)); 335 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, sizeof(rsdp->oem_id)); 336 rsdp->length = cpu_to_le32(sizeof(*rsdp)); 337 rsdp->revision = 0x02; 338 339 /* Point to RSDT */ 340 rsdp->rsdt_physical_address = cpu_to_le32(rsdt); 341 /* Address to be filled by Guest linker */ 342 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, 343 ACPI_BUILD_TABLE_FILE, 344 rsdp_table, &rsdp->rsdt_physical_address, 345 sizeof rsdp->rsdt_physical_address); 346 rsdp->checksum = 0; 347 /* Checksum to be filled by Guest linker */ 348 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 349 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum); 350 351 return rsdp_table; 352 } 353 354 static void 355 build_spcr(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 356 { 357 AcpiSerialPortConsoleRedirection *spcr; 358 const MemMapEntry *uart_memmap = &guest_info->memmap[VIRT_UART]; 359 int irq = guest_info->irqmap[VIRT_UART] + ARM_SPI_BASE; 360 361 spcr = acpi_data_push(table_data, sizeof(*spcr)); 362 363 spcr->interface_type = 0x3; /* ARM PL011 UART */ 364 365 spcr->base_address.space_id = AML_SYSTEM_MEMORY; 366 spcr->base_address.bit_width = 8; 367 spcr->base_address.bit_offset = 0; 368 spcr->base_address.access_width = 1; 369 spcr->base_address.address = cpu_to_le64(uart_memmap->base); 370 371 spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */ 372 spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */ 373 374 spcr->baud = 3; /* Baud Rate: 3 = 9600 */ 375 spcr->parity = 0; /* No Parity */ 376 spcr->stopbits = 1; /* 1 Stop bit */ 377 spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */ 378 spcr->term_type = 0; /* Terminal Type: 0 = VT100 */ 379 380 spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */ 381 spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */ 382 383 build_header(linker, table_data, (void *)spcr, "SPCR", sizeof(*spcr), 2); 384 } 385 386 static void 387 build_mcfg(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 388 { 389 AcpiTableMcfg *mcfg; 390 const MemMapEntry *memmap = guest_info->memmap; 391 int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]); 392 393 mcfg = acpi_data_push(table_data, len); 394 mcfg->allocation[0].address = cpu_to_le64(memmap[VIRT_PCIE_ECAM].base); 395 396 /* Only a single allocation so no need to play with segments */ 397 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 398 mcfg->allocation[0].start_bus_number = 0; 399 mcfg->allocation[0].end_bus_number = (memmap[VIRT_PCIE_ECAM].size 400 / PCIE_MMCFG_SIZE_MIN) - 1; 401 402 build_header(linker, table_data, (void *)mcfg, "MCFG", len, 1); 403 } 404 405 /* GTDT */ 406 static void 407 build_gtdt(GArray *table_data, GArray *linker) 408 { 409 int gtdt_start = table_data->len; 410 AcpiGenericTimerTable *gtdt; 411 412 gtdt = acpi_data_push(table_data, sizeof *gtdt); 413 /* The interrupt values are the same with the device tree when adding 16 */ 414 gtdt->secure_el1_interrupt = ARCH_TIMER_S_EL1_IRQ + 16; 415 gtdt->secure_el1_flags = ACPI_EDGE_SENSITIVE; 416 417 gtdt->non_secure_el1_interrupt = ARCH_TIMER_NS_EL1_IRQ + 16; 418 gtdt->non_secure_el1_flags = ACPI_EDGE_SENSITIVE; 419 420 gtdt->virtual_timer_interrupt = ARCH_TIMER_VIRT_IRQ + 16; 421 gtdt->virtual_timer_flags = ACPI_EDGE_SENSITIVE; 422 423 gtdt->non_secure_el2_interrupt = ARCH_TIMER_NS_EL2_IRQ + 16; 424 gtdt->non_secure_el2_flags = ACPI_EDGE_SENSITIVE; 425 426 build_header(linker, table_data, 427 (void *)(table_data->data + gtdt_start), "GTDT", 428 table_data->len - gtdt_start, 2); 429 } 430 431 /* MADT */ 432 static void 433 build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info, 434 VirtAcpiCpuInfo *cpuinfo) 435 { 436 int madt_start = table_data->len; 437 const MemMapEntry *memmap = guest_info->memmap; 438 const int *irqmap = guest_info->irqmap; 439 AcpiMultipleApicTable *madt; 440 AcpiMadtGenericDistributor *gicd; 441 AcpiMadtGenericMsiFrame *gic_msi; 442 int i; 443 444 madt = acpi_data_push(table_data, sizeof *madt); 445 446 for (i = 0; i < guest_info->smp_cpus; i++) { 447 AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data, 448 sizeof *gicc); 449 gicc->type = ACPI_APIC_GENERIC_INTERRUPT; 450 gicc->length = sizeof(*gicc); 451 gicc->base_address = memmap[VIRT_GIC_CPU].base; 452 gicc->cpu_interface_number = i; 453 gicc->arm_mpidr = i; 454 gicc->uid = i; 455 if (test_bit(i, cpuinfo->found_cpus)) { 456 gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED); 457 } 458 } 459 460 gicd = acpi_data_push(table_data, sizeof *gicd); 461 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR; 462 gicd->length = sizeof(*gicd); 463 gicd->base_address = memmap[VIRT_GIC_DIST].base; 464 465 gic_msi = acpi_data_push(table_data, sizeof *gic_msi); 466 gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME; 467 gic_msi->length = sizeof(*gic_msi); 468 gic_msi->gic_msi_frame_id = 0; 469 gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base); 470 gic_msi->flags = cpu_to_le32(1); 471 gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS); 472 gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE); 473 474 build_header(linker, table_data, 475 (void *)(table_data->data + madt_start), "APIC", 476 table_data->len - madt_start, 3); 477 } 478 479 /* FADT */ 480 static void 481 build_fadt(GArray *table_data, GArray *linker, unsigned dsdt) 482 { 483 AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); 484 485 /* Hardware Reduced = 1 and use PSCI 0.2+ and with HVC */ 486 fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI); 487 fadt->arm_boot_flags = cpu_to_le16((1 << ACPI_FADT_ARM_USE_PSCI_G_0_2) | 488 (1 << ACPI_FADT_ARM_PSCI_USE_HVC)); 489 490 /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */ 491 fadt->minor_revision = 0x1; 492 493 fadt->dsdt = cpu_to_le32(dsdt); 494 /* DSDT address to be filled by Guest linker */ 495 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 496 ACPI_BUILD_TABLE_FILE, 497 table_data, &fadt->dsdt, 498 sizeof fadt->dsdt); 499 500 build_header(linker, table_data, 501 (void *)fadt, "FACP", sizeof(*fadt), 5); 502 } 503 504 /* DSDT */ 505 static void 506 build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 507 { 508 Aml *scope, *dsdt; 509 const MemMapEntry *memmap = guest_info->memmap; 510 const int *irqmap = guest_info->irqmap; 511 512 dsdt = init_aml_allocator(); 513 /* Reserve space for header */ 514 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 515 516 scope = aml_scope("\\_SB"); 517 acpi_dsdt_add_cpus(scope, guest_info->smp_cpus); 518 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], 519 (irqmap[VIRT_UART] + ARM_SPI_BASE)); 520 acpi_dsdt_add_rtc(scope, &memmap[VIRT_RTC], 521 (irqmap[VIRT_RTC] + ARM_SPI_BASE)); 522 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); 523 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], 524 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); 525 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), 526 guest_info->use_highmem); 527 528 aml_append(dsdt, scope); 529 530 /* copy AML table into ACPI tables blob and patch header there */ 531 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 532 build_header(linker, table_data, 533 (void *)(table_data->data + table_data->len - dsdt->buf->len), 534 "DSDT", dsdt->buf->len, 2); 535 free_aml_allocator(); 536 } 537 538 typedef 539 struct AcpiBuildState { 540 /* Copy of table in RAM (for patching). */ 541 MemoryRegion *table_mr; 542 MemoryRegion *rsdp_mr; 543 MemoryRegion *linker_mr; 544 /* Is table patched? */ 545 bool patched; 546 VirtGuestInfo *guest_info; 547 } AcpiBuildState; 548 549 static 550 void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables) 551 { 552 GArray *table_offsets; 553 unsigned dsdt, rsdt; 554 VirtAcpiCpuInfo cpuinfo; 555 GArray *tables_blob = tables->table_data; 556 557 virt_acpi_get_cpu_info(&cpuinfo); 558 559 table_offsets = g_array_new(false, true /* clear */, 560 sizeof(uint32_t)); 561 562 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, 563 64, false /* high memory */); 564 565 /* 566 * The ACPI v5.1 tables for Hardware-reduced ACPI platform are: 567 * RSDP 568 * RSDT 569 * FADT 570 * GTDT 571 * MADT 572 * MCFG 573 * DSDT 574 */ 575 576 /* DSDT is pointed to by FADT */ 577 dsdt = tables_blob->len; 578 build_dsdt(tables_blob, tables->linker, guest_info); 579 580 /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */ 581 acpi_add_table(table_offsets, tables_blob); 582 build_fadt(tables_blob, tables->linker, dsdt); 583 584 acpi_add_table(table_offsets, tables_blob); 585 build_madt(tables_blob, tables->linker, guest_info, &cpuinfo); 586 587 acpi_add_table(table_offsets, tables_blob); 588 build_gtdt(tables_blob, tables->linker); 589 590 acpi_add_table(table_offsets, tables_blob); 591 build_mcfg(tables_blob, tables->linker, guest_info); 592 593 acpi_add_table(table_offsets, tables_blob); 594 build_spcr(tables_blob, tables->linker, guest_info); 595 596 /* RSDT is pointed to by RSDP */ 597 rsdt = tables_blob->len; 598 build_rsdt(tables_blob, tables->linker, table_offsets); 599 600 /* RSDP is in FSEG memory, so allocate it separately */ 601 build_rsdp(tables->rsdp, tables->linker, rsdt); 602 603 /* Cleanup memory that's no longer used. */ 604 g_array_free(table_offsets, true); 605 } 606 607 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 608 { 609 uint32_t size = acpi_data_len(data); 610 611 /* Make sure RAM size is correct - in case it got changed 612 * e.g. by migration */ 613 memory_region_ram_resize(mr, size, &error_abort); 614 615 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 616 memory_region_set_dirty(mr, 0, size); 617 } 618 619 static void virt_acpi_build_update(void *build_opaque, uint32_t offset) 620 { 621 AcpiBuildState *build_state = build_opaque; 622 AcpiBuildTables tables; 623 624 /* No state to update or already patched? Nothing to do. */ 625 if (!build_state || build_state->patched) { 626 return; 627 } 628 build_state->patched = true; 629 630 acpi_build_tables_init(&tables); 631 632 virt_acpi_build(build_state->guest_info, &tables); 633 634 acpi_ram_update(build_state->table_mr, tables.table_data); 635 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 636 acpi_ram_update(build_state->linker_mr, tables.linker); 637 638 639 acpi_build_tables_cleanup(&tables, true); 640 } 641 642 static void virt_acpi_build_reset(void *build_opaque) 643 { 644 AcpiBuildState *build_state = build_opaque; 645 build_state->patched = false; 646 } 647 648 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, 649 GArray *blob, const char *name, 650 uint64_t max_size) 651 { 652 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 653 name, virt_acpi_build_update, build_state); 654 } 655 656 static const VMStateDescription vmstate_virt_acpi_build = { 657 .name = "virt_acpi_build", 658 .version_id = 1, 659 .minimum_version_id = 1, 660 .fields = (VMStateField[]) { 661 VMSTATE_BOOL(patched, AcpiBuildState), 662 VMSTATE_END_OF_LIST() 663 }, 664 }; 665 666 void virt_acpi_setup(VirtGuestInfo *guest_info) 667 { 668 AcpiBuildTables tables; 669 AcpiBuildState *build_state; 670 671 if (!guest_info->fw_cfg) { 672 trace_virt_acpi_setup(); 673 return; 674 } 675 676 if (!acpi_enabled) { 677 trace_virt_acpi_setup(); 678 return; 679 } 680 681 build_state = g_malloc0(sizeof *build_state); 682 build_state->guest_info = guest_info; 683 684 acpi_build_tables_init(&tables); 685 virt_acpi_build(build_state->guest_info, &tables); 686 687 /* Now expose it all to Guest */ 688 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, 689 ACPI_BUILD_TABLE_FILE, 690 ACPI_BUILD_TABLE_MAX_SIZE); 691 assert(build_state->table_mr != NULL); 692 693 build_state->linker_mr = 694 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); 695 696 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 697 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 698 699 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, 700 ACPI_BUILD_RSDP_FILE, 0); 701 702 qemu_register_reset(virt_acpi_build_reset, build_state); 703 virt_acpi_build_reset(build_state); 704 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 705 706 /* Cleanup tables but don't free the memory: we track it 707 * in build_state. 708 */ 709 acpi_build_tables_cleanup(&tables, false); 710 } 711