1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * ARM virt ACPI generation 4 * 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 6 * Copyright (C) 2006 Fabrice Bellard 7 * Copyright (C) 2013 Red Hat Inc 8 * 9 * Author: Michael S. Tsirkin <mst@redhat.com> 10 * 11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 12 * 13 * Author: Shannon Zhao <zhaoshenglong@huawei.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "qapi/error.h" 31 #include "qemu/bitmap.h" 32 #include "trace.h" 33 #include "hw/core/cpu.h" 34 #include "target/arm/cpu.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/acpi/aml-build.h" 40 #include "hw/acpi/utils.h" 41 #include "hw/acpi/pci.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "hw/acpi/generic_event_device.h" 44 #include "hw/pci/pcie_host.h" 45 #include "hw/pci/pci.h" 46 #include "hw/arm/virt.h" 47 #include "hw/mem/nvdimm.h" 48 #include "sysemu/numa.h" 49 #include "sysemu/reset.h" 50 #include "kvm_arm.h" 51 #include "migration/vmstate.h" 52 53 #define ARM_SPI_BASE 32 54 55 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) 56 { 57 uint16_t i; 58 59 for (i = 0; i < smp_cpus; i++) { 60 Aml *dev = aml_device("C%.03X", i); 61 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 62 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 63 aml_append(scope, dev); 64 } 65 } 66 67 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 68 uint32_t uart_irq) 69 { 70 Aml *dev = aml_device("COM0"); 71 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); 72 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 73 74 Aml *crs = aml_resource_template(); 75 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 76 uart_memmap->size, AML_READ_WRITE)); 77 aml_append(crs, 78 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 79 AML_EXCLUSIVE, &uart_irq, 1)); 80 aml_append(dev, aml_name_decl("_CRS", crs)); 81 82 aml_append(scope, dev); 83 } 84 85 static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) 86 { 87 Aml *dev = aml_device("FWCF"); 88 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 89 /* device present, functioning, decoding, not shown in UI */ 90 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 91 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 92 93 Aml *crs = aml_resource_template(); 94 aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, 95 fw_cfg_memmap->size, AML_READ_WRITE)); 96 aml_append(dev, aml_name_decl("_CRS", crs)); 97 aml_append(scope, dev); 98 } 99 100 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) 101 { 102 Aml *dev, *crs; 103 hwaddr base = flash_memmap->base; 104 hwaddr size = flash_memmap->size / 2; 105 106 dev = aml_device("FLS0"); 107 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 108 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 109 110 crs = aml_resource_template(); 111 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 112 aml_append(dev, aml_name_decl("_CRS", crs)); 113 aml_append(scope, dev); 114 115 dev = aml_device("FLS1"); 116 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 117 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 118 crs = aml_resource_template(); 119 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); 120 aml_append(dev, aml_name_decl("_CRS", crs)); 121 aml_append(scope, dev); 122 } 123 124 static void acpi_dsdt_add_virtio(Aml *scope, 125 const MemMapEntry *virtio_mmio_memmap, 126 uint32_t mmio_irq, int num) 127 { 128 hwaddr base = virtio_mmio_memmap->base; 129 hwaddr size = virtio_mmio_memmap->size; 130 int i; 131 132 for (i = 0; i < num; i++) { 133 uint32_t irq = mmio_irq + i; 134 Aml *dev = aml_device("VR%02u", i); 135 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); 136 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 137 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 138 139 Aml *crs = aml_resource_template(); 140 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 141 aml_append(crs, 142 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 143 AML_EXCLUSIVE, &irq, 1)); 144 aml_append(dev, aml_name_decl("_CRS", crs)); 145 aml_append(scope, dev); 146 base += size; 147 } 148 } 149 150 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, 151 uint32_t irq, bool use_highmem, bool highmem_ecam) 152 { 153 int ecam_id = VIRT_ECAM_ID(highmem_ecam); 154 Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; 155 int i, slot_no; 156 hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base; 157 hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size; 158 hwaddr base_pio = memmap[VIRT_PCIE_PIO].base; 159 hwaddr size_pio = memmap[VIRT_PCIE_PIO].size; 160 hwaddr base_ecam = memmap[ecam_id].base; 161 hwaddr size_ecam = memmap[ecam_id].size; 162 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 163 164 Aml *dev = aml_device("%s", "PCI0"); 165 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); 166 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); 167 aml_append(dev, aml_name_decl("_SEG", aml_int(0))); 168 aml_append(dev, aml_name_decl("_BBN", aml_int(0))); 169 aml_append(dev, aml_name_decl("_UID", aml_string("PCI0"))); 170 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); 171 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 172 173 /* Declare the PCI Routing Table. */ 174 Aml *rt_pkg = aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS); 175 for (slot_no = 0; slot_no < PCI_SLOT_MAX; slot_no++) { 176 for (i = 0; i < PCI_NUM_PINS; i++) { 177 int gsi = (i + slot_no) % PCI_NUM_PINS; 178 Aml *pkg = aml_package(4); 179 aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF)); 180 aml_append(pkg, aml_int(i)); 181 aml_append(pkg, aml_name("GSI%d", gsi)); 182 aml_append(pkg, aml_int(0)); 183 aml_append(rt_pkg, pkg); 184 } 185 } 186 aml_append(dev, aml_name_decl("_PRT", rt_pkg)); 187 188 /* Create GSI link device */ 189 for (i = 0; i < PCI_NUM_PINS; i++) { 190 uint32_t irqs = irq + i; 191 Aml *dev_gsi = aml_device("GSI%d", i); 192 aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); 193 aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i))); 194 crs = aml_resource_template(); 195 aml_append(crs, 196 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 197 AML_EXCLUSIVE, &irqs, 1)); 198 aml_append(dev_gsi, aml_name_decl("_PRS", crs)); 199 crs = aml_resource_template(); 200 aml_append(crs, 201 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 202 AML_EXCLUSIVE, &irqs, 1)); 203 aml_append(dev_gsi, aml_name_decl("_CRS", crs)); 204 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 205 aml_append(dev_gsi, method); 206 aml_append(dev, dev_gsi); 207 } 208 209 method = aml_method("_CBA", 0, AML_NOTSERIALIZED); 210 aml_append(method, aml_return(aml_int(base_ecam))); 211 aml_append(dev, method); 212 213 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 214 Aml *rbuf = aml_resource_template(); 215 aml_append(rbuf, 216 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 217 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, 218 nr_pcie_buses)); 219 aml_append(rbuf, 220 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 221 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio, 222 base_mmio + size_mmio - 1, 0x0000, size_mmio)); 223 aml_append(rbuf, 224 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 225 AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio, 226 size_pio)); 227 228 if (use_highmem) { 229 hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base; 230 hwaddr size_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].size; 231 232 aml_append(rbuf, 233 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 234 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, 235 base_mmio_high, 236 base_mmio_high + size_mmio_high - 1, 0x0000, 237 size_mmio_high)); 238 } 239 240 aml_append(method, aml_return(rbuf)); 241 aml_append(dev, method); 242 243 /* Declare an _OSC (OS Control Handoff) method */ 244 aml_append(dev, aml_name_decl("SUPP", aml_int(0))); 245 aml_append(dev, aml_name_decl("CTRL", aml_int(0))); 246 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 247 aml_append(method, 248 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 249 250 /* PCI Firmware Specification 3.0 251 * 4.5.1. _OSC Interface for PCI Host Bridge Devices 252 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is 253 * identified by the Universal Unique IDentifier (UUID) 254 * 33DB4D5B-1FF7-401C-9657-7441C03DD766 255 */ 256 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"); 257 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 258 aml_append(ifctx, 259 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 260 aml_append(ifctx, 261 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 262 aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); 263 aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); 264 265 /* 266 * Allow OS control for all 5 features: 267 * PCIeHotplug SHPCHotplug PME AER PCIeCapability. 268 */ 269 aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F), 270 aml_name("CTRL"))); 271 272 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); 273 aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08), 274 aml_name("CDW1"))); 275 aml_append(ifctx, ifctx1); 276 277 ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL")))); 278 aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10), 279 aml_name("CDW1"))); 280 aml_append(ifctx, ifctx1); 281 282 aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3"))); 283 aml_append(ifctx, aml_return(aml_arg(3))); 284 aml_append(method, ifctx); 285 286 elsectx = aml_else(); 287 aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4), 288 aml_name("CDW1"))); 289 aml_append(elsectx, aml_return(aml_arg(3))); 290 aml_append(method, elsectx); 291 aml_append(dev, method); 292 293 method = aml_method("_DSM", 4, AML_NOTSERIALIZED); 294 295 /* PCI Firmware Specification 3.0 296 * 4.6.1. _DSM for PCI Express Slot Information 297 * The UUID in _DSM in this context is 298 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} 299 */ 300 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 301 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 302 ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0))); 303 uint8_t byte_list[1] = {1}; 304 buf = aml_buffer(1, byte_list); 305 aml_append(ifctx1, aml_return(buf)); 306 aml_append(ifctx, ifctx1); 307 aml_append(method, ifctx); 308 309 byte_list[0] = 0; 310 buf = aml_buffer(1, byte_list); 311 aml_append(method, aml_return(buf)); 312 aml_append(dev, method); 313 314 Aml *dev_res0 = aml_device("%s", "RES0"); 315 aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); 316 crs = aml_resource_template(); 317 aml_append(crs, 318 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 319 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_ecam, 320 base_ecam + size_ecam - 1, 0x0000, size_ecam)); 321 aml_append(dev_res0, aml_name_decl("_CRS", crs)); 322 aml_append(dev, dev_res0); 323 aml_append(scope, dev); 324 } 325 326 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, 327 uint32_t gpio_irq) 328 { 329 Aml *dev = aml_device("GPO0"); 330 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); 331 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 332 333 Aml *crs = aml_resource_template(); 334 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, 335 AML_READ_WRITE)); 336 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 337 AML_EXCLUSIVE, &gpio_irq, 1)); 338 aml_append(dev, aml_name_decl("_CRS", crs)); 339 340 Aml *aei = aml_resource_template(); 341 /* Pin 3 for power button */ 342 const uint32_t pin_list[1] = {3}; 343 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, 344 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, 345 "GPO0", NULL, 0)); 346 aml_append(dev, aml_name_decl("_AEI", aei)); 347 348 /* _E03 is handle for power button */ 349 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); 350 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), 351 aml_int(0x80))); 352 aml_append(dev, method); 353 aml_append(scope, dev); 354 } 355 356 static void acpi_dsdt_add_power_button(Aml *scope) 357 { 358 Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE); 359 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C"))); 360 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 361 aml_append(scope, dev); 362 } 363 364 static void 365 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 366 { 367 int nb_nodes, iort_start = table_data->len; 368 AcpiIortIdMapping *idmap; 369 AcpiIortItsGroup *its; 370 AcpiIortTable *iort; 371 AcpiIortSmmu3 *smmu; 372 size_t node_size, iort_node_offset, iort_length, smmu_offset = 0; 373 AcpiIortRC *rc; 374 375 iort = acpi_data_push(table_data, sizeof(*iort)); 376 377 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 378 nb_nodes = 3; /* RC, ITS, SMMUv3 */ 379 } else { 380 nb_nodes = 2; /* RC, ITS */ 381 } 382 383 iort_length = sizeof(*iort); 384 iort->node_count = cpu_to_le32(nb_nodes); 385 /* 386 * Use a copy in case table_data->data moves during acpi_data_push 387 * operations. 388 */ 389 iort_node_offset = sizeof(*iort); 390 iort->node_offset = cpu_to_le32(iort_node_offset); 391 392 /* ITS group node */ 393 node_size = sizeof(*its) + sizeof(uint32_t); 394 iort_length += node_size; 395 its = acpi_data_push(table_data, node_size); 396 397 its->type = ACPI_IORT_NODE_ITS_GROUP; 398 its->length = cpu_to_le16(node_size); 399 its->its_count = cpu_to_le32(1); 400 its->identifiers[0] = 0; /* MADT translation_id */ 401 402 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 403 int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; 404 405 /* SMMUv3 node */ 406 smmu_offset = iort_node_offset + node_size; 407 node_size = sizeof(*smmu) + sizeof(*idmap); 408 iort_length += node_size; 409 smmu = acpi_data_push(table_data, node_size); 410 411 smmu->type = ACPI_IORT_NODE_SMMU_V3; 412 smmu->length = cpu_to_le16(node_size); 413 smmu->mapping_count = cpu_to_le32(1); 414 smmu->mapping_offset = cpu_to_le32(sizeof(*smmu)); 415 smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base); 416 smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE); 417 smmu->event_gsiv = cpu_to_le32(irq); 418 smmu->pri_gsiv = cpu_to_le32(irq + 1); 419 smmu->gerr_gsiv = cpu_to_le32(irq + 2); 420 smmu->sync_gsiv = cpu_to_le32(irq + 3); 421 422 /* Identity RID mapping covering the whole input RID range */ 423 idmap = &smmu->id_mapping_array[0]; 424 idmap->input_base = 0; 425 idmap->id_count = cpu_to_le32(0xFFFF); 426 idmap->output_base = 0; 427 /* output IORT node is the ITS group node (the first node) */ 428 idmap->output_reference = cpu_to_le32(iort_node_offset); 429 } 430 431 /* Root Complex Node */ 432 node_size = sizeof(*rc) + sizeof(*idmap); 433 iort_length += node_size; 434 rc = acpi_data_push(table_data, node_size); 435 436 rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX; 437 rc->length = cpu_to_le16(node_size); 438 rc->mapping_count = cpu_to_le32(1); 439 rc->mapping_offset = cpu_to_le32(sizeof(*rc)); 440 441 /* fully coherent device */ 442 rc->memory_properties.cache_coherency = cpu_to_le32(1); 443 rc->memory_properties.memory_flags = 0x3; /* CCA = CPM = DCAS = 1 */ 444 rc->pci_segment_number = 0; /* MCFG pci_segment */ 445 446 /* Identity RID mapping covering the whole input RID range */ 447 idmap = &rc->id_mapping_array[0]; 448 idmap->input_base = 0; 449 idmap->id_count = cpu_to_le32(0xFFFF); 450 idmap->output_base = 0; 451 452 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 453 /* output IORT node is the smmuv3 node */ 454 idmap->output_reference = cpu_to_le32(smmu_offset); 455 } else { 456 /* output IORT node is the ITS group node (the first node) */ 457 idmap->output_reference = cpu_to_le32(iort_node_offset); 458 } 459 460 /* 461 * Update the pointer address in case table_data->data moves during above 462 * acpi_data_push operations. 463 */ 464 iort = (AcpiIortTable *)(table_data->data + iort_start); 465 iort->length = cpu_to_le32(iort_length); 466 467 build_header(linker, table_data, (void *)(table_data->data + iort_start), 468 "IORT", table_data->len - iort_start, 0, NULL, NULL); 469 } 470 471 static void 472 build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 473 { 474 AcpiSerialPortConsoleRedirection *spcr; 475 const MemMapEntry *uart_memmap = &vms->memmap[VIRT_UART]; 476 int irq = vms->irqmap[VIRT_UART] + ARM_SPI_BASE; 477 int spcr_start = table_data->len; 478 479 spcr = acpi_data_push(table_data, sizeof(*spcr)); 480 481 spcr->interface_type = 0x3; /* ARM PL011 UART */ 482 483 spcr->base_address.space_id = AML_SYSTEM_MEMORY; 484 spcr->base_address.bit_width = 8; 485 spcr->base_address.bit_offset = 0; 486 spcr->base_address.access_width = 1; 487 spcr->base_address.address = cpu_to_le64(uart_memmap->base); 488 489 spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */ 490 spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */ 491 492 spcr->baud = 3; /* Baud Rate: 3 = 9600 */ 493 spcr->parity = 0; /* No Parity */ 494 spcr->stopbits = 1; /* 1 Stop bit */ 495 spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */ 496 spcr->term_type = 0; /* Terminal Type: 0 = VT100 */ 497 498 spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */ 499 spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */ 500 501 build_header(linker, table_data, (void *)(table_data->data + spcr_start), 502 "SPCR", table_data->len - spcr_start, 2, NULL, NULL); 503 } 504 505 static void 506 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 507 { 508 AcpiSystemResourceAffinityTable *srat; 509 AcpiSratProcessorGiccAffinity *core; 510 AcpiSratMemoryAffinity *numamem; 511 int i, srat_start; 512 uint64_t mem_base; 513 MachineClass *mc = MACHINE_GET_CLASS(vms); 514 MachineState *ms = MACHINE(vms); 515 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); 516 517 srat_start = table_data->len; 518 srat = acpi_data_push(table_data, sizeof(*srat)); 519 srat->reserved1 = cpu_to_le32(1); 520 521 for (i = 0; i < cpu_list->len; ++i) { 522 core = acpi_data_push(table_data, sizeof(*core)); 523 core->type = ACPI_SRAT_PROCESSOR_GICC; 524 core->length = sizeof(*core); 525 core->proximity = cpu_to_le32(cpu_list->cpus[i].props.node_id); 526 core->acpi_processor_uid = cpu_to_le32(i); 527 core->flags = cpu_to_le32(1); 528 } 529 530 mem_base = vms->memmap[VIRT_MEM].base; 531 for (i = 0; i < ms->numa_state->num_nodes; ++i) { 532 if (ms->numa_state->nodes[i].node_mem > 0) { 533 numamem = acpi_data_push(table_data, sizeof(*numamem)); 534 build_srat_memory(numamem, mem_base, 535 ms->numa_state->nodes[i].node_mem, i, 536 MEM_AFFINITY_ENABLED); 537 mem_base += ms->numa_state->nodes[i].node_mem; 538 } 539 } 540 541 if (ms->device_memory) { 542 numamem = acpi_data_push(table_data, sizeof *numamem); 543 build_srat_memory(numamem, ms->device_memory->base, 544 memory_region_size(&ms->device_memory->mr), 545 ms->numa_state->num_nodes - 1, 546 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 547 } 548 549 build_header(linker, table_data, (void *)(table_data->data + srat_start), 550 "SRAT", table_data->len - srat_start, 3, NULL, NULL); 551 } 552 553 /* GTDT */ 554 static void 555 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 556 { 557 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 558 int gtdt_start = table_data->len; 559 AcpiGenericTimerTable *gtdt; 560 uint32_t irqflags; 561 562 if (vmc->claim_edge_triggered_timers) { 563 irqflags = ACPI_GTDT_INTERRUPT_MODE_EDGE; 564 } else { 565 irqflags = ACPI_GTDT_INTERRUPT_MODE_LEVEL; 566 } 567 568 gtdt = acpi_data_push(table_data, sizeof *gtdt); 569 /* The interrupt values are the same with the device tree when adding 16 */ 570 gtdt->secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_S_EL1_IRQ + 16); 571 gtdt->secure_el1_flags = cpu_to_le32(irqflags); 572 573 gtdt->non_secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ + 16); 574 gtdt->non_secure_el1_flags = cpu_to_le32(irqflags | 575 ACPI_GTDT_CAP_ALWAYS_ON); 576 577 gtdt->virtual_timer_interrupt = cpu_to_le32(ARCH_TIMER_VIRT_IRQ + 16); 578 gtdt->virtual_timer_flags = cpu_to_le32(irqflags); 579 580 gtdt->non_secure_el2_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ + 16); 581 gtdt->non_secure_el2_flags = cpu_to_le32(irqflags); 582 583 build_header(linker, table_data, 584 (void *)(table_data->data + gtdt_start), "GTDT", 585 table_data->len - gtdt_start, 2, NULL, NULL); 586 } 587 588 /* MADT */ 589 static void 590 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 591 { 592 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 593 int madt_start = table_data->len; 594 const MemMapEntry *memmap = vms->memmap; 595 const int *irqmap = vms->irqmap; 596 AcpiMultipleApicTable *madt; 597 AcpiMadtGenericDistributor *gicd; 598 AcpiMadtGenericMsiFrame *gic_msi; 599 int i; 600 601 madt = acpi_data_push(table_data, sizeof *madt); 602 603 gicd = acpi_data_push(table_data, sizeof *gicd); 604 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR; 605 gicd->length = sizeof(*gicd); 606 gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base); 607 gicd->version = vms->gic_version; 608 609 for (i = 0; i < vms->smp_cpus; i++) { 610 AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data, 611 sizeof(*gicc)); 612 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 613 614 gicc->type = ACPI_APIC_GENERIC_CPU_INTERFACE; 615 gicc->length = sizeof(*gicc); 616 if (vms->gic_version == 2) { 617 gicc->base_address = cpu_to_le64(memmap[VIRT_GIC_CPU].base); 618 gicc->gich_base_address = cpu_to_le64(memmap[VIRT_GIC_HYP].base); 619 gicc->gicv_base_address = cpu_to_le64(memmap[VIRT_GIC_VCPU].base); 620 } 621 gicc->cpu_interface_number = cpu_to_le32(i); 622 gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity); 623 gicc->uid = cpu_to_le32(i); 624 gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED); 625 626 if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 627 gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ)); 628 } 629 if (vms->virt) { 630 gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ)); 631 } 632 } 633 634 if (vms->gic_version == 3) { 635 AcpiMadtGenericTranslator *gic_its; 636 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 637 AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data, 638 sizeof *gicr); 639 640 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 641 gicr->length = sizeof(*gicr); 642 gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base); 643 gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size); 644 645 if (nb_redist_regions == 2) { 646 gicr = acpi_data_push(table_data, sizeof(*gicr)); 647 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 648 gicr->length = sizeof(*gicr); 649 gicr->base_address = 650 cpu_to_le64(memmap[VIRT_HIGH_GIC_REDIST2].base); 651 gicr->range_length = 652 cpu_to_le32(memmap[VIRT_HIGH_GIC_REDIST2].size); 653 } 654 655 if (its_class_name() && !vmc->no_its) { 656 gic_its = acpi_data_push(table_data, sizeof *gic_its); 657 gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR; 658 gic_its->length = sizeof(*gic_its); 659 gic_its->translation_id = 0; 660 gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base); 661 } 662 } else { 663 gic_msi = acpi_data_push(table_data, sizeof *gic_msi); 664 gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME; 665 gic_msi->length = sizeof(*gic_msi); 666 gic_msi->gic_msi_frame_id = 0; 667 gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base); 668 gic_msi->flags = cpu_to_le32(1); 669 gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS); 670 gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE); 671 } 672 673 build_header(linker, table_data, 674 (void *)(table_data->data + madt_start), "APIC", 675 table_data->len - madt_start, 3, NULL, NULL); 676 } 677 678 /* FADT */ 679 static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker, 680 VirtMachineState *vms, unsigned dsdt_tbl_offset) 681 { 682 /* ACPI v5.1 */ 683 AcpiFadtData fadt = { 684 .rev = 5, 685 .minor_ver = 1, 686 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, 687 .xdsdt_tbl_offset = &dsdt_tbl_offset, 688 }; 689 690 switch (vms->psci_conduit) { 691 case QEMU_PSCI_CONDUIT_DISABLED: 692 fadt.arm_boot_arch = 0; 693 break; 694 case QEMU_PSCI_CONDUIT_HVC: 695 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT | 696 ACPI_FADT_ARM_PSCI_USE_HVC; 697 break; 698 case QEMU_PSCI_CONDUIT_SMC: 699 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT; 700 break; 701 default: 702 g_assert_not_reached(); 703 } 704 705 build_fadt(table_data, linker, &fadt, NULL, NULL); 706 } 707 708 /* DSDT */ 709 static void 710 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 711 { 712 Aml *scope, *dsdt; 713 MachineState *ms = MACHINE(vms); 714 const MemMapEntry *memmap = vms->memmap; 715 const int *irqmap = vms->irqmap; 716 717 dsdt = init_aml_allocator(); 718 /* Reserve space for header */ 719 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 720 721 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. 722 * While UEFI can use libfdt to disable the RTC device node in the DTB that 723 * it passes to the OS, it cannot modify AML. Therefore, we won't generate 724 * the RTC ACPI device at all when using UEFI. 725 */ 726 scope = aml_scope("\\_SB"); 727 acpi_dsdt_add_cpus(scope, vms->smp_cpus); 728 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], 729 (irqmap[VIRT_UART] + ARM_SPI_BASE)); 730 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); 731 acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); 732 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], 733 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); 734 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), 735 vms->highmem, vms->highmem_ecam); 736 if (vms->acpi_dev) { 737 build_ged_aml(scope, "\\_SB."GED_DEVICE, 738 HOTPLUG_HANDLER(vms->acpi_dev), 739 irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY, 740 memmap[VIRT_ACPI_GED].base); 741 } else { 742 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], 743 (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); 744 } 745 746 if (vms->acpi_dev) { 747 uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev), 748 "ged-event", &error_abort); 749 750 if (event & ACPI_GED_MEM_HOTPLUG_EVT) { 751 build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL, 752 AML_SYSTEM_MEMORY, 753 memmap[VIRT_PCDIMM_ACPI].base); 754 } 755 } 756 757 acpi_dsdt_add_power_button(scope); 758 759 aml_append(dsdt, scope); 760 761 /* copy AML table into ACPI tables blob and patch header there */ 762 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 763 build_header(linker, table_data, 764 (void *)(table_data->data + table_data->len - dsdt->buf->len), 765 "DSDT", dsdt->buf->len, 2, NULL, NULL); 766 free_aml_allocator(); 767 } 768 769 typedef 770 struct AcpiBuildState { 771 /* Copy of table in RAM (for patching). */ 772 MemoryRegion *table_mr; 773 MemoryRegion *rsdp_mr; 774 MemoryRegion *linker_mr; 775 /* Is table patched? */ 776 bool patched; 777 } AcpiBuildState; 778 779 static 780 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) 781 { 782 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 783 GArray *table_offsets; 784 unsigned dsdt, xsdt; 785 GArray *tables_blob = tables->table_data; 786 MachineState *ms = MACHINE(vms); 787 788 table_offsets = g_array_new(false, true /* clear */, 789 sizeof(uint32_t)); 790 791 bios_linker_loader_alloc(tables->linker, 792 ACPI_BUILD_TABLE_FILE, tables_blob, 793 64, false /* high memory */); 794 795 /* DSDT is pointed to by FADT */ 796 dsdt = tables_blob->len; 797 build_dsdt(tables_blob, tables->linker, vms); 798 799 /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */ 800 acpi_add_table(table_offsets, tables_blob); 801 build_fadt_rev5(tables_blob, tables->linker, vms, dsdt); 802 803 acpi_add_table(table_offsets, tables_blob); 804 build_madt(tables_blob, tables->linker, vms); 805 806 acpi_add_table(table_offsets, tables_blob); 807 build_gtdt(tables_blob, tables->linker, vms); 808 809 acpi_add_table(table_offsets, tables_blob); 810 { 811 AcpiMcfgInfo mcfg = { 812 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, 813 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, 814 }; 815 build_mcfg(tables_blob, tables->linker, &mcfg); 816 } 817 818 acpi_add_table(table_offsets, tables_blob); 819 build_spcr(tables_blob, tables->linker, vms); 820 821 if (ms->numa_state->num_nodes > 0) { 822 acpi_add_table(table_offsets, tables_blob); 823 build_srat(tables_blob, tables->linker, vms); 824 if (ms->numa_state->have_numa_distance) { 825 acpi_add_table(table_offsets, tables_blob); 826 build_slit(tables_blob, tables->linker, ms); 827 } 828 } 829 830 if (ms->nvdimms_state->is_enabled) { 831 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 832 ms->nvdimms_state, ms->ram_slots); 833 } 834 835 if (its_class_name() && !vmc->no_its) { 836 acpi_add_table(table_offsets, tables_blob); 837 build_iort(tables_blob, tables->linker, vms); 838 } 839 840 /* XSDT is pointed to by RSDP */ 841 xsdt = tables_blob->len; 842 build_xsdt(tables_blob, tables->linker, table_offsets, NULL, NULL); 843 844 /* RSDP is in FSEG memory, so allocate it separately */ 845 { 846 AcpiRsdpData rsdp_data = { 847 .revision = 2, 848 .oem_id = ACPI_BUILD_APPNAME6, 849 .xsdt_tbl_offset = &xsdt, 850 .rsdt_tbl_offset = NULL, 851 }; 852 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 853 } 854 855 /* Cleanup memory that's no longer used. */ 856 g_array_free(table_offsets, true); 857 } 858 859 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 860 { 861 uint32_t size = acpi_data_len(data); 862 863 /* Make sure RAM size is correct - in case it got changed 864 * e.g. by migration */ 865 memory_region_ram_resize(mr, size, &error_abort); 866 867 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 868 memory_region_set_dirty(mr, 0, size); 869 } 870 871 static void virt_acpi_build_update(void *build_opaque) 872 { 873 AcpiBuildState *build_state = build_opaque; 874 AcpiBuildTables tables; 875 876 /* No state to update or already patched? Nothing to do. */ 877 if (!build_state || build_state->patched) { 878 return; 879 } 880 build_state->patched = true; 881 882 acpi_build_tables_init(&tables); 883 884 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables); 885 886 acpi_ram_update(build_state->table_mr, tables.table_data); 887 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 888 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 889 890 acpi_build_tables_cleanup(&tables, true); 891 } 892 893 static void virt_acpi_build_reset(void *build_opaque) 894 { 895 AcpiBuildState *build_state = build_opaque; 896 build_state->patched = false; 897 } 898 899 static const VMStateDescription vmstate_virt_acpi_build = { 900 .name = "virt_acpi_build", 901 .version_id = 1, 902 .minimum_version_id = 1, 903 .fields = (VMStateField[]) { 904 VMSTATE_BOOL(patched, AcpiBuildState), 905 VMSTATE_END_OF_LIST() 906 }, 907 }; 908 909 void virt_acpi_setup(VirtMachineState *vms) 910 { 911 AcpiBuildTables tables; 912 AcpiBuildState *build_state; 913 914 if (!vms->fw_cfg) { 915 trace_virt_acpi_setup(); 916 return; 917 } 918 919 if (!virt_is_acpi_enabled(vms)) { 920 trace_virt_acpi_setup(); 921 return; 922 } 923 924 build_state = g_malloc0(sizeof *build_state); 925 926 acpi_build_tables_init(&tables); 927 virt_acpi_build(vms, &tables); 928 929 /* Now expose it all to Guest */ 930 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, 931 build_state, tables.table_data, 932 ACPI_BUILD_TABLE_FILE, 933 ACPI_BUILD_TABLE_MAX_SIZE); 934 assert(build_state->table_mr != NULL); 935 936 build_state->linker_mr = 937 acpi_add_rom_blob(virt_acpi_build_update, build_state, 938 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0); 939 940 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, 941 acpi_data_len(tables.tcpalog)); 942 943 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, 944 build_state, tables.rsdp, 945 ACPI_BUILD_RSDP_FILE, 0); 946 947 qemu_register_reset(virt_acpi_build_reset, build_state); 948 virt_acpi_build_reset(build_state); 949 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 950 951 /* Cleanup tables but don't free the memory: we track it 952 * in build_state. 953 */ 954 acpi_build_tables_cleanup(&tables, false); 955 } 956