1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * ARM virt ACPI generation 4 * 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 6 * Copyright (C) 2006 Fabrice Bellard 7 * Copyright (C) 2013 Red Hat Inc 8 * 9 * Author: Michael S. Tsirkin <mst@redhat.com> 10 * 11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 12 * 13 * Author: Shannon Zhao <zhaoshenglong@huawei.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "qapi/error.h" 31 #include "qemu/bitmap.h" 32 #include "trace.h" 33 #include "hw/core/cpu.h" 34 #include "target/arm/cpu.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/acpi/aml-build.h" 40 #include "hw/acpi/utils.h" 41 #include "hw/acpi/pci.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "hw/acpi/generic_event_device.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/pci/pcie_host.h" 46 #include "hw/pci/pci.h" 47 #include "hw/pci-host/gpex.h" 48 #include "hw/arm/virt.h" 49 #include "hw/mem/nvdimm.h" 50 #include "hw/platform-bus.h" 51 #include "sysemu/numa.h" 52 #include "sysemu/reset.h" 53 #include "sysemu/tpm.h" 54 #include "kvm_arm.h" 55 #include "migration/vmstate.h" 56 #include "hw/acpi/ghes.h" 57 58 #define ARM_SPI_BASE 32 59 60 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) 61 { 62 uint16_t i; 63 64 for (i = 0; i < smp_cpus; i++) { 65 Aml *dev = aml_device("C%.03X", i); 66 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 67 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 68 aml_append(scope, dev); 69 } 70 } 71 72 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 73 uint32_t uart_irq) 74 { 75 Aml *dev = aml_device("COM0"); 76 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); 77 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 78 79 Aml *crs = aml_resource_template(); 80 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 81 uart_memmap->size, AML_READ_WRITE)); 82 aml_append(crs, 83 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 84 AML_EXCLUSIVE, &uart_irq, 1)); 85 aml_append(dev, aml_name_decl("_CRS", crs)); 86 87 aml_append(scope, dev); 88 } 89 90 static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) 91 { 92 Aml *dev = aml_device("FWCF"); 93 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 94 /* device present, functioning, decoding, not shown in UI */ 95 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 96 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 97 98 Aml *crs = aml_resource_template(); 99 aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, 100 fw_cfg_memmap->size, AML_READ_WRITE)); 101 aml_append(dev, aml_name_decl("_CRS", crs)); 102 aml_append(scope, dev); 103 } 104 105 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) 106 { 107 Aml *dev, *crs; 108 hwaddr base = flash_memmap->base; 109 hwaddr size = flash_memmap->size / 2; 110 111 dev = aml_device("FLS0"); 112 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 113 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 114 115 crs = aml_resource_template(); 116 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 117 aml_append(dev, aml_name_decl("_CRS", crs)); 118 aml_append(scope, dev); 119 120 dev = aml_device("FLS1"); 121 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 122 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 123 crs = aml_resource_template(); 124 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); 125 aml_append(dev, aml_name_decl("_CRS", crs)); 126 aml_append(scope, dev); 127 } 128 129 static void acpi_dsdt_add_virtio(Aml *scope, 130 const MemMapEntry *virtio_mmio_memmap, 131 uint32_t mmio_irq, int num) 132 { 133 hwaddr base = virtio_mmio_memmap->base; 134 hwaddr size = virtio_mmio_memmap->size; 135 int i; 136 137 for (i = 0; i < num; i++) { 138 uint32_t irq = mmio_irq + i; 139 Aml *dev = aml_device("VR%02u", i); 140 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); 141 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 142 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 143 144 Aml *crs = aml_resource_template(); 145 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 146 aml_append(crs, 147 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 148 AML_EXCLUSIVE, &irq, 1)); 149 aml_append(dev, aml_name_decl("_CRS", crs)); 150 aml_append(scope, dev); 151 base += size; 152 } 153 } 154 155 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, 156 uint32_t irq, bool use_highmem, bool highmem_ecam, 157 VirtMachineState *vms) 158 { 159 int ecam_id = VIRT_ECAM_ID(highmem_ecam); 160 struct GPEXConfig cfg = { 161 .mmio32 = memmap[VIRT_PCIE_MMIO], 162 .pio = memmap[VIRT_PCIE_PIO], 163 .ecam = memmap[ecam_id], 164 .irq = irq, 165 .bus = vms->bus, 166 }; 167 168 if (use_highmem) { 169 cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO]; 170 } 171 172 acpi_dsdt_add_gpex(scope, &cfg); 173 } 174 175 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, 176 uint32_t gpio_irq) 177 { 178 Aml *dev = aml_device("GPO0"); 179 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); 180 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 181 182 Aml *crs = aml_resource_template(); 183 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, 184 AML_READ_WRITE)); 185 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 186 AML_EXCLUSIVE, &gpio_irq, 1)); 187 aml_append(dev, aml_name_decl("_CRS", crs)); 188 189 Aml *aei = aml_resource_template(); 190 /* Pin 3 for power button */ 191 const uint32_t pin_list[1] = {3}; 192 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, 193 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, 194 "GPO0", NULL, 0)); 195 aml_append(dev, aml_name_decl("_AEI", aei)); 196 197 /* _E03 is handle for power button */ 198 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); 199 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), 200 aml_int(0x80))); 201 aml_append(dev, method); 202 aml_append(scope, dev); 203 } 204 205 static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms) 206 { 207 PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); 208 hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base; 209 SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find()); 210 MemoryRegion *sbdev_mr; 211 hwaddr tpm_base; 212 213 if (!sbdev) { 214 return; 215 } 216 217 tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); 218 assert(tpm_base != -1); 219 220 tpm_base += pbus_base; 221 222 sbdev_mr = sysbus_mmio_get_region(sbdev, 0); 223 224 Aml *dev = aml_device("TPM0"); 225 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 226 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 227 228 Aml *crs = aml_resource_template(); 229 aml_append(crs, 230 aml_memory32_fixed(tpm_base, 231 (uint32_t)memory_region_size(sbdev_mr), 232 AML_READ_WRITE)); 233 aml_append(dev, aml_name_decl("_CRS", crs)); 234 aml_append(scope, dev); 235 } 236 237 static void 238 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 239 { 240 int nb_nodes, iort_start = table_data->len; 241 AcpiIortIdMapping *idmap; 242 AcpiIortItsGroup *its; 243 AcpiIortTable *iort; 244 AcpiIortSmmu3 *smmu; 245 size_t node_size, iort_node_offset, iort_length, smmu_offset = 0; 246 AcpiIortRC *rc; 247 248 iort = acpi_data_push(table_data, sizeof(*iort)); 249 250 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 251 nb_nodes = 3; /* RC, ITS, SMMUv3 */ 252 } else { 253 nb_nodes = 2; /* RC, ITS */ 254 } 255 256 iort_length = sizeof(*iort); 257 iort->node_count = cpu_to_le32(nb_nodes); 258 /* 259 * Use a copy in case table_data->data moves during acpi_data_push 260 * operations. 261 */ 262 iort_node_offset = sizeof(*iort); 263 iort->node_offset = cpu_to_le32(iort_node_offset); 264 265 /* ITS group node */ 266 node_size = sizeof(*its) + sizeof(uint32_t); 267 iort_length += node_size; 268 its = acpi_data_push(table_data, node_size); 269 270 its->type = ACPI_IORT_NODE_ITS_GROUP; 271 its->length = cpu_to_le16(node_size); 272 its->its_count = cpu_to_le32(1); 273 its->identifiers[0] = 0; /* MADT translation_id */ 274 275 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 276 int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; 277 278 /* SMMUv3 node */ 279 smmu_offset = iort_node_offset + node_size; 280 node_size = sizeof(*smmu) + sizeof(*idmap); 281 iort_length += node_size; 282 smmu = acpi_data_push(table_data, node_size); 283 284 smmu->type = ACPI_IORT_NODE_SMMU_V3; 285 smmu->length = cpu_to_le16(node_size); 286 smmu->mapping_count = cpu_to_le32(1); 287 smmu->mapping_offset = cpu_to_le32(sizeof(*smmu)); 288 smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base); 289 smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE); 290 smmu->event_gsiv = cpu_to_le32(irq); 291 smmu->pri_gsiv = cpu_to_le32(irq + 1); 292 smmu->gerr_gsiv = cpu_to_le32(irq + 2); 293 smmu->sync_gsiv = cpu_to_le32(irq + 3); 294 295 /* Identity RID mapping covering the whole input RID range */ 296 idmap = &smmu->id_mapping_array[0]; 297 idmap->input_base = 0; 298 idmap->id_count = cpu_to_le32(0xFFFF); 299 idmap->output_base = 0; 300 /* output IORT node is the ITS group node (the first node) */ 301 idmap->output_reference = cpu_to_le32(iort_node_offset); 302 } 303 304 /* Root Complex Node */ 305 node_size = sizeof(*rc) + sizeof(*idmap); 306 iort_length += node_size; 307 rc = acpi_data_push(table_data, node_size); 308 309 rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX; 310 rc->length = cpu_to_le16(node_size); 311 rc->mapping_count = cpu_to_le32(1); 312 rc->mapping_offset = cpu_to_le32(sizeof(*rc)); 313 314 /* fully coherent device */ 315 rc->memory_properties.cache_coherency = cpu_to_le32(1); 316 rc->memory_properties.memory_flags = 0x3; /* CCA = CPM = DCAS = 1 */ 317 rc->pci_segment_number = 0; /* MCFG pci_segment */ 318 319 /* Identity RID mapping covering the whole input RID range */ 320 idmap = &rc->id_mapping_array[0]; 321 idmap->input_base = 0; 322 idmap->id_count = cpu_to_le32(0xFFFF); 323 idmap->output_base = 0; 324 325 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 326 /* output IORT node is the smmuv3 node */ 327 idmap->output_reference = cpu_to_le32(smmu_offset); 328 } else { 329 /* output IORT node is the ITS group node (the first node) */ 330 idmap->output_reference = cpu_to_le32(iort_node_offset); 331 } 332 333 /* 334 * Update the pointer address in case table_data->data moves during above 335 * acpi_data_push operations. 336 */ 337 iort = (AcpiIortTable *)(table_data->data + iort_start); 338 iort->length = cpu_to_le32(iort_length); 339 340 build_header(linker, table_data, (void *)(table_data->data + iort_start), 341 "IORT", table_data->len - iort_start, 0, NULL, NULL); 342 } 343 344 static void 345 build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 346 { 347 AcpiSerialPortConsoleRedirection *spcr; 348 const MemMapEntry *uart_memmap = &vms->memmap[VIRT_UART]; 349 int irq = vms->irqmap[VIRT_UART] + ARM_SPI_BASE; 350 int spcr_start = table_data->len; 351 352 spcr = acpi_data_push(table_data, sizeof(*spcr)); 353 354 spcr->interface_type = 0x3; /* ARM PL011 UART */ 355 356 spcr->base_address.space_id = AML_SYSTEM_MEMORY; 357 spcr->base_address.bit_width = 8; 358 spcr->base_address.bit_offset = 0; 359 spcr->base_address.access_width = 1; 360 spcr->base_address.address = cpu_to_le64(uart_memmap->base); 361 362 spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */ 363 spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */ 364 365 spcr->baud = 3; /* Baud Rate: 3 = 9600 */ 366 spcr->parity = 0; /* No Parity */ 367 spcr->stopbits = 1; /* 1 Stop bit */ 368 spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */ 369 spcr->term_type = 0; /* Terminal Type: 0 = VT100 */ 370 371 spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */ 372 spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */ 373 374 build_header(linker, table_data, (void *)(table_data->data + spcr_start), 375 "SPCR", table_data->len - spcr_start, 2, NULL, NULL); 376 } 377 378 static void 379 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 380 { 381 AcpiSystemResourceAffinityTable *srat; 382 AcpiSratProcessorGiccAffinity *core; 383 AcpiSratMemoryAffinity *numamem; 384 int i, srat_start; 385 uint64_t mem_base; 386 MachineClass *mc = MACHINE_GET_CLASS(vms); 387 MachineState *ms = MACHINE(vms); 388 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); 389 390 srat_start = table_data->len; 391 srat = acpi_data_push(table_data, sizeof(*srat)); 392 srat->reserved1 = cpu_to_le32(1); 393 394 for (i = 0; i < cpu_list->len; ++i) { 395 core = acpi_data_push(table_data, sizeof(*core)); 396 core->type = ACPI_SRAT_PROCESSOR_GICC; 397 core->length = sizeof(*core); 398 core->proximity = cpu_to_le32(cpu_list->cpus[i].props.node_id); 399 core->acpi_processor_uid = cpu_to_le32(i); 400 core->flags = cpu_to_le32(1); 401 } 402 403 mem_base = vms->memmap[VIRT_MEM].base; 404 for (i = 0; i < ms->numa_state->num_nodes; ++i) { 405 if (ms->numa_state->nodes[i].node_mem > 0) { 406 numamem = acpi_data_push(table_data, sizeof(*numamem)); 407 build_srat_memory(numamem, mem_base, 408 ms->numa_state->nodes[i].node_mem, i, 409 MEM_AFFINITY_ENABLED); 410 mem_base += ms->numa_state->nodes[i].node_mem; 411 } 412 } 413 414 if (ms->nvdimms_state->is_enabled) { 415 nvdimm_build_srat(table_data); 416 } 417 418 if (ms->device_memory) { 419 numamem = acpi_data_push(table_data, sizeof *numamem); 420 build_srat_memory(numamem, ms->device_memory->base, 421 memory_region_size(&ms->device_memory->mr), 422 ms->numa_state->num_nodes - 1, 423 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 424 } 425 426 build_header(linker, table_data, (void *)(table_data->data + srat_start), 427 "SRAT", table_data->len - srat_start, 3, NULL, NULL); 428 } 429 430 /* GTDT */ 431 static void 432 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 433 { 434 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 435 int gtdt_start = table_data->len; 436 AcpiGenericTimerTable *gtdt; 437 uint32_t irqflags; 438 439 if (vmc->claim_edge_triggered_timers) { 440 irqflags = ACPI_GTDT_INTERRUPT_MODE_EDGE; 441 } else { 442 irqflags = ACPI_GTDT_INTERRUPT_MODE_LEVEL; 443 } 444 445 gtdt = acpi_data_push(table_data, sizeof *gtdt); 446 /* The interrupt values are the same with the device tree when adding 16 */ 447 gtdt->secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_S_EL1_IRQ + 16); 448 gtdt->secure_el1_flags = cpu_to_le32(irqflags); 449 450 gtdt->non_secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ + 16); 451 gtdt->non_secure_el1_flags = cpu_to_le32(irqflags | 452 ACPI_GTDT_CAP_ALWAYS_ON); 453 454 gtdt->virtual_timer_interrupt = cpu_to_le32(ARCH_TIMER_VIRT_IRQ + 16); 455 gtdt->virtual_timer_flags = cpu_to_le32(irqflags); 456 457 gtdt->non_secure_el2_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ + 16); 458 gtdt->non_secure_el2_flags = cpu_to_le32(irqflags); 459 460 build_header(linker, table_data, 461 (void *)(table_data->data + gtdt_start), "GTDT", 462 table_data->len - gtdt_start, 2, NULL, NULL); 463 } 464 465 /* MADT */ 466 static void 467 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 468 { 469 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 470 int madt_start = table_data->len; 471 const MemMapEntry *memmap = vms->memmap; 472 const int *irqmap = vms->irqmap; 473 AcpiMadtGenericDistributor *gicd; 474 AcpiMadtGenericMsiFrame *gic_msi; 475 int i; 476 477 acpi_data_push(table_data, sizeof(AcpiMultipleApicTable)); 478 479 gicd = acpi_data_push(table_data, sizeof *gicd); 480 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR; 481 gicd->length = sizeof(*gicd); 482 gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base); 483 gicd->version = vms->gic_version; 484 485 for (i = 0; i < vms->smp_cpus; i++) { 486 AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data, 487 sizeof(*gicc)); 488 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 489 490 gicc->type = ACPI_APIC_GENERIC_CPU_INTERFACE; 491 gicc->length = sizeof(*gicc); 492 if (vms->gic_version == 2) { 493 gicc->base_address = cpu_to_le64(memmap[VIRT_GIC_CPU].base); 494 gicc->gich_base_address = cpu_to_le64(memmap[VIRT_GIC_HYP].base); 495 gicc->gicv_base_address = cpu_to_le64(memmap[VIRT_GIC_VCPU].base); 496 } 497 gicc->cpu_interface_number = cpu_to_le32(i); 498 gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity); 499 gicc->uid = cpu_to_le32(i); 500 gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED); 501 502 if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 503 gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ)); 504 } 505 if (vms->virt) { 506 gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ)); 507 } 508 } 509 510 if (vms->gic_version == 3) { 511 AcpiMadtGenericTranslator *gic_its; 512 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 513 AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data, 514 sizeof *gicr); 515 516 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 517 gicr->length = sizeof(*gicr); 518 gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base); 519 gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size); 520 521 if (nb_redist_regions == 2) { 522 gicr = acpi_data_push(table_data, sizeof(*gicr)); 523 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 524 gicr->length = sizeof(*gicr); 525 gicr->base_address = 526 cpu_to_le64(memmap[VIRT_HIGH_GIC_REDIST2].base); 527 gicr->range_length = 528 cpu_to_le32(memmap[VIRT_HIGH_GIC_REDIST2].size); 529 } 530 531 if (its_class_name() && !vmc->no_its) { 532 gic_its = acpi_data_push(table_data, sizeof *gic_its); 533 gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR; 534 gic_its->length = sizeof(*gic_its); 535 gic_its->translation_id = 0; 536 gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base); 537 } 538 } else { 539 gic_msi = acpi_data_push(table_data, sizeof *gic_msi); 540 gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME; 541 gic_msi->length = sizeof(*gic_msi); 542 gic_msi->gic_msi_frame_id = 0; 543 gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base); 544 gic_msi->flags = cpu_to_le32(1); 545 gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS); 546 gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE); 547 } 548 549 build_header(linker, table_data, 550 (void *)(table_data->data + madt_start), "APIC", 551 table_data->len - madt_start, 3, NULL, NULL); 552 } 553 554 /* FADT */ 555 static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker, 556 VirtMachineState *vms, unsigned dsdt_tbl_offset) 557 { 558 /* ACPI v5.1 */ 559 AcpiFadtData fadt = { 560 .rev = 5, 561 .minor_ver = 1, 562 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, 563 .xdsdt_tbl_offset = &dsdt_tbl_offset, 564 }; 565 566 switch (vms->psci_conduit) { 567 case QEMU_PSCI_CONDUIT_DISABLED: 568 fadt.arm_boot_arch = 0; 569 break; 570 case QEMU_PSCI_CONDUIT_HVC: 571 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT | 572 ACPI_FADT_ARM_PSCI_USE_HVC; 573 break; 574 case QEMU_PSCI_CONDUIT_SMC: 575 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT; 576 break; 577 default: 578 g_assert_not_reached(); 579 } 580 581 build_fadt(table_data, linker, &fadt, NULL, NULL); 582 } 583 584 /* DSDT */ 585 static void 586 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 587 { 588 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 589 Aml *scope, *dsdt; 590 MachineState *ms = MACHINE(vms); 591 const MemMapEntry *memmap = vms->memmap; 592 const int *irqmap = vms->irqmap; 593 594 dsdt = init_aml_allocator(); 595 /* Reserve space for header */ 596 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 597 598 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. 599 * While UEFI can use libfdt to disable the RTC device node in the DTB that 600 * it passes to the OS, it cannot modify AML. Therefore, we won't generate 601 * the RTC ACPI device at all when using UEFI. 602 */ 603 scope = aml_scope("\\_SB"); 604 acpi_dsdt_add_cpus(scope, vms->smp_cpus); 605 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], 606 (irqmap[VIRT_UART] + ARM_SPI_BASE)); 607 if (vmc->acpi_expose_flash) { 608 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); 609 } 610 acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); 611 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], 612 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); 613 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), 614 vms->highmem, vms->highmem_ecam, vms); 615 if (vms->acpi_dev) { 616 build_ged_aml(scope, "\\_SB."GED_DEVICE, 617 HOTPLUG_HANDLER(vms->acpi_dev), 618 irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY, 619 memmap[VIRT_ACPI_GED].base); 620 } else { 621 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], 622 (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); 623 } 624 625 if (vms->acpi_dev) { 626 uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev), 627 "ged-event", &error_abort); 628 629 if (event & ACPI_GED_MEM_HOTPLUG_EVT) { 630 build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL, 631 AML_SYSTEM_MEMORY, 632 memmap[VIRT_PCDIMM_ACPI].base); 633 } 634 } 635 636 acpi_dsdt_add_power_button(scope); 637 acpi_dsdt_add_tpm(scope, vms); 638 639 aml_append(dsdt, scope); 640 641 /* copy AML table into ACPI tables blob and patch header there */ 642 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 643 build_header(linker, table_data, 644 (void *)(table_data->data + table_data->len - dsdt->buf->len), 645 "DSDT", dsdt->buf->len, 2, NULL, NULL); 646 free_aml_allocator(); 647 } 648 649 typedef 650 struct AcpiBuildState { 651 /* Copy of table in RAM (for patching). */ 652 MemoryRegion *table_mr; 653 MemoryRegion *rsdp_mr; 654 MemoryRegion *linker_mr; 655 /* Is table patched? */ 656 bool patched; 657 } AcpiBuildState; 658 659 static 660 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) 661 { 662 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 663 GArray *table_offsets; 664 unsigned dsdt, xsdt; 665 GArray *tables_blob = tables->table_data; 666 MachineState *ms = MACHINE(vms); 667 668 table_offsets = g_array_new(false, true /* clear */, 669 sizeof(uint32_t)); 670 671 bios_linker_loader_alloc(tables->linker, 672 ACPI_BUILD_TABLE_FILE, tables_blob, 673 64, false /* high memory */); 674 675 /* DSDT is pointed to by FADT */ 676 dsdt = tables_blob->len; 677 build_dsdt(tables_blob, tables->linker, vms); 678 679 /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */ 680 acpi_add_table(table_offsets, tables_blob); 681 build_fadt_rev5(tables_blob, tables->linker, vms, dsdt); 682 683 acpi_add_table(table_offsets, tables_blob); 684 build_madt(tables_blob, tables->linker, vms); 685 686 acpi_add_table(table_offsets, tables_blob); 687 build_gtdt(tables_blob, tables->linker, vms); 688 689 acpi_add_table(table_offsets, tables_blob); 690 { 691 AcpiMcfgInfo mcfg = { 692 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, 693 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, 694 }; 695 build_mcfg(tables_blob, tables->linker, &mcfg); 696 } 697 698 acpi_add_table(table_offsets, tables_blob); 699 build_spcr(tables_blob, tables->linker, vms); 700 701 if (vms->ras) { 702 build_ghes_error_table(tables->hardware_errors, tables->linker); 703 acpi_add_table(table_offsets, tables_blob); 704 acpi_build_hest(tables_blob, tables->linker); 705 } 706 707 if (ms->numa_state->num_nodes > 0) { 708 acpi_add_table(table_offsets, tables_blob); 709 build_srat(tables_blob, tables->linker, vms); 710 if (ms->numa_state->have_numa_distance) { 711 acpi_add_table(table_offsets, tables_blob); 712 build_slit(tables_blob, tables->linker, ms); 713 } 714 } 715 716 if (ms->nvdimms_state->is_enabled) { 717 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 718 ms->nvdimms_state, ms->ram_slots); 719 } 720 721 if (its_class_name() && !vmc->no_its) { 722 acpi_add_table(table_offsets, tables_blob); 723 build_iort(tables_blob, tables->linker, vms); 724 } 725 726 if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) { 727 acpi_add_table(table_offsets, tables_blob); 728 build_tpm2(tables_blob, tables->linker, tables->tcpalog); 729 } 730 731 /* XSDT is pointed to by RSDP */ 732 xsdt = tables_blob->len; 733 build_xsdt(tables_blob, tables->linker, table_offsets, NULL, NULL); 734 735 /* RSDP is in FSEG memory, so allocate it separately */ 736 { 737 AcpiRsdpData rsdp_data = { 738 .revision = 2, 739 .oem_id = ACPI_BUILD_APPNAME6, 740 .xsdt_tbl_offset = &xsdt, 741 .rsdt_tbl_offset = NULL, 742 }; 743 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 744 } 745 746 /* Cleanup memory that's no longer used. */ 747 g_array_free(table_offsets, true); 748 } 749 750 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 751 { 752 uint32_t size = acpi_data_len(data); 753 754 /* Make sure RAM size is correct - in case it got changed 755 * e.g. by migration */ 756 memory_region_ram_resize(mr, size, &error_abort); 757 758 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 759 memory_region_set_dirty(mr, 0, size); 760 } 761 762 static void virt_acpi_build_update(void *build_opaque) 763 { 764 AcpiBuildState *build_state = build_opaque; 765 AcpiBuildTables tables; 766 767 /* No state to update or already patched? Nothing to do. */ 768 if (!build_state || build_state->patched) { 769 return; 770 } 771 build_state->patched = true; 772 773 acpi_build_tables_init(&tables); 774 775 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables); 776 777 acpi_ram_update(build_state->table_mr, tables.table_data); 778 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 779 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 780 781 acpi_build_tables_cleanup(&tables, true); 782 } 783 784 static void virt_acpi_build_reset(void *build_opaque) 785 { 786 AcpiBuildState *build_state = build_opaque; 787 build_state->patched = false; 788 } 789 790 static const VMStateDescription vmstate_virt_acpi_build = { 791 .name = "virt_acpi_build", 792 .version_id = 1, 793 .minimum_version_id = 1, 794 .fields = (VMStateField[]) { 795 VMSTATE_BOOL(patched, AcpiBuildState), 796 VMSTATE_END_OF_LIST() 797 }, 798 }; 799 800 void virt_acpi_setup(VirtMachineState *vms) 801 { 802 AcpiBuildTables tables; 803 AcpiBuildState *build_state; 804 AcpiGedState *acpi_ged_state; 805 806 if (!vms->fw_cfg) { 807 trace_virt_acpi_setup(); 808 return; 809 } 810 811 if (!virt_is_acpi_enabled(vms)) { 812 trace_virt_acpi_setup(); 813 return; 814 } 815 816 build_state = g_malloc0(sizeof *build_state); 817 818 acpi_build_tables_init(&tables); 819 virt_acpi_build(vms, &tables); 820 821 /* Now expose it all to Guest */ 822 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, 823 build_state, tables.table_data, 824 ACPI_BUILD_TABLE_FILE, 825 ACPI_BUILD_TABLE_MAX_SIZE); 826 assert(build_state->table_mr != NULL); 827 828 build_state->linker_mr = 829 acpi_add_rom_blob(virt_acpi_build_update, build_state, 830 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0); 831 832 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, 833 acpi_data_len(tables.tcpalog)); 834 835 if (vms->ras) { 836 assert(vms->acpi_dev); 837 acpi_ged_state = ACPI_GED(vms->acpi_dev); 838 acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state, 839 vms->fw_cfg, tables.hardware_errors); 840 } 841 842 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, 843 build_state, tables.rsdp, 844 ACPI_BUILD_RSDP_FILE, 0); 845 846 qemu_register_reset(virt_acpi_build_reset, build_state); 847 virt_acpi_build_reset(build_state); 848 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 849 850 /* Cleanup tables but don't free the memory: we track it 851 * in build_state. 852 */ 853 acpi_build_tables_cleanup(&tables, false); 854 } 855