1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * ARM virt ACPI generation 4 * 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 6 * Copyright (C) 2006 Fabrice Bellard 7 * Copyright (C) 2013 Red Hat Inc 8 * 9 * Author: Michael S. Tsirkin <mst@redhat.com> 10 * 11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 12 * 13 * Author: Shannon Zhao <zhaoshenglong@huawei.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "qapi/error.h" 31 #include "qemu/bitmap.h" 32 #include "qemu/error-report.h" 33 #include "trace.h" 34 #include "hw/core/cpu.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg_acpi.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/acpi/aml-build.h" 40 #include "hw/acpi/utils.h" 41 #include "hw/acpi/pci.h" 42 #include "hw/acpi/cxl.h" 43 #include "hw/acpi/memory_hotplug.h" 44 #include "hw/acpi/generic_event_device.h" 45 #include "hw/acpi/tpm.h" 46 #include "hw/acpi/hmat.h" 47 #include "hw/cxl/cxl.h" 48 #include "hw/pci/pcie_host.h" 49 #include "hw/pci/pci.h" 50 #include "hw/pci/pci_bus.h" 51 #include "hw/pci-host/gpex.h" 52 #include "hw/arm/virt.h" 53 #include "hw/intc/arm_gicv3_its_common.h" 54 #include "hw/mem/nvdimm.h" 55 #include "hw/platform-bus.h" 56 #include "system/numa.h" 57 #include "system/reset.h" 58 #include "system/tpm.h" 59 #include "migration/vmstate.h" 60 #include "hw/acpi/ghes.h" 61 #include "hw/acpi/viot.h" 62 #include "hw/virtio/virtio-acpi.h" 63 #include "target/arm/multiprocessing.h" 64 65 #define ARM_SPI_BASE 32 66 67 #define ACPI_BUILD_TABLE_SIZE 0x20000 68 69 static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms) 70 { 71 MachineState *ms = MACHINE(vms); 72 uint16_t i; 73 74 for (i = 0; i < ms->smp.cpus; i++) { 75 Aml *dev = aml_device("C%.03X", i); 76 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 77 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 78 aml_append(scope, dev); 79 } 80 } 81 82 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 83 uint32_t uart_irq, int uartidx) 84 { 85 Aml *dev = aml_device("COM%d", uartidx); 86 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); 87 aml_append(dev, aml_name_decl("_UID", aml_int(uartidx))); 88 89 Aml *crs = aml_resource_template(); 90 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 91 uart_memmap->size, AML_READ_WRITE)); 92 aml_append(crs, 93 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 94 AML_EXCLUSIVE, &uart_irq, 1)); 95 aml_append(dev, aml_name_decl("_CRS", crs)); 96 97 aml_append(scope, dev); 98 } 99 100 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) 101 { 102 Aml *dev, *crs; 103 hwaddr base = flash_memmap->base; 104 hwaddr size = flash_memmap->size / 2; 105 106 dev = aml_device("FLS0"); 107 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 108 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 109 110 crs = aml_resource_template(); 111 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 112 aml_append(dev, aml_name_decl("_CRS", crs)); 113 aml_append(scope, dev); 114 115 dev = aml_device("FLS1"); 116 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 117 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 118 crs = aml_resource_template(); 119 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); 120 aml_append(dev, aml_name_decl("_CRS", crs)); 121 aml_append(scope, dev); 122 } 123 124 static void build_acpi0017(Aml *table) 125 { 126 Aml *dev, *scope, *method; 127 128 scope = aml_scope("_SB"); 129 dev = aml_device("CXLM"); 130 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); 131 132 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 133 aml_append(method, aml_return(aml_int(0x0B))); 134 aml_append(dev, method); 135 build_cxl_dsm_method(dev); 136 137 aml_append(scope, dev); 138 aml_append(table, scope); 139 } 140 141 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, 142 uint32_t irq, VirtMachineState *vms) 143 { 144 int ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 145 bool cxl_present = false; 146 PCIBus *bus = vms->bus; 147 struct GPEXConfig cfg = { 148 .mmio32 = memmap[VIRT_PCIE_MMIO], 149 .pio = memmap[VIRT_PCIE_PIO], 150 .ecam = memmap[ecam_id], 151 .irq = irq, 152 .bus = vms->bus, 153 }; 154 155 if (vms->highmem_mmio) { 156 cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO]; 157 } 158 159 acpi_dsdt_add_gpex(scope, &cfg); 160 QLIST_FOREACH(bus, &vms->bus->child, sibling) { 161 if (pci_bus_is_cxl(bus)) { 162 cxl_present = true; 163 } 164 } 165 if (cxl_present) { 166 build_acpi0017(scope); 167 } 168 } 169 170 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, 171 uint32_t gpio_irq) 172 { 173 Aml *dev = aml_device("GPO0"); 174 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); 175 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 176 177 Aml *crs = aml_resource_template(); 178 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, 179 AML_READ_WRITE)); 180 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 181 AML_EXCLUSIVE, &gpio_irq, 1)); 182 aml_append(dev, aml_name_decl("_CRS", crs)); 183 184 Aml *aei = aml_resource_template(); 185 186 const uint32_t pin = GPIO_PIN_POWER_BUTTON; 187 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, 188 AML_EXCLUSIVE, AML_PULL_UP, 0, &pin, 1, 189 "GPO0", NULL, 0)); 190 aml_append(dev, aml_name_decl("_AEI", aei)); 191 192 /* _E03 is handle for power button */ 193 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); 194 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), 195 aml_int(0x80))); 196 aml_append(dev, method); 197 aml_append(scope, dev); 198 } 199 200 #ifdef CONFIG_TPM 201 static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms) 202 { 203 PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); 204 hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base; 205 SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find()); 206 MemoryRegion *sbdev_mr; 207 hwaddr tpm_base; 208 209 if (!sbdev) { 210 return; 211 } 212 213 tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); 214 assert(tpm_base != -1); 215 216 tpm_base += pbus_base; 217 218 sbdev_mr = sysbus_mmio_get_region(sbdev, 0); 219 220 Aml *dev = aml_device("TPM0"); 221 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 222 aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device"))); 223 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 224 225 Aml *crs = aml_resource_template(); 226 aml_append(crs, 227 aml_memory32_fixed(tpm_base, 228 (uint32_t)memory_region_size(sbdev_mr), 229 AML_READ_WRITE)); 230 aml_append(dev, aml_name_decl("_CRS", crs)); 231 aml_append(scope, dev); 232 } 233 #endif 234 235 #define ID_MAPPING_ENTRY_SIZE 20 236 #define SMMU_V3_ENTRY_SIZE 68 237 #define ROOT_COMPLEX_ENTRY_SIZE 36 238 #define IORT_NODE_OFFSET 48 239 240 /* 241 * Append an ID mapping entry as described by "Table 4 ID mapping format" in 242 * "IO Remapping Table System Software on ARM Platforms", Chapter 3. 243 * Document number: ARM DEN 0049E.f, Apr 2024 244 * 245 * Note that @id_count gets internally subtracted by one, following the spec. 246 */ 247 static void build_iort_id_mapping(GArray *table_data, uint32_t input_base, 248 uint32_t id_count, uint32_t out_ref) 249 { 250 build_append_int_noprefix(table_data, input_base, 4); /* Input base */ 251 /* Number of IDs - The number of IDs in the range minus one */ 252 build_append_int_noprefix(table_data, id_count - 1, 4); 253 build_append_int_noprefix(table_data, input_base, 4); /* Output base */ 254 build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference */ 255 /* Flags */ 256 build_append_int_noprefix(table_data, 0 /* Single mapping (disabled) */, 4); 257 } 258 259 struct AcpiIortIdMapping { 260 uint32_t input_base; 261 uint32_t id_count; 262 }; 263 typedef struct AcpiIortIdMapping AcpiIortIdMapping; 264 265 /* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */ 266 static int 267 iort_host_bridges(Object *obj, void *opaque) 268 { 269 GArray *idmap_blob = opaque; 270 271 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 272 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 273 274 if (bus && !pci_bus_bypass_iommu(bus)) { 275 int min_bus, max_bus; 276 277 pci_bus_range(bus, &min_bus, &max_bus); 278 279 AcpiIortIdMapping idmap = { 280 .input_base = min_bus << 8, 281 .id_count = (max_bus - min_bus + 1) << 8, 282 }; 283 g_array_append_val(idmap_blob, idmap); 284 } 285 } 286 287 return 0; 288 } 289 290 static int iort_idmap_compare(gconstpointer a, gconstpointer b) 291 { 292 AcpiIortIdMapping *idmap_a = (AcpiIortIdMapping *)a; 293 AcpiIortIdMapping *idmap_b = (AcpiIortIdMapping *)b; 294 295 return idmap_a->input_base - idmap_b->input_base; 296 } 297 298 /* Compute ID ranges (RIDs) from RC that are directed to the ITS Group node */ 299 static void create_rc_its_idmaps(GArray *its_idmaps, GArray *smmu_idmaps) 300 { 301 AcpiIortIdMapping *idmap; 302 AcpiIortIdMapping next_range = {0}; 303 304 /* 305 * Based on the RID ranges that are directed to the SMMU, determine the 306 * bypassed RID ranges, i.e., the ones that are directed to the ITS Group 307 * node and do not pass through the SMMU, by subtracting the SMMU-bound 308 * ranges from the full RID range (0x0000–0xFFFF). 309 */ 310 for (int i = 0; i < smmu_idmaps->len; i++) { 311 idmap = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); 312 313 if (next_range.input_base < idmap->input_base) { 314 next_range.id_count = idmap->input_base - next_range.input_base; 315 g_array_append_val(its_idmaps, next_range); 316 } 317 318 next_range.input_base = idmap->input_base + idmap->id_count; 319 } 320 321 /* 322 * Append the last RC -> ITS ID mapping. 323 * 324 * RIDs are 16-bit, according to the PCI Express 2.0 Base Specification, rev 325 * 0.9, section 2.2.6.2, "Transaction Descriptor - Transaction ID Field", 326 * hence the end of the range is 0x10000. 327 */ 328 if (next_range.input_base < 0x10000) { 329 next_range.id_count = 0x10000 - next_range.input_base; 330 g_array_append_val(its_idmaps, next_range); 331 } 332 } 333 334 335 /* 336 * Input Output Remapping Table (IORT) 337 * Conforms to "IO Remapping Table System Software on ARM Platforms", 338 * Document number: ARM DEN 0049E.b, Feb 2021 339 */ 340 static void 341 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 342 { 343 int i, nb_nodes, rc_mapping_count; 344 size_t node_size, smmu_offset = 0; 345 uint32_t id = 0; 346 GArray *rc_smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); 347 GArray *rc_its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); 348 349 AcpiTable table = { .sig = "IORT", .rev = 3, .oem_id = vms->oem_id, 350 .oem_table_id = vms->oem_table_id }; 351 /* Table 2 The IORT */ 352 acpi_table_begin(&table, table_data); 353 354 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 355 object_child_foreach_recursive(object_get_root(), 356 iort_host_bridges, rc_smmu_idmaps); 357 358 /* Sort the smmu idmap by input_base */ 359 g_array_sort(rc_smmu_idmaps, iort_idmap_compare); 360 361 /* 362 * Knowing the ID ranges from the RC to the SMMU, it's possible to 363 * determine the ID ranges from RC that are directed to the ITS. 364 */ 365 create_rc_its_idmaps(rc_its_idmaps, rc_smmu_idmaps); 366 367 nb_nodes = 2; /* RC and SMMUv3 */ 368 rc_mapping_count = rc_smmu_idmaps->len; 369 370 if (vms->its) { 371 /* 372 * Knowing the ID ranges from the RC to the SMMU, it's possible to 373 * determine the ID ranges from RC that go directly to ITS. 374 */ 375 create_rc_its_idmaps(rc_its_idmaps, rc_smmu_idmaps); 376 377 nb_nodes++; /* ITS */ 378 rc_mapping_count += rc_its_idmaps->len; 379 } 380 } else { 381 if (vms->its) { 382 nb_nodes = 2; /* RC and ITS */ 383 rc_mapping_count = 1; /* Direct map to ITS */ 384 } else { 385 nb_nodes = 1; /* RC only */ 386 rc_mapping_count = 0; /* No output mapping */ 387 } 388 } 389 /* Number of IORT Nodes */ 390 build_append_int_noprefix(table_data, nb_nodes, 4); 391 392 /* Offset to Array of IORT Nodes */ 393 build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4); 394 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 395 396 if (vms->its) { 397 /* Table 12 ITS Group Format */ 398 build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */ 399 node_size = 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */; 400 build_append_int_noprefix(table_data, node_size, 2); /* Length */ 401 build_append_int_noprefix(table_data, 1, 1); /* Revision */ 402 build_append_int_noprefix(table_data, id++, 4); /* Identifier */ 403 build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */ 404 build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */ 405 build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */ 406 /* GIC ITS Identifier Array */ 407 build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4); 408 } 409 410 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 411 int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; 412 int smmu_mapping_count, offset_to_id_array; 413 414 if (vms->its) { 415 smmu_mapping_count = 1; /* ITS Group node */ 416 offset_to_id_array = SMMU_V3_ENTRY_SIZE; /* Just after the header */ 417 } else { 418 smmu_mapping_count = 0; /* No ID mappings */ 419 offset_to_id_array = 0; /* No ID mappings array */ 420 } 421 smmu_offset = table_data->len - table.table_offset; 422 /* Table 9 SMMUv3 Format */ 423 build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type */ 424 node_size = SMMU_V3_ENTRY_SIZE + 425 (ID_MAPPING_ENTRY_SIZE * smmu_mapping_count); 426 build_append_int_noprefix(table_data, node_size, 2); /* Length */ 427 build_append_int_noprefix(table_data, 4, 1); /* Revision */ 428 build_append_int_noprefix(table_data, id++, 4); /* Identifier */ 429 /* Number of ID mappings */ 430 build_append_int_noprefix(table_data, smmu_mapping_count, 4); 431 /* Reference to ID Array */ 432 build_append_int_noprefix(table_data, offset_to_id_array, 4); 433 /* Base address */ 434 build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base, 8); 435 /* Flags */ 436 build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4); 437 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 438 build_append_int_noprefix(table_data, 0, 8); /* VATOS address */ 439 /* Model */ 440 build_append_int_noprefix(table_data, 0 /* Generic SMMU-v3 */, 4); 441 build_append_int_noprefix(table_data, irq, 4); /* Event */ 442 build_append_int_noprefix(table_data, irq + 1, 4); /* PRI */ 443 build_append_int_noprefix(table_data, irq + 3, 4); /* GERR */ 444 build_append_int_noprefix(table_data, irq + 2, 4); /* Sync */ 445 build_append_int_noprefix(table_data, 0, 4); /* Proximity domain */ 446 /* DeviceID mapping index (ignored since interrupts are GSIV based) */ 447 build_append_int_noprefix(table_data, 0, 4); 448 /* Array of ID mappings */ 449 if (smmu_mapping_count) { 450 /* Output IORT node is the ITS Group node (the first node). */ 451 build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET); 452 } 453 } 454 455 /* Table 17 Root Complex Node */ 456 build_append_int_noprefix(table_data, 2 /* Root complex */, 1); /* Type */ 457 node_size = ROOT_COMPLEX_ENTRY_SIZE + 458 ID_MAPPING_ENTRY_SIZE * rc_mapping_count; 459 build_append_int_noprefix(table_data, node_size, 2); /* Length */ 460 build_append_int_noprefix(table_data, 3, 1); /* Revision */ 461 build_append_int_noprefix(table_data, id++, 4); /* Identifier */ 462 /* Number of ID mappings */ 463 build_append_int_noprefix(table_data, rc_mapping_count, 4); 464 /* Reference to ID Array */ 465 build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 4); 466 467 /* Table 14 Memory access properties */ 468 /* CCA: Cache Coherent Attribute */ 469 build_append_int_noprefix(table_data, 1 /* fully coherent */, 4); 470 build_append_int_noprefix(table_data, 0, 1); /* AH: Note Allocation Hints */ 471 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 472 /* Table 15 Memory Access Flags */ 473 build_append_int_noprefix(table_data, 0x3 /* CCA = CPM = DACS = 1 */, 1); 474 475 build_append_int_noprefix(table_data, 0, 4); /* ATS Attribute */ 476 /* MCFG pci_segment */ 477 build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */ 478 479 /* Memory address size limit */ 480 build_append_int_noprefix(table_data, 64, 1); 481 482 build_append_int_noprefix(table_data, 0, 3); /* Reserved */ 483 484 /* Output Reference */ 485 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 486 AcpiIortIdMapping *range; 487 488 /* 489 * Map RIDs (input) from RC to SMMUv3 nodes: RC -> SMMUv3. 490 * 491 * N.B.: The mapping from SMMUv3 to ITS Group node (SMMUv3 -> ITS) is 492 * defined in the SMMUv3 table, where all SMMUv3 IDs are mapped to the 493 * ITS Group node, if ITS is available. 494 */ 495 for (i = 0; i < rc_smmu_idmaps->len; i++) { 496 range = &g_array_index(rc_smmu_idmaps, AcpiIortIdMapping, i); 497 /* Output IORT node is the SMMUv3 node. */ 498 build_iort_id_mapping(table_data, range->input_base, 499 range->id_count, smmu_offset); 500 } 501 502 if (vms->its) { 503 /* 504 * Map bypassed (don't go through the SMMU) RIDs (input) to 505 * ITS Group node directly: RC -> ITS. 506 */ 507 for (i = 0; i < rc_its_idmaps->len; i++) { 508 range = &g_array_index(rc_its_idmaps, AcpiIortIdMapping, i); 509 /* Output IORT node is the ITS Group node (the first node). */ 510 build_iort_id_mapping(table_data, range->input_base, 511 range->id_count, IORT_NODE_OFFSET); 512 } 513 } 514 } else { 515 /* 516 * Map all RIDs (input) to ITS Group node directly, since there is no 517 * SMMU: RC -> ITS. 518 * Output IORT node is the ITS Group node (the first node). 519 */ 520 build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET); 521 } 522 523 acpi_table_end(linker, &table); 524 g_array_free(rc_smmu_idmaps, true); 525 g_array_free(rc_its_idmaps, true); 526 } 527 528 /* 529 * Serial Port Console Redirection Table (SPCR) 530 * Rev: 1.07 531 */ 532 static void 533 spcr_setup(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 534 { 535 AcpiSpcrData serial = { 536 .interface_type = 3, /* ARM PL011 UART */ 537 .base_addr.id = AML_AS_SYSTEM_MEMORY, 538 .base_addr.width = 32, 539 .base_addr.offset = 0, 540 .base_addr.size = 3, 541 .base_addr.addr = vms->memmap[VIRT_UART0].base, 542 .interrupt_type = (1 << 3),/* Bit[3] ARMH GIC interrupt*/ 543 .pc_interrupt = 0, /* IRQ */ 544 .interrupt = (vms->irqmap[VIRT_UART0] + ARM_SPI_BASE), 545 .baud_rate = 3, /* 9600 */ 546 .parity = 0, /* No Parity */ 547 .stop_bits = 1, /* 1 Stop bit */ 548 .flow_control = 1 << 1, /* RTS/CTS hardware flow control */ 549 .terminal_type = 0, /* VT100 */ 550 .language = 0, /* Language */ 551 .pci_device_id = 0xffff, /* not a PCI device*/ 552 .pci_vendor_id = 0xffff, /* not a PCI device*/ 553 .pci_bus = 0, 554 .pci_device = 0, 555 .pci_function = 0, 556 .pci_flags = 0, 557 .pci_segment = 0, 558 }; 559 /* 560 * Passing NULL as the SPCR Table for Revision 2 doesn't support 561 * NameSpaceString. 562 */ 563 build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id, 564 NULL); 565 } 566 567 /* 568 * ACPI spec, Revision 5.1 569 * 5.2.16 System Resource Affinity Table (SRAT) 570 */ 571 static void 572 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 573 { 574 int i; 575 uint64_t mem_base; 576 MachineClass *mc = MACHINE_GET_CLASS(vms); 577 MachineState *ms = MACHINE(vms); 578 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); 579 AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id, 580 .oem_table_id = vms->oem_table_id }; 581 582 acpi_table_begin(&table, table_data); 583 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 584 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 585 586 for (i = 0; i < cpu_list->len; ++i) { 587 uint32_t nodeid = cpu_list->cpus[i].props.node_id; 588 /* 589 * 5.2.16.4 GICC Affinity Structure 590 */ 591 build_append_int_noprefix(table_data, 3, 1); /* Type */ 592 build_append_int_noprefix(table_data, 18, 1); /* Length */ 593 build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */ 594 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ 595 /* Flags, Table 5-76 */ 596 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 597 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 598 } 599 600 mem_base = vms->memmap[VIRT_MEM].base; 601 for (i = 0; i < ms->numa_state->num_nodes; ++i) { 602 if (ms->numa_state->nodes[i].node_mem > 0) { 603 build_srat_memory(table_data, mem_base, 604 ms->numa_state->nodes[i].node_mem, i, 605 MEM_AFFINITY_ENABLED); 606 mem_base += ms->numa_state->nodes[i].node_mem; 607 } 608 } 609 610 build_srat_generic_affinity_structures(table_data); 611 612 if (ms->nvdimms_state->is_enabled) { 613 nvdimm_build_srat(table_data); 614 } 615 616 if (ms->device_memory) { 617 build_srat_memory(table_data, ms->device_memory->base, 618 memory_region_size(&ms->device_memory->mr), 619 ms->numa_state->num_nodes - 1, 620 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 621 } 622 623 acpi_table_end(linker, &table); 624 } 625 626 /* 627 * ACPI spec, Revision 6.5 628 * 5.2.25 Generic Timer Description Table (GTDT) 629 */ 630 static void 631 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 632 { 633 /* 634 * Table 5-117 Flag Definitions 635 * set only "Timer interrupt Mode" and assume "Timer Interrupt 636 * polarity" bit as '0: Interrupt is Active high' 637 */ 638 const uint32_t irqflags = 0; /* Interrupt is Level triggered */ 639 AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id, 640 .oem_table_id = vms->oem_table_id }; 641 642 acpi_table_begin(&table, table_data); 643 644 /* CntControlBase Physical Address */ 645 build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8); 646 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 647 /* 648 * FIXME: clarify comment: 649 * The interrupt values are the same with the device tree when adding 16 650 */ 651 /* Secure EL1 timer GSIV */ 652 build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ, 4); 653 /* Secure EL1 timer Flags */ 654 build_append_int_noprefix(table_data, irqflags, 4); 655 /* Non-Secure EL1 timer GSIV */ 656 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ, 4); 657 /* Non-Secure EL1 timer Flags */ 658 build_append_int_noprefix(table_data, irqflags | 659 1UL << 2, /* Always-on Capability */ 660 4); 661 /* Virtual timer GSIV */ 662 build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ, 4); 663 /* Virtual Timer Flags */ 664 build_append_int_noprefix(table_data, irqflags, 4); 665 /* Non-Secure EL2 timer GSIV */ 666 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ, 4); 667 /* Non-Secure EL2 timer Flags */ 668 build_append_int_noprefix(table_data, irqflags, 4); 669 /* CntReadBase Physical address */ 670 build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8); 671 /* Platform Timer Count */ 672 build_append_int_noprefix(table_data, 0, 4); 673 /* Platform Timer Offset */ 674 build_append_int_noprefix(table_data, 0, 4); 675 if (vms->ns_el2_virt_timer_irq) { 676 /* Virtual EL2 Timer GSIV */ 677 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, 4); 678 /* Virtual EL2 Timer Flags */ 679 build_append_int_noprefix(table_data, irqflags, 4); 680 } else { 681 build_append_int_noprefix(table_data, 0, 4); 682 build_append_int_noprefix(table_data, 0, 4); 683 } 684 acpi_table_end(linker, &table); 685 } 686 687 /* Debug Port Table 2 (DBG2) */ 688 static void 689 build_dbg2(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 690 { 691 AcpiTable table = { .sig = "DBG2", .rev = 0, .oem_id = vms->oem_id, 692 .oem_table_id = vms->oem_table_id }; 693 int dbg2devicelength; 694 const char name[] = "COM0"; 695 const int namespace_length = sizeof(name); 696 697 acpi_table_begin(&table, table_data); 698 699 dbg2devicelength = 22 + /* BaseAddressRegister[] offset */ 700 12 + /* BaseAddressRegister[] */ 701 4 + /* AddressSize[] */ 702 namespace_length /* NamespaceString[] */; 703 704 /* OffsetDbgDeviceInfo */ 705 build_append_int_noprefix(table_data, 44, 4); 706 /* NumberDbgDeviceInfo */ 707 build_append_int_noprefix(table_data, 1, 4); 708 709 /* Table 2. Debug Device Information structure format */ 710 build_append_int_noprefix(table_data, 0, 1); /* Revision */ 711 build_append_int_noprefix(table_data, dbg2devicelength, 2); /* Length */ 712 /* NumberofGenericAddressRegisters */ 713 build_append_int_noprefix(table_data, 1, 1); 714 /* NameSpaceStringLength */ 715 build_append_int_noprefix(table_data, namespace_length, 2); 716 build_append_int_noprefix(table_data, 38, 2); /* NameSpaceStringOffset */ 717 build_append_int_noprefix(table_data, 0, 2); /* OemDataLength */ 718 /* OemDataOffset (0 means no OEM data) */ 719 build_append_int_noprefix(table_data, 0, 2); 720 721 /* Port Type */ 722 build_append_int_noprefix(table_data, 0x8000 /* Serial */, 2); 723 /* Port Subtype */ 724 build_append_int_noprefix(table_data, 0x3 /* ARM PL011 UART */, 2); 725 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 726 /* BaseAddressRegisterOffset */ 727 build_append_int_noprefix(table_data, 22, 2); 728 /* AddressSizeOffset */ 729 build_append_int_noprefix(table_data, 34, 2); 730 731 /* BaseAddressRegister[] */ 732 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3, 733 vms->memmap[VIRT_UART0].base); 734 735 /* AddressSize[] */ 736 build_append_int_noprefix(table_data, 737 vms->memmap[VIRT_UART0].size, 4); 738 739 /* NamespaceString[] */ 740 g_array_append_vals(table_data, name, namespace_length); 741 742 acpi_table_end(linker, &table); 743 }; 744 745 /* 746 * ACPI spec, Revision 6.0 Errata A 747 * 5.2.12 Multiple APIC Description Table (MADT) 748 */ 749 static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size) 750 { 751 build_append_int_noprefix(table_data, 0xE, 1); /* Type */ 752 build_append_int_noprefix(table_data, 16, 1); /* Length */ 753 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 754 /* Discovery Range Base Address */ 755 build_append_int_noprefix(table_data, base, 8); 756 build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */ 757 } 758 759 static void 760 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 761 { 762 int i; 763 const MemMapEntry *memmap = vms->memmap; 764 AcpiTable table = { .sig = "APIC", .rev = 4, .oem_id = vms->oem_id, 765 .oem_table_id = vms->oem_table_id }; 766 767 acpi_table_begin(&table, table_data); 768 /* Local Interrupt Controller Address */ 769 build_append_int_noprefix(table_data, 0, 4); 770 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 771 772 /* 5.2.12.15 GIC Distributor Structure */ 773 build_append_int_noprefix(table_data, 0xC, 1); /* Type */ 774 build_append_int_noprefix(table_data, 24, 1); /* Length */ 775 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 776 build_append_int_noprefix(table_data, 0, 4); /* GIC ID */ 777 /* Physical Base Address */ 778 build_append_int_noprefix(table_data, memmap[VIRT_GIC_DIST].base, 8); 779 build_append_int_noprefix(table_data, 0, 4); /* System Vector Base */ 780 /* GIC version */ 781 build_append_int_noprefix(table_data, vms->gic_version, 1); 782 build_append_int_noprefix(table_data, 0, 3); /* Reserved */ 783 784 for (i = 0; i < MACHINE(vms)->smp.cpus; i++) { 785 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 786 uint64_t physical_base_address = 0, gich = 0, gicv = 0; 787 uint32_t vgic_interrupt = vms->virt ? ARCH_GIC_MAINT_IRQ : 0; 788 uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ? 789 VIRTUAL_PMU_IRQ : 0; 790 791 if (vms->gic_version == VIRT_GIC_VERSION_2) { 792 physical_base_address = memmap[VIRT_GIC_CPU].base; 793 gicv = memmap[VIRT_GIC_VCPU].base; 794 gich = memmap[VIRT_GIC_HYP].base; 795 } 796 797 /* 5.2.12.14 GIC Structure */ 798 build_append_int_noprefix(table_data, 0xB, 1); /* Type */ 799 build_append_int_noprefix(table_data, 80, 1); /* Length */ 800 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 801 build_append_int_noprefix(table_data, i, 4); /* GIC ID */ 802 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ 803 /* Flags */ 804 build_append_int_noprefix(table_data, 1, 4); /* Enabled */ 805 /* Parking Protocol Version */ 806 build_append_int_noprefix(table_data, 0, 4); 807 /* Performance Interrupt GSIV */ 808 build_append_int_noprefix(table_data, pmu_interrupt, 4); 809 build_append_int_noprefix(table_data, 0, 8); /* Parked Address */ 810 /* Physical Base Address */ 811 build_append_int_noprefix(table_data, physical_base_address, 8); 812 build_append_int_noprefix(table_data, gicv, 8); /* GICV */ 813 build_append_int_noprefix(table_data, gich, 8); /* GICH */ 814 /* VGIC Maintenance interrupt */ 815 build_append_int_noprefix(table_data, vgic_interrupt, 4); 816 build_append_int_noprefix(table_data, 0, 8); /* GICR Base Address*/ 817 /* MPIDR */ 818 build_append_int_noprefix(table_data, arm_cpu_mp_affinity(armcpu), 8); 819 /* Processor Power Efficiency Class */ 820 build_append_int_noprefix(table_data, 0, 1); 821 /* Reserved */ 822 build_append_int_noprefix(table_data, 0, 3); 823 } 824 825 if (vms->gic_version != VIRT_GIC_VERSION_2) { 826 build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base, 827 memmap[VIRT_GIC_REDIST].size); 828 if (virt_gicv3_redist_region_count(vms) == 2) { 829 build_append_gicr(table_data, memmap[VIRT_HIGH_GIC_REDIST2].base, 830 memmap[VIRT_HIGH_GIC_REDIST2].size); 831 } 832 833 if (vms->its) { 834 /* 835 * ACPI spec, Revision 6.0 Errata A 836 * (original 6.0 definition has invalid Length) 837 * 5.2.12.18 GIC ITS Structure 838 */ 839 build_append_int_noprefix(table_data, 0xF, 1); /* Type */ 840 build_append_int_noprefix(table_data, 20, 1); /* Length */ 841 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 842 build_append_int_noprefix(table_data, 0, 4); /* GIC ITS ID */ 843 /* Physical Base Address */ 844 build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].base, 8); 845 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 846 } 847 } else { 848 const uint16_t spi_base = vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE; 849 850 /* 5.2.12.16 GIC MSI Frame Structure */ 851 build_append_int_noprefix(table_data, 0xD, 1); /* Type */ 852 build_append_int_noprefix(table_data, 24, 1); /* Length */ 853 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 854 build_append_int_noprefix(table_data, 0, 4); /* GIC MSI Frame ID */ 855 /* Physical Base Address */ 856 build_append_int_noprefix(table_data, memmap[VIRT_GIC_V2M].base, 8); 857 build_append_int_noprefix(table_data, 1, 4); /* Flags */ 858 /* SPI Count */ 859 build_append_int_noprefix(table_data, NUM_GICV2M_SPIS, 2); 860 build_append_int_noprefix(table_data, spi_base, 2); /* SPI Base */ 861 } 862 acpi_table_end(linker, &table); 863 } 864 865 /* FADT */ 866 static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker, 867 VirtMachineState *vms, unsigned dsdt_tbl_offset) 868 { 869 /* ACPI v6.3 */ 870 AcpiFadtData fadt = { 871 .rev = 6, 872 .minor_ver = 3, 873 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, 874 .xdsdt_tbl_offset = &dsdt_tbl_offset, 875 }; 876 877 switch (vms->psci_conduit) { 878 case QEMU_PSCI_CONDUIT_DISABLED: 879 fadt.arm_boot_arch = 0; 880 break; 881 case QEMU_PSCI_CONDUIT_HVC: 882 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT | 883 ACPI_FADT_ARM_PSCI_USE_HVC; 884 break; 885 case QEMU_PSCI_CONDUIT_SMC: 886 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT; 887 break; 888 default: 889 g_assert_not_reached(); 890 } 891 892 build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id); 893 } 894 895 /* DSDT */ 896 static void 897 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 898 { 899 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 900 Aml *scope, *dsdt; 901 MachineState *ms = MACHINE(vms); 902 const MemMapEntry *memmap = vms->memmap; 903 const int *irqmap = vms->irqmap; 904 AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = vms->oem_id, 905 .oem_table_id = vms->oem_table_id }; 906 907 acpi_table_begin(&table, table_data); 908 dsdt = init_aml_allocator(); 909 910 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. 911 * While UEFI can use libfdt to disable the RTC device node in the DTB that 912 * it passes to the OS, it cannot modify AML. Therefore, we won't generate 913 * the RTC ACPI device at all when using UEFI. 914 */ 915 scope = aml_scope("\\_SB"); 916 acpi_dsdt_add_cpus(scope, vms); 917 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], 918 (irqmap[VIRT_UART0] + ARM_SPI_BASE), 0); 919 if (vms->second_ns_uart_present) { 920 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART1], 921 (irqmap[VIRT_UART1] + ARM_SPI_BASE), 1); 922 } 923 if (vmc->acpi_expose_flash) { 924 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); 925 } 926 fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]); 927 virtio_acpi_dsdt_add(scope, memmap[VIRT_MMIO].base, memmap[VIRT_MMIO].size, 928 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), 929 0, NUM_VIRTIO_TRANSPORTS); 930 acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms); 931 if (vms->acpi_dev) { 932 build_ged_aml(scope, "\\_SB."GED_DEVICE, 933 HOTPLUG_HANDLER(vms->acpi_dev), 934 irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY, 935 memmap[VIRT_ACPI_GED].base); 936 } else { 937 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], 938 (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); 939 } 940 941 if (vms->acpi_dev) { 942 uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev), 943 "ged-event", &error_abort); 944 945 if (event & ACPI_GED_MEM_HOTPLUG_EVT) { 946 build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL, 947 AML_SYSTEM_MEMORY, 948 memmap[VIRT_PCDIMM_ACPI].base); 949 } 950 } 951 952 acpi_dsdt_add_power_button(scope); 953 #ifdef CONFIG_TPM 954 acpi_dsdt_add_tpm(scope, vms); 955 #endif 956 957 aml_append(dsdt, scope); 958 959 /* copy AML table into ACPI tables blob */ 960 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 961 962 acpi_table_end(linker, &table); 963 free_aml_allocator(); 964 } 965 966 typedef 967 struct AcpiBuildState { 968 /* Copy of table in RAM (for patching). */ 969 MemoryRegion *table_mr; 970 MemoryRegion *rsdp_mr; 971 MemoryRegion *linker_mr; 972 /* Is table patched? */ 973 bool patched; 974 } AcpiBuildState; 975 976 static void acpi_align_size(GArray *blob, unsigned align) 977 { 978 /* 979 * Align size to multiple of given size. This reduces the chance 980 * we need to change size in the future (breaking cross version migration). 981 */ 982 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 983 } 984 985 static 986 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) 987 { 988 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 989 GArray *table_offsets; 990 unsigned dsdt, xsdt; 991 GArray *tables_blob = tables->table_data; 992 MachineState *ms = MACHINE(vms); 993 994 table_offsets = g_array_new(false, true /* clear */, 995 sizeof(uint32_t)); 996 997 bios_linker_loader_alloc(tables->linker, 998 ACPI_BUILD_TABLE_FILE, tables_blob, 999 64, false /* high memory */); 1000 1001 /* DSDT is pointed to by FADT */ 1002 dsdt = tables_blob->len; 1003 build_dsdt(tables_blob, tables->linker, vms); 1004 1005 /* FADT MADT PPTT GTDT MCFG SPCR DBG2 pointed to by RSDT */ 1006 acpi_add_table(table_offsets, tables_blob); 1007 build_fadt_rev6(tables_blob, tables->linker, vms, dsdt); 1008 1009 acpi_add_table(table_offsets, tables_blob); 1010 build_madt(tables_blob, tables->linker, vms); 1011 1012 if (!vmc->no_cpu_topology) { 1013 acpi_add_table(table_offsets, tables_blob); 1014 build_pptt(tables_blob, tables->linker, ms, 1015 vms->oem_id, vms->oem_table_id); 1016 } 1017 1018 acpi_add_table(table_offsets, tables_blob); 1019 build_gtdt(tables_blob, tables->linker, vms); 1020 1021 acpi_add_table(table_offsets, tables_blob); 1022 { 1023 AcpiMcfgInfo mcfg = { 1024 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, 1025 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, 1026 }; 1027 build_mcfg(tables_blob, tables->linker, &mcfg, vms->oem_id, 1028 vms->oem_table_id); 1029 } 1030 1031 acpi_add_table(table_offsets, tables_blob); 1032 spcr_setup(tables_blob, tables->linker, vms); 1033 1034 acpi_add_table(table_offsets, tables_blob); 1035 build_dbg2(tables_blob, tables->linker, vms); 1036 1037 if (vms->ras) { 1038 acpi_add_table(table_offsets, tables_blob); 1039 acpi_build_hest(tables_blob, tables->hardware_errors, tables->linker, 1040 vms->oem_id, vms->oem_table_id); 1041 } 1042 1043 if (ms->numa_state->num_nodes > 0) { 1044 acpi_add_table(table_offsets, tables_blob); 1045 build_srat(tables_blob, tables->linker, vms); 1046 if (ms->numa_state->have_numa_distance) { 1047 acpi_add_table(table_offsets, tables_blob); 1048 build_slit(tables_blob, tables->linker, ms, vms->oem_id, 1049 vms->oem_table_id); 1050 } 1051 1052 if (ms->numa_state->hmat_enabled) { 1053 acpi_add_table(table_offsets, tables_blob); 1054 build_hmat(tables_blob, tables->linker, ms->numa_state, 1055 vms->oem_id, vms->oem_table_id); 1056 } 1057 } 1058 1059 if (vms->cxl_devices_state.is_enabled) { 1060 cxl_build_cedt(table_offsets, tables_blob, tables->linker, 1061 vms->oem_id, vms->oem_table_id, &vms->cxl_devices_state); 1062 } 1063 1064 if (ms->nvdimms_state->is_enabled) { 1065 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 1066 ms->nvdimms_state, ms->ram_slots, vms->oem_id, 1067 vms->oem_table_id); 1068 } 1069 1070 acpi_add_table(table_offsets, tables_blob); 1071 build_iort(tables_blob, tables->linker, vms); 1072 1073 #ifdef CONFIG_TPM 1074 if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) { 1075 acpi_add_table(table_offsets, tables_blob); 1076 build_tpm2(tables_blob, tables->linker, tables->tcpalog, vms->oem_id, 1077 vms->oem_table_id); 1078 } 1079 #endif 1080 1081 if (vms->iommu == VIRT_IOMMU_VIRTIO) { 1082 acpi_add_table(table_offsets, tables_blob); 1083 build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf, 1084 vms->oem_id, vms->oem_table_id); 1085 } 1086 1087 /* XSDT is pointed to by RSDP */ 1088 xsdt = tables_blob->len; 1089 build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id, 1090 vms->oem_table_id); 1091 1092 /* RSDP is in FSEG memory, so allocate it separately */ 1093 { 1094 AcpiRsdpData rsdp_data = { 1095 .revision = 2, 1096 .oem_id = vms->oem_id, 1097 .xsdt_tbl_offset = &xsdt, 1098 .rsdt_tbl_offset = NULL, 1099 }; 1100 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 1101 } 1102 1103 /* 1104 * The align size is 128, warn if 64k is not enough therefore 1105 * the align size could be resized. 1106 */ 1107 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 1108 warn_report("ACPI table size %u exceeds %d bytes," 1109 " migration may not work", 1110 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 1111 error_printf("Try removing CPUs, NUMA nodes, memory slots" 1112 " or PCI bridges.\n"); 1113 } 1114 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 1115 1116 1117 /* Cleanup memory that's no longer used. */ 1118 g_array_free(table_offsets, true); 1119 } 1120 1121 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 1122 { 1123 uint32_t size = acpi_data_len(data); 1124 1125 /* Make sure RAM size is correct - in case it got changed 1126 * e.g. by migration */ 1127 memory_region_ram_resize(mr, size, &error_abort); 1128 1129 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 1130 memory_region_set_dirty(mr, 0, size); 1131 } 1132 1133 static void virt_acpi_build_update(void *build_opaque) 1134 { 1135 AcpiBuildState *build_state = build_opaque; 1136 AcpiBuildTables tables; 1137 1138 /* No state to update or already patched? Nothing to do. */ 1139 if (!build_state || build_state->patched) { 1140 return; 1141 } 1142 build_state->patched = true; 1143 1144 acpi_build_tables_init(&tables); 1145 1146 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables); 1147 1148 acpi_ram_update(build_state->table_mr, tables.table_data); 1149 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 1150 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 1151 1152 acpi_build_tables_cleanup(&tables, true); 1153 } 1154 1155 static void virt_acpi_build_reset(void *build_opaque) 1156 { 1157 AcpiBuildState *build_state = build_opaque; 1158 build_state->patched = false; 1159 } 1160 1161 static const VMStateDescription vmstate_virt_acpi_build = { 1162 .name = "virt_acpi_build", 1163 .version_id = 1, 1164 .minimum_version_id = 1, 1165 .fields = (const VMStateField[]) { 1166 VMSTATE_BOOL(patched, AcpiBuildState), 1167 VMSTATE_END_OF_LIST() 1168 }, 1169 }; 1170 1171 void virt_acpi_setup(VirtMachineState *vms) 1172 { 1173 AcpiBuildTables tables; 1174 AcpiBuildState *build_state; 1175 AcpiGedState *acpi_ged_state; 1176 1177 if (!vms->fw_cfg) { 1178 trace_virt_acpi_setup(); 1179 return; 1180 } 1181 1182 if (!virt_is_acpi_enabled(vms)) { 1183 trace_virt_acpi_setup(); 1184 return; 1185 } 1186 1187 build_state = g_malloc0(sizeof *build_state); 1188 1189 acpi_build_tables_init(&tables); 1190 virt_acpi_build(vms, &tables); 1191 1192 /* Now expose it all to Guest */ 1193 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, 1194 build_state, tables.table_data, 1195 ACPI_BUILD_TABLE_FILE); 1196 assert(build_state->table_mr != NULL); 1197 1198 build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update, 1199 build_state, 1200 tables.linker->cmd_blob, 1201 ACPI_BUILD_LOADER_FILE); 1202 1203 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, 1204 acpi_data_len(tables.tcpalog)); 1205 1206 if (vms->ras) { 1207 assert(vms->acpi_dev); 1208 acpi_ged_state = ACPI_GED(vms->acpi_dev); 1209 acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state, 1210 vms->fw_cfg, tables.hardware_errors); 1211 } 1212 1213 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, 1214 build_state, tables.rsdp, 1215 ACPI_BUILD_RSDP_FILE); 1216 1217 qemu_register_reset(virt_acpi_build_reset, build_state); 1218 virt_acpi_build_reset(build_state); 1219 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 1220 1221 /* Cleanup tables but don't free the memory: we track it 1222 * in build_state. 1223 */ 1224 acpi_build_tables_cleanup(&tables, false); 1225 } 1226