xref: /openbmc/qemu/hw/arm/virt-acpi-build.c (revision 64552b6b)
1 /* Support for generating ACPI tables and passing them to Guests
2  *
3  * ARM virt ACPI generation
4  *
5  * Copyright (C) 2008-2010  Kevin O'Connor <kevin@koconnor.net>
6  * Copyright (C) 2006 Fabrice Bellard
7  * Copyright (C) 2013 Red Hat Inc
8  *
9  * Author: Michael S. Tsirkin <mst@redhat.com>
10  *
11  * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
12  *
13  * Author: Shannon Zhao <zhaoshenglong@huawei.com>
14  *
15  * This program is free software; you can redistribute it and/or modify
16  * it under the terms of the GNU General Public License as published by
17  * the Free Software Foundation; either version 2 of the License, or
18  * (at your option) any later version.
19 
20  * This program is distributed in the hope that it will be useful,
21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23  * GNU General Public License for more details.
24 
25  * You should have received a copy of the GNU General Public License along
26  * with this program; if not, see <http://www.gnu.org/licenses/>.
27  */
28 
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "qemu/bitmap.h"
32 #include "trace.h"
33 #include "qom/cpu.h"
34 #include "target/arm/cpu.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/hw.h"
40 #include "hw/acpi/aml-build.h"
41 #include "hw/acpi/utils.h"
42 #include "hw/acpi/pci.h"
43 #include "hw/pci/pcie_host.h"
44 #include "hw/pci/pci.h"
45 #include "hw/arm/virt.h"
46 #include "sysemu/numa.h"
47 #include "sysemu/reset.h"
48 #include "kvm_arm.h"
49 
50 #define ARM_SPI_BASE 32
51 #define ACPI_POWER_BUTTON_DEVICE "PWRB"
52 
53 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
54 {
55     uint16_t i;
56 
57     for (i = 0; i < smp_cpus; i++) {
58         Aml *dev = aml_device("C%.03X", i);
59         aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
60         aml_append(dev, aml_name_decl("_UID", aml_int(i)));
61         aml_append(scope, dev);
62     }
63 }
64 
65 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
66                                            uint32_t uart_irq)
67 {
68     Aml *dev = aml_device("COM0");
69     aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
70     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
71 
72     Aml *crs = aml_resource_template();
73     aml_append(crs, aml_memory32_fixed(uart_memmap->base,
74                                        uart_memmap->size, AML_READ_WRITE));
75     aml_append(crs,
76                aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
77                              AML_EXCLUSIVE, &uart_irq, 1));
78     aml_append(dev, aml_name_decl("_CRS", crs));
79 
80     /* The _ADR entry is used to link this device to the UART described
81      * in the SPCR table, i.e. SPCR.base_address.address == _ADR.
82      */
83     aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base)));
84 
85     aml_append(scope, dev);
86 }
87 
88 static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
89 {
90     Aml *dev = aml_device("FWCF");
91     aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
92     /* device present, functioning, decoding, not shown in UI */
93     aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
94     aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
95 
96     Aml *crs = aml_resource_template();
97     aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
98                                        fw_cfg_memmap->size, AML_READ_WRITE));
99     aml_append(dev, aml_name_decl("_CRS", crs));
100     aml_append(scope, dev);
101 }
102 
103 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
104 {
105     Aml *dev, *crs;
106     hwaddr base = flash_memmap->base;
107     hwaddr size = flash_memmap->size / 2;
108 
109     dev = aml_device("FLS0");
110     aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
111     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
112 
113     crs = aml_resource_template();
114     aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
115     aml_append(dev, aml_name_decl("_CRS", crs));
116     aml_append(scope, dev);
117 
118     dev = aml_device("FLS1");
119     aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
120     aml_append(dev, aml_name_decl("_UID", aml_int(1)));
121     crs = aml_resource_template();
122     aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE));
123     aml_append(dev, aml_name_decl("_CRS", crs));
124     aml_append(scope, dev);
125 }
126 
127 static void acpi_dsdt_add_virtio(Aml *scope,
128                                  const MemMapEntry *virtio_mmio_memmap,
129                                  uint32_t mmio_irq, int num)
130 {
131     hwaddr base = virtio_mmio_memmap->base;
132     hwaddr size = virtio_mmio_memmap->size;
133     int i;
134 
135     for (i = 0; i < num; i++) {
136         uint32_t irq = mmio_irq + i;
137         Aml *dev = aml_device("VR%02u", i);
138         aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
139         aml_append(dev, aml_name_decl("_UID", aml_int(i)));
140         aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
141 
142         Aml *crs = aml_resource_template();
143         aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
144         aml_append(crs,
145                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
146                                  AML_EXCLUSIVE, &irq, 1));
147         aml_append(dev, aml_name_decl("_CRS", crs));
148         aml_append(scope, dev);
149         base += size;
150     }
151 }
152 
153 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
154                               uint32_t irq, bool use_highmem, bool highmem_ecam)
155 {
156     int ecam_id = VIRT_ECAM_ID(highmem_ecam);
157     Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
158     int i, bus_no;
159     hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
160     hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
161     hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
162     hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
163     hwaddr base_ecam = memmap[ecam_id].base;
164     hwaddr size_ecam = memmap[ecam_id].size;
165     int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
166 
167     Aml *dev = aml_device("%s", "PCI0");
168     aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
169     aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
170     aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
171     aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
172     aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
173     aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
174     aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
175     aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
176 
177     /* Declare the PCI Routing Table. */
178     Aml *rt_pkg = aml_varpackage(nr_pcie_buses * PCI_NUM_PINS);
179     for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) {
180         for (i = 0; i < PCI_NUM_PINS; i++) {
181             int gsi = (i + bus_no) % PCI_NUM_PINS;
182             Aml *pkg = aml_package(4);
183             aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF));
184             aml_append(pkg, aml_int(i));
185             aml_append(pkg, aml_name("GSI%d", gsi));
186             aml_append(pkg, aml_int(0));
187             aml_append(rt_pkg, pkg);
188         }
189     }
190     aml_append(dev, aml_name_decl("_PRT", rt_pkg));
191 
192     /* Create GSI link device */
193     for (i = 0; i < PCI_NUM_PINS; i++) {
194         uint32_t irqs =  irq + i;
195         Aml *dev_gsi = aml_device("GSI%d", i);
196         aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
197         aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
198         crs = aml_resource_template();
199         aml_append(crs,
200                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
201                                  AML_EXCLUSIVE, &irqs, 1));
202         aml_append(dev_gsi, aml_name_decl("_PRS", crs));
203         crs = aml_resource_template();
204         aml_append(crs,
205                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
206                                  AML_EXCLUSIVE, &irqs, 1));
207         aml_append(dev_gsi, aml_name_decl("_CRS", crs));
208         method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
209         aml_append(dev_gsi, method);
210         aml_append(dev, dev_gsi);
211     }
212 
213     method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
214     aml_append(method, aml_return(aml_int(base_ecam)));
215     aml_append(dev, method);
216 
217     method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
218     Aml *rbuf = aml_resource_template();
219     aml_append(rbuf,
220         aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
221                             0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
222                             nr_pcie_buses));
223     aml_append(rbuf,
224         aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
225                          AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio,
226                          base_mmio + size_mmio - 1, 0x0000, size_mmio));
227     aml_append(rbuf,
228         aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
229                      AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
230                      size_pio));
231 
232     if (use_highmem) {
233         hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base;
234         hwaddr size_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].size;
235 
236         aml_append(rbuf,
237             aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
238                              AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
239                              base_mmio_high,
240                              base_mmio_high + size_mmio_high - 1, 0x0000,
241                              size_mmio_high));
242     }
243 
244     aml_append(method, aml_name_decl("RBUF", rbuf));
245     aml_append(method, aml_return(rbuf));
246     aml_append(dev, method);
247 
248     /* Declare an _OSC (OS Control Handoff) method */
249     aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
250     aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
251     method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
252     aml_append(method,
253         aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
254 
255     /* PCI Firmware Specification 3.0
256      * 4.5.1. _OSC Interface for PCI Host Bridge Devices
257      * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
258      * identified by the Universal Unique IDentifier (UUID)
259      * 33DB4D5B-1FF7-401C-9657-7441C03DD766
260      */
261     UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
262     ifctx = aml_if(aml_equal(aml_arg(0), UUID));
263     aml_append(ifctx,
264         aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
265     aml_append(ifctx,
266         aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
267     aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
268     aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
269     aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL),
270                                 aml_name("CTRL")));
271 
272     ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
273     aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08), NULL),
274                                  aml_name("CDW1")));
275     aml_append(ifctx, ifctx1);
276 
277     ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
278     aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10), NULL),
279                                  aml_name("CDW1")));
280     aml_append(ifctx, ifctx1);
281 
282     aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
283     aml_append(ifctx, aml_return(aml_arg(3)));
284     aml_append(method, ifctx);
285 
286     elsectx = aml_else();
287     aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4), NULL),
288                                   aml_name("CDW1")));
289     aml_append(elsectx, aml_return(aml_arg(3)));
290     aml_append(method, elsectx);
291     aml_append(dev, method);
292 
293     method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
294 
295     /* PCI Firmware Specification 3.0
296      * 4.6.1. _DSM for PCI Express Slot Information
297      * The UUID in _DSM in this context is
298      * {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
299      */
300     UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
301     ifctx = aml_if(aml_equal(aml_arg(0), UUID));
302     ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
303     uint8_t byte_list[1] = {1};
304     buf = aml_buffer(1, byte_list);
305     aml_append(ifctx1, aml_return(buf));
306     aml_append(ifctx, ifctx1);
307     aml_append(method, ifctx);
308 
309     byte_list[0] = 0;
310     buf = aml_buffer(1, byte_list);
311     aml_append(method, aml_return(buf));
312     aml_append(dev, method);
313 
314     Aml *dev_rp0 = aml_device("%s", "RP0");
315     aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
316     aml_append(dev, dev_rp0);
317 
318     Aml *dev_res0 = aml_device("%s", "RES0");
319     aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02")));
320     crs = aml_resource_template();
321     aml_append(crs,
322         aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
323                          AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_ecam,
324                          base_ecam + size_ecam - 1, 0x0000, size_ecam));
325     aml_append(dev_res0, aml_name_decl("_CRS", crs));
326     aml_append(dev, dev_res0);
327     aml_append(scope, dev);
328 }
329 
330 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
331                                            uint32_t gpio_irq)
332 {
333     Aml *dev = aml_device("GPO0");
334     aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061")));
335     aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
336     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
337 
338     Aml *crs = aml_resource_template();
339     aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size,
340                                        AML_READ_WRITE));
341     aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
342                                   AML_EXCLUSIVE, &gpio_irq, 1));
343     aml_append(dev, aml_name_decl("_CRS", crs));
344 
345     Aml *aei = aml_resource_template();
346     /* Pin 3 for power button */
347     const uint32_t pin_list[1] = {3};
348     aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH,
349                                  AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1,
350                                  "GPO0", NULL, 0));
351     aml_append(dev, aml_name_decl("_AEI", aei));
352 
353     /* _E03 is handle for power button */
354     Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED);
355     aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE),
356                                   aml_int(0x80)));
357     aml_append(dev, method);
358     aml_append(scope, dev);
359 }
360 
361 static void acpi_dsdt_add_power_button(Aml *scope)
362 {
363     Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE);
364     aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C")));
365     aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
366     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
367     aml_append(scope, dev);
368 }
369 
370 static void
371 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
372 {
373     int nb_nodes, iort_start = table_data->len;
374     AcpiIortIdMapping *idmap;
375     AcpiIortItsGroup *its;
376     AcpiIortTable *iort;
377     AcpiIortSmmu3 *smmu;
378     size_t node_size, iort_node_offset, iort_length, smmu_offset = 0;
379     AcpiIortRC *rc;
380 
381     iort = acpi_data_push(table_data, sizeof(*iort));
382 
383     if (vms->iommu == VIRT_IOMMU_SMMUV3) {
384         nb_nodes = 3; /* RC, ITS, SMMUv3 */
385     } else {
386         nb_nodes = 2; /* RC, ITS */
387     }
388 
389     iort_length = sizeof(*iort);
390     iort->node_count = cpu_to_le32(nb_nodes);
391     /*
392      * Use a copy in case table_data->data moves during acpi_data_push
393      * operations.
394      */
395     iort_node_offset = sizeof(*iort);
396     iort->node_offset = cpu_to_le32(iort_node_offset);
397 
398     /* ITS group node */
399     node_size =  sizeof(*its) + sizeof(uint32_t);
400     iort_length += node_size;
401     its = acpi_data_push(table_data, node_size);
402 
403     its->type = ACPI_IORT_NODE_ITS_GROUP;
404     its->length = cpu_to_le16(node_size);
405     its->its_count = cpu_to_le32(1);
406     its->identifiers[0] = 0; /* MADT translation_id */
407 
408     if (vms->iommu == VIRT_IOMMU_SMMUV3) {
409         int irq =  vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE;
410 
411         /* SMMUv3 node */
412         smmu_offset = iort_node_offset + node_size;
413         node_size = sizeof(*smmu) + sizeof(*idmap);
414         iort_length += node_size;
415         smmu = acpi_data_push(table_data, node_size);
416 
417         smmu->type = ACPI_IORT_NODE_SMMU_V3;
418         smmu->length = cpu_to_le16(node_size);
419         smmu->mapping_count = cpu_to_le32(1);
420         smmu->mapping_offset = cpu_to_le32(sizeof(*smmu));
421         smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base);
422         smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE);
423         smmu->event_gsiv = cpu_to_le32(irq);
424         smmu->pri_gsiv = cpu_to_le32(irq + 1);
425         smmu->gerr_gsiv = cpu_to_le32(irq + 2);
426         smmu->sync_gsiv = cpu_to_le32(irq + 3);
427 
428         /* Identity RID mapping covering the whole input RID range */
429         idmap = &smmu->id_mapping_array[0];
430         idmap->input_base = 0;
431         idmap->id_count = cpu_to_le32(0xFFFF);
432         idmap->output_base = 0;
433         /* output IORT node is the ITS group node (the first node) */
434         idmap->output_reference = cpu_to_le32(iort_node_offset);
435     }
436 
437     /* Root Complex Node */
438     node_size = sizeof(*rc) + sizeof(*idmap);
439     iort_length += node_size;
440     rc = acpi_data_push(table_data, node_size);
441 
442     rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX;
443     rc->length = cpu_to_le16(node_size);
444     rc->mapping_count = cpu_to_le32(1);
445     rc->mapping_offset = cpu_to_le32(sizeof(*rc));
446 
447     /* fully coherent device */
448     rc->memory_properties.cache_coherency = cpu_to_le32(1);
449     rc->memory_properties.memory_flags = 0x3; /* CCA = CPM = DCAS = 1 */
450     rc->pci_segment_number = 0; /* MCFG pci_segment */
451 
452     /* Identity RID mapping covering the whole input RID range */
453     idmap = &rc->id_mapping_array[0];
454     idmap->input_base = 0;
455     idmap->id_count = cpu_to_le32(0xFFFF);
456     idmap->output_base = 0;
457 
458     if (vms->iommu == VIRT_IOMMU_SMMUV3) {
459         /* output IORT node is the smmuv3 node */
460         idmap->output_reference = cpu_to_le32(smmu_offset);
461     } else {
462         /* output IORT node is the ITS group node (the first node) */
463         idmap->output_reference = cpu_to_le32(iort_node_offset);
464     }
465 
466     /*
467      * Update the pointer address in case table_data->data moves during above
468      * acpi_data_push operations.
469      */
470     iort = (AcpiIortTable *)(table_data->data + iort_start);
471     iort->length = cpu_to_le32(iort_length);
472 
473     build_header(linker, table_data, (void *)(table_data->data + iort_start),
474                  "IORT", table_data->len - iort_start, 0, NULL, NULL);
475 }
476 
477 static void
478 build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
479 {
480     AcpiSerialPortConsoleRedirection *spcr;
481     const MemMapEntry *uart_memmap = &vms->memmap[VIRT_UART];
482     int irq = vms->irqmap[VIRT_UART] + ARM_SPI_BASE;
483     int spcr_start = table_data->len;
484 
485     spcr = acpi_data_push(table_data, sizeof(*spcr));
486 
487     spcr->interface_type = 0x3;    /* ARM PL011 UART */
488 
489     spcr->base_address.space_id = AML_SYSTEM_MEMORY;
490     spcr->base_address.bit_width = 8;
491     spcr->base_address.bit_offset = 0;
492     spcr->base_address.access_width = 1;
493     spcr->base_address.address = cpu_to_le64(uart_memmap->base);
494 
495     spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */
496     spcr->gsi = cpu_to_le32(irq);  /* Global System Interrupt */
497 
498     spcr->baud = 3;                /* Baud Rate: 3 = 9600 */
499     spcr->parity = 0;              /* No Parity */
500     spcr->stopbits = 1;            /* 1 Stop bit */
501     spcr->flowctrl = (1 << 1);     /* Bit[1] = RTS/CTS hardware flow control */
502     spcr->term_type = 0;           /* Terminal Type: 0 = VT100 */
503 
504     spcr->pci_device_id = 0xffff;  /* PCI Device ID: not a PCI device */
505     spcr->pci_vendor_id = 0xffff;  /* PCI Vendor ID: not a PCI device */
506 
507     build_header(linker, table_data, (void *)(table_data->data + spcr_start),
508                  "SPCR", table_data->len - spcr_start, 2, NULL, NULL);
509 }
510 
511 static void
512 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
513 {
514     AcpiSystemResourceAffinityTable *srat;
515     AcpiSratProcessorGiccAffinity *core;
516     AcpiSratMemoryAffinity *numamem;
517     int i, srat_start;
518     uint64_t mem_base;
519     MachineClass *mc = MACHINE_GET_CLASS(vms);
520     const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(MACHINE(vms));
521 
522     srat_start = table_data->len;
523     srat = acpi_data_push(table_data, sizeof(*srat));
524     srat->reserved1 = cpu_to_le32(1);
525 
526     for (i = 0; i < cpu_list->len; ++i) {
527         core = acpi_data_push(table_data, sizeof(*core));
528         core->type = ACPI_SRAT_PROCESSOR_GICC;
529         core->length = sizeof(*core);
530         core->proximity = cpu_to_le32(cpu_list->cpus[i].props.node_id);
531         core->acpi_processor_uid = cpu_to_le32(i);
532         core->flags = cpu_to_le32(1);
533     }
534 
535     mem_base = vms->memmap[VIRT_MEM].base;
536     for (i = 0; i < nb_numa_nodes; ++i) {
537         if (numa_info[i].node_mem > 0) {
538             numamem = acpi_data_push(table_data, sizeof(*numamem));
539             build_srat_memory(numamem, mem_base, numa_info[i].node_mem, i,
540                               MEM_AFFINITY_ENABLED);
541             mem_base += numa_info[i].node_mem;
542         }
543     }
544 
545     build_header(linker, table_data, (void *)(table_data->data + srat_start),
546                  "SRAT", table_data->len - srat_start, 3, NULL, NULL);
547 }
548 
549 /* GTDT */
550 static void
551 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
552 {
553     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
554     int gtdt_start = table_data->len;
555     AcpiGenericTimerTable *gtdt;
556     uint32_t irqflags;
557 
558     if (vmc->claim_edge_triggered_timers) {
559         irqflags = ACPI_GTDT_INTERRUPT_MODE_EDGE;
560     } else {
561         irqflags = ACPI_GTDT_INTERRUPT_MODE_LEVEL;
562     }
563 
564     gtdt = acpi_data_push(table_data, sizeof *gtdt);
565     /* The interrupt values are the same with the device tree when adding 16 */
566     gtdt->secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_S_EL1_IRQ + 16);
567     gtdt->secure_el1_flags = cpu_to_le32(irqflags);
568 
569     gtdt->non_secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ + 16);
570     gtdt->non_secure_el1_flags = cpu_to_le32(irqflags |
571                                              ACPI_GTDT_CAP_ALWAYS_ON);
572 
573     gtdt->virtual_timer_interrupt = cpu_to_le32(ARCH_TIMER_VIRT_IRQ + 16);
574     gtdt->virtual_timer_flags = cpu_to_le32(irqflags);
575 
576     gtdt->non_secure_el2_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ + 16);
577     gtdt->non_secure_el2_flags = cpu_to_le32(irqflags);
578 
579     build_header(linker, table_data,
580                  (void *)(table_data->data + gtdt_start), "GTDT",
581                  table_data->len - gtdt_start, 2, NULL, NULL);
582 }
583 
584 /* MADT */
585 static void
586 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
587 {
588     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
589     int madt_start = table_data->len;
590     const MemMapEntry *memmap = vms->memmap;
591     const int *irqmap = vms->irqmap;
592     AcpiMultipleApicTable *madt;
593     AcpiMadtGenericDistributor *gicd;
594     AcpiMadtGenericMsiFrame *gic_msi;
595     int i;
596 
597     madt = acpi_data_push(table_data, sizeof *madt);
598 
599     gicd = acpi_data_push(table_data, sizeof *gicd);
600     gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
601     gicd->length = sizeof(*gicd);
602     gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base);
603     gicd->version = vms->gic_version;
604 
605     for (i = 0; i < vms->smp_cpus; i++) {
606         AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data,
607                                                            sizeof(*gicc));
608         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
609 
610         gicc->type = ACPI_APIC_GENERIC_CPU_INTERFACE;
611         gicc->length = sizeof(*gicc);
612         if (vms->gic_version == 2) {
613             gicc->base_address = cpu_to_le64(memmap[VIRT_GIC_CPU].base);
614             gicc->gich_base_address = cpu_to_le64(memmap[VIRT_GIC_HYP].base);
615             gicc->gicv_base_address = cpu_to_le64(memmap[VIRT_GIC_VCPU].base);
616         }
617         gicc->cpu_interface_number = cpu_to_le32(i);
618         gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity);
619         gicc->uid = cpu_to_le32(i);
620         gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED);
621 
622         if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
623             gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ));
624         }
625         if (vms->virt) {
626             gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ));
627         }
628     }
629 
630     if (vms->gic_version == 3) {
631         AcpiMadtGenericTranslator *gic_its;
632         int nb_redist_regions = virt_gicv3_redist_region_count(vms);
633         AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,
634                                                          sizeof *gicr);
635 
636         gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
637         gicr->length = sizeof(*gicr);
638         gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);
639         gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);
640 
641         if (nb_redist_regions == 2) {
642             gicr = acpi_data_push(table_data, sizeof(*gicr));
643             gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
644             gicr->length = sizeof(*gicr);
645             gicr->base_address =
646                 cpu_to_le64(memmap[VIRT_HIGH_GIC_REDIST2].base);
647             gicr->range_length =
648                 cpu_to_le32(memmap[VIRT_HIGH_GIC_REDIST2].size);
649         }
650 
651         if (its_class_name() && !vmc->no_its) {
652             gic_its = acpi_data_push(table_data, sizeof *gic_its);
653             gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR;
654             gic_its->length = sizeof(*gic_its);
655             gic_its->translation_id = 0;
656             gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base);
657         }
658     } else {
659         gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
660         gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
661         gic_msi->length = sizeof(*gic_msi);
662         gic_msi->gic_msi_frame_id = 0;
663         gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base);
664         gic_msi->flags = cpu_to_le32(1);
665         gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS);
666         gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE);
667     }
668 
669     build_header(linker, table_data,
670                  (void *)(table_data->data + madt_start), "APIC",
671                  table_data->len - madt_start, 3, NULL, NULL);
672 }
673 
674 /* FADT */
675 static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker,
676                             VirtMachineState *vms, unsigned dsdt_tbl_offset)
677 {
678     /* ACPI v5.1 */
679     AcpiFadtData fadt = {
680         .rev = 5,
681         .minor_ver = 1,
682         .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
683         .xdsdt_tbl_offset = &dsdt_tbl_offset,
684     };
685 
686     switch (vms->psci_conduit) {
687     case QEMU_PSCI_CONDUIT_DISABLED:
688         fadt.arm_boot_arch = 0;
689         break;
690     case QEMU_PSCI_CONDUIT_HVC:
691         fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT |
692                              ACPI_FADT_ARM_PSCI_USE_HVC;
693         break;
694     case QEMU_PSCI_CONDUIT_SMC:
695         fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT;
696         break;
697     default:
698         g_assert_not_reached();
699     }
700 
701     build_fadt(table_data, linker, &fadt, NULL, NULL);
702 }
703 
704 /* DSDT */
705 static void
706 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
707 {
708     Aml *scope, *dsdt;
709     const MemMapEntry *memmap = vms->memmap;
710     const int *irqmap = vms->irqmap;
711 
712     dsdt = init_aml_allocator();
713     /* Reserve space for header */
714     acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
715 
716     /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware.
717      * While UEFI can use libfdt to disable the RTC device node in the DTB that
718      * it passes to the OS, it cannot modify AML. Therefore, we won't generate
719      * the RTC ACPI device at all when using UEFI.
720      */
721     scope = aml_scope("\\_SB");
722     acpi_dsdt_add_cpus(scope, vms->smp_cpus);
723     acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
724                        (irqmap[VIRT_UART] + ARM_SPI_BASE));
725     acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
726     acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
727     acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
728                     (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
729     acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE),
730                       vms->highmem, vms->highmem_ecam);
731     acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO],
732                        (irqmap[VIRT_GPIO] + ARM_SPI_BASE));
733     acpi_dsdt_add_power_button(scope);
734 
735     aml_append(dsdt, scope);
736 
737     /* copy AML table into ACPI tables blob and patch header there */
738     g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
739     build_header(linker, table_data,
740         (void *)(table_data->data + table_data->len - dsdt->buf->len),
741         "DSDT", dsdt->buf->len, 2, NULL, NULL);
742     free_aml_allocator();
743 }
744 
745 typedef
746 struct AcpiBuildState {
747     /* Copy of table in RAM (for patching). */
748     MemoryRegion *table_mr;
749     MemoryRegion *rsdp_mr;
750     MemoryRegion *linker_mr;
751     /* Is table patched? */
752     bool patched;
753 } AcpiBuildState;
754 
755 static
756 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
757 {
758     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
759     GArray *table_offsets;
760     unsigned dsdt, xsdt;
761     GArray *tables_blob = tables->table_data;
762 
763     table_offsets = g_array_new(false, true /* clear */,
764                                         sizeof(uint32_t));
765 
766     bios_linker_loader_alloc(tables->linker,
767                              ACPI_BUILD_TABLE_FILE, tables_blob,
768                              64, false /* high memory */);
769 
770     /* DSDT is pointed to by FADT */
771     dsdt = tables_blob->len;
772     build_dsdt(tables_blob, tables->linker, vms);
773 
774     /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */
775     acpi_add_table(table_offsets, tables_blob);
776     build_fadt_rev5(tables_blob, tables->linker, vms, dsdt);
777 
778     acpi_add_table(table_offsets, tables_blob);
779     build_madt(tables_blob, tables->linker, vms);
780 
781     acpi_add_table(table_offsets, tables_blob);
782     build_gtdt(tables_blob, tables->linker, vms);
783 
784     acpi_add_table(table_offsets, tables_blob);
785     {
786         AcpiMcfgInfo mcfg = {
787            .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base,
788            .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size,
789         };
790         build_mcfg(tables_blob, tables->linker, &mcfg);
791     }
792 
793     acpi_add_table(table_offsets, tables_blob);
794     build_spcr(tables_blob, tables->linker, vms);
795 
796     if (nb_numa_nodes > 0) {
797         acpi_add_table(table_offsets, tables_blob);
798         build_srat(tables_blob, tables->linker, vms);
799         if (have_numa_distance) {
800             acpi_add_table(table_offsets, tables_blob);
801             build_slit(tables_blob, tables->linker);
802         }
803     }
804 
805     if (its_class_name() && !vmc->no_its) {
806         acpi_add_table(table_offsets, tables_blob);
807         build_iort(tables_blob, tables->linker, vms);
808     }
809 
810     /* XSDT is pointed to by RSDP */
811     xsdt = tables_blob->len;
812     build_xsdt(tables_blob, tables->linker, table_offsets, NULL, NULL);
813 
814     /* RSDP is in FSEG memory, so allocate it separately */
815     {
816         AcpiRsdpData rsdp_data = {
817             .revision = 2,
818             .oem_id = ACPI_BUILD_APPNAME6,
819             .xsdt_tbl_offset = &xsdt,
820             .rsdt_tbl_offset = NULL,
821         };
822         build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
823     }
824 
825     /* Cleanup memory that's no longer used. */
826     g_array_free(table_offsets, true);
827 }
828 
829 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
830 {
831     uint32_t size = acpi_data_len(data);
832 
833     /* Make sure RAM size is correct - in case it got changed
834      * e.g. by migration */
835     memory_region_ram_resize(mr, size, &error_abort);
836 
837     memcpy(memory_region_get_ram_ptr(mr), data->data, size);
838     memory_region_set_dirty(mr, 0, size);
839 }
840 
841 static void virt_acpi_build_update(void *build_opaque)
842 {
843     AcpiBuildState *build_state = build_opaque;
844     AcpiBuildTables tables;
845 
846     /* No state to update or already patched? Nothing to do. */
847     if (!build_state || build_state->patched) {
848         return;
849     }
850     build_state->patched = true;
851 
852     acpi_build_tables_init(&tables);
853 
854     virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables);
855 
856     acpi_ram_update(build_state->table_mr, tables.table_data);
857     acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
858     acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
859 
860     acpi_build_tables_cleanup(&tables, true);
861 }
862 
863 static void virt_acpi_build_reset(void *build_opaque)
864 {
865     AcpiBuildState *build_state = build_opaque;
866     build_state->patched = false;
867 }
868 
869 static const VMStateDescription vmstate_virt_acpi_build = {
870     .name = "virt_acpi_build",
871     .version_id = 1,
872     .minimum_version_id = 1,
873     .fields = (VMStateField[]) {
874         VMSTATE_BOOL(patched, AcpiBuildState),
875         VMSTATE_END_OF_LIST()
876     },
877 };
878 
879 void virt_acpi_setup(VirtMachineState *vms)
880 {
881     AcpiBuildTables tables;
882     AcpiBuildState *build_state;
883 
884     if (!vms->fw_cfg) {
885         trace_virt_acpi_setup();
886         return;
887     }
888 
889     if (!acpi_enabled) {
890         trace_virt_acpi_setup();
891         return;
892     }
893 
894     build_state = g_malloc0(sizeof *build_state);
895 
896     acpi_build_tables_init(&tables);
897     virt_acpi_build(vms, &tables);
898 
899     /* Now expose it all to Guest */
900     build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update,
901                                               build_state, tables.table_data,
902                                               ACPI_BUILD_TABLE_FILE,
903                                               ACPI_BUILD_TABLE_MAX_SIZE);
904     assert(build_state->table_mr != NULL);
905 
906     build_state->linker_mr =
907         acpi_add_rom_blob(virt_acpi_build_update, build_state,
908                           tables.linker->cmd_blob, "etc/table-loader", 0);
909 
910     fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
911                     acpi_data_len(tables.tcpalog));
912 
913     build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update,
914                                              build_state, tables.rsdp,
915                                              ACPI_BUILD_RSDP_FILE, 0);
916 
917     qemu_register_reset(virt_acpi_build_reset, build_state);
918     virt_acpi_build_reset(build_state);
919     vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
920 
921     /* Cleanup tables but don't free the memory: we track it
922      * in build_state.
923      */
924     acpi_build_tables_cleanup(&tables, false);
925 }
926