1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * ARM virt ACPI generation 4 * 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 6 * Copyright (C) 2006 Fabrice Bellard 7 * Copyright (C) 2013 Red Hat Inc 8 * 9 * Author: Michael S. Tsirkin <mst@redhat.com> 10 * 11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 12 * 13 * Author: Shannon Zhao <zhaoshenglong@huawei.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "qapi/error.h" 31 #include "qemu/bitmap.h" 32 #include "qemu/error-report.h" 33 #include "trace.h" 34 #include "hw/core/cpu.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg_acpi.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/acpi/aml-build.h" 40 #include "hw/acpi/utils.h" 41 #include "hw/acpi/pci.h" 42 #include "hw/acpi/cxl.h" 43 #include "hw/acpi/memory_hotplug.h" 44 #include "hw/acpi/generic_event_device.h" 45 #include "hw/acpi/tpm.h" 46 #include "hw/acpi/hmat.h" 47 #include "hw/cxl/cxl.h" 48 #include "hw/pci/pcie_host.h" 49 #include "hw/pci/pci.h" 50 #include "hw/pci/pci_bus.h" 51 #include "hw/pci-host/gpex.h" 52 #include "hw/arm/virt.h" 53 #include "hw/intc/arm_gicv3_its_common.h" 54 #include "hw/mem/nvdimm.h" 55 #include "hw/platform-bus.h" 56 #include "system/numa.h" 57 #include "system/reset.h" 58 #include "system/tpm.h" 59 #include "migration/vmstate.h" 60 #include "hw/acpi/ghes.h" 61 #include "hw/acpi/viot.h" 62 #include "hw/virtio/virtio-acpi.h" 63 #include "target/arm/multiprocessing.h" 64 65 #define ARM_SPI_BASE 32 66 67 #define ACPI_BUILD_TABLE_SIZE 0x20000 68 69 static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms) 70 { 71 MachineState *ms = MACHINE(vms); 72 uint16_t i; 73 74 for (i = 0; i < ms->smp.cpus; i++) { 75 Aml *dev = aml_device("C%.03X", i); 76 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 77 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 78 aml_append(scope, dev); 79 } 80 } 81 82 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 83 uint32_t uart_irq, int uartidx) 84 { 85 Aml *dev = aml_device("COM%d", uartidx); 86 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); 87 aml_append(dev, aml_name_decl("_UID", aml_int(uartidx))); 88 89 Aml *crs = aml_resource_template(); 90 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 91 uart_memmap->size, AML_READ_WRITE)); 92 aml_append(crs, 93 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 94 AML_EXCLUSIVE, &uart_irq, 1)); 95 aml_append(dev, aml_name_decl("_CRS", crs)); 96 97 aml_append(scope, dev); 98 } 99 100 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) 101 { 102 Aml *dev, *crs; 103 hwaddr base = flash_memmap->base; 104 hwaddr size = flash_memmap->size / 2; 105 106 dev = aml_device("FLS0"); 107 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 108 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 109 110 crs = aml_resource_template(); 111 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 112 aml_append(dev, aml_name_decl("_CRS", crs)); 113 aml_append(scope, dev); 114 115 dev = aml_device("FLS1"); 116 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 117 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 118 crs = aml_resource_template(); 119 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); 120 aml_append(dev, aml_name_decl("_CRS", crs)); 121 aml_append(scope, dev); 122 } 123 124 static void build_acpi0017(Aml *table) 125 { 126 Aml *dev, *scope, *method; 127 128 scope = aml_scope("_SB"); 129 dev = aml_device("CXLM"); 130 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); 131 132 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 133 aml_append(method, aml_return(aml_int(0x0B))); 134 aml_append(dev, method); 135 build_cxl_dsm_method(dev); 136 137 aml_append(scope, dev); 138 aml_append(table, scope); 139 } 140 141 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, 142 uint32_t irq, VirtMachineState *vms) 143 { 144 int ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 145 bool cxl_present = false; 146 PCIBus *bus = vms->bus; 147 struct GPEXConfig cfg = { 148 .mmio32 = memmap[VIRT_PCIE_MMIO], 149 .pio = memmap[VIRT_PCIE_PIO], 150 .ecam = memmap[ecam_id], 151 .irq = irq, 152 .bus = vms->bus, 153 }; 154 155 if (vms->highmem_mmio) { 156 cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO]; 157 } 158 159 acpi_dsdt_add_gpex(scope, &cfg); 160 QLIST_FOREACH(bus, &vms->bus->child, sibling) { 161 if (pci_bus_is_cxl(bus)) { 162 cxl_present = true; 163 } 164 } 165 if (cxl_present) { 166 build_acpi0017(scope); 167 } 168 } 169 170 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, 171 uint32_t gpio_irq) 172 { 173 Aml *dev = aml_device("GPO0"); 174 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); 175 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 176 177 Aml *crs = aml_resource_template(); 178 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, 179 AML_READ_WRITE)); 180 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 181 AML_EXCLUSIVE, &gpio_irq, 1)); 182 aml_append(dev, aml_name_decl("_CRS", crs)); 183 184 Aml *aei = aml_resource_template(); 185 186 const uint32_t pin = GPIO_PIN_POWER_BUTTON; 187 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, 188 AML_EXCLUSIVE, AML_PULL_UP, 0, &pin, 1, 189 "GPO0", NULL, 0)); 190 aml_append(dev, aml_name_decl("_AEI", aei)); 191 192 /* _E03 is handle for power button */ 193 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); 194 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), 195 aml_int(0x80))); 196 aml_append(dev, method); 197 aml_append(scope, dev); 198 } 199 200 #ifdef CONFIG_TPM 201 static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms) 202 { 203 PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); 204 hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base; 205 SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find()); 206 MemoryRegion *sbdev_mr; 207 hwaddr tpm_base; 208 209 if (!sbdev) { 210 return; 211 } 212 213 tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); 214 assert(tpm_base != -1); 215 216 tpm_base += pbus_base; 217 218 sbdev_mr = sysbus_mmio_get_region(sbdev, 0); 219 220 Aml *dev = aml_device("TPM0"); 221 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 222 aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device"))); 223 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 224 225 Aml *crs = aml_resource_template(); 226 aml_append(crs, 227 aml_memory32_fixed(tpm_base, 228 (uint32_t)memory_region_size(sbdev_mr), 229 AML_READ_WRITE)); 230 aml_append(dev, aml_name_decl("_CRS", crs)); 231 aml_append(scope, dev); 232 } 233 #endif 234 235 #define ID_MAPPING_ENTRY_SIZE 20 236 #define SMMU_V3_ENTRY_SIZE 68 237 #define ROOT_COMPLEX_ENTRY_SIZE 36 238 #define IORT_NODE_OFFSET 48 239 240 /* 241 * Append an ID mapping entry as described by "Table 4 ID mapping format" in 242 * "IO Remapping Table System Software on ARM Platforms", Chapter 3. 243 * Document number: ARM DEN 0049E.f, Apr 2024 244 * 245 * Note that @id_count gets internally subtracted by one, following the spec. 246 */ 247 static void build_iort_id_mapping(GArray *table_data, uint32_t input_base, 248 uint32_t id_count, uint32_t out_ref) 249 { 250 build_append_int_noprefix(table_data, input_base, 4); /* Input base */ 251 /* Number of IDs - The number of IDs in the range minus one */ 252 build_append_int_noprefix(table_data, id_count - 1, 4); 253 build_append_int_noprefix(table_data, input_base, 4); /* Output base */ 254 build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference */ 255 /* Flags */ 256 build_append_int_noprefix(table_data, 0 /* Single mapping (disabled) */, 4); 257 } 258 259 struct AcpiIortIdMapping { 260 uint32_t input_base; 261 uint32_t id_count; 262 }; 263 typedef struct AcpiIortIdMapping AcpiIortIdMapping; 264 265 /* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */ 266 static int 267 iort_host_bridges(Object *obj, void *opaque) 268 { 269 GArray *idmap_blob = opaque; 270 271 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 272 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 273 274 if (bus && !pci_bus_bypass_iommu(bus)) { 275 int min_bus, max_bus; 276 277 pci_bus_range(bus, &min_bus, &max_bus); 278 279 AcpiIortIdMapping idmap = { 280 .input_base = min_bus << 8, 281 .id_count = (max_bus - min_bus + 1) << 8, 282 }; 283 g_array_append_val(idmap_blob, idmap); 284 } 285 } 286 287 return 0; 288 } 289 290 static int iort_idmap_compare(gconstpointer a, gconstpointer b) 291 { 292 AcpiIortIdMapping *idmap_a = (AcpiIortIdMapping *)a; 293 AcpiIortIdMapping *idmap_b = (AcpiIortIdMapping *)b; 294 295 return idmap_a->input_base - idmap_b->input_base; 296 } 297 298 /* Compute ID ranges (RIDs) from RC that are directed to the ITS Group node */ 299 static void create_rc_its_idmaps(GArray *its_idmaps, GArray *smmu_idmaps) 300 { 301 AcpiIortIdMapping *idmap; 302 AcpiIortIdMapping next_range = {0}; 303 304 /* 305 * Based on the RID ranges that are directed to the SMMU, determine the 306 * bypassed RID ranges, i.e., the ones that are directed to the ITS Group 307 * node and do not pass through the SMMU, by subtracting the SMMU-bound 308 * ranges from the full RID range (0x0000–0xFFFF). 309 */ 310 for (int i = 0; i < smmu_idmaps->len; i++) { 311 idmap = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); 312 313 if (next_range.input_base < idmap->input_base) { 314 next_range.id_count = idmap->input_base - next_range.input_base; 315 g_array_append_val(its_idmaps, next_range); 316 } 317 318 next_range.input_base = idmap->input_base + idmap->id_count; 319 } 320 321 /* 322 * Append the last RC -> ITS ID mapping. 323 * 324 * RIDs are 16-bit, according to the PCI Express 2.0 Base Specification, rev 325 * 0.9, section 2.2.6.2, "Transaction Descriptor - Transaction ID Field", 326 * hence the end of the range is 0x10000. 327 */ 328 if (next_range.input_base < 0x10000) { 329 next_range.id_count = 0x10000 - next_range.input_base; 330 g_array_append_val(its_idmaps, next_range); 331 } 332 } 333 334 335 /* 336 * Input Output Remapping Table (IORT) 337 * Conforms to "IO Remapping Table System Software on ARM Platforms", 338 * Document number: ARM DEN 0049E.b, Feb 2021 339 */ 340 static void 341 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 342 { 343 int i, nb_nodes, rc_mapping_count; 344 size_t node_size, smmu_offset = 0; 345 uint32_t id = 0; 346 GArray *rc_smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); 347 GArray *rc_its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); 348 349 AcpiTable table = { .sig = "IORT", .rev = 3, .oem_id = vms->oem_id, 350 .oem_table_id = vms->oem_table_id }; 351 /* Table 2 The IORT */ 352 acpi_table_begin(&table, table_data); 353 354 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 355 object_child_foreach_recursive(object_get_root(), 356 iort_host_bridges, rc_smmu_idmaps); 357 358 /* Sort the smmu idmap by input_base */ 359 g_array_sort(rc_smmu_idmaps, iort_idmap_compare); 360 361 nb_nodes = 2; /* RC and SMMUv3 */ 362 rc_mapping_count = rc_smmu_idmaps->len; 363 364 if (vms->its) { 365 /* 366 * Knowing the ID ranges from the RC to the SMMU, it's possible to 367 * determine the ID ranges from RC that go directly to ITS. 368 */ 369 create_rc_its_idmaps(rc_its_idmaps, rc_smmu_idmaps); 370 371 nb_nodes++; /* ITS */ 372 rc_mapping_count += rc_its_idmaps->len; 373 } 374 } else { 375 if (vms->its) { 376 nb_nodes = 2; /* RC and ITS */ 377 rc_mapping_count = 1; /* Direct map to ITS */ 378 } else { 379 nb_nodes = 1; /* RC only */ 380 rc_mapping_count = 0; /* No output mapping */ 381 } 382 } 383 /* Number of IORT Nodes */ 384 build_append_int_noprefix(table_data, nb_nodes, 4); 385 386 /* Offset to Array of IORT Nodes */ 387 build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4); 388 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 389 390 if (vms->its) { 391 /* Table 12 ITS Group Format */ 392 build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */ 393 node_size = 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */; 394 build_append_int_noprefix(table_data, node_size, 2); /* Length */ 395 build_append_int_noprefix(table_data, 1, 1); /* Revision */ 396 build_append_int_noprefix(table_data, id++, 4); /* Identifier */ 397 build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */ 398 build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */ 399 build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */ 400 /* GIC ITS Identifier Array */ 401 build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4); 402 } 403 404 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 405 int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; 406 int smmu_mapping_count, offset_to_id_array; 407 408 if (vms->its) { 409 smmu_mapping_count = 1; /* ITS Group node */ 410 offset_to_id_array = SMMU_V3_ENTRY_SIZE; /* Just after the header */ 411 } else { 412 smmu_mapping_count = 0; /* No ID mappings */ 413 offset_to_id_array = 0; /* No ID mappings array */ 414 } 415 smmu_offset = table_data->len - table.table_offset; 416 /* Table 9 SMMUv3 Format */ 417 build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type */ 418 node_size = SMMU_V3_ENTRY_SIZE + 419 (ID_MAPPING_ENTRY_SIZE * smmu_mapping_count); 420 build_append_int_noprefix(table_data, node_size, 2); /* Length */ 421 build_append_int_noprefix(table_data, 4, 1); /* Revision */ 422 build_append_int_noprefix(table_data, id++, 4); /* Identifier */ 423 /* Number of ID mappings */ 424 build_append_int_noprefix(table_data, smmu_mapping_count, 4); 425 /* Reference to ID Array */ 426 build_append_int_noprefix(table_data, offset_to_id_array, 4); 427 /* Base address */ 428 build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base, 8); 429 /* Flags */ 430 build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4); 431 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 432 build_append_int_noprefix(table_data, 0, 8); /* VATOS address */ 433 /* Model */ 434 build_append_int_noprefix(table_data, 0 /* Generic SMMU-v3 */, 4); 435 build_append_int_noprefix(table_data, irq, 4); /* Event */ 436 build_append_int_noprefix(table_data, irq + 1, 4); /* PRI */ 437 build_append_int_noprefix(table_data, irq + 3, 4); /* GERR */ 438 build_append_int_noprefix(table_data, irq + 2, 4); /* Sync */ 439 build_append_int_noprefix(table_data, 0, 4); /* Proximity domain */ 440 /* DeviceID mapping index (ignored since interrupts are GSIV based) */ 441 build_append_int_noprefix(table_data, 0, 4); 442 /* Array of ID mappings */ 443 if (smmu_mapping_count) { 444 /* Output IORT node is the ITS Group node (the first node). */ 445 build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET); 446 } 447 } 448 449 /* Table 17 Root Complex Node */ 450 build_append_int_noprefix(table_data, 2 /* Root complex */, 1); /* Type */ 451 node_size = ROOT_COMPLEX_ENTRY_SIZE + 452 ID_MAPPING_ENTRY_SIZE * rc_mapping_count; 453 build_append_int_noprefix(table_data, node_size, 2); /* Length */ 454 build_append_int_noprefix(table_data, 3, 1); /* Revision */ 455 build_append_int_noprefix(table_data, id++, 4); /* Identifier */ 456 /* Number of ID mappings */ 457 build_append_int_noprefix(table_data, rc_mapping_count, 4); 458 /* Reference to ID Array */ 459 build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 4); 460 461 /* Table 14 Memory access properties */ 462 /* CCA: Cache Coherent Attribute */ 463 build_append_int_noprefix(table_data, 1 /* fully coherent */, 4); 464 build_append_int_noprefix(table_data, 0, 1); /* AH: Note Allocation Hints */ 465 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 466 /* Table 15 Memory Access Flags */ 467 build_append_int_noprefix(table_data, 0x3 /* CCA = CPM = DACS = 1 */, 1); 468 469 build_append_int_noprefix(table_data, 0, 4); /* ATS Attribute */ 470 /* MCFG pci_segment */ 471 build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */ 472 473 /* Memory address size limit */ 474 build_append_int_noprefix(table_data, 64, 1); 475 476 build_append_int_noprefix(table_data, 0, 3); /* Reserved */ 477 478 /* Output Reference */ 479 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 480 AcpiIortIdMapping *range; 481 482 /* 483 * Map RIDs (input) from RC to SMMUv3 nodes: RC -> SMMUv3. 484 * 485 * N.B.: The mapping from SMMUv3 to ITS Group node (SMMUv3 -> ITS) is 486 * defined in the SMMUv3 table, where all SMMUv3 IDs are mapped to the 487 * ITS Group node, if ITS is available. 488 */ 489 for (i = 0; i < rc_smmu_idmaps->len; i++) { 490 range = &g_array_index(rc_smmu_idmaps, AcpiIortIdMapping, i); 491 /* Output IORT node is the SMMUv3 node. */ 492 build_iort_id_mapping(table_data, range->input_base, 493 range->id_count, smmu_offset); 494 } 495 496 if (vms->its) { 497 /* 498 * Map bypassed (don't go through the SMMU) RIDs (input) to 499 * ITS Group node directly: RC -> ITS. 500 */ 501 for (i = 0; i < rc_its_idmaps->len; i++) { 502 range = &g_array_index(rc_its_idmaps, AcpiIortIdMapping, i); 503 /* Output IORT node is the ITS Group node (the first node). */ 504 build_iort_id_mapping(table_data, range->input_base, 505 range->id_count, IORT_NODE_OFFSET); 506 } 507 } 508 } else { 509 /* 510 * Map all RIDs (input) to ITS Group node directly, since there is no 511 * SMMU: RC -> ITS. 512 * Output IORT node is the ITS Group node (the first node). 513 */ 514 build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET); 515 } 516 517 acpi_table_end(linker, &table); 518 g_array_free(rc_smmu_idmaps, true); 519 g_array_free(rc_its_idmaps, true); 520 } 521 522 /* 523 * Serial Port Console Redirection Table (SPCR) 524 * Rev: 1.07 525 */ 526 static void 527 spcr_setup(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 528 { 529 AcpiSpcrData serial = { 530 .interface_type = 3, /* ARM PL011 UART */ 531 .base_addr.id = AML_AS_SYSTEM_MEMORY, 532 .base_addr.width = 32, 533 .base_addr.offset = 0, 534 .base_addr.size = 3, 535 .base_addr.addr = vms->memmap[VIRT_UART0].base, 536 .interrupt_type = (1 << 3),/* Bit[3] ARMH GIC interrupt*/ 537 .pc_interrupt = 0, /* IRQ */ 538 .interrupt = (vms->irqmap[VIRT_UART0] + ARM_SPI_BASE), 539 .baud_rate = 3, /* 9600 */ 540 .parity = 0, /* No Parity */ 541 .stop_bits = 1, /* 1 Stop bit */ 542 .flow_control = 1 << 1, /* RTS/CTS hardware flow control */ 543 .terminal_type = 0, /* VT100 */ 544 .language = 0, /* Language */ 545 .pci_device_id = 0xffff, /* not a PCI device*/ 546 .pci_vendor_id = 0xffff, /* not a PCI device*/ 547 .pci_bus = 0, 548 .pci_device = 0, 549 .pci_function = 0, 550 .pci_flags = 0, 551 .pci_segment = 0, 552 }; 553 /* 554 * Passing NULL as the SPCR Table for Revision 2 doesn't support 555 * NameSpaceString. 556 */ 557 build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id, 558 NULL); 559 } 560 561 /* 562 * ACPI spec, Revision 5.1 563 * 5.2.16 System Resource Affinity Table (SRAT) 564 */ 565 static void 566 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 567 { 568 int i; 569 uint64_t mem_base; 570 MachineClass *mc = MACHINE_GET_CLASS(vms); 571 MachineState *ms = MACHINE(vms); 572 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); 573 AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id, 574 .oem_table_id = vms->oem_table_id }; 575 576 acpi_table_begin(&table, table_data); 577 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 578 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 579 580 for (i = 0; i < cpu_list->len; ++i) { 581 uint32_t nodeid = cpu_list->cpus[i].props.node_id; 582 /* 583 * 5.2.16.4 GICC Affinity Structure 584 */ 585 build_append_int_noprefix(table_data, 3, 1); /* Type */ 586 build_append_int_noprefix(table_data, 18, 1); /* Length */ 587 build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */ 588 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ 589 /* Flags, Table 5-76 */ 590 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 591 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 592 } 593 594 mem_base = vms->memmap[VIRT_MEM].base; 595 for (i = 0; i < ms->numa_state->num_nodes; ++i) { 596 if (ms->numa_state->nodes[i].node_mem > 0) { 597 build_srat_memory(table_data, mem_base, 598 ms->numa_state->nodes[i].node_mem, i, 599 MEM_AFFINITY_ENABLED); 600 mem_base += ms->numa_state->nodes[i].node_mem; 601 } 602 } 603 604 build_srat_generic_affinity_structures(table_data); 605 606 if (ms->nvdimms_state->is_enabled) { 607 nvdimm_build_srat(table_data); 608 } 609 610 if (ms->device_memory) { 611 build_srat_memory(table_data, ms->device_memory->base, 612 memory_region_size(&ms->device_memory->mr), 613 ms->numa_state->num_nodes - 1, 614 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 615 } 616 617 acpi_table_end(linker, &table); 618 } 619 620 /* 621 * ACPI spec, Revision 6.5 622 * 5.2.25 Generic Timer Description Table (GTDT) 623 */ 624 static void 625 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 626 { 627 /* 628 * Table 5-117 Flag Definitions 629 * set only "Timer interrupt Mode" and assume "Timer Interrupt 630 * polarity" bit as '0: Interrupt is Active high' 631 */ 632 const uint32_t irqflags = 0; /* Interrupt is Level triggered */ 633 AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id, 634 .oem_table_id = vms->oem_table_id }; 635 636 acpi_table_begin(&table, table_data); 637 638 /* CntControlBase Physical Address */ 639 build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8); 640 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 641 /* 642 * FIXME: clarify comment: 643 * The interrupt values are the same with the device tree when adding 16 644 */ 645 /* Secure EL1 timer GSIV */ 646 build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ, 4); 647 /* Secure EL1 timer Flags */ 648 build_append_int_noprefix(table_data, irqflags, 4); 649 /* Non-Secure EL1 timer GSIV */ 650 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ, 4); 651 /* Non-Secure EL1 timer Flags */ 652 build_append_int_noprefix(table_data, irqflags | 653 1UL << 2, /* Always-on Capability */ 654 4); 655 /* Virtual timer GSIV */ 656 build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ, 4); 657 /* Virtual Timer Flags */ 658 build_append_int_noprefix(table_data, irqflags, 4); 659 /* Non-Secure EL2 timer GSIV */ 660 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ, 4); 661 /* Non-Secure EL2 timer Flags */ 662 build_append_int_noprefix(table_data, irqflags, 4); 663 /* CntReadBase Physical address */ 664 build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8); 665 /* Platform Timer Count */ 666 build_append_int_noprefix(table_data, 0, 4); 667 /* Platform Timer Offset */ 668 build_append_int_noprefix(table_data, 0, 4); 669 if (vms->ns_el2_virt_timer_irq) { 670 /* Virtual EL2 Timer GSIV */ 671 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, 4); 672 /* Virtual EL2 Timer Flags */ 673 build_append_int_noprefix(table_data, irqflags, 4); 674 } else { 675 build_append_int_noprefix(table_data, 0, 4); 676 build_append_int_noprefix(table_data, 0, 4); 677 } 678 acpi_table_end(linker, &table); 679 } 680 681 /* Debug Port Table 2 (DBG2) */ 682 static void 683 build_dbg2(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 684 { 685 AcpiTable table = { .sig = "DBG2", .rev = 0, .oem_id = vms->oem_id, 686 .oem_table_id = vms->oem_table_id }; 687 int dbg2devicelength; 688 const char name[] = "COM0"; 689 const int namespace_length = sizeof(name); 690 691 acpi_table_begin(&table, table_data); 692 693 dbg2devicelength = 22 + /* BaseAddressRegister[] offset */ 694 12 + /* BaseAddressRegister[] */ 695 4 + /* AddressSize[] */ 696 namespace_length /* NamespaceString[] */; 697 698 /* OffsetDbgDeviceInfo */ 699 build_append_int_noprefix(table_data, 44, 4); 700 /* NumberDbgDeviceInfo */ 701 build_append_int_noprefix(table_data, 1, 4); 702 703 /* Table 2. Debug Device Information structure format */ 704 build_append_int_noprefix(table_data, 0, 1); /* Revision */ 705 build_append_int_noprefix(table_data, dbg2devicelength, 2); /* Length */ 706 /* NumberofGenericAddressRegisters */ 707 build_append_int_noprefix(table_data, 1, 1); 708 /* NameSpaceStringLength */ 709 build_append_int_noprefix(table_data, namespace_length, 2); 710 build_append_int_noprefix(table_data, 38, 2); /* NameSpaceStringOffset */ 711 build_append_int_noprefix(table_data, 0, 2); /* OemDataLength */ 712 /* OemDataOffset (0 means no OEM data) */ 713 build_append_int_noprefix(table_data, 0, 2); 714 715 /* Port Type */ 716 build_append_int_noprefix(table_data, 0x8000 /* Serial */, 2); 717 /* Port Subtype */ 718 build_append_int_noprefix(table_data, 0x3 /* ARM PL011 UART */, 2); 719 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 720 /* BaseAddressRegisterOffset */ 721 build_append_int_noprefix(table_data, 22, 2); 722 /* AddressSizeOffset */ 723 build_append_int_noprefix(table_data, 34, 2); 724 725 /* BaseAddressRegister[] */ 726 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3, 727 vms->memmap[VIRT_UART0].base); 728 729 /* AddressSize[] */ 730 build_append_int_noprefix(table_data, 731 vms->memmap[VIRT_UART0].size, 4); 732 733 /* NamespaceString[] */ 734 g_array_append_vals(table_data, name, namespace_length); 735 736 acpi_table_end(linker, &table); 737 }; 738 739 /* 740 * ACPI spec, Revision 6.0 Errata A 741 * 5.2.12 Multiple APIC Description Table (MADT) 742 */ 743 static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size) 744 { 745 build_append_int_noprefix(table_data, 0xE, 1); /* Type */ 746 build_append_int_noprefix(table_data, 16, 1); /* Length */ 747 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 748 /* Discovery Range Base Address */ 749 build_append_int_noprefix(table_data, base, 8); 750 build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */ 751 } 752 753 static void 754 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 755 { 756 int i; 757 const MemMapEntry *memmap = vms->memmap; 758 AcpiTable table = { .sig = "APIC", .rev = 4, .oem_id = vms->oem_id, 759 .oem_table_id = vms->oem_table_id }; 760 761 acpi_table_begin(&table, table_data); 762 /* Local Interrupt Controller Address */ 763 build_append_int_noprefix(table_data, 0, 4); 764 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 765 766 /* 5.2.12.15 GIC Distributor Structure */ 767 build_append_int_noprefix(table_data, 0xC, 1); /* Type */ 768 build_append_int_noprefix(table_data, 24, 1); /* Length */ 769 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 770 build_append_int_noprefix(table_data, 0, 4); /* GIC ID */ 771 /* Physical Base Address */ 772 build_append_int_noprefix(table_data, memmap[VIRT_GIC_DIST].base, 8); 773 build_append_int_noprefix(table_data, 0, 4); /* System Vector Base */ 774 /* GIC version */ 775 build_append_int_noprefix(table_data, vms->gic_version, 1); 776 build_append_int_noprefix(table_data, 0, 3); /* Reserved */ 777 778 for (i = 0; i < MACHINE(vms)->smp.cpus; i++) { 779 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 780 uint64_t physical_base_address = 0, gich = 0, gicv = 0; 781 uint32_t vgic_interrupt = vms->virt ? ARCH_GIC_MAINT_IRQ : 0; 782 uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ? 783 VIRTUAL_PMU_IRQ : 0; 784 785 if (vms->gic_version == VIRT_GIC_VERSION_2) { 786 physical_base_address = memmap[VIRT_GIC_CPU].base; 787 gicv = memmap[VIRT_GIC_VCPU].base; 788 gich = memmap[VIRT_GIC_HYP].base; 789 } 790 791 /* 5.2.12.14 GIC Structure */ 792 build_append_int_noprefix(table_data, 0xB, 1); /* Type */ 793 build_append_int_noprefix(table_data, 80, 1); /* Length */ 794 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 795 build_append_int_noprefix(table_data, i, 4); /* GIC ID */ 796 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ 797 /* Flags */ 798 build_append_int_noprefix(table_data, 1, 4); /* Enabled */ 799 /* Parking Protocol Version */ 800 build_append_int_noprefix(table_data, 0, 4); 801 /* Performance Interrupt GSIV */ 802 build_append_int_noprefix(table_data, pmu_interrupt, 4); 803 build_append_int_noprefix(table_data, 0, 8); /* Parked Address */ 804 /* Physical Base Address */ 805 build_append_int_noprefix(table_data, physical_base_address, 8); 806 build_append_int_noprefix(table_data, gicv, 8); /* GICV */ 807 build_append_int_noprefix(table_data, gich, 8); /* GICH */ 808 /* VGIC Maintenance interrupt */ 809 build_append_int_noprefix(table_data, vgic_interrupt, 4); 810 build_append_int_noprefix(table_data, 0, 8); /* GICR Base Address*/ 811 /* MPIDR */ 812 build_append_int_noprefix(table_data, arm_cpu_mp_affinity(armcpu), 8); 813 /* Processor Power Efficiency Class */ 814 build_append_int_noprefix(table_data, 0, 1); 815 /* Reserved */ 816 build_append_int_noprefix(table_data, 0, 3); 817 } 818 819 if (vms->gic_version != VIRT_GIC_VERSION_2) { 820 build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base, 821 memmap[VIRT_GIC_REDIST].size); 822 if (virt_gicv3_redist_region_count(vms) == 2) { 823 build_append_gicr(table_data, memmap[VIRT_HIGH_GIC_REDIST2].base, 824 memmap[VIRT_HIGH_GIC_REDIST2].size); 825 } 826 827 if (vms->its) { 828 /* 829 * ACPI spec, Revision 6.0 Errata A 830 * (original 6.0 definition has invalid Length) 831 * 5.2.12.18 GIC ITS Structure 832 */ 833 build_append_int_noprefix(table_data, 0xF, 1); /* Type */ 834 build_append_int_noprefix(table_data, 20, 1); /* Length */ 835 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 836 build_append_int_noprefix(table_data, 0, 4); /* GIC ITS ID */ 837 /* Physical Base Address */ 838 build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].base, 8); 839 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 840 } 841 } else { 842 const uint16_t spi_base = vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE; 843 844 /* 5.2.12.16 GIC MSI Frame Structure */ 845 build_append_int_noprefix(table_data, 0xD, 1); /* Type */ 846 build_append_int_noprefix(table_data, 24, 1); /* Length */ 847 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 848 build_append_int_noprefix(table_data, 0, 4); /* GIC MSI Frame ID */ 849 /* Physical Base Address */ 850 build_append_int_noprefix(table_data, memmap[VIRT_GIC_V2M].base, 8); 851 build_append_int_noprefix(table_data, 1, 4); /* Flags */ 852 /* SPI Count */ 853 build_append_int_noprefix(table_data, NUM_GICV2M_SPIS, 2); 854 build_append_int_noprefix(table_data, spi_base, 2); /* SPI Base */ 855 } 856 acpi_table_end(linker, &table); 857 } 858 859 /* FADT */ 860 static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker, 861 VirtMachineState *vms, unsigned dsdt_tbl_offset) 862 { 863 /* ACPI v6.3 */ 864 AcpiFadtData fadt = { 865 .rev = 6, 866 .minor_ver = 3, 867 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, 868 .xdsdt_tbl_offset = &dsdt_tbl_offset, 869 }; 870 871 switch (vms->psci_conduit) { 872 case QEMU_PSCI_CONDUIT_DISABLED: 873 fadt.arm_boot_arch = 0; 874 break; 875 case QEMU_PSCI_CONDUIT_HVC: 876 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT | 877 ACPI_FADT_ARM_PSCI_USE_HVC; 878 break; 879 case QEMU_PSCI_CONDUIT_SMC: 880 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT; 881 break; 882 default: 883 g_assert_not_reached(); 884 } 885 886 build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id); 887 } 888 889 /* DSDT */ 890 static void 891 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 892 { 893 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 894 Aml *scope, *dsdt; 895 MachineState *ms = MACHINE(vms); 896 const MemMapEntry *memmap = vms->memmap; 897 const int *irqmap = vms->irqmap; 898 AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = vms->oem_id, 899 .oem_table_id = vms->oem_table_id }; 900 901 acpi_table_begin(&table, table_data); 902 dsdt = init_aml_allocator(); 903 904 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. 905 * While UEFI can use libfdt to disable the RTC device node in the DTB that 906 * it passes to the OS, it cannot modify AML. Therefore, we won't generate 907 * the RTC ACPI device at all when using UEFI. 908 */ 909 scope = aml_scope("\\_SB"); 910 acpi_dsdt_add_cpus(scope, vms); 911 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], 912 (irqmap[VIRT_UART0] + ARM_SPI_BASE), 0); 913 if (vms->second_ns_uart_present) { 914 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART1], 915 (irqmap[VIRT_UART1] + ARM_SPI_BASE), 1); 916 } 917 if (vmc->acpi_expose_flash) { 918 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); 919 } 920 fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]); 921 virtio_acpi_dsdt_add(scope, memmap[VIRT_MMIO].base, memmap[VIRT_MMIO].size, 922 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), 923 0, NUM_VIRTIO_TRANSPORTS); 924 acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms); 925 if (vms->acpi_dev) { 926 build_ged_aml(scope, "\\_SB."GED_DEVICE, 927 HOTPLUG_HANDLER(vms->acpi_dev), 928 irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY, 929 memmap[VIRT_ACPI_GED].base); 930 } else { 931 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], 932 (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); 933 } 934 935 if (vms->acpi_dev) { 936 uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev), 937 "ged-event", &error_abort); 938 939 if (event & ACPI_GED_MEM_HOTPLUG_EVT) { 940 build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL, 941 AML_SYSTEM_MEMORY, 942 memmap[VIRT_PCDIMM_ACPI].base); 943 } 944 } 945 946 acpi_dsdt_add_power_button(scope); 947 #ifdef CONFIG_TPM 948 acpi_dsdt_add_tpm(scope, vms); 949 #endif 950 951 aml_append(dsdt, scope); 952 953 /* copy AML table into ACPI tables blob */ 954 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 955 956 acpi_table_end(linker, &table); 957 free_aml_allocator(); 958 } 959 960 typedef 961 struct AcpiBuildState { 962 /* Copy of table in RAM (for patching). */ 963 MemoryRegion *table_mr; 964 MemoryRegion *rsdp_mr; 965 MemoryRegion *linker_mr; 966 /* Is table patched? */ 967 bool patched; 968 } AcpiBuildState; 969 970 static void acpi_align_size(GArray *blob, unsigned align) 971 { 972 /* 973 * Align size to multiple of given size. This reduces the chance 974 * we need to change size in the future (breaking cross version migration). 975 */ 976 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 977 } 978 979 static 980 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) 981 { 982 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 983 GArray *table_offsets; 984 unsigned dsdt, xsdt; 985 GArray *tables_blob = tables->table_data; 986 MachineState *ms = MACHINE(vms); 987 988 table_offsets = g_array_new(false, true /* clear */, 989 sizeof(uint32_t)); 990 991 bios_linker_loader_alloc(tables->linker, 992 ACPI_BUILD_TABLE_FILE, tables_blob, 993 64, false /* high memory */); 994 995 /* DSDT is pointed to by FADT */ 996 dsdt = tables_blob->len; 997 build_dsdt(tables_blob, tables->linker, vms); 998 999 /* FADT MADT PPTT GTDT MCFG SPCR DBG2 pointed to by RSDT */ 1000 acpi_add_table(table_offsets, tables_blob); 1001 build_fadt_rev6(tables_blob, tables->linker, vms, dsdt); 1002 1003 acpi_add_table(table_offsets, tables_blob); 1004 build_madt(tables_blob, tables->linker, vms); 1005 1006 if (!vmc->no_cpu_topology) { 1007 acpi_add_table(table_offsets, tables_blob); 1008 build_pptt(tables_blob, tables->linker, ms, 1009 vms->oem_id, vms->oem_table_id); 1010 } 1011 1012 acpi_add_table(table_offsets, tables_blob); 1013 build_gtdt(tables_blob, tables->linker, vms); 1014 1015 acpi_add_table(table_offsets, tables_blob); 1016 { 1017 AcpiMcfgInfo mcfg = { 1018 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, 1019 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, 1020 }; 1021 build_mcfg(tables_blob, tables->linker, &mcfg, vms->oem_id, 1022 vms->oem_table_id); 1023 } 1024 1025 acpi_add_table(table_offsets, tables_blob); 1026 spcr_setup(tables_blob, tables->linker, vms); 1027 1028 acpi_add_table(table_offsets, tables_blob); 1029 build_dbg2(tables_blob, tables->linker, vms); 1030 1031 if (vms->ras) { 1032 acpi_add_table(table_offsets, tables_blob); 1033 acpi_build_hest(tables_blob, tables->hardware_errors, tables->linker, 1034 vms->oem_id, vms->oem_table_id); 1035 } 1036 1037 if (ms->numa_state->num_nodes > 0) { 1038 acpi_add_table(table_offsets, tables_blob); 1039 build_srat(tables_blob, tables->linker, vms); 1040 if (ms->numa_state->have_numa_distance) { 1041 acpi_add_table(table_offsets, tables_blob); 1042 build_slit(tables_blob, tables->linker, ms, vms->oem_id, 1043 vms->oem_table_id); 1044 } 1045 1046 if (ms->numa_state->hmat_enabled) { 1047 acpi_add_table(table_offsets, tables_blob); 1048 build_hmat(tables_blob, tables->linker, ms->numa_state, 1049 vms->oem_id, vms->oem_table_id); 1050 } 1051 } 1052 1053 if (vms->cxl_devices_state.is_enabled) { 1054 cxl_build_cedt(table_offsets, tables_blob, tables->linker, 1055 vms->oem_id, vms->oem_table_id, &vms->cxl_devices_state); 1056 } 1057 1058 if (ms->nvdimms_state->is_enabled) { 1059 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 1060 ms->nvdimms_state, ms->ram_slots, vms->oem_id, 1061 vms->oem_table_id); 1062 } 1063 1064 acpi_add_table(table_offsets, tables_blob); 1065 build_iort(tables_blob, tables->linker, vms); 1066 1067 #ifdef CONFIG_TPM 1068 if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) { 1069 acpi_add_table(table_offsets, tables_blob); 1070 build_tpm2(tables_blob, tables->linker, tables->tcpalog, vms->oem_id, 1071 vms->oem_table_id); 1072 } 1073 #endif 1074 1075 if (vms->iommu == VIRT_IOMMU_VIRTIO) { 1076 acpi_add_table(table_offsets, tables_blob); 1077 build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf, 1078 vms->oem_id, vms->oem_table_id); 1079 } 1080 1081 /* XSDT is pointed to by RSDP */ 1082 xsdt = tables_blob->len; 1083 build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id, 1084 vms->oem_table_id); 1085 1086 /* RSDP is in FSEG memory, so allocate it separately */ 1087 { 1088 AcpiRsdpData rsdp_data = { 1089 .revision = 2, 1090 .oem_id = vms->oem_id, 1091 .xsdt_tbl_offset = &xsdt, 1092 .rsdt_tbl_offset = NULL, 1093 }; 1094 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 1095 } 1096 1097 /* 1098 * The align size is 128, warn if 64k is not enough therefore 1099 * the align size could be resized. 1100 */ 1101 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 1102 warn_report("ACPI table size %u exceeds %d bytes," 1103 " migration may not work", 1104 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 1105 error_printf("Try removing CPUs, NUMA nodes, memory slots" 1106 " or PCI bridges.\n"); 1107 } 1108 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 1109 1110 1111 /* Cleanup memory that's no longer used. */ 1112 g_array_free(table_offsets, true); 1113 } 1114 1115 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 1116 { 1117 uint32_t size = acpi_data_len(data); 1118 1119 /* Make sure RAM size is correct - in case it got changed 1120 * e.g. by migration */ 1121 memory_region_ram_resize(mr, size, &error_abort); 1122 1123 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 1124 memory_region_set_dirty(mr, 0, size); 1125 } 1126 1127 static void virt_acpi_build_update(void *build_opaque) 1128 { 1129 AcpiBuildState *build_state = build_opaque; 1130 AcpiBuildTables tables; 1131 1132 /* No state to update or already patched? Nothing to do. */ 1133 if (!build_state || build_state->patched) { 1134 return; 1135 } 1136 build_state->patched = true; 1137 1138 acpi_build_tables_init(&tables); 1139 1140 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables); 1141 1142 acpi_ram_update(build_state->table_mr, tables.table_data); 1143 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 1144 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 1145 1146 acpi_build_tables_cleanup(&tables, true); 1147 } 1148 1149 static void virt_acpi_build_reset(void *build_opaque) 1150 { 1151 AcpiBuildState *build_state = build_opaque; 1152 build_state->patched = false; 1153 } 1154 1155 static const VMStateDescription vmstate_virt_acpi_build = { 1156 .name = "virt_acpi_build", 1157 .version_id = 1, 1158 .minimum_version_id = 1, 1159 .fields = (const VMStateField[]) { 1160 VMSTATE_BOOL(patched, AcpiBuildState), 1161 VMSTATE_END_OF_LIST() 1162 }, 1163 }; 1164 1165 void virt_acpi_setup(VirtMachineState *vms) 1166 { 1167 AcpiBuildTables tables; 1168 AcpiBuildState *build_state; 1169 AcpiGedState *acpi_ged_state; 1170 1171 if (!vms->fw_cfg) { 1172 trace_virt_acpi_setup(); 1173 return; 1174 } 1175 1176 if (!virt_is_acpi_enabled(vms)) { 1177 trace_virt_acpi_setup(); 1178 return; 1179 } 1180 1181 build_state = g_malloc0(sizeof *build_state); 1182 1183 acpi_build_tables_init(&tables); 1184 virt_acpi_build(vms, &tables); 1185 1186 /* Now expose it all to Guest */ 1187 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, 1188 build_state, tables.table_data, 1189 ACPI_BUILD_TABLE_FILE); 1190 assert(build_state->table_mr != NULL); 1191 1192 build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update, 1193 build_state, 1194 tables.linker->cmd_blob, 1195 ACPI_BUILD_LOADER_FILE); 1196 1197 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, 1198 acpi_data_len(tables.tcpalog)); 1199 1200 if (vms->ras) { 1201 assert(vms->acpi_dev); 1202 acpi_ged_state = ACPI_GED(vms->acpi_dev); 1203 acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state, 1204 vms->fw_cfg, tables.hardware_errors); 1205 } 1206 1207 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, 1208 build_state, tables.rsdp, 1209 ACPI_BUILD_RSDP_FILE); 1210 1211 qemu_register_reset(virt_acpi_build_reset, build_state); 1212 virt_acpi_build_reset(build_state); 1213 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 1214 1215 /* Cleanup tables but don't free the memory: we track it 1216 * in build_state. 1217 */ 1218 acpi_build_tables_cleanup(&tables, false); 1219 } 1220