1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * ARM virt ACPI generation 4 * 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 6 * Copyright (C) 2006 Fabrice Bellard 7 * Copyright (C) 2013 Red Hat Inc 8 * 9 * Author: Michael S. Tsirkin <mst@redhat.com> 10 * 11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 12 * 13 * Author: Shannon Zhao <zhaoshenglong@huawei.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "qapi/error.h" 31 #include "qemu/bitmap.h" 32 #include "qemu/error-report.h" 33 #include "trace.h" 34 #include "hw/core/cpu.h" 35 #include "target/arm/cpu.h" 36 #include "hw/acpi/acpi-defs.h" 37 #include "hw/acpi/acpi.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/acpi/aml-build.h" 41 #include "hw/acpi/utils.h" 42 #include "hw/acpi/pci.h" 43 #include "hw/acpi/memory_hotplug.h" 44 #include "hw/acpi/generic_event_device.h" 45 #include "hw/acpi/tpm.h" 46 #include "hw/acpi/hmat.h" 47 #include "hw/pci/pcie_host.h" 48 #include "hw/pci/pci.h" 49 #include "hw/pci/pci_bus.h" 50 #include "hw/pci-host/gpex.h" 51 #include "hw/arm/virt.h" 52 #include "hw/intc/arm_gicv3_its_common.h" 53 #include "hw/mem/nvdimm.h" 54 #include "hw/platform-bus.h" 55 #include "sysemu/numa.h" 56 #include "sysemu/reset.h" 57 #include "sysemu/tpm.h" 58 #include "migration/vmstate.h" 59 #include "hw/acpi/ghes.h" 60 #include "hw/acpi/viot.h" 61 62 #define ARM_SPI_BASE 32 63 64 #define ACPI_BUILD_TABLE_SIZE 0x20000 65 66 static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms) 67 { 68 MachineState *ms = MACHINE(vms); 69 uint16_t i; 70 71 for (i = 0; i < ms->smp.cpus; i++) { 72 Aml *dev = aml_device("C%.03X", i); 73 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 74 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 75 aml_append(scope, dev); 76 } 77 } 78 79 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 80 uint32_t uart_irq) 81 { 82 Aml *dev = aml_device("COM0"); 83 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); 84 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 85 86 Aml *crs = aml_resource_template(); 87 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 88 uart_memmap->size, AML_READ_WRITE)); 89 aml_append(crs, 90 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 91 AML_EXCLUSIVE, &uart_irq, 1)); 92 aml_append(dev, aml_name_decl("_CRS", crs)); 93 94 aml_append(scope, dev); 95 } 96 97 static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) 98 { 99 Aml *dev = aml_device("FWCF"); 100 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 101 /* device present, functioning, decoding, not shown in UI */ 102 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 103 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 104 105 Aml *crs = aml_resource_template(); 106 aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, 107 fw_cfg_memmap->size, AML_READ_WRITE)); 108 aml_append(dev, aml_name_decl("_CRS", crs)); 109 aml_append(scope, dev); 110 } 111 112 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) 113 { 114 Aml *dev, *crs; 115 hwaddr base = flash_memmap->base; 116 hwaddr size = flash_memmap->size / 2; 117 118 dev = aml_device("FLS0"); 119 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 120 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 121 122 crs = aml_resource_template(); 123 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 124 aml_append(dev, aml_name_decl("_CRS", crs)); 125 aml_append(scope, dev); 126 127 dev = aml_device("FLS1"); 128 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 129 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 130 crs = aml_resource_template(); 131 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); 132 aml_append(dev, aml_name_decl("_CRS", crs)); 133 aml_append(scope, dev); 134 } 135 136 static void acpi_dsdt_add_virtio(Aml *scope, 137 const MemMapEntry *virtio_mmio_memmap, 138 uint32_t mmio_irq, int num) 139 { 140 hwaddr base = virtio_mmio_memmap->base; 141 hwaddr size = virtio_mmio_memmap->size; 142 int i; 143 144 for (i = 0; i < num; i++) { 145 uint32_t irq = mmio_irq + i; 146 Aml *dev = aml_device("VR%02u", i); 147 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); 148 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 149 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 150 151 Aml *crs = aml_resource_template(); 152 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 153 aml_append(crs, 154 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 155 AML_EXCLUSIVE, &irq, 1)); 156 aml_append(dev, aml_name_decl("_CRS", crs)); 157 aml_append(scope, dev); 158 base += size; 159 } 160 } 161 162 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, 163 uint32_t irq, VirtMachineState *vms) 164 { 165 int ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 166 struct GPEXConfig cfg = { 167 .mmio32 = memmap[VIRT_PCIE_MMIO], 168 .pio = memmap[VIRT_PCIE_PIO], 169 .ecam = memmap[ecam_id], 170 .irq = irq, 171 .bus = vms->bus, 172 }; 173 174 if (vms->highmem_mmio) { 175 cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO]; 176 } 177 178 acpi_dsdt_add_gpex(scope, &cfg); 179 } 180 181 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, 182 uint32_t gpio_irq) 183 { 184 Aml *dev = aml_device("GPO0"); 185 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); 186 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 187 188 Aml *crs = aml_resource_template(); 189 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, 190 AML_READ_WRITE)); 191 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 192 AML_EXCLUSIVE, &gpio_irq, 1)); 193 aml_append(dev, aml_name_decl("_CRS", crs)); 194 195 Aml *aei = aml_resource_template(); 196 /* Pin 3 for power button */ 197 const uint32_t pin_list[1] = {3}; 198 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, 199 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, 200 "GPO0", NULL, 0)); 201 aml_append(dev, aml_name_decl("_AEI", aei)); 202 203 /* _E03 is handle for power button */ 204 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); 205 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), 206 aml_int(0x80))); 207 aml_append(dev, method); 208 aml_append(scope, dev); 209 } 210 211 #ifdef CONFIG_TPM 212 static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms) 213 { 214 PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); 215 hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base; 216 SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find()); 217 MemoryRegion *sbdev_mr; 218 hwaddr tpm_base; 219 220 if (!sbdev) { 221 return; 222 } 223 224 tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); 225 assert(tpm_base != -1); 226 227 tpm_base += pbus_base; 228 229 sbdev_mr = sysbus_mmio_get_region(sbdev, 0); 230 231 Aml *dev = aml_device("TPM0"); 232 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 233 aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device"))); 234 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 235 236 Aml *crs = aml_resource_template(); 237 aml_append(crs, 238 aml_memory32_fixed(tpm_base, 239 (uint32_t)memory_region_size(sbdev_mr), 240 AML_READ_WRITE)); 241 aml_append(dev, aml_name_decl("_CRS", crs)); 242 aml_append(scope, dev); 243 } 244 #endif 245 246 #define ID_MAPPING_ENTRY_SIZE 20 247 #define SMMU_V3_ENTRY_SIZE 68 248 #define ROOT_COMPLEX_ENTRY_SIZE 36 249 #define IORT_NODE_OFFSET 48 250 251 static void build_iort_id_mapping(GArray *table_data, uint32_t input_base, 252 uint32_t id_count, uint32_t out_ref) 253 { 254 /* Table 4 ID mapping format */ 255 build_append_int_noprefix(table_data, input_base, 4); /* Input base */ 256 build_append_int_noprefix(table_data, id_count, 4); /* Number of IDs */ 257 build_append_int_noprefix(table_data, input_base, 4); /* Output base */ 258 build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference */ 259 /* Flags */ 260 build_append_int_noprefix(table_data, 0 /* Single mapping (disabled) */, 4); 261 } 262 263 struct AcpiIortIdMapping { 264 uint32_t input_base; 265 uint32_t id_count; 266 }; 267 typedef struct AcpiIortIdMapping AcpiIortIdMapping; 268 269 /* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */ 270 static int 271 iort_host_bridges(Object *obj, void *opaque) 272 { 273 GArray *idmap_blob = opaque; 274 275 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 276 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 277 278 if (bus && !pci_bus_bypass_iommu(bus)) { 279 int min_bus, max_bus; 280 281 pci_bus_range(bus, &min_bus, &max_bus); 282 283 AcpiIortIdMapping idmap = { 284 .input_base = min_bus << 8, 285 .id_count = (max_bus - min_bus + 1) << 8, 286 }; 287 g_array_append_val(idmap_blob, idmap); 288 } 289 } 290 291 return 0; 292 } 293 294 static int iort_idmap_compare(gconstpointer a, gconstpointer b) 295 { 296 AcpiIortIdMapping *idmap_a = (AcpiIortIdMapping *)a; 297 AcpiIortIdMapping *idmap_b = (AcpiIortIdMapping *)b; 298 299 return idmap_a->input_base - idmap_b->input_base; 300 } 301 302 /* 303 * Input Output Remapping Table (IORT) 304 * Conforms to "IO Remapping Table System Software on ARM Platforms", 305 * Document number: ARM DEN 0049E.b, Feb 2021 306 */ 307 static void 308 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 309 { 310 int i, nb_nodes, rc_mapping_count; 311 const uint32_t iort_node_offset = IORT_NODE_OFFSET; 312 size_t node_size, smmu_offset = 0; 313 AcpiIortIdMapping *idmap; 314 uint32_t id = 0; 315 GArray *smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); 316 GArray *its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); 317 318 AcpiTable table = { .sig = "IORT", .rev = 3, .oem_id = vms->oem_id, 319 .oem_table_id = vms->oem_table_id }; 320 /* Table 2 The IORT */ 321 acpi_table_begin(&table, table_data); 322 323 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 324 AcpiIortIdMapping next_range = {0}; 325 326 object_child_foreach_recursive(object_get_root(), 327 iort_host_bridges, smmu_idmaps); 328 329 /* Sort the smmu idmap by input_base */ 330 g_array_sort(smmu_idmaps, iort_idmap_compare); 331 332 /* 333 * Split the whole RIDs by mapping from RC to SMMU, 334 * build the ID mapping from RC to ITS directly. 335 */ 336 for (i = 0; i < smmu_idmaps->len; i++) { 337 idmap = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); 338 339 if (next_range.input_base < idmap->input_base) { 340 next_range.id_count = idmap->input_base - next_range.input_base; 341 g_array_append_val(its_idmaps, next_range); 342 } 343 344 next_range.input_base = idmap->input_base + idmap->id_count; 345 } 346 347 /* Append the last RC -> ITS ID mapping */ 348 if (next_range.input_base < 0xFFFF) { 349 next_range.id_count = 0xFFFF - next_range.input_base; 350 g_array_append_val(its_idmaps, next_range); 351 } 352 353 nb_nodes = 3; /* RC, ITS, SMMUv3 */ 354 rc_mapping_count = smmu_idmaps->len + its_idmaps->len; 355 } else { 356 nb_nodes = 2; /* RC, ITS */ 357 rc_mapping_count = 1; 358 } 359 /* Number of IORT Nodes */ 360 build_append_int_noprefix(table_data, nb_nodes, 4); 361 362 /* Offset to Array of IORT Nodes */ 363 build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4); 364 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 365 366 /* Table 12 ITS Group Format */ 367 build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */ 368 node_size = 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */; 369 build_append_int_noprefix(table_data, node_size, 2); /* Length */ 370 build_append_int_noprefix(table_data, 1, 1); /* Revision */ 371 build_append_int_noprefix(table_data, id++, 4); /* Identifier */ 372 build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */ 373 build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */ 374 build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */ 375 /* GIC ITS Identifier Array */ 376 build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4); 377 378 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 379 int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; 380 381 smmu_offset = table_data->len - table.table_offset; 382 /* Table 9 SMMUv3 Format */ 383 build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type */ 384 node_size = SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE; 385 build_append_int_noprefix(table_data, node_size, 2); /* Length */ 386 build_append_int_noprefix(table_data, 4, 1); /* Revision */ 387 build_append_int_noprefix(table_data, id++, 4); /* Identifier */ 388 build_append_int_noprefix(table_data, 1, 4); /* Number of ID mappings */ 389 /* Reference to ID Array */ 390 build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4); 391 /* Base address */ 392 build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base, 8); 393 /* Flags */ 394 build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4); 395 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 396 build_append_int_noprefix(table_data, 0, 8); /* VATOS address */ 397 /* Model */ 398 build_append_int_noprefix(table_data, 0 /* Generic SMMU-v3 */, 4); 399 build_append_int_noprefix(table_data, irq, 4); /* Event */ 400 build_append_int_noprefix(table_data, irq + 1, 4); /* PRI */ 401 build_append_int_noprefix(table_data, irq + 3, 4); /* GERR */ 402 build_append_int_noprefix(table_data, irq + 2, 4); /* Sync */ 403 build_append_int_noprefix(table_data, 0, 4); /* Proximity domain */ 404 /* DeviceID mapping index (ignored since interrupts are GSIV based) */ 405 build_append_int_noprefix(table_data, 0, 4); 406 407 /* output IORT node is the ITS group node (the first node) */ 408 build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET); 409 } 410 411 /* Table 17 Root Complex Node */ 412 build_append_int_noprefix(table_data, 2 /* Root complex */, 1); /* Type */ 413 node_size = ROOT_COMPLEX_ENTRY_SIZE + 414 ID_MAPPING_ENTRY_SIZE * rc_mapping_count; 415 build_append_int_noprefix(table_data, node_size, 2); /* Length */ 416 build_append_int_noprefix(table_data, 3, 1); /* Revision */ 417 build_append_int_noprefix(table_data, id++, 4); /* Identifier */ 418 /* Number of ID mappings */ 419 build_append_int_noprefix(table_data, rc_mapping_count, 4); 420 /* Reference to ID Array */ 421 build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 4); 422 423 /* Table 14 Memory access properties */ 424 /* CCA: Cache Coherent Attribute */ 425 build_append_int_noprefix(table_data, 1 /* fully coherent */, 4); 426 build_append_int_noprefix(table_data, 0, 1); /* AH: Note Allocation Hints */ 427 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 428 /* Table 15 Memory Access Flags */ 429 build_append_int_noprefix(table_data, 0x3 /* CCA = CPM = DACS = 1 */, 1); 430 431 build_append_int_noprefix(table_data, 0, 4); /* ATS Attribute */ 432 /* MCFG pci_segment */ 433 build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */ 434 435 /* Memory address size limit */ 436 build_append_int_noprefix(table_data, 64, 1); 437 438 build_append_int_noprefix(table_data, 0, 3); /* Reserved */ 439 440 /* Output Reference */ 441 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 442 AcpiIortIdMapping *range; 443 444 /* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */ 445 for (i = 0; i < smmu_idmaps->len; i++) { 446 range = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); 447 /* output IORT node is the smmuv3 node */ 448 build_iort_id_mapping(table_data, range->input_base, 449 range->id_count, smmu_offset); 450 } 451 452 /* bypassed RIDs connect to ITS group node directly: RC -> ITS */ 453 for (i = 0; i < its_idmaps->len; i++) { 454 range = &g_array_index(its_idmaps, AcpiIortIdMapping, i); 455 /* output IORT node is the ITS group node (the first node) */ 456 build_iort_id_mapping(table_data, range->input_base, 457 range->id_count, iort_node_offset); 458 } 459 } else { 460 /* output IORT node is the ITS group node (the first node) */ 461 build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET); 462 } 463 464 acpi_table_end(linker, &table); 465 g_array_free(smmu_idmaps, true); 466 g_array_free(its_idmaps, true); 467 } 468 469 /* 470 * Serial Port Console Redirection Table (SPCR) 471 * Rev: 1.07 472 */ 473 static void 474 build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 475 { 476 AcpiTable table = { .sig = "SPCR", .rev = 2, .oem_id = vms->oem_id, 477 .oem_table_id = vms->oem_table_id }; 478 479 acpi_table_begin(&table, table_data); 480 481 /* Interface Type */ 482 build_append_int_noprefix(table_data, 3, 1); /* ARM PL011 UART */ 483 build_append_int_noprefix(table_data, 0, 3); /* Reserved */ 484 /* Base Address */ 485 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 8, 0, 1, 486 vms->memmap[VIRT_UART].base); 487 /* Interrupt Type */ 488 build_append_int_noprefix(table_data, 489 (1 << 3) /* Bit[3] ARMH GIC interrupt */, 1); 490 build_append_int_noprefix(table_data, 0, 1); /* IRQ */ 491 /* Global System Interrupt */ 492 build_append_int_noprefix(table_data, 493 vms->irqmap[VIRT_UART] + ARM_SPI_BASE, 4); 494 build_append_int_noprefix(table_data, 3 /* 9600 */, 1); /* Baud Rate */ 495 build_append_int_noprefix(table_data, 0 /* No Parity */, 1); /* Parity */ 496 /* Stop Bits */ 497 build_append_int_noprefix(table_data, 1 /* 1 Stop bit */, 1); 498 /* Flow Control */ 499 build_append_int_noprefix(table_data, 500 (1 << 1) /* RTS/CTS hardware flow control */, 1); 501 /* Terminal Type */ 502 build_append_int_noprefix(table_data, 0 /* VT100 */, 1); 503 build_append_int_noprefix(table_data, 0, 1); /* Language */ 504 /* PCI Device ID */ 505 build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2); 506 /* PCI Vendor ID */ 507 build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2); 508 build_append_int_noprefix(table_data, 0, 1); /* PCI Bus Number */ 509 build_append_int_noprefix(table_data, 0, 1); /* PCI Device Number */ 510 build_append_int_noprefix(table_data, 0, 1); /* PCI Function Number */ 511 build_append_int_noprefix(table_data, 0, 4); /* PCI Flags */ 512 build_append_int_noprefix(table_data, 0, 1); /* PCI Segment */ 513 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 514 515 acpi_table_end(linker, &table); 516 } 517 518 /* 519 * ACPI spec, Revision 5.1 520 * 5.2.16 System Resource Affinity Table (SRAT) 521 */ 522 static void 523 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 524 { 525 int i; 526 uint64_t mem_base; 527 MachineClass *mc = MACHINE_GET_CLASS(vms); 528 MachineState *ms = MACHINE(vms); 529 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); 530 AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id, 531 .oem_table_id = vms->oem_table_id }; 532 533 acpi_table_begin(&table, table_data); 534 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 535 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 536 537 for (i = 0; i < cpu_list->len; ++i) { 538 uint32_t nodeid = cpu_list->cpus[i].props.node_id; 539 /* 540 * 5.2.16.4 GICC Affinity Structure 541 */ 542 build_append_int_noprefix(table_data, 3, 1); /* Type */ 543 build_append_int_noprefix(table_data, 18, 1); /* Length */ 544 build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */ 545 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ 546 /* Flags, Table 5-76 */ 547 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 548 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 549 } 550 551 mem_base = vms->memmap[VIRT_MEM].base; 552 for (i = 0; i < ms->numa_state->num_nodes; ++i) { 553 if (ms->numa_state->nodes[i].node_mem > 0) { 554 build_srat_memory(table_data, mem_base, 555 ms->numa_state->nodes[i].node_mem, i, 556 MEM_AFFINITY_ENABLED); 557 mem_base += ms->numa_state->nodes[i].node_mem; 558 } 559 } 560 561 if (ms->nvdimms_state->is_enabled) { 562 nvdimm_build_srat(table_data); 563 } 564 565 if (ms->device_memory) { 566 build_srat_memory(table_data, ms->device_memory->base, 567 memory_region_size(&ms->device_memory->mr), 568 ms->numa_state->num_nodes - 1, 569 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 570 } 571 572 acpi_table_end(linker, &table); 573 } 574 575 /* 576 * ACPI spec, Revision 5.1 577 * 5.2.24 Generic Timer Description Table (GTDT) 578 */ 579 static void 580 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 581 { 582 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 583 /* 584 * Table 5-117 Flag Definitions 585 * set only "Timer interrupt Mode" and assume "Timer Interrupt 586 * polarity" bit as '0: Interrupt is Active high' 587 */ 588 uint32_t irqflags = vmc->claim_edge_triggered_timers ? 589 1 : /* Interrupt is Edge triggered */ 590 0; /* Interrupt is Level triggered */ 591 AcpiTable table = { .sig = "GTDT", .rev = 2, .oem_id = vms->oem_id, 592 .oem_table_id = vms->oem_table_id }; 593 594 acpi_table_begin(&table, table_data); 595 596 /* CntControlBase Physical Address */ 597 build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8); 598 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 599 /* 600 * FIXME: clarify comment: 601 * The interrupt values are the same with the device tree when adding 16 602 */ 603 /* Secure EL1 timer GSIV */ 604 build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ + 16, 4); 605 /* Secure EL1 timer Flags */ 606 build_append_int_noprefix(table_data, irqflags, 4); 607 /* Non-Secure EL1 timer GSIV */ 608 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ + 16, 4); 609 /* Non-Secure EL1 timer Flags */ 610 build_append_int_noprefix(table_data, irqflags | 611 1UL << 2, /* Always-on Capability */ 612 4); 613 /* Virtual timer GSIV */ 614 build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ + 16, 4); 615 /* Virtual Timer Flags */ 616 build_append_int_noprefix(table_data, irqflags, 4); 617 /* Non-Secure EL2 timer GSIV */ 618 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ + 16, 4); 619 /* Non-Secure EL2 timer Flags */ 620 build_append_int_noprefix(table_data, irqflags, 4); 621 /* CntReadBase Physical address */ 622 build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8); 623 /* Platform Timer Count */ 624 build_append_int_noprefix(table_data, 0, 4); 625 /* Platform Timer Offset */ 626 build_append_int_noprefix(table_data, 0, 4); 627 628 acpi_table_end(linker, &table); 629 } 630 631 /* Debug Port Table 2 (DBG2) */ 632 static void 633 build_dbg2(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 634 { 635 AcpiTable table = { .sig = "DBG2", .rev = 0, .oem_id = vms->oem_id, 636 .oem_table_id = vms->oem_table_id }; 637 int dbg2devicelength; 638 const char name[] = "COM0"; 639 const int namespace_length = sizeof(name); 640 641 acpi_table_begin(&table, table_data); 642 643 dbg2devicelength = 22 + /* BaseAddressRegister[] offset */ 644 12 + /* BaseAddressRegister[] */ 645 4 + /* AddressSize[] */ 646 namespace_length /* NamespaceString[] */; 647 648 /* OffsetDbgDeviceInfo */ 649 build_append_int_noprefix(table_data, 44, 4); 650 /* NumberDbgDeviceInfo */ 651 build_append_int_noprefix(table_data, 1, 4); 652 653 /* Table 2. Debug Device Information structure format */ 654 build_append_int_noprefix(table_data, 0, 1); /* Revision */ 655 build_append_int_noprefix(table_data, dbg2devicelength, 2); /* Length */ 656 /* NumberofGenericAddressRegisters */ 657 build_append_int_noprefix(table_data, 1, 1); 658 /* NameSpaceStringLength */ 659 build_append_int_noprefix(table_data, namespace_length, 2); 660 build_append_int_noprefix(table_data, 38, 2); /* NameSpaceStringOffset */ 661 build_append_int_noprefix(table_data, 0, 2); /* OemDataLength */ 662 /* OemDataOffset (0 means no OEM data) */ 663 build_append_int_noprefix(table_data, 0, 2); 664 665 /* Port Type */ 666 build_append_int_noprefix(table_data, 0x8000 /* Serial */, 2); 667 /* Port Subtype */ 668 build_append_int_noprefix(table_data, 0x3 /* ARM PL011 UART */, 2); 669 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 670 /* BaseAddressRegisterOffset */ 671 build_append_int_noprefix(table_data, 22, 2); 672 /* AddressSizeOffset */ 673 build_append_int_noprefix(table_data, 34, 2); 674 675 /* BaseAddressRegister[] */ 676 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 8, 0, 1, 677 vms->memmap[VIRT_UART].base); 678 679 /* AddressSize[] */ 680 build_append_int_noprefix(table_data, 681 vms->memmap[VIRT_UART].size, 4); 682 683 /* NamespaceString[] */ 684 g_array_append_vals(table_data, name, namespace_length); 685 686 acpi_table_end(linker, &table); 687 }; 688 689 /* 690 * ACPI spec, Revision 6.0 Errata A 691 * 5.2.12 Multiple APIC Description Table (MADT) 692 */ 693 static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size) 694 { 695 build_append_int_noprefix(table_data, 0xE, 1); /* Type */ 696 build_append_int_noprefix(table_data, 16, 1); /* Length */ 697 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 698 /* Discovery Range Base Address */ 699 build_append_int_noprefix(table_data, base, 8); 700 build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */ 701 } 702 703 static void 704 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 705 { 706 int i; 707 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 708 const MemMapEntry *memmap = vms->memmap; 709 AcpiTable table = { .sig = "APIC", .rev = 4, .oem_id = vms->oem_id, 710 .oem_table_id = vms->oem_table_id }; 711 712 acpi_table_begin(&table, table_data); 713 /* Local Interrupt Controller Address */ 714 build_append_int_noprefix(table_data, 0, 4); 715 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 716 717 /* 5.2.12.15 GIC Distributor Structure */ 718 build_append_int_noprefix(table_data, 0xC, 1); /* Type */ 719 build_append_int_noprefix(table_data, 24, 1); /* Length */ 720 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 721 build_append_int_noprefix(table_data, 0, 4); /* GIC ID */ 722 /* Physical Base Address */ 723 build_append_int_noprefix(table_data, memmap[VIRT_GIC_DIST].base, 8); 724 build_append_int_noprefix(table_data, 0, 4); /* System Vector Base */ 725 /* GIC version */ 726 build_append_int_noprefix(table_data, vms->gic_version, 1); 727 build_append_int_noprefix(table_data, 0, 3); /* Reserved */ 728 729 for (i = 0; i < MACHINE(vms)->smp.cpus; i++) { 730 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 731 uint64_t physical_base_address = 0, gich = 0, gicv = 0; 732 uint32_t vgic_interrupt = vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : 0; 733 uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ? 734 PPI(VIRTUAL_PMU_IRQ) : 0; 735 736 if (vms->gic_version == VIRT_GIC_VERSION_2) { 737 physical_base_address = memmap[VIRT_GIC_CPU].base; 738 gicv = memmap[VIRT_GIC_VCPU].base; 739 gich = memmap[VIRT_GIC_HYP].base; 740 } 741 742 /* 5.2.12.14 GIC Structure */ 743 build_append_int_noprefix(table_data, 0xB, 1); /* Type */ 744 build_append_int_noprefix(table_data, 80, 1); /* Length */ 745 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 746 build_append_int_noprefix(table_data, i, 4); /* GIC ID */ 747 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ 748 /* Flags */ 749 build_append_int_noprefix(table_data, 1, 4); /* Enabled */ 750 /* Parking Protocol Version */ 751 build_append_int_noprefix(table_data, 0, 4); 752 /* Performance Interrupt GSIV */ 753 build_append_int_noprefix(table_data, pmu_interrupt, 4); 754 build_append_int_noprefix(table_data, 0, 8); /* Parked Address */ 755 /* Physical Base Address */ 756 build_append_int_noprefix(table_data, physical_base_address, 8); 757 build_append_int_noprefix(table_data, gicv, 8); /* GICV */ 758 build_append_int_noprefix(table_data, gich, 8); /* GICH */ 759 /* VGIC Maintenance interrupt */ 760 build_append_int_noprefix(table_data, vgic_interrupt, 4); 761 build_append_int_noprefix(table_data, 0, 8); /* GICR Base Address*/ 762 /* MPIDR */ 763 build_append_int_noprefix(table_data, armcpu->mp_affinity, 8); 764 /* Processor Power Efficiency Class */ 765 build_append_int_noprefix(table_data, 0, 1); 766 /* Reserved */ 767 build_append_int_noprefix(table_data, 0, 3); 768 } 769 770 if (vms->gic_version != VIRT_GIC_VERSION_2) { 771 build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base, 772 memmap[VIRT_GIC_REDIST].size); 773 if (virt_gicv3_redist_region_count(vms) == 2) { 774 build_append_gicr(table_data, memmap[VIRT_HIGH_GIC_REDIST2].base, 775 memmap[VIRT_HIGH_GIC_REDIST2].size); 776 } 777 778 if (its_class_name() && !vmc->no_its) { 779 /* 780 * ACPI spec, Revision 6.0 Errata A 781 * (original 6.0 definition has invalid Length) 782 * 5.2.12.18 GIC ITS Structure 783 */ 784 build_append_int_noprefix(table_data, 0xF, 1); /* Type */ 785 build_append_int_noprefix(table_data, 20, 1); /* Length */ 786 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 787 build_append_int_noprefix(table_data, 0, 4); /* GIC ITS ID */ 788 /* Physical Base Address */ 789 build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].base, 8); 790 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 791 } 792 } else { 793 const uint16_t spi_base = vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE; 794 795 /* 5.2.12.16 GIC MSI Frame Structure */ 796 build_append_int_noprefix(table_data, 0xD, 1); /* Type */ 797 build_append_int_noprefix(table_data, 24, 1); /* Length */ 798 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 799 build_append_int_noprefix(table_data, 0, 4); /* GIC MSI Frame ID */ 800 /* Physical Base Address */ 801 build_append_int_noprefix(table_data, memmap[VIRT_GIC_V2M].base, 8); 802 build_append_int_noprefix(table_data, 1, 4); /* Flags */ 803 /* SPI Count */ 804 build_append_int_noprefix(table_data, NUM_GICV2M_SPIS, 2); 805 build_append_int_noprefix(table_data, spi_base, 2); /* SPI Base */ 806 } 807 acpi_table_end(linker, &table); 808 } 809 810 /* FADT */ 811 static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker, 812 VirtMachineState *vms, unsigned dsdt_tbl_offset) 813 { 814 /* ACPI v6.0 */ 815 AcpiFadtData fadt = { 816 .rev = 6, 817 .minor_ver = 0, 818 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, 819 .xdsdt_tbl_offset = &dsdt_tbl_offset, 820 }; 821 822 switch (vms->psci_conduit) { 823 case QEMU_PSCI_CONDUIT_DISABLED: 824 fadt.arm_boot_arch = 0; 825 break; 826 case QEMU_PSCI_CONDUIT_HVC: 827 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT | 828 ACPI_FADT_ARM_PSCI_USE_HVC; 829 break; 830 case QEMU_PSCI_CONDUIT_SMC: 831 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT; 832 break; 833 default: 834 g_assert_not_reached(); 835 } 836 837 build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id); 838 } 839 840 /* DSDT */ 841 static void 842 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 843 { 844 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 845 Aml *scope, *dsdt; 846 MachineState *ms = MACHINE(vms); 847 const MemMapEntry *memmap = vms->memmap; 848 const int *irqmap = vms->irqmap; 849 AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = vms->oem_id, 850 .oem_table_id = vms->oem_table_id }; 851 852 acpi_table_begin(&table, table_data); 853 dsdt = init_aml_allocator(); 854 855 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. 856 * While UEFI can use libfdt to disable the RTC device node in the DTB that 857 * it passes to the OS, it cannot modify AML. Therefore, we won't generate 858 * the RTC ACPI device at all when using UEFI. 859 */ 860 scope = aml_scope("\\_SB"); 861 acpi_dsdt_add_cpus(scope, vms); 862 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], 863 (irqmap[VIRT_UART] + ARM_SPI_BASE)); 864 if (vmc->acpi_expose_flash) { 865 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); 866 } 867 acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); 868 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], 869 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); 870 acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms); 871 if (vms->acpi_dev) { 872 build_ged_aml(scope, "\\_SB."GED_DEVICE, 873 HOTPLUG_HANDLER(vms->acpi_dev), 874 irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY, 875 memmap[VIRT_ACPI_GED].base); 876 } else { 877 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], 878 (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); 879 } 880 881 if (vms->acpi_dev) { 882 uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev), 883 "ged-event", &error_abort); 884 885 if (event & ACPI_GED_MEM_HOTPLUG_EVT) { 886 build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL, 887 AML_SYSTEM_MEMORY, 888 memmap[VIRT_PCDIMM_ACPI].base); 889 } 890 } 891 892 acpi_dsdt_add_power_button(scope); 893 #ifdef CONFIG_TPM 894 acpi_dsdt_add_tpm(scope, vms); 895 #endif 896 897 aml_append(dsdt, scope); 898 899 /* copy AML table into ACPI tables blob */ 900 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 901 902 acpi_table_end(linker, &table); 903 free_aml_allocator(); 904 } 905 906 typedef 907 struct AcpiBuildState { 908 /* Copy of table in RAM (for patching). */ 909 MemoryRegion *table_mr; 910 MemoryRegion *rsdp_mr; 911 MemoryRegion *linker_mr; 912 /* Is table patched? */ 913 bool patched; 914 } AcpiBuildState; 915 916 static void acpi_align_size(GArray *blob, unsigned align) 917 { 918 /* 919 * Align size to multiple of given size. This reduces the chance 920 * we need to change size in the future (breaking cross version migration). 921 */ 922 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 923 } 924 925 static 926 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) 927 { 928 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 929 GArray *table_offsets; 930 unsigned dsdt, xsdt; 931 GArray *tables_blob = tables->table_data; 932 MachineState *ms = MACHINE(vms); 933 934 table_offsets = g_array_new(false, true /* clear */, 935 sizeof(uint32_t)); 936 937 bios_linker_loader_alloc(tables->linker, 938 ACPI_BUILD_TABLE_FILE, tables_blob, 939 64, false /* high memory */); 940 941 /* DSDT is pointed to by FADT */ 942 dsdt = tables_blob->len; 943 build_dsdt(tables_blob, tables->linker, vms); 944 945 /* FADT MADT PPTT GTDT MCFG SPCR DBG2 pointed to by RSDT */ 946 acpi_add_table(table_offsets, tables_blob); 947 build_fadt_rev6(tables_blob, tables->linker, vms, dsdt); 948 949 acpi_add_table(table_offsets, tables_blob); 950 build_madt(tables_blob, tables->linker, vms); 951 952 if (!vmc->no_cpu_topology) { 953 acpi_add_table(table_offsets, tables_blob); 954 build_pptt(tables_blob, tables->linker, ms, 955 vms->oem_id, vms->oem_table_id); 956 } 957 958 acpi_add_table(table_offsets, tables_blob); 959 build_gtdt(tables_blob, tables->linker, vms); 960 961 acpi_add_table(table_offsets, tables_blob); 962 { 963 AcpiMcfgInfo mcfg = { 964 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, 965 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, 966 }; 967 build_mcfg(tables_blob, tables->linker, &mcfg, vms->oem_id, 968 vms->oem_table_id); 969 } 970 971 acpi_add_table(table_offsets, tables_blob); 972 build_spcr(tables_blob, tables->linker, vms); 973 974 acpi_add_table(table_offsets, tables_blob); 975 build_dbg2(tables_blob, tables->linker, vms); 976 977 if (vms->ras) { 978 build_ghes_error_table(tables->hardware_errors, tables->linker); 979 acpi_add_table(table_offsets, tables_blob); 980 acpi_build_hest(tables_blob, tables->linker, vms->oem_id, 981 vms->oem_table_id); 982 } 983 984 if (ms->numa_state->num_nodes > 0) { 985 acpi_add_table(table_offsets, tables_blob); 986 build_srat(tables_blob, tables->linker, vms); 987 if (ms->numa_state->have_numa_distance) { 988 acpi_add_table(table_offsets, tables_blob); 989 build_slit(tables_blob, tables->linker, ms, vms->oem_id, 990 vms->oem_table_id); 991 } 992 993 if (ms->numa_state->hmat_enabled) { 994 acpi_add_table(table_offsets, tables_blob); 995 build_hmat(tables_blob, tables->linker, ms->numa_state, 996 vms->oem_id, vms->oem_table_id); 997 } 998 } 999 1000 if (ms->nvdimms_state->is_enabled) { 1001 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 1002 ms->nvdimms_state, ms->ram_slots, vms->oem_id, 1003 vms->oem_table_id); 1004 } 1005 1006 if (its_class_name() && !vmc->no_its) { 1007 acpi_add_table(table_offsets, tables_blob); 1008 build_iort(tables_blob, tables->linker, vms); 1009 } 1010 1011 #ifdef CONFIG_TPM 1012 if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) { 1013 acpi_add_table(table_offsets, tables_blob); 1014 build_tpm2(tables_blob, tables->linker, tables->tcpalog, vms->oem_id, 1015 vms->oem_table_id); 1016 } 1017 #endif 1018 1019 if (vms->iommu == VIRT_IOMMU_VIRTIO) { 1020 acpi_add_table(table_offsets, tables_blob); 1021 build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf, 1022 vms->oem_id, vms->oem_table_id); 1023 } 1024 1025 /* XSDT is pointed to by RSDP */ 1026 xsdt = tables_blob->len; 1027 build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id, 1028 vms->oem_table_id); 1029 1030 /* RSDP is in FSEG memory, so allocate it separately */ 1031 { 1032 AcpiRsdpData rsdp_data = { 1033 .revision = 2, 1034 .oem_id = vms->oem_id, 1035 .xsdt_tbl_offset = &xsdt, 1036 .rsdt_tbl_offset = NULL, 1037 }; 1038 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 1039 } 1040 1041 /* 1042 * The align size is 128, warn if 64k is not enough therefore 1043 * the align size could be resized. 1044 */ 1045 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 1046 warn_report("ACPI table size %u exceeds %d bytes," 1047 " migration may not work", 1048 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 1049 error_printf("Try removing CPUs, NUMA nodes, memory slots" 1050 " or PCI bridges."); 1051 } 1052 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 1053 1054 1055 /* Cleanup memory that's no longer used. */ 1056 g_array_free(table_offsets, true); 1057 } 1058 1059 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 1060 { 1061 uint32_t size = acpi_data_len(data); 1062 1063 /* Make sure RAM size is correct - in case it got changed 1064 * e.g. by migration */ 1065 memory_region_ram_resize(mr, size, &error_abort); 1066 1067 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 1068 memory_region_set_dirty(mr, 0, size); 1069 } 1070 1071 static void virt_acpi_build_update(void *build_opaque) 1072 { 1073 AcpiBuildState *build_state = build_opaque; 1074 AcpiBuildTables tables; 1075 1076 /* No state to update or already patched? Nothing to do. */ 1077 if (!build_state || build_state->patched) { 1078 return; 1079 } 1080 build_state->patched = true; 1081 1082 acpi_build_tables_init(&tables); 1083 1084 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables); 1085 1086 acpi_ram_update(build_state->table_mr, tables.table_data); 1087 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 1088 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 1089 1090 acpi_build_tables_cleanup(&tables, true); 1091 } 1092 1093 static void virt_acpi_build_reset(void *build_opaque) 1094 { 1095 AcpiBuildState *build_state = build_opaque; 1096 build_state->patched = false; 1097 } 1098 1099 static const VMStateDescription vmstate_virt_acpi_build = { 1100 .name = "virt_acpi_build", 1101 .version_id = 1, 1102 .minimum_version_id = 1, 1103 .fields = (VMStateField[]) { 1104 VMSTATE_BOOL(patched, AcpiBuildState), 1105 VMSTATE_END_OF_LIST() 1106 }, 1107 }; 1108 1109 void virt_acpi_setup(VirtMachineState *vms) 1110 { 1111 AcpiBuildTables tables; 1112 AcpiBuildState *build_state; 1113 AcpiGedState *acpi_ged_state; 1114 1115 if (!vms->fw_cfg) { 1116 trace_virt_acpi_setup(); 1117 return; 1118 } 1119 1120 if (!virt_is_acpi_enabled(vms)) { 1121 trace_virt_acpi_setup(); 1122 return; 1123 } 1124 1125 build_state = g_malloc0(sizeof *build_state); 1126 1127 acpi_build_tables_init(&tables); 1128 virt_acpi_build(vms, &tables); 1129 1130 /* Now expose it all to Guest */ 1131 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, 1132 build_state, tables.table_data, 1133 ACPI_BUILD_TABLE_FILE); 1134 assert(build_state->table_mr != NULL); 1135 1136 build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update, 1137 build_state, 1138 tables.linker->cmd_blob, 1139 ACPI_BUILD_LOADER_FILE); 1140 1141 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, 1142 acpi_data_len(tables.tcpalog)); 1143 1144 if (vms->ras) { 1145 assert(vms->acpi_dev); 1146 acpi_ged_state = ACPI_GED(vms->acpi_dev); 1147 acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state, 1148 vms->fw_cfg, tables.hardware_errors); 1149 } 1150 1151 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, 1152 build_state, tables.rsdp, 1153 ACPI_BUILD_RSDP_FILE); 1154 1155 qemu_register_reset(virt_acpi_build_reset, build_state); 1156 virt_acpi_build_reset(build_state); 1157 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 1158 1159 /* Cleanup tables but don't free the memory: we track it 1160 * in build_state. 1161 */ 1162 acpi_build_tables_cleanup(&tables, false); 1163 } 1164