1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * ARM virt ACPI generation 4 * 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 6 * Copyright (C) 2006 Fabrice Bellard 7 * Copyright (C) 2013 Red Hat Inc 8 * 9 * Author: Michael S. Tsirkin <mst@redhat.com> 10 * 11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 12 * 13 * Author: Shannon Zhao <zhaoshenglong@huawei.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "qapi/error.h" 31 #include "qemu/bitmap.h" 32 #include "qemu/error-report.h" 33 #include "trace.h" 34 #include "hw/core/cpu.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg_acpi.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/acpi/aml-build.h" 40 #include "hw/acpi/utils.h" 41 #include "hw/acpi/pci.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "hw/acpi/generic_event_device.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/hmat.h" 46 #include "hw/pci/pcie_host.h" 47 #include "hw/pci/pci.h" 48 #include "hw/pci/pci_bus.h" 49 #include "hw/pci-host/gpex.h" 50 #include "hw/arm/virt.h" 51 #include "hw/intc/arm_gicv3_its_common.h" 52 #include "hw/mem/nvdimm.h" 53 #include "hw/platform-bus.h" 54 #include "sysemu/numa.h" 55 #include "sysemu/reset.h" 56 #include "sysemu/tpm.h" 57 #include "migration/vmstate.h" 58 #include "hw/acpi/ghes.h" 59 #include "hw/acpi/viot.h" 60 #include "hw/virtio/virtio-acpi.h" 61 #include "target/arm/multiprocessing.h" 62 63 #define ARM_SPI_BASE 32 64 65 #define ACPI_BUILD_TABLE_SIZE 0x20000 66 67 static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms) 68 { 69 MachineState *ms = MACHINE(vms); 70 uint16_t i; 71 72 for (i = 0; i < ms->smp.cpus; i++) { 73 Aml *dev = aml_device("C%.03X", i); 74 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 75 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 76 aml_append(scope, dev); 77 } 78 } 79 80 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 81 uint32_t uart_irq) 82 { 83 Aml *dev = aml_device("COM0"); 84 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); 85 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 86 87 Aml *crs = aml_resource_template(); 88 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 89 uart_memmap->size, AML_READ_WRITE)); 90 aml_append(crs, 91 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 92 AML_EXCLUSIVE, &uart_irq, 1)); 93 aml_append(dev, aml_name_decl("_CRS", crs)); 94 95 aml_append(scope, dev); 96 } 97 98 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) 99 { 100 Aml *dev, *crs; 101 hwaddr base = flash_memmap->base; 102 hwaddr size = flash_memmap->size / 2; 103 104 dev = aml_device("FLS0"); 105 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 106 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 107 108 crs = aml_resource_template(); 109 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 110 aml_append(dev, aml_name_decl("_CRS", crs)); 111 aml_append(scope, dev); 112 113 dev = aml_device("FLS1"); 114 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 115 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 116 crs = aml_resource_template(); 117 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); 118 aml_append(dev, aml_name_decl("_CRS", crs)); 119 aml_append(scope, dev); 120 } 121 122 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, 123 uint32_t irq, VirtMachineState *vms) 124 { 125 int ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 126 struct GPEXConfig cfg = { 127 .mmio32 = memmap[VIRT_PCIE_MMIO], 128 .pio = memmap[VIRT_PCIE_PIO], 129 .ecam = memmap[ecam_id], 130 .irq = irq, 131 .bus = vms->bus, 132 }; 133 134 if (vms->highmem_mmio) { 135 cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO]; 136 } 137 138 acpi_dsdt_add_gpex(scope, &cfg); 139 } 140 141 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, 142 uint32_t gpio_irq) 143 { 144 Aml *dev = aml_device("GPO0"); 145 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); 146 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 147 148 Aml *crs = aml_resource_template(); 149 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, 150 AML_READ_WRITE)); 151 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 152 AML_EXCLUSIVE, &gpio_irq, 1)); 153 aml_append(dev, aml_name_decl("_CRS", crs)); 154 155 Aml *aei = aml_resource_template(); 156 /* Pin 3 for power button */ 157 const uint32_t pin_list[1] = {3}; 158 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, 159 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, 160 "GPO0", NULL, 0)); 161 aml_append(dev, aml_name_decl("_AEI", aei)); 162 163 /* _E03 is handle for power button */ 164 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); 165 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), 166 aml_int(0x80))); 167 aml_append(dev, method); 168 aml_append(scope, dev); 169 } 170 171 #ifdef CONFIG_TPM 172 static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms) 173 { 174 PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); 175 hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base; 176 SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find()); 177 MemoryRegion *sbdev_mr; 178 hwaddr tpm_base; 179 180 if (!sbdev) { 181 return; 182 } 183 184 tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); 185 assert(tpm_base != -1); 186 187 tpm_base += pbus_base; 188 189 sbdev_mr = sysbus_mmio_get_region(sbdev, 0); 190 191 Aml *dev = aml_device("TPM0"); 192 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 193 aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device"))); 194 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 195 196 Aml *crs = aml_resource_template(); 197 aml_append(crs, 198 aml_memory32_fixed(tpm_base, 199 (uint32_t)memory_region_size(sbdev_mr), 200 AML_READ_WRITE)); 201 aml_append(dev, aml_name_decl("_CRS", crs)); 202 aml_append(scope, dev); 203 } 204 #endif 205 206 #define ID_MAPPING_ENTRY_SIZE 20 207 #define SMMU_V3_ENTRY_SIZE 68 208 #define ROOT_COMPLEX_ENTRY_SIZE 36 209 #define IORT_NODE_OFFSET 48 210 211 static void build_iort_id_mapping(GArray *table_data, uint32_t input_base, 212 uint32_t id_count, uint32_t out_ref) 213 { 214 /* Table 4 ID mapping format */ 215 build_append_int_noprefix(table_data, input_base, 4); /* Input base */ 216 build_append_int_noprefix(table_data, id_count, 4); /* Number of IDs */ 217 build_append_int_noprefix(table_data, input_base, 4); /* Output base */ 218 build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference */ 219 /* Flags */ 220 build_append_int_noprefix(table_data, 0 /* Single mapping (disabled) */, 4); 221 } 222 223 struct AcpiIortIdMapping { 224 uint32_t input_base; 225 uint32_t id_count; 226 }; 227 typedef struct AcpiIortIdMapping AcpiIortIdMapping; 228 229 /* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */ 230 static int 231 iort_host_bridges(Object *obj, void *opaque) 232 { 233 GArray *idmap_blob = opaque; 234 235 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 236 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 237 238 if (bus && !pci_bus_bypass_iommu(bus)) { 239 int min_bus, max_bus; 240 241 pci_bus_range(bus, &min_bus, &max_bus); 242 243 AcpiIortIdMapping idmap = { 244 .input_base = min_bus << 8, 245 .id_count = (max_bus - min_bus + 1) << 8, 246 }; 247 g_array_append_val(idmap_blob, idmap); 248 } 249 } 250 251 return 0; 252 } 253 254 static int iort_idmap_compare(gconstpointer a, gconstpointer b) 255 { 256 AcpiIortIdMapping *idmap_a = (AcpiIortIdMapping *)a; 257 AcpiIortIdMapping *idmap_b = (AcpiIortIdMapping *)b; 258 259 return idmap_a->input_base - idmap_b->input_base; 260 } 261 262 /* 263 * Input Output Remapping Table (IORT) 264 * Conforms to "IO Remapping Table System Software on ARM Platforms", 265 * Document number: ARM DEN 0049E.b, Feb 2021 266 */ 267 static void 268 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 269 { 270 int i, nb_nodes, rc_mapping_count; 271 const uint32_t iort_node_offset = IORT_NODE_OFFSET; 272 size_t node_size, smmu_offset = 0; 273 AcpiIortIdMapping *idmap; 274 uint32_t id = 0; 275 GArray *smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); 276 GArray *its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); 277 278 AcpiTable table = { .sig = "IORT", .rev = 3, .oem_id = vms->oem_id, 279 .oem_table_id = vms->oem_table_id }; 280 /* Table 2 The IORT */ 281 acpi_table_begin(&table, table_data); 282 283 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 284 AcpiIortIdMapping next_range = {0}; 285 286 object_child_foreach_recursive(object_get_root(), 287 iort_host_bridges, smmu_idmaps); 288 289 /* Sort the smmu idmap by input_base */ 290 g_array_sort(smmu_idmaps, iort_idmap_compare); 291 292 /* 293 * Split the whole RIDs by mapping from RC to SMMU, 294 * build the ID mapping from RC to ITS directly. 295 */ 296 for (i = 0; i < smmu_idmaps->len; i++) { 297 idmap = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); 298 299 if (next_range.input_base < idmap->input_base) { 300 next_range.id_count = idmap->input_base - next_range.input_base; 301 g_array_append_val(its_idmaps, next_range); 302 } 303 304 next_range.input_base = idmap->input_base + idmap->id_count; 305 } 306 307 /* Append the last RC -> ITS ID mapping */ 308 if (next_range.input_base < 0xFFFF) { 309 next_range.id_count = 0xFFFF - next_range.input_base; 310 g_array_append_val(its_idmaps, next_range); 311 } 312 313 nb_nodes = 3; /* RC, ITS, SMMUv3 */ 314 rc_mapping_count = smmu_idmaps->len + its_idmaps->len; 315 } else { 316 nb_nodes = 2; /* RC, ITS */ 317 rc_mapping_count = 1; 318 } 319 /* Number of IORT Nodes */ 320 build_append_int_noprefix(table_data, nb_nodes, 4); 321 322 /* Offset to Array of IORT Nodes */ 323 build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4); 324 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 325 326 /* Table 12 ITS Group Format */ 327 build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */ 328 node_size = 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */; 329 build_append_int_noprefix(table_data, node_size, 2); /* Length */ 330 build_append_int_noprefix(table_data, 1, 1); /* Revision */ 331 build_append_int_noprefix(table_data, id++, 4); /* Identifier */ 332 build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */ 333 build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */ 334 build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */ 335 /* GIC ITS Identifier Array */ 336 build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4); 337 338 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 339 int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; 340 341 smmu_offset = table_data->len - table.table_offset; 342 /* Table 9 SMMUv3 Format */ 343 build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type */ 344 node_size = SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE; 345 build_append_int_noprefix(table_data, node_size, 2); /* Length */ 346 build_append_int_noprefix(table_data, 4, 1); /* Revision */ 347 build_append_int_noprefix(table_data, id++, 4); /* Identifier */ 348 build_append_int_noprefix(table_data, 1, 4); /* Number of ID mappings */ 349 /* Reference to ID Array */ 350 build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4); 351 /* Base address */ 352 build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base, 8); 353 /* Flags */ 354 build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4); 355 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 356 build_append_int_noprefix(table_data, 0, 8); /* VATOS address */ 357 /* Model */ 358 build_append_int_noprefix(table_data, 0 /* Generic SMMU-v3 */, 4); 359 build_append_int_noprefix(table_data, irq, 4); /* Event */ 360 build_append_int_noprefix(table_data, irq + 1, 4); /* PRI */ 361 build_append_int_noprefix(table_data, irq + 3, 4); /* GERR */ 362 build_append_int_noprefix(table_data, irq + 2, 4); /* Sync */ 363 build_append_int_noprefix(table_data, 0, 4); /* Proximity domain */ 364 /* DeviceID mapping index (ignored since interrupts are GSIV based) */ 365 build_append_int_noprefix(table_data, 0, 4); 366 367 /* output IORT node is the ITS group node (the first node) */ 368 build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET); 369 } 370 371 /* Table 17 Root Complex Node */ 372 build_append_int_noprefix(table_data, 2 /* Root complex */, 1); /* Type */ 373 node_size = ROOT_COMPLEX_ENTRY_SIZE + 374 ID_MAPPING_ENTRY_SIZE * rc_mapping_count; 375 build_append_int_noprefix(table_data, node_size, 2); /* Length */ 376 build_append_int_noprefix(table_data, 3, 1); /* Revision */ 377 build_append_int_noprefix(table_data, id++, 4); /* Identifier */ 378 /* Number of ID mappings */ 379 build_append_int_noprefix(table_data, rc_mapping_count, 4); 380 /* Reference to ID Array */ 381 build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 4); 382 383 /* Table 14 Memory access properties */ 384 /* CCA: Cache Coherent Attribute */ 385 build_append_int_noprefix(table_data, 1 /* fully coherent */, 4); 386 build_append_int_noprefix(table_data, 0, 1); /* AH: Note Allocation Hints */ 387 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 388 /* Table 15 Memory Access Flags */ 389 build_append_int_noprefix(table_data, 0x3 /* CCA = CPM = DACS = 1 */, 1); 390 391 build_append_int_noprefix(table_data, 0, 4); /* ATS Attribute */ 392 /* MCFG pci_segment */ 393 build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */ 394 395 /* Memory address size limit */ 396 build_append_int_noprefix(table_data, 64, 1); 397 398 build_append_int_noprefix(table_data, 0, 3); /* Reserved */ 399 400 /* Output Reference */ 401 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 402 AcpiIortIdMapping *range; 403 404 /* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */ 405 for (i = 0; i < smmu_idmaps->len; i++) { 406 range = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); 407 /* output IORT node is the smmuv3 node */ 408 build_iort_id_mapping(table_data, range->input_base, 409 range->id_count, smmu_offset); 410 } 411 412 /* bypassed RIDs connect to ITS group node directly: RC -> ITS */ 413 for (i = 0; i < its_idmaps->len; i++) { 414 range = &g_array_index(its_idmaps, AcpiIortIdMapping, i); 415 /* output IORT node is the ITS group node (the first node) */ 416 build_iort_id_mapping(table_data, range->input_base, 417 range->id_count, iort_node_offset); 418 } 419 } else { 420 /* output IORT node is the ITS group node (the first node) */ 421 build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET); 422 } 423 424 acpi_table_end(linker, &table); 425 g_array_free(smmu_idmaps, true); 426 g_array_free(its_idmaps, true); 427 } 428 429 /* 430 * Serial Port Console Redirection Table (SPCR) 431 * Rev: 1.07 432 */ 433 static void 434 spcr_setup(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 435 { 436 AcpiSpcrData serial = { 437 .interface_type = 3, /* ARM PL011 UART */ 438 .base_addr.id = AML_AS_SYSTEM_MEMORY, 439 .base_addr.width = 32, 440 .base_addr.offset = 0, 441 .base_addr.size = 3, 442 .base_addr.addr = vms->memmap[VIRT_UART].base, 443 .interrupt_type = (1 << 3),/* Bit[3] ARMH GIC interrupt*/ 444 .pc_interrupt = 0, /* IRQ */ 445 .interrupt = (vms->irqmap[VIRT_UART] + ARM_SPI_BASE), 446 .baud_rate = 3, /* 9600 */ 447 .parity = 0, /* No Parity */ 448 .stop_bits = 1, /* 1 Stop bit */ 449 .flow_control = 1 << 1, /* RTS/CTS hardware flow control */ 450 .terminal_type = 0, /* VT100 */ 451 .language = 0, /* Language */ 452 .pci_device_id = 0xffff, /* not a PCI device*/ 453 .pci_vendor_id = 0xffff, /* not a PCI device*/ 454 .pci_bus = 0, 455 .pci_device = 0, 456 .pci_function = 0, 457 .pci_flags = 0, 458 .pci_segment = 0, 459 }; 460 461 build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id); 462 } 463 464 /* 465 * ACPI spec, Revision 5.1 466 * 5.2.16 System Resource Affinity Table (SRAT) 467 */ 468 static void 469 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 470 { 471 int i; 472 uint64_t mem_base; 473 MachineClass *mc = MACHINE_GET_CLASS(vms); 474 MachineState *ms = MACHINE(vms); 475 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); 476 AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id, 477 .oem_table_id = vms->oem_table_id }; 478 479 acpi_table_begin(&table, table_data); 480 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 481 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 482 483 for (i = 0; i < cpu_list->len; ++i) { 484 uint32_t nodeid = cpu_list->cpus[i].props.node_id; 485 /* 486 * 5.2.16.4 GICC Affinity Structure 487 */ 488 build_append_int_noprefix(table_data, 3, 1); /* Type */ 489 build_append_int_noprefix(table_data, 18, 1); /* Length */ 490 build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */ 491 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ 492 /* Flags, Table 5-76 */ 493 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 494 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 495 } 496 497 mem_base = vms->memmap[VIRT_MEM].base; 498 for (i = 0; i < ms->numa_state->num_nodes; ++i) { 499 if (ms->numa_state->nodes[i].node_mem > 0) { 500 build_srat_memory(table_data, mem_base, 501 ms->numa_state->nodes[i].node_mem, i, 502 MEM_AFFINITY_ENABLED); 503 mem_base += ms->numa_state->nodes[i].node_mem; 504 } 505 } 506 507 if (ms->nvdimms_state->is_enabled) { 508 nvdimm_build_srat(table_data); 509 } 510 511 if (ms->device_memory) { 512 build_srat_memory(table_data, ms->device_memory->base, 513 memory_region_size(&ms->device_memory->mr), 514 ms->numa_state->num_nodes - 1, 515 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 516 } 517 518 acpi_table_end(linker, &table); 519 } 520 521 /* 522 * ACPI spec, Revision 6.5 523 * 5.2.25 Generic Timer Description Table (GTDT) 524 */ 525 static void 526 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 527 { 528 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 529 /* 530 * Table 5-117 Flag Definitions 531 * set only "Timer interrupt Mode" and assume "Timer Interrupt 532 * polarity" bit as '0: Interrupt is Active high' 533 */ 534 uint32_t irqflags = vmc->claim_edge_triggered_timers ? 535 1 : /* Interrupt is Edge triggered */ 536 0; /* Interrupt is Level triggered */ 537 AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id, 538 .oem_table_id = vms->oem_table_id }; 539 540 acpi_table_begin(&table, table_data); 541 542 /* CntControlBase Physical Address */ 543 build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8); 544 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 545 /* 546 * FIXME: clarify comment: 547 * The interrupt values are the same with the device tree when adding 16 548 */ 549 /* Secure EL1 timer GSIV */ 550 build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ, 4); 551 /* Secure EL1 timer Flags */ 552 build_append_int_noprefix(table_data, irqflags, 4); 553 /* Non-Secure EL1 timer GSIV */ 554 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ, 4); 555 /* Non-Secure EL1 timer Flags */ 556 build_append_int_noprefix(table_data, irqflags | 557 1UL << 2, /* Always-on Capability */ 558 4); 559 /* Virtual timer GSIV */ 560 build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ, 4); 561 /* Virtual Timer Flags */ 562 build_append_int_noprefix(table_data, irqflags, 4); 563 /* Non-Secure EL2 timer GSIV */ 564 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ, 4); 565 /* Non-Secure EL2 timer Flags */ 566 build_append_int_noprefix(table_data, irqflags, 4); 567 /* CntReadBase Physical address */ 568 build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8); 569 /* Platform Timer Count */ 570 build_append_int_noprefix(table_data, 0, 4); 571 /* Platform Timer Offset */ 572 build_append_int_noprefix(table_data, 0, 4); 573 if (vms->ns_el2_virt_timer_irq) { 574 /* Virtual EL2 Timer GSIV */ 575 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, 4); 576 /* Virtual EL2 Timer Flags */ 577 build_append_int_noprefix(table_data, irqflags, 4); 578 } else { 579 build_append_int_noprefix(table_data, 0, 4); 580 build_append_int_noprefix(table_data, 0, 4); 581 } 582 acpi_table_end(linker, &table); 583 } 584 585 /* Debug Port Table 2 (DBG2) */ 586 static void 587 build_dbg2(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 588 { 589 AcpiTable table = { .sig = "DBG2", .rev = 0, .oem_id = vms->oem_id, 590 .oem_table_id = vms->oem_table_id }; 591 int dbg2devicelength; 592 const char name[] = "COM0"; 593 const int namespace_length = sizeof(name); 594 595 acpi_table_begin(&table, table_data); 596 597 dbg2devicelength = 22 + /* BaseAddressRegister[] offset */ 598 12 + /* BaseAddressRegister[] */ 599 4 + /* AddressSize[] */ 600 namespace_length /* NamespaceString[] */; 601 602 /* OffsetDbgDeviceInfo */ 603 build_append_int_noprefix(table_data, 44, 4); 604 /* NumberDbgDeviceInfo */ 605 build_append_int_noprefix(table_data, 1, 4); 606 607 /* Table 2. Debug Device Information structure format */ 608 build_append_int_noprefix(table_data, 0, 1); /* Revision */ 609 build_append_int_noprefix(table_data, dbg2devicelength, 2); /* Length */ 610 /* NumberofGenericAddressRegisters */ 611 build_append_int_noprefix(table_data, 1, 1); 612 /* NameSpaceStringLength */ 613 build_append_int_noprefix(table_data, namespace_length, 2); 614 build_append_int_noprefix(table_data, 38, 2); /* NameSpaceStringOffset */ 615 build_append_int_noprefix(table_data, 0, 2); /* OemDataLength */ 616 /* OemDataOffset (0 means no OEM data) */ 617 build_append_int_noprefix(table_data, 0, 2); 618 619 /* Port Type */ 620 build_append_int_noprefix(table_data, 0x8000 /* Serial */, 2); 621 /* Port Subtype */ 622 build_append_int_noprefix(table_data, 0x3 /* ARM PL011 UART */, 2); 623 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 624 /* BaseAddressRegisterOffset */ 625 build_append_int_noprefix(table_data, 22, 2); 626 /* AddressSizeOffset */ 627 build_append_int_noprefix(table_data, 34, 2); 628 629 /* BaseAddressRegister[] */ 630 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3, 631 vms->memmap[VIRT_UART].base); 632 633 /* AddressSize[] */ 634 build_append_int_noprefix(table_data, 635 vms->memmap[VIRT_UART].size, 4); 636 637 /* NamespaceString[] */ 638 g_array_append_vals(table_data, name, namespace_length); 639 640 acpi_table_end(linker, &table); 641 }; 642 643 /* 644 * ACPI spec, Revision 6.0 Errata A 645 * 5.2.12 Multiple APIC Description Table (MADT) 646 */ 647 static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size) 648 { 649 build_append_int_noprefix(table_data, 0xE, 1); /* Type */ 650 build_append_int_noprefix(table_data, 16, 1); /* Length */ 651 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 652 /* Discovery Range Base Address */ 653 build_append_int_noprefix(table_data, base, 8); 654 build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */ 655 } 656 657 static void 658 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 659 { 660 int i; 661 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 662 const MemMapEntry *memmap = vms->memmap; 663 AcpiTable table = { .sig = "APIC", .rev = 4, .oem_id = vms->oem_id, 664 .oem_table_id = vms->oem_table_id }; 665 666 acpi_table_begin(&table, table_data); 667 /* Local Interrupt Controller Address */ 668 build_append_int_noprefix(table_data, 0, 4); 669 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 670 671 /* 5.2.12.15 GIC Distributor Structure */ 672 build_append_int_noprefix(table_data, 0xC, 1); /* Type */ 673 build_append_int_noprefix(table_data, 24, 1); /* Length */ 674 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 675 build_append_int_noprefix(table_data, 0, 4); /* GIC ID */ 676 /* Physical Base Address */ 677 build_append_int_noprefix(table_data, memmap[VIRT_GIC_DIST].base, 8); 678 build_append_int_noprefix(table_data, 0, 4); /* System Vector Base */ 679 /* GIC version */ 680 build_append_int_noprefix(table_data, vms->gic_version, 1); 681 build_append_int_noprefix(table_data, 0, 3); /* Reserved */ 682 683 for (i = 0; i < MACHINE(vms)->smp.cpus; i++) { 684 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 685 uint64_t physical_base_address = 0, gich = 0, gicv = 0; 686 uint32_t vgic_interrupt = vms->virt ? ARCH_GIC_MAINT_IRQ : 0; 687 uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ? 688 VIRTUAL_PMU_IRQ : 0; 689 690 if (vms->gic_version == VIRT_GIC_VERSION_2) { 691 physical_base_address = memmap[VIRT_GIC_CPU].base; 692 gicv = memmap[VIRT_GIC_VCPU].base; 693 gich = memmap[VIRT_GIC_HYP].base; 694 } 695 696 /* 5.2.12.14 GIC Structure */ 697 build_append_int_noprefix(table_data, 0xB, 1); /* Type */ 698 build_append_int_noprefix(table_data, 80, 1); /* Length */ 699 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 700 build_append_int_noprefix(table_data, i, 4); /* GIC ID */ 701 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ 702 /* Flags */ 703 build_append_int_noprefix(table_data, 1, 4); /* Enabled */ 704 /* Parking Protocol Version */ 705 build_append_int_noprefix(table_data, 0, 4); 706 /* Performance Interrupt GSIV */ 707 build_append_int_noprefix(table_data, pmu_interrupt, 4); 708 build_append_int_noprefix(table_data, 0, 8); /* Parked Address */ 709 /* Physical Base Address */ 710 build_append_int_noprefix(table_data, physical_base_address, 8); 711 build_append_int_noprefix(table_data, gicv, 8); /* GICV */ 712 build_append_int_noprefix(table_data, gich, 8); /* GICH */ 713 /* VGIC Maintenance interrupt */ 714 build_append_int_noprefix(table_data, vgic_interrupt, 4); 715 build_append_int_noprefix(table_data, 0, 8); /* GICR Base Address*/ 716 /* MPIDR */ 717 build_append_int_noprefix(table_data, arm_cpu_mp_affinity(armcpu), 8); 718 /* Processor Power Efficiency Class */ 719 build_append_int_noprefix(table_data, 0, 1); 720 /* Reserved */ 721 build_append_int_noprefix(table_data, 0, 3); 722 } 723 724 if (vms->gic_version != VIRT_GIC_VERSION_2) { 725 build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base, 726 memmap[VIRT_GIC_REDIST].size); 727 if (virt_gicv3_redist_region_count(vms) == 2) { 728 build_append_gicr(table_data, memmap[VIRT_HIGH_GIC_REDIST2].base, 729 memmap[VIRT_HIGH_GIC_REDIST2].size); 730 } 731 732 if (its_class_name() && !vmc->no_its) { 733 /* 734 * ACPI spec, Revision 6.0 Errata A 735 * (original 6.0 definition has invalid Length) 736 * 5.2.12.18 GIC ITS Structure 737 */ 738 build_append_int_noprefix(table_data, 0xF, 1); /* Type */ 739 build_append_int_noprefix(table_data, 20, 1); /* Length */ 740 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 741 build_append_int_noprefix(table_data, 0, 4); /* GIC ITS ID */ 742 /* Physical Base Address */ 743 build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].base, 8); 744 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 745 } 746 } else { 747 const uint16_t spi_base = vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE; 748 749 /* 5.2.12.16 GIC MSI Frame Structure */ 750 build_append_int_noprefix(table_data, 0xD, 1); /* Type */ 751 build_append_int_noprefix(table_data, 24, 1); /* Length */ 752 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 753 build_append_int_noprefix(table_data, 0, 4); /* GIC MSI Frame ID */ 754 /* Physical Base Address */ 755 build_append_int_noprefix(table_data, memmap[VIRT_GIC_V2M].base, 8); 756 build_append_int_noprefix(table_data, 1, 4); /* Flags */ 757 /* SPI Count */ 758 build_append_int_noprefix(table_data, NUM_GICV2M_SPIS, 2); 759 build_append_int_noprefix(table_data, spi_base, 2); /* SPI Base */ 760 } 761 acpi_table_end(linker, &table); 762 } 763 764 /* FADT */ 765 static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker, 766 VirtMachineState *vms, unsigned dsdt_tbl_offset) 767 { 768 /* ACPI v6.3 */ 769 AcpiFadtData fadt = { 770 .rev = 6, 771 .minor_ver = 3, 772 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, 773 .xdsdt_tbl_offset = &dsdt_tbl_offset, 774 }; 775 776 switch (vms->psci_conduit) { 777 case QEMU_PSCI_CONDUIT_DISABLED: 778 fadt.arm_boot_arch = 0; 779 break; 780 case QEMU_PSCI_CONDUIT_HVC: 781 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT | 782 ACPI_FADT_ARM_PSCI_USE_HVC; 783 break; 784 case QEMU_PSCI_CONDUIT_SMC: 785 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT; 786 break; 787 default: 788 g_assert_not_reached(); 789 } 790 791 build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id); 792 } 793 794 /* DSDT */ 795 static void 796 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 797 { 798 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 799 Aml *scope, *dsdt; 800 MachineState *ms = MACHINE(vms); 801 const MemMapEntry *memmap = vms->memmap; 802 const int *irqmap = vms->irqmap; 803 AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = vms->oem_id, 804 .oem_table_id = vms->oem_table_id }; 805 806 acpi_table_begin(&table, table_data); 807 dsdt = init_aml_allocator(); 808 809 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. 810 * While UEFI can use libfdt to disable the RTC device node in the DTB that 811 * it passes to the OS, it cannot modify AML. Therefore, we won't generate 812 * the RTC ACPI device at all when using UEFI. 813 */ 814 scope = aml_scope("\\_SB"); 815 acpi_dsdt_add_cpus(scope, vms); 816 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], 817 (irqmap[VIRT_UART] + ARM_SPI_BASE)); 818 if (vmc->acpi_expose_flash) { 819 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); 820 } 821 fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]); 822 virtio_acpi_dsdt_add(scope, memmap[VIRT_MMIO].base, memmap[VIRT_MMIO].size, 823 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), 824 0, NUM_VIRTIO_TRANSPORTS); 825 acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms); 826 if (vms->acpi_dev) { 827 build_ged_aml(scope, "\\_SB."GED_DEVICE, 828 HOTPLUG_HANDLER(vms->acpi_dev), 829 irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY, 830 memmap[VIRT_ACPI_GED].base); 831 } else { 832 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], 833 (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); 834 } 835 836 if (vms->acpi_dev) { 837 uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev), 838 "ged-event", &error_abort); 839 840 if (event & ACPI_GED_MEM_HOTPLUG_EVT) { 841 build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL, 842 AML_SYSTEM_MEMORY, 843 memmap[VIRT_PCDIMM_ACPI].base); 844 } 845 } 846 847 acpi_dsdt_add_power_button(scope); 848 #ifdef CONFIG_TPM 849 acpi_dsdt_add_tpm(scope, vms); 850 #endif 851 852 aml_append(dsdt, scope); 853 854 /* copy AML table into ACPI tables blob */ 855 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 856 857 acpi_table_end(linker, &table); 858 free_aml_allocator(); 859 } 860 861 typedef 862 struct AcpiBuildState { 863 /* Copy of table in RAM (for patching). */ 864 MemoryRegion *table_mr; 865 MemoryRegion *rsdp_mr; 866 MemoryRegion *linker_mr; 867 /* Is table patched? */ 868 bool patched; 869 } AcpiBuildState; 870 871 static void acpi_align_size(GArray *blob, unsigned align) 872 { 873 /* 874 * Align size to multiple of given size. This reduces the chance 875 * we need to change size in the future (breaking cross version migration). 876 */ 877 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 878 } 879 880 static 881 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) 882 { 883 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 884 GArray *table_offsets; 885 unsigned dsdt, xsdt; 886 GArray *tables_blob = tables->table_data; 887 MachineState *ms = MACHINE(vms); 888 889 table_offsets = g_array_new(false, true /* clear */, 890 sizeof(uint32_t)); 891 892 bios_linker_loader_alloc(tables->linker, 893 ACPI_BUILD_TABLE_FILE, tables_blob, 894 64, false /* high memory */); 895 896 /* DSDT is pointed to by FADT */ 897 dsdt = tables_blob->len; 898 build_dsdt(tables_blob, tables->linker, vms); 899 900 /* FADT MADT PPTT GTDT MCFG SPCR DBG2 pointed to by RSDT */ 901 acpi_add_table(table_offsets, tables_blob); 902 build_fadt_rev6(tables_blob, tables->linker, vms, dsdt); 903 904 acpi_add_table(table_offsets, tables_blob); 905 build_madt(tables_blob, tables->linker, vms); 906 907 if (!vmc->no_cpu_topology) { 908 acpi_add_table(table_offsets, tables_blob); 909 build_pptt(tables_blob, tables->linker, ms, 910 vms->oem_id, vms->oem_table_id); 911 } 912 913 acpi_add_table(table_offsets, tables_blob); 914 build_gtdt(tables_blob, tables->linker, vms); 915 916 acpi_add_table(table_offsets, tables_blob); 917 { 918 AcpiMcfgInfo mcfg = { 919 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, 920 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, 921 }; 922 build_mcfg(tables_blob, tables->linker, &mcfg, vms->oem_id, 923 vms->oem_table_id); 924 } 925 926 acpi_add_table(table_offsets, tables_blob); 927 spcr_setup(tables_blob, tables->linker, vms); 928 929 acpi_add_table(table_offsets, tables_blob); 930 build_dbg2(tables_blob, tables->linker, vms); 931 932 if (vms->ras) { 933 build_ghes_error_table(tables->hardware_errors, tables->linker); 934 acpi_add_table(table_offsets, tables_blob); 935 acpi_build_hest(tables_blob, tables->linker, vms->oem_id, 936 vms->oem_table_id); 937 } 938 939 if (ms->numa_state->num_nodes > 0) { 940 acpi_add_table(table_offsets, tables_blob); 941 build_srat(tables_blob, tables->linker, vms); 942 if (ms->numa_state->have_numa_distance) { 943 acpi_add_table(table_offsets, tables_blob); 944 build_slit(tables_blob, tables->linker, ms, vms->oem_id, 945 vms->oem_table_id); 946 } 947 948 if (ms->numa_state->hmat_enabled) { 949 acpi_add_table(table_offsets, tables_blob); 950 build_hmat(tables_blob, tables->linker, ms->numa_state, 951 vms->oem_id, vms->oem_table_id); 952 } 953 } 954 955 if (ms->nvdimms_state->is_enabled) { 956 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 957 ms->nvdimms_state, ms->ram_slots, vms->oem_id, 958 vms->oem_table_id); 959 } 960 961 if (its_class_name() && !vmc->no_its) { 962 acpi_add_table(table_offsets, tables_blob); 963 build_iort(tables_blob, tables->linker, vms); 964 } 965 966 #ifdef CONFIG_TPM 967 if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) { 968 acpi_add_table(table_offsets, tables_blob); 969 build_tpm2(tables_blob, tables->linker, tables->tcpalog, vms->oem_id, 970 vms->oem_table_id); 971 } 972 #endif 973 974 if (vms->iommu == VIRT_IOMMU_VIRTIO) { 975 acpi_add_table(table_offsets, tables_blob); 976 build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf, 977 vms->oem_id, vms->oem_table_id); 978 } 979 980 /* XSDT is pointed to by RSDP */ 981 xsdt = tables_blob->len; 982 build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id, 983 vms->oem_table_id); 984 985 /* RSDP is in FSEG memory, so allocate it separately */ 986 { 987 AcpiRsdpData rsdp_data = { 988 .revision = 2, 989 .oem_id = vms->oem_id, 990 .xsdt_tbl_offset = &xsdt, 991 .rsdt_tbl_offset = NULL, 992 }; 993 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 994 } 995 996 /* 997 * The align size is 128, warn if 64k is not enough therefore 998 * the align size could be resized. 999 */ 1000 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 1001 warn_report("ACPI table size %u exceeds %d bytes," 1002 " migration may not work", 1003 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 1004 error_printf("Try removing CPUs, NUMA nodes, memory slots" 1005 " or PCI bridges.\n"); 1006 } 1007 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 1008 1009 1010 /* Cleanup memory that's no longer used. */ 1011 g_array_free(table_offsets, true); 1012 } 1013 1014 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 1015 { 1016 uint32_t size = acpi_data_len(data); 1017 1018 /* Make sure RAM size is correct - in case it got changed 1019 * e.g. by migration */ 1020 memory_region_ram_resize(mr, size, &error_abort); 1021 1022 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 1023 memory_region_set_dirty(mr, 0, size); 1024 } 1025 1026 static void virt_acpi_build_update(void *build_opaque) 1027 { 1028 AcpiBuildState *build_state = build_opaque; 1029 AcpiBuildTables tables; 1030 1031 /* No state to update or already patched? Nothing to do. */ 1032 if (!build_state || build_state->patched) { 1033 return; 1034 } 1035 build_state->patched = true; 1036 1037 acpi_build_tables_init(&tables); 1038 1039 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables); 1040 1041 acpi_ram_update(build_state->table_mr, tables.table_data); 1042 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 1043 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 1044 1045 acpi_build_tables_cleanup(&tables, true); 1046 } 1047 1048 static void virt_acpi_build_reset(void *build_opaque) 1049 { 1050 AcpiBuildState *build_state = build_opaque; 1051 build_state->patched = false; 1052 } 1053 1054 static const VMStateDescription vmstate_virt_acpi_build = { 1055 .name = "virt_acpi_build", 1056 .version_id = 1, 1057 .minimum_version_id = 1, 1058 .fields = (const VMStateField[]) { 1059 VMSTATE_BOOL(patched, AcpiBuildState), 1060 VMSTATE_END_OF_LIST() 1061 }, 1062 }; 1063 1064 void virt_acpi_setup(VirtMachineState *vms) 1065 { 1066 AcpiBuildTables tables; 1067 AcpiBuildState *build_state; 1068 AcpiGedState *acpi_ged_state; 1069 1070 if (!vms->fw_cfg) { 1071 trace_virt_acpi_setup(); 1072 return; 1073 } 1074 1075 if (!virt_is_acpi_enabled(vms)) { 1076 trace_virt_acpi_setup(); 1077 return; 1078 } 1079 1080 build_state = g_malloc0(sizeof *build_state); 1081 1082 acpi_build_tables_init(&tables); 1083 virt_acpi_build(vms, &tables); 1084 1085 /* Now expose it all to Guest */ 1086 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, 1087 build_state, tables.table_data, 1088 ACPI_BUILD_TABLE_FILE); 1089 assert(build_state->table_mr != NULL); 1090 1091 build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update, 1092 build_state, 1093 tables.linker->cmd_blob, 1094 ACPI_BUILD_LOADER_FILE); 1095 1096 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, 1097 acpi_data_len(tables.tcpalog)); 1098 1099 if (vms->ras) { 1100 assert(vms->acpi_dev); 1101 acpi_ged_state = ACPI_GED(vms->acpi_dev); 1102 acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state, 1103 vms->fw_cfg, tables.hardware_errors); 1104 } 1105 1106 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, 1107 build_state, tables.rsdp, 1108 ACPI_BUILD_RSDP_FILE); 1109 1110 qemu_register_reset(virt_acpi_build_reset, build_state); 1111 virt_acpi_build_reset(build_state); 1112 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 1113 1114 /* Cleanup tables but don't free the memory: we track it 1115 * in build_state. 1116 */ 1117 acpi_build_tables_cleanup(&tables, false); 1118 } 1119