1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * ARM virt ACPI generation 4 * 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 6 * Copyright (C) 2006 Fabrice Bellard 7 * Copyright (C) 2013 Red Hat Inc 8 * 9 * Author: Michael S. Tsirkin <mst@redhat.com> 10 * 11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 12 * 13 * Author: Shannon Zhao <zhaoshenglong@huawei.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "qapi/error.h" 31 #include "qemu-common.h" 32 #include "hw/arm/virt-acpi-build.h" 33 #include "qemu/bitmap.h" 34 #include "trace.h" 35 #include "qom/cpu.h" 36 #include "target-arm/cpu.h" 37 #include "hw/acpi/acpi-defs.h" 38 #include "hw/acpi/acpi.h" 39 #include "hw/nvram/fw_cfg.h" 40 #include "hw/acpi/bios-linker-loader.h" 41 #include "hw/loader.h" 42 #include "hw/hw.h" 43 #include "hw/acpi/aml-build.h" 44 #include "hw/pci/pcie_host.h" 45 #include "hw/pci/pci.h" 46 #include "sysemu/numa.h" 47 48 #define ARM_SPI_BASE 32 49 #define ACPI_POWER_BUTTON_DEVICE "PWRB" 50 51 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) 52 { 53 uint16_t i; 54 55 for (i = 0; i < smp_cpus; i++) { 56 Aml *dev = aml_device("C%03x", i); 57 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 58 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 59 aml_append(scope, dev); 60 } 61 } 62 63 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 64 uint32_t uart_irq) 65 { 66 Aml *dev = aml_device("COM0"); 67 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); 68 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 69 70 Aml *crs = aml_resource_template(); 71 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 72 uart_memmap->size, AML_READ_WRITE)); 73 aml_append(crs, 74 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 75 AML_EXCLUSIVE, &uart_irq, 1)); 76 aml_append(dev, aml_name_decl("_CRS", crs)); 77 78 /* The _ADR entry is used to link this device to the UART described 79 * in the SPCR table, i.e. SPCR.base_address.address == _ADR. 80 */ 81 aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base))); 82 83 aml_append(scope, dev); 84 } 85 86 static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) 87 { 88 Aml *dev = aml_device("FWCF"); 89 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 90 /* device present, functioning, decoding, not shown in UI */ 91 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 92 93 Aml *crs = aml_resource_template(); 94 aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, 95 fw_cfg_memmap->size, AML_READ_WRITE)); 96 aml_append(dev, aml_name_decl("_CRS", crs)); 97 aml_append(scope, dev); 98 } 99 100 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) 101 { 102 Aml *dev, *crs; 103 hwaddr base = flash_memmap->base; 104 hwaddr size = flash_memmap->size / 2; 105 106 dev = aml_device("FLS0"); 107 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 108 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 109 110 crs = aml_resource_template(); 111 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 112 aml_append(dev, aml_name_decl("_CRS", crs)); 113 aml_append(scope, dev); 114 115 dev = aml_device("FLS1"); 116 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 117 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 118 crs = aml_resource_template(); 119 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); 120 aml_append(dev, aml_name_decl("_CRS", crs)); 121 aml_append(scope, dev); 122 } 123 124 static void acpi_dsdt_add_virtio(Aml *scope, 125 const MemMapEntry *virtio_mmio_memmap, 126 uint32_t mmio_irq, int num) 127 { 128 hwaddr base = virtio_mmio_memmap->base; 129 hwaddr size = virtio_mmio_memmap->size; 130 int i; 131 132 for (i = 0; i < num; i++) { 133 uint32_t irq = mmio_irq + i; 134 Aml *dev = aml_device("VR%02u", i); 135 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); 136 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 137 138 Aml *crs = aml_resource_template(); 139 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 140 aml_append(crs, 141 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 142 AML_EXCLUSIVE, &irq, 1)); 143 aml_append(dev, aml_name_decl("_CRS", crs)); 144 aml_append(scope, dev); 145 base += size; 146 } 147 } 148 149 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, 150 uint32_t irq, bool use_highmem) 151 { 152 Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; 153 int i, bus_no; 154 hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base; 155 hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size; 156 hwaddr base_pio = memmap[VIRT_PCIE_PIO].base; 157 hwaddr size_pio = memmap[VIRT_PCIE_PIO].size; 158 hwaddr base_ecam = memmap[VIRT_PCIE_ECAM].base; 159 hwaddr size_ecam = memmap[VIRT_PCIE_ECAM].size; 160 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 161 162 Aml *dev = aml_device("%s", "PCI0"); 163 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); 164 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); 165 aml_append(dev, aml_name_decl("_SEG", aml_int(0))); 166 aml_append(dev, aml_name_decl("_BBN", aml_int(0))); 167 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 168 aml_append(dev, aml_name_decl("_UID", aml_string("PCI0"))); 169 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); 170 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 171 172 /* Declare the PCI Routing Table. */ 173 Aml *rt_pkg = aml_package(nr_pcie_buses * PCI_NUM_PINS); 174 for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) { 175 for (i = 0; i < PCI_NUM_PINS; i++) { 176 int gsi = (i + bus_no) % PCI_NUM_PINS; 177 Aml *pkg = aml_package(4); 178 aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF)); 179 aml_append(pkg, aml_int(i)); 180 aml_append(pkg, aml_name("GSI%d", gsi)); 181 aml_append(pkg, aml_int(0)); 182 aml_append(rt_pkg, pkg); 183 } 184 } 185 aml_append(dev, aml_name_decl("_PRT", rt_pkg)); 186 187 /* Create GSI link device */ 188 for (i = 0; i < PCI_NUM_PINS; i++) { 189 uint32_t irqs = irq + i; 190 Aml *dev_gsi = aml_device("GSI%d", i); 191 aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); 192 aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0))); 193 crs = aml_resource_template(); 194 aml_append(crs, 195 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 196 AML_EXCLUSIVE, &irqs, 1)); 197 aml_append(dev_gsi, aml_name_decl("_PRS", crs)); 198 crs = aml_resource_template(); 199 aml_append(crs, 200 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 201 AML_EXCLUSIVE, &irqs, 1)); 202 aml_append(dev_gsi, aml_name_decl("_CRS", crs)); 203 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 204 aml_append(dev_gsi, method); 205 aml_append(dev, dev_gsi); 206 } 207 208 method = aml_method("_CBA", 0, AML_NOTSERIALIZED); 209 aml_append(method, aml_return(aml_int(base_ecam))); 210 aml_append(dev, method); 211 212 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 213 Aml *rbuf = aml_resource_template(); 214 aml_append(rbuf, 215 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 216 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, 217 nr_pcie_buses)); 218 aml_append(rbuf, 219 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 220 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio, 221 base_mmio + size_mmio - 1, 0x0000, size_mmio)); 222 aml_append(rbuf, 223 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 224 AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio, 225 size_pio)); 226 227 if (use_highmem) { 228 hwaddr base_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].base; 229 hwaddr size_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].size; 230 231 aml_append(rbuf, 232 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 233 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, 234 base_mmio_high, base_mmio_high, 0x0000, 235 size_mmio_high)); 236 } 237 238 aml_append(method, aml_name_decl("RBUF", rbuf)); 239 aml_append(method, aml_return(rbuf)); 240 aml_append(dev, method); 241 242 /* Declare an _OSC (OS Control Handoff) method */ 243 aml_append(dev, aml_name_decl("SUPP", aml_int(0))); 244 aml_append(dev, aml_name_decl("CTRL", aml_int(0))); 245 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 246 aml_append(method, 247 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 248 249 /* PCI Firmware Specification 3.0 250 * 4.5.1. _OSC Interface for PCI Host Bridge Devices 251 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is 252 * identified by the Universal Unique IDentifier (UUID) 253 * 33DB4D5B-1FF7-401C-9657-7441C03DD766 254 */ 255 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"); 256 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 257 aml_append(ifctx, 258 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 259 aml_append(ifctx, 260 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 261 aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); 262 aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); 263 aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL), 264 aml_name("CTRL"))); 265 266 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); 267 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08), NULL), 268 aml_name("CDW1"))); 269 aml_append(ifctx, ifctx1); 270 271 ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL")))); 272 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10), NULL), 273 aml_name("CDW1"))); 274 aml_append(ifctx, ifctx1); 275 276 aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3"))); 277 aml_append(ifctx, aml_return(aml_arg(3))); 278 aml_append(method, ifctx); 279 280 elsectx = aml_else(); 281 aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4), NULL), 282 aml_name("CDW1"))); 283 aml_append(elsectx, aml_return(aml_arg(3))); 284 aml_append(method, elsectx); 285 aml_append(dev, method); 286 287 method = aml_method("_DSM", 4, AML_NOTSERIALIZED); 288 289 /* PCI Firmware Specification 3.0 290 * 4.6.1. _DSM for PCI Express Slot Information 291 * The UUID in _DSM in this context is 292 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} 293 */ 294 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 295 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 296 ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0))); 297 uint8_t byte_list[1] = {1}; 298 buf = aml_buffer(1, byte_list); 299 aml_append(ifctx1, aml_return(buf)); 300 aml_append(ifctx, ifctx1); 301 aml_append(method, ifctx); 302 303 byte_list[0] = 0; 304 buf = aml_buffer(1, byte_list); 305 aml_append(method, aml_return(buf)); 306 aml_append(dev, method); 307 308 Aml *dev_rp0 = aml_device("%s", "RP0"); 309 aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0))); 310 aml_append(dev, dev_rp0); 311 aml_append(scope, dev); 312 } 313 314 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, 315 uint32_t gpio_irq) 316 { 317 Aml *dev = aml_device("GPO0"); 318 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); 319 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 320 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 321 322 Aml *crs = aml_resource_template(); 323 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, 324 AML_READ_WRITE)); 325 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 326 AML_EXCLUSIVE, &gpio_irq, 1)); 327 aml_append(dev, aml_name_decl("_CRS", crs)); 328 329 Aml *aei = aml_resource_template(); 330 /* Pin 3 for power button */ 331 const uint32_t pin_list[1] = {3}; 332 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, 333 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, 334 "GPO0", NULL, 0)); 335 aml_append(dev, aml_name_decl("_AEI", aei)); 336 337 /* _E03 is handle for power button */ 338 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); 339 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), 340 aml_int(0x80))); 341 aml_append(dev, method); 342 aml_append(scope, dev); 343 } 344 345 static void acpi_dsdt_add_power_button(Aml *scope) 346 { 347 Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE); 348 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C"))); 349 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 350 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 351 aml_append(scope, dev); 352 } 353 354 /* RSDP */ 355 static GArray * 356 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) 357 { 358 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 359 360 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, 361 true /* fseg memory */); 362 363 memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature)); 364 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, sizeof(rsdp->oem_id)); 365 rsdp->length = cpu_to_le32(sizeof(*rsdp)); 366 rsdp->revision = 0x02; 367 368 /* Point to RSDT */ 369 rsdp->rsdt_physical_address = cpu_to_le32(rsdt); 370 /* Address to be filled by Guest linker */ 371 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, 372 ACPI_BUILD_TABLE_FILE, 373 rsdp_table, &rsdp->rsdt_physical_address, 374 sizeof rsdp->rsdt_physical_address); 375 rsdp->checksum = 0; 376 /* Checksum to be filled by Guest linker */ 377 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 378 rsdp_table, rsdp, sizeof *rsdp, 379 &rsdp->checksum); 380 381 return rsdp_table; 382 } 383 384 static void 385 build_spcr(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 386 { 387 AcpiSerialPortConsoleRedirection *spcr; 388 const MemMapEntry *uart_memmap = &guest_info->memmap[VIRT_UART]; 389 int irq = guest_info->irqmap[VIRT_UART] + ARM_SPI_BASE; 390 391 spcr = acpi_data_push(table_data, sizeof(*spcr)); 392 393 spcr->interface_type = 0x3; /* ARM PL011 UART */ 394 395 spcr->base_address.space_id = AML_SYSTEM_MEMORY; 396 spcr->base_address.bit_width = 8; 397 spcr->base_address.bit_offset = 0; 398 spcr->base_address.access_width = 1; 399 spcr->base_address.address = cpu_to_le64(uart_memmap->base); 400 401 spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */ 402 spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */ 403 404 spcr->baud = 3; /* Baud Rate: 3 = 9600 */ 405 spcr->parity = 0; /* No Parity */ 406 spcr->stopbits = 1; /* 1 Stop bit */ 407 spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */ 408 spcr->term_type = 0; /* Terminal Type: 0 = VT100 */ 409 410 spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */ 411 spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */ 412 413 build_header(linker, table_data, (void *)spcr, "SPCR", sizeof(*spcr), 2, 414 NULL, NULL); 415 } 416 417 static void 418 build_srat(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 419 { 420 AcpiSystemResourceAffinityTable *srat; 421 AcpiSratProcessorGiccAffinity *core; 422 AcpiSratMemoryAffinity *numamem; 423 int i, j, srat_start; 424 uint64_t mem_base; 425 uint32_t *cpu_node = g_malloc0(guest_info->smp_cpus * sizeof(uint32_t)); 426 427 for (i = 0; i < guest_info->smp_cpus; i++) { 428 for (j = 0; j < nb_numa_nodes; j++) { 429 if (test_bit(i, numa_info[j].node_cpu)) { 430 cpu_node[i] = j; 431 break; 432 } 433 } 434 } 435 436 srat_start = table_data->len; 437 srat = acpi_data_push(table_data, sizeof(*srat)); 438 srat->reserved1 = cpu_to_le32(1); 439 440 for (i = 0; i < guest_info->smp_cpus; ++i) { 441 core = acpi_data_push(table_data, sizeof(*core)); 442 core->type = ACPI_SRAT_PROCESSOR_GICC; 443 core->length = sizeof(*core); 444 core->proximity = cpu_to_le32(cpu_node[i]); 445 core->acpi_processor_uid = cpu_to_le32(i); 446 core->flags = cpu_to_le32(1); 447 } 448 g_free(cpu_node); 449 450 mem_base = guest_info->memmap[VIRT_MEM].base; 451 for (i = 0; i < nb_numa_nodes; ++i) { 452 numamem = acpi_data_push(table_data, sizeof(*numamem)); 453 build_srat_memory(numamem, mem_base, numa_info[i].node_mem, i, 454 MEM_AFFINITY_ENABLED); 455 mem_base += numa_info[i].node_mem; 456 } 457 458 build_header(linker, table_data, 459 (void *)(table_data->data + srat_start), "SRAT", 460 table_data->len - srat_start, 3, NULL, NULL); 461 } 462 463 static void 464 build_mcfg(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 465 { 466 AcpiTableMcfg *mcfg; 467 const MemMapEntry *memmap = guest_info->memmap; 468 int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]); 469 470 mcfg = acpi_data_push(table_data, len); 471 mcfg->allocation[0].address = cpu_to_le64(memmap[VIRT_PCIE_ECAM].base); 472 473 /* Only a single allocation so no need to play with segments */ 474 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 475 mcfg->allocation[0].start_bus_number = 0; 476 mcfg->allocation[0].end_bus_number = (memmap[VIRT_PCIE_ECAM].size 477 / PCIE_MMCFG_SIZE_MIN) - 1; 478 479 build_header(linker, table_data, (void *)mcfg, "MCFG", len, 1, NULL, NULL); 480 } 481 482 /* GTDT */ 483 static void 484 build_gtdt(GArray *table_data, GArray *linker) 485 { 486 int gtdt_start = table_data->len; 487 AcpiGenericTimerTable *gtdt; 488 489 gtdt = acpi_data_push(table_data, sizeof *gtdt); 490 /* The interrupt values are the same with the device tree when adding 16 */ 491 gtdt->secure_el1_interrupt = ARCH_TIMER_S_EL1_IRQ + 16; 492 gtdt->secure_el1_flags = ACPI_EDGE_SENSITIVE; 493 494 gtdt->non_secure_el1_interrupt = ARCH_TIMER_NS_EL1_IRQ + 16; 495 gtdt->non_secure_el1_flags = ACPI_EDGE_SENSITIVE | ACPI_GTDT_ALWAYS_ON; 496 497 gtdt->virtual_timer_interrupt = ARCH_TIMER_VIRT_IRQ + 16; 498 gtdt->virtual_timer_flags = ACPI_EDGE_SENSITIVE; 499 500 gtdt->non_secure_el2_interrupt = ARCH_TIMER_NS_EL2_IRQ + 16; 501 gtdt->non_secure_el2_flags = ACPI_EDGE_SENSITIVE; 502 503 build_header(linker, table_data, 504 (void *)(table_data->data + gtdt_start), "GTDT", 505 table_data->len - gtdt_start, 2, NULL, NULL); 506 } 507 508 /* MADT */ 509 static void 510 build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 511 { 512 int madt_start = table_data->len; 513 const MemMapEntry *memmap = guest_info->memmap; 514 const int *irqmap = guest_info->irqmap; 515 AcpiMultipleApicTable *madt; 516 AcpiMadtGenericDistributor *gicd; 517 AcpiMadtGenericMsiFrame *gic_msi; 518 int i; 519 520 madt = acpi_data_push(table_data, sizeof *madt); 521 522 gicd = acpi_data_push(table_data, sizeof *gicd); 523 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR; 524 gicd->length = sizeof(*gicd); 525 gicd->base_address = memmap[VIRT_GIC_DIST].base; 526 527 for (i = 0; i < guest_info->smp_cpus; i++) { 528 AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data, 529 sizeof *gicc); 530 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 531 532 gicc->type = ACPI_APIC_GENERIC_INTERRUPT; 533 gicc->length = sizeof(*gicc); 534 if (guest_info->gic_version == 2) { 535 gicc->base_address = memmap[VIRT_GIC_CPU].base; 536 } 537 gicc->cpu_interface_number = i; 538 gicc->arm_mpidr = armcpu->mp_affinity; 539 gicc->uid = i; 540 gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED); 541 } 542 543 if (guest_info->gic_version == 3) { 544 AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data, 545 sizeof *gicr); 546 547 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 548 gicr->length = sizeof(*gicr); 549 gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base); 550 gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size); 551 } else { 552 gic_msi = acpi_data_push(table_data, sizeof *gic_msi); 553 gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME; 554 gic_msi->length = sizeof(*gic_msi); 555 gic_msi->gic_msi_frame_id = 0; 556 gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base); 557 gic_msi->flags = cpu_to_le32(1); 558 gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS); 559 gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE); 560 } 561 562 build_header(linker, table_data, 563 (void *)(table_data->data + madt_start), "APIC", 564 table_data->len - madt_start, 3, NULL, NULL); 565 } 566 567 /* FADT */ 568 static void 569 build_fadt(GArray *table_data, GArray *linker, unsigned dsdt) 570 { 571 AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); 572 573 /* Hardware Reduced = 1 and use PSCI 0.2+ and with HVC */ 574 fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI); 575 fadt->arm_boot_flags = cpu_to_le16((1 << ACPI_FADT_ARM_USE_PSCI_G_0_2) | 576 (1 << ACPI_FADT_ARM_PSCI_USE_HVC)); 577 578 /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */ 579 fadt->minor_revision = 0x1; 580 581 fadt->dsdt = cpu_to_le32(dsdt); 582 /* DSDT address to be filled by Guest linker */ 583 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 584 ACPI_BUILD_TABLE_FILE, 585 table_data, &fadt->dsdt, 586 sizeof fadt->dsdt); 587 588 build_header(linker, table_data, 589 (void *)fadt, "FACP", sizeof(*fadt), 5, NULL, NULL); 590 } 591 592 /* DSDT */ 593 static void 594 build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 595 { 596 Aml *scope, *dsdt; 597 const MemMapEntry *memmap = guest_info->memmap; 598 const int *irqmap = guest_info->irqmap; 599 600 dsdt = init_aml_allocator(); 601 /* Reserve space for header */ 602 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 603 604 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. 605 * While UEFI can use libfdt to disable the RTC device node in the DTB that 606 * it passes to the OS, it cannot modify AML. Therefore, we won't generate 607 * the RTC ACPI device at all when using UEFI. 608 */ 609 scope = aml_scope("\\_SB"); 610 acpi_dsdt_add_cpus(scope, guest_info->smp_cpus); 611 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], 612 (irqmap[VIRT_UART] + ARM_SPI_BASE)); 613 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); 614 acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); 615 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], 616 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); 617 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), 618 guest_info->use_highmem); 619 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], 620 (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); 621 acpi_dsdt_add_power_button(scope); 622 623 aml_append(dsdt, scope); 624 625 /* copy AML table into ACPI tables blob and patch header there */ 626 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 627 build_header(linker, table_data, 628 (void *)(table_data->data + table_data->len - dsdt->buf->len), 629 "DSDT", dsdt->buf->len, 2, NULL, NULL); 630 free_aml_allocator(); 631 } 632 633 typedef 634 struct AcpiBuildState { 635 /* Copy of table in RAM (for patching). */ 636 MemoryRegion *table_mr; 637 MemoryRegion *rsdp_mr; 638 MemoryRegion *linker_mr; 639 /* Is table patched? */ 640 bool patched; 641 VirtGuestInfo *guest_info; 642 } AcpiBuildState; 643 644 static 645 void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables) 646 { 647 GArray *table_offsets; 648 unsigned dsdt, rsdt; 649 GArray *tables_blob = tables->table_data; 650 651 table_offsets = g_array_new(false, true /* clear */, 652 sizeof(uint32_t)); 653 654 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, 655 64, false /* high memory */); 656 657 /* 658 * The ACPI v5.1 tables for Hardware-reduced ACPI platform are: 659 * RSDP 660 * RSDT 661 * FADT 662 * GTDT 663 * MADT 664 * MCFG 665 * DSDT 666 */ 667 668 /* DSDT is pointed to by FADT */ 669 dsdt = tables_blob->len; 670 build_dsdt(tables_blob, tables->linker, guest_info); 671 672 /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */ 673 acpi_add_table(table_offsets, tables_blob); 674 build_fadt(tables_blob, tables->linker, dsdt); 675 676 acpi_add_table(table_offsets, tables_blob); 677 build_madt(tables_blob, tables->linker, guest_info); 678 679 acpi_add_table(table_offsets, tables_blob); 680 build_gtdt(tables_blob, tables->linker); 681 682 acpi_add_table(table_offsets, tables_blob); 683 build_mcfg(tables_blob, tables->linker, guest_info); 684 685 acpi_add_table(table_offsets, tables_blob); 686 build_spcr(tables_blob, tables->linker, guest_info); 687 688 if (nb_numa_nodes > 0) { 689 acpi_add_table(table_offsets, tables_blob); 690 build_srat(tables_blob, tables->linker, guest_info); 691 } 692 693 /* RSDT is pointed to by RSDP */ 694 rsdt = tables_blob->len; 695 build_rsdt(tables_blob, tables->linker, table_offsets, NULL, NULL); 696 697 /* RSDP is in FSEG memory, so allocate it separately */ 698 build_rsdp(tables->rsdp, tables->linker, rsdt); 699 700 /* Cleanup memory that's no longer used. */ 701 g_array_free(table_offsets, true); 702 } 703 704 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 705 { 706 uint32_t size = acpi_data_len(data); 707 708 /* Make sure RAM size is correct - in case it got changed 709 * e.g. by migration */ 710 memory_region_ram_resize(mr, size, &error_abort); 711 712 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 713 memory_region_set_dirty(mr, 0, size); 714 } 715 716 static void virt_acpi_build_update(void *build_opaque) 717 { 718 AcpiBuildState *build_state = build_opaque; 719 AcpiBuildTables tables; 720 721 /* No state to update or already patched? Nothing to do. */ 722 if (!build_state || build_state->patched) { 723 return; 724 } 725 build_state->patched = true; 726 727 acpi_build_tables_init(&tables); 728 729 virt_acpi_build(build_state->guest_info, &tables); 730 731 acpi_ram_update(build_state->table_mr, tables.table_data); 732 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 733 acpi_ram_update(build_state->linker_mr, tables.linker); 734 735 736 acpi_build_tables_cleanup(&tables, true); 737 } 738 739 static void virt_acpi_build_reset(void *build_opaque) 740 { 741 AcpiBuildState *build_state = build_opaque; 742 build_state->patched = false; 743 } 744 745 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, 746 GArray *blob, const char *name, 747 uint64_t max_size) 748 { 749 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 750 name, virt_acpi_build_update, build_state); 751 } 752 753 static const VMStateDescription vmstate_virt_acpi_build = { 754 .name = "virt_acpi_build", 755 .version_id = 1, 756 .minimum_version_id = 1, 757 .fields = (VMStateField[]) { 758 VMSTATE_BOOL(patched, AcpiBuildState), 759 VMSTATE_END_OF_LIST() 760 }, 761 }; 762 763 void virt_acpi_setup(VirtGuestInfo *guest_info) 764 { 765 AcpiBuildTables tables; 766 AcpiBuildState *build_state; 767 768 if (!guest_info->fw_cfg) { 769 trace_virt_acpi_setup(); 770 return; 771 } 772 773 if (!acpi_enabled) { 774 trace_virt_acpi_setup(); 775 return; 776 } 777 778 build_state = g_malloc0(sizeof *build_state); 779 build_state->guest_info = guest_info; 780 781 acpi_build_tables_init(&tables); 782 virt_acpi_build(build_state->guest_info, &tables); 783 784 /* Now expose it all to Guest */ 785 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, 786 ACPI_BUILD_TABLE_FILE, 787 ACPI_BUILD_TABLE_MAX_SIZE); 788 assert(build_state->table_mr != NULL); 789 790 build_state->linker_mr = 791 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); 792 793 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 794 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 795 796 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, 797 ACPI_BUILD_RSDP_FILE, 0); 798 799 qemu_register_reset(virt_acpi_build_reset, build_state); 800 virt_acpi_build_reset(build_state); 801 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 802 803 /* Cleanup tables but don't free the memory: we track it 804 * in build_state. 805 */ 806 acpi_build_tables_cleanup(&tables, false); 807 } 808