1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * ARM virt ACPI generation 4 * 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 6 * Copyright (C) 2006 Fabrice Bellard 7 * Copyright (C) 2013 Red Hat Inc 8 * 9 * Author: Michael S. Tsirkin <mst@redhat.com> 10 * 11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 12 * 13 * Author: Shannon Zhao <zhaoshenglong@huawei.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "qapi/error.h" 31 #include "qemu/bitmap.h" 32 #include "trace.h" 33 #include "hw/core/cpu.h" 34 #include "target/arm/cpu.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/acpi/aml-build.h" 40 #include "hw/acpi/utils.h" 41 #include "hw/acpi/pci.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "hw/acpi/generic_event_device.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/pci/pcie_host.h" 46 #include "hw/pci/pci.h" 47 #include "hw/pci-host/gpex.h" 48 #include "hw/arm/virt.h" 49 #include "hw/mem/nvdimm.h" 50 #include "hw/platform-bus.h" 51 #include "sysemu/numa.h" 52 #include "sysemu/reset.h" 53 #include "sysemu/tpm.h" 54 #include "kvm_arm.h" 55 #include "migration/vmstate.h" 56 #include "hw/acpi/ghes.h" 57 58 #define ARM_SPI_BASE 32 59 60 #define ACPI_BUILD_TABLE_SIZE 0x20000 61 62 static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms) 63 { 64 MachineState *ms = MACHINE(vms); 65 uint16_t i; 66 67 for (i = 0; i < ms->smp.cpus; i++) { 68 Aml *dev = aml_device("C%.03X", i); 69 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 70 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 71 aml_append(scope, dev); 72 } 73 } 74 75 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 76 uint32_t uart_irq) 77 { 78 Aml *dev = aml_device("COM0"); 79 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); 80 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 81 82 Aml *crs = aml_resource_template(); 83 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 84 uart_memmap->size, AML_READ_WRITE)); 85 aml_append(crs, 86 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 87 AML_EXCLUSIVE, &uart_irq, 1)); 88 aml_append(dev, aml_name_decl("_CRS", crs)); 89 90 aml_append(scope, dev); 91 } 92 93 static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) 94 { 95 Aml *dev = aml_device("FWCF"); 96 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 97 /* device present, functioning, decoding, not shown in UI */ 98 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 99 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 100 101 Aml *crs = aml_resource_template(); 102 aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, 103 fw_cfg_memmap->size, AML_READ_WRITE)); 104 aml_append(dev, aml_name_decl("_CRS", crs)); 105 aml_append(scope, dev); 106 } 107 108 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) 109 { 110 Aml *dev, *crs; 111 hwaddr base = flash_memmap->base; 112 hwaddr size = flash_memmap->size / 2; 113 114 dev = aml_device("FLS0"); 115 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 116 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 117 118 crs = aml_resource_template(); 119 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 120 aml_append(dev, aml_name_decl("_CRS", crs)); 121 aml_append(scope, dev); 122 123 dev = aml_device("FLS1"); 124 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 125 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 126 crs = aml_resource_template(); 127 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); 128 aml_append(dev, aml_name_decl("_CRS", crs)); 129 aml_append(scope, dev); 130 } 131 132 static void acpi_dsdt_add_virtio(Aml *scope, 133 const MemMapEntry *virtio_mmio_memmap, 134 uint32_t mmio_irq, int num) 135 { 136 hwaddr base = virtio_mmio_memmap->base; 137 hwaddr size = virtio_mmio_memmap->size; 138 int i; 139 140 for (i = 0; i < num; i++) { 141 uint32_t irq = mmio_irq + i; 142 Aml *dev = aml_device("VR%02u", i); 143 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); 144 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 145 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 146 147 Aml *crs = aml_resource_template(); 148 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 149 aml_append(crs, 150 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 151 AML_EXCLUSIVE, &irq, 1)); 152 aml_append(dev, aml_name_decl("_CRS", crs)); 153 aml_append(scope, dev); 154 base += size; 155 } 156 } 157 158 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, 159 uint32_t irq, bool use_highmem, bool highmem_ecam, 160 VirtMachineState *vms) 161 { 162 int ecam_id = VIRT_ECAM_ID(highmem_ecam); 163 struct GPEXConfig cfg = { 164 .mmio32 = memmap[VIRT_PCIE_MMIO], 165 .pio = memmap[VIRT_PCIE_PIO], 166 .ecam = memmap[ecam_id], 167 .irq = irq, 168 .bus = vms->bus, 169 }; 170 171 if (use_highmem) { 172 cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO]; 173 } 174 175 acpi_dsdt_add_gpex(scope, &cfg); 176 } 177 178 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, 179 uint32_t gpio_irq) 180 { 181 Aml *dev = aml_device("GPO0"); 182 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); 183 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 184 185 Aml *crs = aml_resource_template(); 186 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, 187 AML_READ_WRITE)); 188 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 189 AML_EXCLUSIVE, &gpio_irq, 1)); 190 aml_append(dev, aml_name_decl("_CRS", crs)); 191 192 Aml *aei = aml_resource_template(); 193 /* Pin 3 for power button */ 194 const uint32_t pin_list[1] = {3}; 195 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, 196 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, 197 "GPO0", NULL, 0)); 198 aml_append(dev, aml_name_decl("_AEI", aei)); 199 200 /* _E03 is handle for power button */ 201 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); 202 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), 203 aml_int(0x80))); 204 aml_append(dev, method); 205 aml_append(scope, dev); 206 } 207 208 #ifdef CONFIG_TPM 209 static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms) 210 { 211 PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); 212 hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base; 213 SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find()); 214 MemoryRegion *sbdev_mr; 215 hwaddr tpm_base; 216 217 if (!sbdev) { 218 return; 219 } 220 221 tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); 222 assert(tpm_base != -1); 223 224 tpm_base += pbus_base; 225 226 sbdev_mr = sysbus_mmio_get_region(sbdev, 0); 227 228 Aml *dev = aml_device("TPM0"); 229 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 230 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 231 232 Aml *crs = aml_resource_template(); 233 aml_append(crs, 234 aml_memory32_fixed(tpm_base, 235 (uint32_t)memory_region_size(sbdev_mr), 236 AML_READ_WRITE)); 237 aml_append(dev, aml_name_decl("_CRS", crs)); 238 aml_append(scope, dev); 239 } 240 #endif 241 242 static void 243 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 244 { 245 int nb_nodes, iort_start = table_data->len; 246 AcpiIortIdMapping *idmap; 247 AcpiIortItsGroup *its; 248 AcpiIortTable *iort; 249 AcpiIortSmmu3 *smmu; 250 size_t node_size, iort_node_offset, iort_length, smmu_offset = 0; 251 AcpiIortRC *rc; 252 253 iort = acpi_data_push(table_data, sizeof(*iort)); 254 255 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 256 nb_nodes = 3; /* RC, ITS, SMMUv3 */ 257 } else { 258 nb_nodes = 2; /* RC, ITS */ 259 } 260 261 iort_length = sizeof(*iort); 262 iort->node_count = cpu_to_le32(nb_nodes); 263 /* 264 * Use a copy in case table_data->data moves during acpi_data_push 265 * operations. 266 */ 267 iort_node_offset = sizeof(*iort); 268 iort->node_offset = cpu_to_le32(iort_node_offset); 269 270 /* ITS group node */ 271 node_size = sizeof(*its) + sizeof(uint32_t); 272 iort_length += node_size; 273 its = acpi_data_push(table_data, node_size); 274 275 its->type = ACPI_IORT_NODE_ITS_GROUP; 276 its->length = cpu_to_le16(node_size); 277 its->its_count = cpu_to_le32(1); 278 its->identifiers[0] = 0; /* MADT translation_id */ 279 280 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 281 int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; 282 283 /* SMMUv3 node */ 284 smmu_offset = iort_node_offset + node_size; 285 node_size = sizeof(*smmu) + sizeof(*idmap); 286 iort_length += node_size; 287 smmu = acpi_data_push(table_data, node_size); 288 289 smmu->type = ACPI_IORT_NODE_SMMU_V3; 290 smmu->length = cpu_to_le16(node_size); 291 smmu->mapping_count = cpu_to_le32(1); 292 smmu->mapping_offset = cpu_to_le32(sizeof(*smmu)); 293 smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base); 294 smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE); 295 smmu->event_gsiv = cpu_to_le32(irq); 296 smmu->pri_gsiv = cpu_to_le32(irq + 1); 297 smmu->sync_gsiv = cpu_to_le32(irq + 2); 298 smmu->gerr_gsiv = cpu_to_le32(irq + 3); 299 300 /* Identity RID mapping covering the whole input RID range */ 301 idmap = &smmu->id_mapping_array[0]; 302 idmap->input_base = 0; 303 idmap->id_count = cpu_to_le32(0xFFFF); 304 idmap->output_base = 0; 305 /* output IORT node is the ITS group node (the first node) */ 306 idmap->output_reference = cpu_to_le32(iort_node_offset); 307 } 308 309 /* Root Complex Node */ 310 node_size = sizeof(*rc) + sizeof(*idmap); 311 iort_length += node_size; 312 rc = acpi_data_push(table_data, node_size); 313 314 rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX; 315 rc->length = cpu_to_le16(node_size); 316 rc->mapping_count = cpu_to_le32(1); 317 rc->mapping_offset = cpu_to_le32(sizeof(*rc)); 318 319 /* fully coherent device */ 320 rc->memory_properties.cache_coherency = cpu_to_le32(1); 321 rc->memory_properties.memory_flags = 0x3; /* CCA = CPM = DCAS = 1 */ 322 rc->pci_segment_number = 0; /* MCFG pci_segment */ 323 324 /* Identity RID mapping covering the whole input RID range */ 325 idmap = &rc->id_mapping_array[0]; 326 idmap->input_base = 0; 327 idmap->id_count = cpu_to_le32(0xFFFF); 328 idmap->output_base = 0; 329 330 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 331 /* output IORT node is the smmuv3 node */ 332 idmap->output_reference = cpu_to_le32(smmu_offset); 333 } else { 334 /* output IORT node is the ITS group node (the first node) */ 335 idmap->output_reference = cpu_to_le32(iort_node_offset); 336 } 337 338 /* 339 * Update the pointer address in case table_data->data moves during above 340 * acpi_data_push operations. 341 */ 342 iort = (AcpiIortTable *)(table_data->data + iort_start); 343 iort->length = cpu_to_le32(iort_length); 344 345 build_header(linker, table_data, (void *)(table_data->data + iort_start), 346 "IORT", table_data->len - iort_start, 0, vms->oem_id, 347 vms->oem_table_id); 348 } 349 350 static void 351 build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 352 { 353 AcpiSerialPortConsoleRedirection *spcr; 354 const MemMapEntry *uart_memmap = &vms->memmap[VIRT_UART]; 355 int irq = vms->irqmap[VIRT_UART] + ARM_SPI_BASE; 356 int spcr_start = table_data->len; 357 358 spcr = acpi_data_push(table_data, sizeof(*spcr)); 359 360 spcr->interface_type = 0x3; /* ARM PL011 UART */ 361 362 spcr->base_address.space_id = AML_SYSTEM_MEMORY; 363 spcr->base_address.bit_width = 8; 364 spcr->base_address.bit_offset = 0; 365 spcr->base_address.access_width = 1; 366 spcr->base_address.address = cpu_to_le64(uart_memmap->base); 367 368 spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */ 369 spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */ 370 371 spcr->baud = 3; /* Baud Rate: 3 = 9600 */ 372 spcr->parity = 0; /* No Parity */ 373 spcr->stopbits = 1; /* 1 Stop bit */ 374 spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */ 375 spcr->term_type = 0; /* Terminal Type: 0 = VT100 */ 376 377 spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */ 378 spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */ 379 380 build_header(linker, table_data, (void *)(table_data->data + spcr_start), 381 "SPCR", table_data->len - spcr_start, 2, vms->oem_id, 382 vms->oem_table_id); 383 } 384 385 static void 386 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 387 { 388 AcpiSystemResourceAffinityTable *srat; 389 AcpiSratProcessorGiccAffinity *core; 390 AcpiSratMemoryAffinity *numamem; 391 int i, srat_start; 392 uint64_t mem_base; 393 MachineClass *mc = MACHINE_GET_CLASS(vms); 394 MachineState *ms = MACHINE(vms); 395 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); 396 397 srat_start = table_data->len; 398 srat = acpi_data_push(table_data, sizeof(*srat)); 399 srat->reserved1 = cpu_to_le32(1); 400 401 for (i = 0; i < cpu_list->len; ++i) { 402 core = acpi_data_push(table_data, sizeof(*core)); 403 core->type = ACPI_SRAT_PROCESSOR_GICC; 404 core->length = sizeof(*core); 405 core->proximity = cpu_to_le32(cpu_list->cpus[i].props.node_id); 406 core->acpi_processor_uid = cpu_to_le32(i); 407 core->flags = cpu_to_le32(1); 408 } 409 410 mem_base = vms->memmap[VIRT_MEM].base; 411 for (i = 0; i < ms->numa_state->num_nodes; ++i) { 412 if (ms->numa_state->nodes[i].node_mem > 0) { 413 numamem = acpi_data_push(table_data, sizeof(*numamem)); 414 build_srat_memory(numamem, mem_base, 415 ms->numa_state->nodes[i].node_mem, i, 416 MEM_AFFINITY_ENABLED); 417 mem_base += ms->numa_state->nodes[i].node_mem; 418 } 419 } 420 421 if (ms->nvdimms_state->is_enabled) { 422 nvdimm_build_srat(table_data); 423 } 424 425 if (ms->device_memory) { 426 numamem = acpi_data_push(table_data, sizeof *numamem); 427 build_srat_memory(numamem, ms->device_memory->base, 428 memory_region_size(&ms->device_memory->mr), 429 ms->numa_state->num_nodes - 1, 430 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 431 } 432 433 build_header(linker, table_data, (void *)(table_data->data + srat_start), 434 "SRAT", table_data->len - srat_start, 3, vms->oem_id, 435 vms->oem_table_id); 436 } 437 438 /* GTDT */ 439 static void 440 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 441 { 442 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 443 int gtdt_start = table_data->len; 444 AcpiGenericTimerTable *gtdt; 445 uint32_t irqflags; 446 447 if (vmc->claim_edge_triggered_timers) { 448 irqflags = ACPI_GTDT_INTERRUPT_MODE_EDGE; 449 } else { 450 irqflags = ACPI_GTDT_INTERRUPT_MODE_LEVEL; 451 } 452 453 gtdt = acpi_data_push(table_data, sizeof *gtdt); 454 /* The interrupt values are the same with the device tree when adding 16 */ 455 gtdt->secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_S_EL1_IRQ + 16); 456 gtdt->secure_el1_flags = cpu_to_le32(irqflags); 457 458 gtdt->non_secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ + 16); 459 gtdt->non_secure_el1_flags = cpu_to_le32(irqflags | 460 ACPI_GTDT_CAP_ALWAYS_ON); 461 462 gtdt->virtual_timer_interrupt = cpu_to_le32(ARCH_TIMER_VIRT_IRQ + 16); 463 gtdt->virtual_timer_flags = cpu_to_le32(irqflags); 464 465 gtdt->non_secure_el2_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ + 16); 466 gtdt->non_secure_el2_flags = cpu_to_le32(irqflags); 467 468 build_header(linker, table_data, 469 (void *)(table_data->data + gtdt_start), "GTDT", 470 table_data->len - gtdt_start, 2, vms->oem_id, 471 vms->oem_table_id); 472 } 473 474 /* MADT */ 475 static void 476 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 477 { 478 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 479 int madt_start = table_data->len; 480 const MemMapEntry *memmap = vms->memmap; 481 const int *irqmap = vms->irqmap; 482 AcpiMadtGenericDistributor *gicd; 483 AcpiMadtGenericMsiFrame *gic_msi; 484 int i; 485 486 acpi_data_push(table_data, sizeof(AcpiMultipleApicTable)); 487 488 gicd = acpi_data_push(table_data, sizeof *gicd); 489 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR; 490 gicd->length = sizeof(*gicd); 491 gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base); 492 gicd->version = vms->gic_version; 493 494 for (i = 0; i < MACHINE(vms)->smp.cpus; i++) { 495 AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data, 496 sizeof(*gicc)); 497 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 498 499 gicc->type = ACPI_APIC_GENERIC_CPU_INTERFACE; 500 gicc->length = sizeof(*gicc); 501 if (vms->gic_version == 2) { 502 gicc->base_address = cpu_to_le64(memmap[VIRT_GIC_CPU].base); 503 gicc->gich_base_address = cpu_to_le64(memmap[VIRT_GIC_HYP].base); 504 gicc->gicv_base_address = cpu_to_le64(memmap[VIRT_GIC_VCPU].base); 505 } 506 gicc->cpu_interface_number = cpu_to_le32(i); 507 gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity); 508 gicc->uid = cpu_to_le32(i); 509 gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED); 510 511 if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 512 gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ)); 513 } 514 if (vms->virt) { 515 gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ)); 516 } 517 } 518 519 if (vms->gic_version == 3) { 520 AcpiMadtGenericTranslator *gic_its; 521 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 522 AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data, 523 sizeof *gicr); 524 525 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 526 gicr->length = sizeof(*gicr); 527 gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base); 528 gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size); 529 530 if (nb_redist_regions == 2) { 531 gicr = acpi_data_push(table_data, sizeof(*gicr)); 532 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 533 gicr->length = sizeof(*gicr); 534 gicr->base_address = 535 cpu_to_le64(memmap[VIRT_HIGH_GIC_REDIST2].base); 536 gicr->range_length = 537 cpu_to_le32(memmap[VIRT_HIGH_GIC_REDIST2].size); 538 } 539 540 if (its_class_name() && !vmc->no_its) { 541 gic_its = acpi_data_push(table_data, sizeof *gic_its); 542 gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR; 543 gic_its->length = sizeof(*gic_its); 544 gic_its->translation_id = 0; 545 gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base); 546 } 547 } else { 548 gic_msi = acpi_data_push(table_data, sizeof *gic_msi); 549 gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME; 550 gic_msi->length = sizeof(*gic_msi); 551 gic_msi->gic_msi_frame_id = 0; 552 gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base); 553 gic_msi->flags = cpu_to_le32(1); 554 gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS); 555 gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE); 556 } 557 558 build_header(linker, table_data, 559 (void *)(table_data->data + madt_start), "APIC", 560 table_data->len - madt_start, 3, vms->oem_id, 561 vms->oem_table_id); 562 } 563 564 /* FADT */ 565 static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker, 566 VirtMachineState *vms, unsigned dsdt_tbl_offset) 567 { 568 /* ACPI v5.1 */ 569 AcpiFadtData fadt = { 570 .rev = 5, 571 .minor_ver = 1, 572 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, 573 .xdsdt_tbl_offset = &dsdt_tbl_offset, 574 }; 575 576 switch (vms->psci_conduit) { 577 case QEMU_PSCI_CONDUIT_DISABLED: 578 fadt.arm_boot_arch = 0; 579 break; 580 case QEMU_PSCI_CONDUIT_HVC: 581 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT | 582 ACPI_FADT_ARM_PSCI_USE_HVC; 583 break; 584 case QEMU_PSCI_CONDUIT_SMC: 585 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT; 586 break; 587 default: 588 g_assert_not_reached(); 589 } 590 591 build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id); 592 } 593 594 /* DSDT */ 595 static void 596 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 597 { 598 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 599 Aml *scope, *dsdt; 600 MachineState *ms = MACHINE(vms); 601 const MemMapEntry *memmap = vms->memmap; 602 const int *irqmap = vms->irqmap; 603 604 dsdt = init_aml_allocator(); 605 /* Reserve space for header */ 606 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 607 608 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. 609 * While UEFI can use libfdt to disable the RTC device node in the DTB that 610 * it passes to the OS, it cannot modify AML. Therefore, we won't generate 611 * the RTC ACPI device at all when using UEFI. 612 */ 613 scope = aml_scope("\\_SB"); 614 acpi_dsdt_add_cpus(scope, vms); 615 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], 616 (irqmap[VIRT_UART] + ARM_SPI_BASE)); 617 if (vmc->acpi_expose_flash) { 618 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); 619 } 620 acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); 621 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], 622 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); 623 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), 624 vms->highmem, vms->highmem_ecam, vms); 625 if (vms->acpi_dev) { 626 build_ged_aml(scope, "\\_SB."GED_DEVICE, 627 HOTPLUG_HANDLER(vms->acpi_dev), 628 irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY, 629 memmap[VIRT_ACPI_GED].base); 630 } else { 631 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], 632 (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); 633 } 634 635 if (vms->acpi_dev) { 636 uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev), 637 "ged-event", &error_abort); 638 639 if (event & ACPI_GED_MEM_HOTPLUG_EVT) { 640 build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL, 641 AML_SYSTEM_MEMORY, 642 memmap[VIRT_PCDIMM_ACPI].base); 643 } 644 } 645 646 acpi_dsdt_add_power_button(scope); 647 #ifdef CONFIG_TPM 648 acpi_dsdt_add_tpm(scope, vms); 649 #endif 650 651 aml_append(dsdt, scope); 652 653 /* copy AML table into ACPI tables blob and patch header there */ 654 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 655 build_header(linker, table_data, 656 (void *)(table_data->data + table_data->len - dsdt->buf->len), 657 "DSDT", dsdt->buf->len, 2, vms->oem_id, 658 vms->oem_table_id); 659 free_aml_allocator(); 660 } 661 662 typedef 663 struct AcpiBuildState { 664 /* Copy of table in RAM (for patching). */ 665 MemoryRegion *table_mr; 666 MemoryRegion *rsdp_mr; 667 MemoryRegion *linker_mr; 668 /* Is table patched? */ 669 bool patched; 670 } AcpiBuildState; 671 672 static void acpi_align_size(GArray *blob, unsigned align) 673 { 674 /* 675 * Align size to multiple of given size. This reduces the chance 676 * we need to change size in the future (breaking cross version migration). 677 */ 678 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 679 } 680 681 static 682 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) 683 { 684 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 685 GArray *table_offsets; 686 unsigned dsdt, xsdt; 687 GArray *tables_blob = tables->table_data; 688 MachineState *ms = MACHINE(vms); 689 690 table_offsets = g_array_new(false, true /* clear */, 691 sizeof(uint32_t)); 692 693 bios_linker_loader_alloc(tables->linker, 694 ACPI_BUILD_TABLE_FILE, tables_blob, 695 64, false /* high memory */); 696 697 /* DSDT is pointed to by FADT */ 698 dsdt = tables_blob->len; 699 build_dsdt(tables_blob, tables->linker, vms); 700 701 /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */ 702 acpi_add_table(table_offsets, tables_blob); 703 build_fadt_rev5(tables_blob, tables->linker, vms, dsdt); 704 705 acpi_add_table(table_offsets, tables_blob); 706 build_madt(tables_blob, tables->linker, vms); 707 708 acpi_add_table(table_offsets, tables_blob); 709 build_gtdt(tables_blob, tables->linker, vms); 710 711 acpi_add_table(table_offsets, tables_blob); 712 { 713 AcpiMcfgInfo mcfg = { 714 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, 715 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, 716 }; 717 build_mcfg(tables_blob, tables->linker, &mcfg, vms->oem_id, 718 vms->oem_table_id); 719 } 720 721 acpi_add_table(table_offsets, tables_blob); 722 build_spcr(tables_blob, tables->linker, vms); 723 724 if (vms->ras) { 725 build_ghes_error_table(tables->hardware_errors, tables->linker); 726 acpi_add_table(table_offsets, tables_blob); 727 acpi_build_hest(tables_blob, tables->linker, vms->oem_id, 728 vms->oem_table_id); 729 } 730 731 if (ms->numa_state->num_nodes > 0) { 732 acpi_add_table(table_offsets, tables_blob); 733 build_srat(tables_blob, tables->linker, vms); 734 if (ms->numa_state->have_numa_distance) { 735 acpi_add_table(table_offsets, tables_blob); 736 build_slit(tables_blob, tables->linker, ms, vms->oem_id, 737 vms->oem_table_id); 738 } 739 } 740 741 if (ms->nvdimms_state->is_enabled) { 742 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 743 ms->nvdimms_state, ms->ram_slots, vms->oem_id, 744 vms->oem_table_id); 745 } 746 747 if (its_class_name() && !vmc->no_its) { 748 acpi_add_table(table_offsets, tables_blob); 749 build_iort(tables_blob, tables->linker, vms); 750 } 751 752 #ifdef CONFIG_TPM 753 if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) { 754 acpi_add_table(table_offsets, tables_blob); 755 build_tpm2(tables_blob, tables->linker, tables->tcpalog, vms->oem_id, 756 vms->oem_table_id); 757 } 758 #endif 759 760 /* XSDT is pointed to by RSDP */ 761 xsdt = tables_blob->len; 762 build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id, 763 vms->oem_table_id); 764 765 /* RSDP is in FSEG memory, so allocate it separately */ 766 { 767 AcpiRsdpData rsdp_data = { 768 .revision = 2, 769 .oem_id = vms->oem_id, 770 .xsdt_tbl_offset = &xsdt, 771 .rsdt_tbl_offset = NULL, 772 }; 773 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 774 } 775 776 /* 777 * The align size is 128, warn if 64k is not enough therefore 778 * the align size could be resized. 779 */ 780 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 781 warn_report("ACPI table size %u exceeds %d bytes," 782 " migration may not work", 783 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 784 error_printf("Try removing CPUs, NUMA nodes, memory slots" 785 " or PCI bridges."); 786 } 787 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 788 789 790 /* Cleanup memory that's no longer used. */ 791 g_array_free(table_offsets, true); 792 } 793 794 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 795 { 796 uint32_t size = acpi_data_len(data); 797 798 /* Make sure RAM size is correct - in case it got changed 799 * e.g. by migration */ 800 memory_region_ram_resize(mr, size, &error_abort); 801 802 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 803 memory_region_set_dirty(mr, 0, size); 804 } 805 806 static void virt_acpi_build_update(void *build_opaque) 807 { 808 AcpiBuildState *build_state = build_opaque; 809 AcpiBuildTables tables; 810 811 /* No state to update or already patched? Nothing to do. */ 812 if (!build_state || build_state->patched) { 813 return; 814 } 815 build_state->patched = true; 816 817 acpi_build_tables_init(&tables); 818 819 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables); 820 821 acpi_ram_update(build_state->table_mr, tables.table_data); 822 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 823 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 824 825 acpi_build_tables_cleanup(&tables, true); 826 } 827 828 static void virt_acpi_build_reset(void *build_opaque) 829 { 830 AcpiBuildState *build_state = build_opaque; 831 build_state->patched = false; 832 } 833 834 static const VMStateDescription vmstate_virt_acpi_build = { 835 .name = "virt_acpi_build", 836 .version_id = 1, 837 .minimum_version_id = 1, 838 .fields = (VMStateField[]) { 839 VMSTATE_BOOL(patched, AcpiBuildState), 840 VMSTATE_END_OF_LIST() 841 }, 842 }; 843 844 void virt_acpi_setup(VirtMachineState *vms) 845 { 846 AcpiBuildTables tables; 847 AcpiBuildState *build_state; 848 AcpiGedState *acpi_ged_state; 849 850 if (!vms->fw_cfg) { 851 trace_virt_acpi_setup(); 852 return; 853 } 854 855 if (!virt_is_acpi_enabled(vms)) { 856 trace_virt_acpi_setup(); 857 return; 858 } 859 860 build_state = g_malloc0(sizeof *build_state); 861 862 acpi_build_tables_init(&tables); 863 virt_acpi_build(vms, &tables); 864 865 /* Now expose it all to Guest */ 866 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, 867 build_state, tables.table_data, 868 ACPI_BUILD_TABLE_FILE); 869 assert(build_state->table_mr != NULL); 870 871 build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update, 872 build_state, 873 tables.linker->cmd_blob, 874 ACPI_BUILD_LOADER_FILE); 875 876 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, 877 acpi_data_len(tables.tcpalog)); 878 879 if (vms->ras) { 880 assert(vms->acpi_dev); 881 acpi_ged_state = ACPI_GED(vms->acpi_dev); 882 acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state, 883 vms->fw_cfg, tables.hardware_errors); 884 } 885 886 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, 887 build_state, tables.rsdp, 888 ACPI_BUILD_RSDP_FILE); 889 890 qemu_register_reset(virt_acpi_build_reset, build_state); 891 virt_acpi_build_reset(build_state); 892 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 893 894 /* Cleanup tables but don't free the memory: we track it 895 * in build_state. 896 */ 897 acpi_build_tables_cleanup(&tables, false); 898 } 899