1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * ARM virt ACPI generation 4 * 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 6 * Copyright (C) 2006 Fabrice Bellard 7 * Copyright (C) 2013 Red Hat Inc 8 * 9 * Author: Michael S. Tsirkin <mst@redhat.com> 10 * 11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 12 * 13 * Author: Shannon Zhao <zhaoshenglong@huawei.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "qapi/error.h" 31 #include "qemu/bitmap.h" 32 #include "trace.h" 33 #include "hw/core/cpu.h" 34 #include "target/arm/cpu.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/acpi/aml-build.h" 40 #include "hw/acpi/utils.h" 41 #include "hw/acpi/pci.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "hw/acpi/generic_event_device.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/pci/pcie_host.h" 46 #include "hw/pci/pci.h" 47 #include "hw/arm/virt.h" 48 #include "hw/mem/nvdimm.h" 49 #include "sysemu/numa.h" 50 #include "sysemu/reset.h" 51 #include "sysemu/tpm.h" 52 #include "kvm_arm.h" 53 #include "migration/vmstate.h" 54 #include "hw/acpi/ghes.h" 55 56 #define ARM_SPI_BASE 32 57 58 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) 59 { 60 uint16_t i; 61 62 for (i = 0; i < smp_cpus; i++) { 63 Aml *dev = aml_device("C%.03X", i); 64 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 65 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 66 aml_append(scope, dev); 67 } 68 } 69 70 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 71 uint32_t uart_irq) 72 { 73 Aml *dev = aml_device("COM0"); 74 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); 75 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 76 77 Aml *crs = aml_resource_template(); 78 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 79 uart_memmap->size, AML_READ_WRITE)); 80 aml_append(crs, 81 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 82 AML_EXCLUSIVE, &uart_irq, 1)); 83 aml_append(dev, aml_name_decl("_CRS", crs)); 84 85 aml_append(scope, dev); 86 } 87 88 static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) 89 { 90 Aml *dev = aml_device("FWCF"); 91 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 92 /* device present, functioning, decoding, not shown in UI */ 93 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 94 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 95 96 Aml *crs = aml_resource_template(); 97 aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, 98 fw_cfg_memmap->size, AML_READ_WRITE)); 99 aml_append(dev, aml_name_decl("_CRS", crs)); 100 aml_append(scope, dev); 101 } 102 103 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) 104 { 105 Aml *dev, *crs; 106 hwaddr base = flash_memmap->base; 107 hwaddr size = flash_memmap->size / 2; 108 109 dev = aml_device("FLS0"); 110 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 111 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 112 113 crs = aml_resource_template(); 114 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 115 aml_append(dev, aml_name_decl("_CRS", crs)); 116 aml_append(scope, dev); 117 118 dev = aml_device("FLS1"); 119 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 120 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 121 crs = aml_resource_template(); 122 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); 123 aml_append(dev, aml_name_decl("_CRS", crs)); 124 aml_append(scope, dev); 125 } 126 127 static void acpi_dsdt_add_virtio(Aml *scope, 128 const MemMapEntry *virtio_mmio_memmap, 129 uint32_t mmio_irq, int num) 130 { 131 hwaddr base = virtio_mmio_memmap->base; 132 hwaddr size = virtio_mmio_memmap->size; 133 int i; 134 135 for (i = 0; i < num; i++) { 136 uint32_t irq = mmio_irq + i; 137 Aml *dev = aml_device("VR%02u", i); 138 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); 139 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 140 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 141 142 Aml *crs = aml_resource_template(); 143 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 144 aml_append(crs, 145 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 146 AML_EXCLUSIVE, &irq, 1)); 147 aml_append(dev, aml_name_decl("_CRS", crs)); 148 aml_append(scope, dev); 149 base += size; 150 } 151 } 152 153 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, 154 uint32_t irq, bool use_highmem, bool highmem_ecam) 155 { 156 int ecam_id = VIRT_ECAM_ID(highmem_ecam); 157 Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; 158 int i, slot_no; 159 hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base; 160 hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size; 161 hwaddr base_pio = memmap[VIRT_PCIE_PIO].base; 162 hwaddr size_pio = memmap[VIRT_PCIE_PIO].size; 163 hwaddr base_ecam = memmap[ecam_id].base; 164 hwaddr size_ecam = memmap[ecam_id].size; 165 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 166 167 Aml *dev = aml_device("%s", "PCI0"); 168 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); 169 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); 170 aml_append(dev, aml_name_decl("_SEG", aml_int(0))); 171 aml_append(dev, aml_name_decl("_BBN", aml_int(0))); 172 aml_append(dev, aml_name_decl("_UID", aml_string("PCI0"))); 173 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); 174 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 175 176 /* Declare the PCI Routing Table. */ 177 Aml *rt_pkg = aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS); 178 for (slot_no = 0; slot_no < PCI_SLOT_MAX; slot_no++) { 179 for (i = 0; i < PCI_NUM_PINS; i++) { 180 int gsi = (i + slot_no) % PCI_NUM_PINS; 181 Aml *pkg = aml_package(4); 182 aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF)); 183 aml_append(pkg, aml_int(i)); 184 aml_append(pkg, aml_name("GSI%d", gsi)); 185 aml_append(pkg, aml_int(0)); 186 aml_append(rt_pkg, pkg); 187 } 188 } 189 aml_append(dev, aml_name_decl("_PRT", rt_pkg)); 190 191 /* Create GSI link device */ 192 for (i = 0; i < PCI_NUM_PINS; i++) { 193 uint32_t irqs = irq + i; 194 Aml *dev_gsi = aml_device("GSI%d", i); 195 aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); 196 aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i))); 197 crs = aml_resource_template(); 198 aml_append(crs, 199 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 200 AML_EXCLUSIVE, &irqs, 1)); 201 aml_append(dev_gsi, aml_name_decl("_PRS", crs)); 202 crs = aml_resource_template(); 203 aml_append(crs, 204 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 205 AML_EXCLUSIVE, &irqs, 1)); 206 aml_append(dev_gsi, aml_name_decl("_CRS", crs)); 207 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 208 aml_append(dev_gsi, method); 209 aml_append(dev, dev_gsi); 210 } 211 212 method = aml_method("_CBA", 0, AML_NOTSERIALIZED); 213 aml_append(method, aml_return(aml_int(base_ecam))); 214 aml_append(dev, method); 215 216 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 217 Aml *rbuf = aml_resource_template(); 218 aml_append(rbuf, 219 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 220 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, 221 nr_pcie_buses)); 222 aml_append(rbuf, 223 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 224 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio, 225 base_mmio + size_mmio - 1, 0x0000, size_mmio)); 226 aml_append(rbuf, 227 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 228 AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio, 229 size_pio)); 230 231 if (use_highmem) { 232 hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base; 233 hwaddr size_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].size; 234 235 aml_append(rbuf, 236 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 237 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, 238 base_mmio_high, 239 base_mmio_high + size_mmio_high - 1, 0x0000, 240 size_mmio_high)); 241 } 242 243 aml_append(method, aml_return(rbuf)); 244 aml_append(dev, method); 245 246 /* Declare an _OSC (OS Control Handoff) method */ 247 aml_append(dev, aml_name_decl("SUPP", aml_int(0))); 248 aml_append(dev, aml_name_decl("CTRL", aml_int(0))); 249 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 250 aml_append(method, 251 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 252 253 /* PCI Firmware Specification 3.0 254 * 4.5.1. _OSC Interface for PCI Host Bridge Devices 255 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is 256 * identified by the Universal Unique IDentifier (UUID) 257 * 33DB4D5B-1FF7-401C-9657-7441C03DD766 258 */ 259 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"); 260 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 261 aml_append(ifctx, 262 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 263 aml_append(ifctx, 264 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 265 aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); 266 aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); 267 268 /* 269 * Allow OS control for all 5 features: 270 * PCIeHotplug SHPCHotplug PME AER PCIeCapability. 271 */ 272 aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F), 273 aml_name("CTRL"))); 274 275 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); 276 aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08), 277 aml_name("CDW1"))); 278 aml_append(ifctx, ifctx1); 279 280 ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL")))); 281 aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10), 282 aml_name("CDW1"))); 283 aml_append(ifctx, ifctx1); 284 285 aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3"))); 286 aml_append(ifctx, aml_return(aml_arg(3))); 287 aml_append(method, ifctx); 288 289 elsectx = aml_else(); 290 aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4), 291 aml_name("CDW1"))); 292 aml_append(elsectx, aml_return(aml_arg(3))); 293 aml_append(method, elsectx); 294 aml_append(dev, method); 295 296 method = aml_method("_DSM", 4, AML_NOTSERIALIZED); 297 298 /* PCI Firmware Specification 3.0 299 * 4.6.1. _DSM for PCI Express Slot Information 300 * The UUID in _DSM in this context is 301 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} 302 */ 303 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 304 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 305 ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0))); 306 uint8_t byte_list[1] = {1}; 307 buf = aml_buffer(1, byte_list); 308 aml_append(ifctx1, aml_return(buf)); 309 aml_append(ifctx, ifctx1); 310 aml_append(method, ifctx); 311 312 byte_list[0] = 0; 313 buf = aml_buffer(1, byte_list); 314 aml_append(method, aml_return(buf)); 315 aml_append(dev, method); 316 317 Aml *dev_res0 = aml_device("%s", "RES0"); 318 aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); 319 crs = aml_resource_template(); 320 aml_append(crs, 321 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 322 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_ecam, 323 base_ecam + size_ecam - 1, 0x0000, size_ecam)); 324 aml_append(dev_res0, aml_name_decl("_CRS", crs)); 325 aml_append(dev, dev_res0); 326 aml_append(scope, dev); 327 } 328 329 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, 330 uint32_t gpio_irq) 331 { 332 Aml *dev = aml_device("GPO0"); 333 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); 334 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 335 336 Aml *crs = aml_resource_template(); 337 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, 338 AML_READ_WRITE)); 339 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 340 AML_EXCLUSIVE, &gpio_irq, 1)); 341 aml_append(dev, aml_name_decl("_CRS", crs)); 342 343 Aml *aei = aml_resource_template(); 344 /* Pin 3 for power button */ 345 const uint32_t pin_list[1] = {3}; 346 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, 347 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, 348 "GPO0", NULL, 0)); 349 aml_append(dev, aml_name_decl("_AEI", aei)); 350 351 /* _E03 is handle for power button */ 352 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); 353 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), 354 aml_int(0x80))); 355 aml_append(dev, method); 356 aml_append(scope, dev); 357 } 358 359 static void acpi_dsdt_add_power_button(Aml *scope) 360 { 361 Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE); 362 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C"))); 363 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 364 aml_append(scope, dev); 365 } 366 367 static void 368 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 369 { 370 int nb_nodes, iort_start = table_data->len; 371 AcpiIortIdMapping *idmap; 372 AcpiIortItsGroup *its; 373 AcpiIortTable *iort; 374 AcpiIortSmmu3 *smmu; 375 size_t node_size, iort_node_offset, iort_length, smmu_offset = 0; 376 AcpiIortRC *rc; 377 378 iort = acpi_data_push(table_data, sizeof(*iort)); 379 380 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 381 nb_nodes = 3; /* RC, ITS, SMMUv3 */ 382 } else { 383 nb_nodes = 2; /* RC, ITS */ 384 } 385 386 iort_length = sizeof(*iort); 387 iort->node_count = cpu_to_le32(nb_nodes); 388 /* 389 * Use a copy in case table_data->data moves during acpi_data_push 390 * operations. 391 */ 392 iort_node_offset = sizeof(*iort); 393 iort->node_offset = cpu_to_le32(iort_node_offset); 394 395 /* ITS group node */ 396 node_size = sizeof(*its) + sizeof(uint32_t); 397 iort_length += node_size; 398 its = acpi_data_push(table_data, node_size); 399 400 its->type = ACPI_IORT_NODE_ITS_GROUP; 401 its->length = cpu_to_le16(node_size); 402 its->its_count = cpu_to_le32(1); 403 its->identifiers[0] = 0; /* MADT translation_id */ 404 405 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 406 int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; 407 408 /* SMMUv3 node */ 409 smmu_offset = iort_node_offset + node_size; 410 node_size = sizeof(*smmu) + sizeof(*idmap); 411 iort_length += node_size; 412 smmu = acpi_data_push(table_data, node_size); 413 414 smmu->type = ACPI_IORT_NODE_SMMU_V3; 415 smmu->length = cpu_to_le16(node_size); 416 smmu->mapping_count = cpu_to_le32(1); 417 smmu->mapping_offset = cpu_to_le32(sizeof(*smmu)); 418 smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base); 419 smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE); 420 smmu->event_gsiv = cpu_to_le32(irq); 421 smmu->pri_gsiv = cpu_to_le32(irq + 1); 422 smmu->gerr_gsiv = cpu_to_le32(irq + 2); 423 smmu->sync_gsiv = cpu_to_le32(irq + 3); 424 425 /* Identity RID mapping covering the whole input RID range */ 426 idmap = &smmu->id_mapping_array[0]; 427 idmap->input_base = 0; 428 idmap->id_count = cpu_to_le32(0xFFFF); 429 idmap->output_base = 0; 430 /* output IORT node is the ITS group node (the first node) */ 431 idmap->output_reference = cpu_to_le32(iort_node_offset); 432 } 433 434 /* Root Complex Node */ 435 node_size = sizeof(*rc) + sizeof(*idmap); 436 iort_length += node_size; 437 rc = acpi_data_push(table_data, node_size); 438 439 rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX; 440 rc->length = cpu_to_le16(node_size); 441 rc->mapping_count = cpu_to_le32(1); 442 rc->mapping_offset = cpu_to_le32(sizeof(*rc)); 443 444 /* fully coherent device */ 445 rc->memory_properties.cache_coherency = cpu_to_le32(1); 446 rc->memory_properties.memory_flags = 0x3; /* CCA = CPM = DCAS = 1 */ 447 rc->pci_segment_number = 0; /* MCFG pci_segment */ 448 449 /* Identity RID mapping covering the whole input RID range */ 450 idmap = &rc->id_mapping_array[0]; 451 idmap->input_base = 0; 452 idmap->id_count = cpu_to_le32(0xFFFF); 453 idmap->output_base = 0; 454 455 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 456 /* output IORT node is the smmuv3 node */ 457 idmap->output_reference = cpu_to_le32(smmu_offset); 458 } else { 459 /* output IORT node is the ITS group node (the first node) */ 460 idmap->output_reference = cpu_to_le32(iort_node_offset); 461 } 462 463 /* 464 * Update the pointer address in case table_data->data moves during above 465 * acpi_data_push operations. 466 */ 467 iort = (AcpiIortTable *)(table_data->data + iort_start); 468 iort->length = cpu_to_le32(iort_length); 469 470 build_header(linker, table_data, (void *)(table_data->data + iort_start), 471 "IORT", table_data->len - iort_start, 0, NULL, NULL); 472 } 473 474 static void 475 build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 476 { 477 AcpiSerialPortConsoleRedirection *spcr; 478 const MemMapEntry *uart_memmap = &vms->memmap[VIRT_UART]; 479 int irq = vms->irqmap[VIRT_UART] + ARM_SPI_BASE; 480 int spcr_start = table_data->len; 481 482 spcr = acpi_data_push(table_data, sizeof(*spcr)); 483 484 spcr->interface_type = 0x3; /* ARM PL011 UART */ 485 486 spcr->base_address.space_id = AML_SYSTEM_MEMORY; 487 spcr->base_address.bit_width = 8; 488 spcr->base_address.bit_offset = 0; 489 spcr->base_address.access_width = 1; 490 spcr->base_address.address = cpu_to_le64(uart_memmap->base); 491 492 spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */ 493 spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */ 494 495 spcr->baud = 3; /* Baud Rate: 3 = 9600 */ 496 spcr->parity = 0; /* No Parity */ 497 spcr->stopbits = 1; /* 1 Stop bit */ 498 spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */ 499 spcr->term_type = 0; /* Terminal Type: 0 = VT100 */ 500 501 spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */ 502 spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */ 503 504 build_header(linker, table_data, (void *)(table_data->data + spcr_start), 505 "SPCR", table_data->len - spcr_start, 2, NULL, NULL); 506 } 507 508 static void 509 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 510 { 511 AcpiSystemResourceAffinityTable *srat; 512 AcpiSratProcessorGiccAffinity *core; 513 AcpiSratMemoryAffinity *numamem; 514 int i, srat_start; 515 uint64_t mem_base; 516 MachineClass *mc = MACHINE_GET_CLASS(vms); 517 MachineState *ms = MACHINE(vms); 518 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); 519 520 srat_start = table_data->len; 521 srat = acpi_data_push(table_data, sizeof(*srat)); 522 srat->reserved1 = cpu_to_le32(1); 523 524 for (i = 0; i < cpu_list->len; ++i) { 525 core = acpi_data_push(table_data, sizeof(*core)); 526 core->type = ACPI_SRAT_PROCESSOR_GICC; 527 core->length = sizeof(*core); 528 core->proximity = cpu_to_le32(cpu_list->cpus[i].props.node_id); 529 core->acpi_processor_uid = cpu_to_le32(i); 530 core->flags = cpu_to_le32(1); 531 } 532 533 mem_base = vms->memmap[VIRT_MEM].base; 534 for (i = 0; i < ms->numa_state->num_nodes; ++i) { 535 if (ms->numa_state->nodes[i].node_mem > 0) { 536 numamem = acpi_data_push(table_data, sizeof(*numamem)); 537 build_srat_memory(numamem, mem_base, 538 ms->numa_state->nodes[i].node_mem, i, 539 MEM_AFFINITY_ENABLED); 540 mem_base += ms->numa_state->nodes[i].node_mem; 541 } 542 } 543 544 if (ms->nvdimms_state->is_enabled) { 545 nvdimm_build_srat(table_data); 546 } 547 548 if (ms->device_memory) { 549 numamem = acpi_data_push(table_data, sizeof *numamem); 550 build_srat_memory(numamem, ms->device_memory->base, 551 memory_region_size(&ms->device_memory->mr), 552 ms->numa_state->num_nodes - 1, 553 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 554 } 555 556 build_header(linker, table_data, (void *)(table_data->data + srat_start), 557 "SRAT", table_data->len - srat_start, 3, NULL, NULL); 558 } 559 560 /* GTDT */ 561 static void 562 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 563 { 564 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 565 int gtdt_start = table_data->len; 566 AcpiGenericTimerTable *gtdt; 567 uint32_t irqflags; 568 569 if (vmc->claim_edge_triggered_timers) { 570 irqflags = ACPI_GTDT_INTERRUPT_MODE_EDGE; 571 } else { 572 irqflags = ACPI_GTDT_INTERRUPT_MODE_LEVEL; 573 } 574 575 gtdt = acpi_data_push(table_data, sizeof *gtdt); 576 /* The interrupt values are the same with the device tree when adding 16 */ 577 gtdt->secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_S_EL1_IRQ + 16); 578 gtdt->secure_el1_flags = cpu_to_le32(irqflags); 579 580 gtdt->non_secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ + 16); 581 gtdt->non_secure_el1_flags = cpu_to_le32(irqflags | 582 ACPI_GTDT_CAP_ALWAYS_ON); 583 584 gtdt->virtual_timer_interrupt = cpu_to_le32(ARCH_TIMER_VIRT_IRQ + 16); 585 gtdt->virtual_timer_flags = cpu_to_le32(irqflags); 586 587 gtdt->non_secure_el2_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ + 16); 588 gtdt->non_secure_el2_flags = cpu_to_le32(irqflags); 589 590 build_header(linker, table_data, 591 (void *)(table_data->data + gtdt_start), "GTDT", 592 table_data->len - gtdt_start, 2, NULL, NULL); 593 } 594 595 /* MADT */ 596 static void 597 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 598 { 599 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 600 int madt_start = table_data->len; 601 const MemMapEntry *memmap = vms->memmap; 602 const int *irqmap = vms->irqmap; 603 AcpiMultipleApicTable *madt; 604 AcpiMadtGenericDistributor *gicd; 605 AcpiMadtGenericMsiFrame *gic_msi; 606 int i; 607 608 madt = acpi_data_push(table_data, sizeof *madt); 609 610 gicd = acpi_data_push(table_data, sizeof *gicd); 611 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR; 612 gicd->length = sizeof(*gicd); 613 gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base); 614 gicd->version = vms->gic_version; 615 616 for (i = 0; i < vms->smp_cpus; i++) { 617 AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data, 618 sizeof(*gicc)); 619 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 620 621 gicc->type = ACPI_APIC_GENERIC_CPU_INTERFACE; 622 gicc->length = sizeof(*gicc); 623 if (vms->gic_version == 2) { 624 gicc->base_address = cpu_to_le64(memmap[VIRT_GIC_CPU].base); 625 gicc->gich_base_address = cpu_to_le64(memmap[VIRT_GIC_HYP].base); 626 gicc->gicv_base_address = cpu_to_le64(memmap[VIRT_GIC_VCPU].base); 627 } 628 gicc->cpu_interface_number = cpu_to_le32(i); 629 gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity); 630 gicc->uid = cpu_to_le32(i); 631 gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED); 632 633 if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 634 gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ)); 635 } 636 if (vms->virt) { 637 gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ)); 638 } 639 } 640 641 if (vms->gic_version == 3) { 642 AcpiMadtGenericTranslator *gic_its; 643 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 644 AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data, 645 sizeof *gicr); 646 647 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 648 gicr->length = sizeof(*gicr); 649 gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base); 650 gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size); 651 652 if (nb_redist_regions == 2) { 653 gicr = acpi_data_push(table_data, sizeof(*gicr)); 654 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 655 gicr->length = sizeof(*gicr); 656 gicr->base_address = 657 cpu_to_le64(memmap[VIRT_HIGH_GIC_REDIST2].base); 658 gicr->range_length = 659 cpu_to_le32(memmap[VIRT_HIGH_GIC_REDIST2].size); 660 } 661 662 if (its_class_name() && !vmc->no_its) { 663 gic_its = acpi_data_push(table_data, sizeof *gic_its); 664 gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR; 665 gic_its->length = sizeof(*gic_its); 666 gic_its->translation_id = 0; 667 gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base); 668 } 669 } else { 670 gic_msi = acpi_data_push(table_data, sizeof *gic_msi); 671 gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME; 672 gic_msi->length = sizeof(*gic_msi); 673 gic_msi->gic_msi_frame_id = 0; 674 gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base); 675 gic_msi->flags = cpu_to_le32(1); 676 gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS); 677 gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE); 678 } 679 680 build_header(linker, table_data, 681 (void *)(table_data->data + madt_start), "APIC", 682 table_data->len - madt_start, 3, NULL, NULL); 683 } 684 685 /* FADT */ 686 static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker, 687 VirtMachineState *vms, unsigned dsdt_tbl_offset) 688 { 689 /* ACPI v5.1 */ 690 AcpiFadtData fadt = { 691 .rev = 5, 692 .minor_ver = 1, 693 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, 694 .xdsdt_tbl_offset = &dsdt_tbl_offset, 695 }; 696 697 switch (vms->psci_conduit) { 698 case QEMU_PSCI_CONDUIT_DISABLED: 699 fadt.arm_boot_arch = 0; 700 break; 701 case QEMU_PSCI_CONDUIT_HVC: 702 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT | 703 ACPI_FADT_ARM_PSCI_USE_HVC; 704 break; 705 case QEMU_PSCI_CONDUIT_SMC: 706 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT; 707 break; 708 default: 709 g_assert_not_reached(); 710 } 711 712 build_fadt(table_data, linker, &fadt, NULL, NULL); 713 } 714 715 /* DSDT */ 716 static void 717 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 718 { 719 Aml *scope, *dsdt; 720 MachineState *ms = MACHINE(vms); 721 const MemMapEntry *memmap = vms->memmap; 722 const int *irqmap = vms->irqmap; 723 724 dsdt = init_aml_allocator(); 725 /* Reserve space for header */ 726 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 727 728 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. 729 * While UEFI can use libfdt to disable the RTC device node in the DTB that 730 * it passes to the OS, it cannot modify AML. Therefore, we won't generate 731 * the RTC ACPI device at all when using UEFI. 732 */ 733 scope = aml_scope("\\_SB"); 734 acpi_dsdt_add_cpus(scope, vms->smp_cpus); 735 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], 736 (irqmap[VIRT_UART] + ARM_SPI_BASE)); 737 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); 738 acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); 739 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], 740 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); 741 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), 742 vms->highmem, vms->highmem_ecam); 743 if (vms->acpi_dev) { 744 build_ged_aml(scope, "\\_SB."GED_DEVICE, 745 HOTPLUG_HANDLER(vms->acpi_dev), 746 irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY, 747 memmap[VIRT_ACPI_GED].base); 748 } else { 749 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], 750 (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); 751 } 752 753 if (vms->acpi_dev) { 754 uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev), 755 "ged-event", &error_abort); 756 757 if (event & ACPI_GED_MEM_HOTPLUG_EVT) { 758 build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL, 759 AML_SYSTEM_MEMORY, 760 memmap[VIRT_PCDIMM_ACPI].base); 761 } 762 } 763 764 acpi_dsdt_add_power_button(scope); 765 766 aml_append(dsdt, scope); 767 768 /* copy AML table into ACPI tables blob and patch header there */ 769 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 770 build_header(linker, table_data, 771 (void *)(table_data->data + table_data->len - dsdt->buf->len), 772 "DSDT", dsdt->buf->len, 2, NULL, NULL); 773 free_aml_allocator(); 774 } 775 776 typedef 777 struct AcpiBuildState { 778 /* Copy of table in RAM (for patching). */ 779 MemoryRegion *table_mr; 780 MemoryRegion *rsdp_mr; 781 MemoryRegion *linker_mr; 782 /* Is table patched? */ 783 bool patched; 784 } AcpiBuildState; 785 786 static 787 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) 788 { 789 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 790 GArray *table_offsets; 791 unsigned dsdt, xsdt; 792 GArray *tables_blob = tables->table_data; 793 MachineState *ms = MACHINE(vms); 794 795 table_offsets = g_array_new(false, true /* clear */, 796 sizeof(uint32_t)); 797 798 bios_linker_loader_alloc(tables->linker, 799 ACPI_BUILD_TABLE_FILE, tables_blob, 800 64, false /* high memory */); 801 802 /* DSDT is pointed to by FADT */ 803 dsdt = tables_blob->len; 804 build_dsdt(tables_blob, tables->linker, vms); 805 806 /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */ 807 acpi_add_table(table_offsets, tables_blob); 808 build_fadt_rev5(tables_blob, tables->linker, vms, dsdt); 809 810 acpi_add_table(table_offsets, tables_blob); 811 build_madt(tables_blob, tables->linker, vms); 812 813 acpi_add_table(table_offsets, tables_blob); 814 build_gtdt(tables_blob, tables->linker, vms); 815 816 acpi_add_table(table_offsets, tables_blob); 817 { 818 AcpiMcfgInfo mcfg = { 819 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, 820 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, 821 }; 822 build_mcfg(tables_blob, tables->linker, &mcfg); 823 } 824 825 acpi_add_table(table_offsets, tables_blob); 826 build_spcr(tables_blob, tables->linker, vms); 827 828 if (vms->ras) { 829 build_ghes_error_table(tables->hardware_errors, tables->linker); 830 acpi_add_table(table_offsets, tables_blob); 831 acpi_build_hest(tables_blob, tables->linker); 832 } 833 834 if (ms->numa_state->num_nodes > 0) { 835 acpi_add_table(table_offsets, tables_blob); 836 build_srat(tables_blob, tables->linker, vms); 837 if (ms->numa_state->have_numa_distance) { 838 acpi_add_table(table_offsets, tables_blob); 839 build_slit(tables_blob, tables->linker, ms); 840 } 841 } 842 843 if (ms->nvdimms_state->is_enabled) { 844 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 845 ms->nvdimms_state, ms->ram_slots); 846 } 847 848 if (its_class_name() && !vmc->no_its) { 849 acpi_add_table(table_offsets, tables_blob); 850 build_iort(tables_blob, tables->linker, vms); 851 } 852 853 if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) { 854 acpi_add_table(table_offsets, tables_blob); 855 build_tpm2(tables_blob, tables->linker, tables->tcpalog); 856 } 857 858 /* XSDT is pointed to by RSDP */ 859 xsdt = tables_blob->len; 860 build_xsdt(tables_blob, tables->linker, table_offsets, NULL, NULL); 861 862 /* RSDP is in FSEG memory, so allocate it separately */ 863 { 864 AcpiRsdpData rsdp_data = { 865 .revision = 2, 866 .oem_id = ACPI_BUILD_APPNAME6, 867 .xsdt_tbl_offset = &xsdt, 868 .rsdt_tbl_offset = NULL, 869 }; 870 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 871 } 872 873 /* Cleanup memory that's no longer used. */ 874 g_array_free(table_offsets, true); 875 } 876 877 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 878 { 879 uint32_t size = acpi_data_len(data); 880 881 /* Make sure RAM size is correct - in case it got changed 882 * e.g. by migration */ 883 memory_region_ram_resize(mr, size, &error_abort); 884 885 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 886 memory_region_set_dirty(mr, 0, size); 887 } 888 889 static void virt_acpi_build_update(void *build_opaque) 890 { 891 AcpiBuildState *build_state = build_opaque; 892 AcpiBuildTables tables; 893 894 /* No state to update or already patched? Nothing to do. */ 895 if (!build_state || build_state->patched) { 896 return; 897 } 898 build_state->patched = true; 899 900 acpi_build_tables_init(&tables); 901 902 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables); 903 904 acpi_ram_update(build_state->table_mr, tables.table_data); 905 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 906 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 907 908 acpi_build_tables_cleanup(&tables, true); 909 } 910 911 static void virt_acpi_build_reset(void *build_opaque) 912 { 913 AcpiBuildState *build_state = build_opaque; 914 build_state->patched = false; 915 } 916 917 static const VMStateDescription vmstate_virt_acpi_build = { 918 .name = "virt_acpi_build", 919 .version_id = 1, 920 .minimum_version_id = 1, 921 .fields = (VMStateField[]) { 922 VMSTATE_BOOL(patched, AcpiBuildState), 923 VMSTATE_END_OF_LIST() 924 }, 925 }; 926 927 void virt_acpi_setup(VirtMachineState *vms) 928 { 929 AcpiBuildTables tables; 930 AcpiBuildState *build_state; 931 AcpiGedState *acpi_ged_state; 932 933 if (!vms->fw_cfg) { 934 trace_virt_acpi_setup(); 935 return; 936 } 937 938 if (!virt_is_acpi_enabled(vms)) { 939 trace_virt_acpi_setup(); 940 return; 941 } 942 943 build_state = g_malloc0(sizeof *build_state); 944 945 acpi_build_tables_init(&tables); 946 virt_acpi_build(vms, &tables); 947 948 /* Now expose it all to Guest */ 949 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, 950 build_state, tables.table_data, 951 ACPI_BUILD_TABLE_FILE, 952 ACPI_BUILD_TABLE_MAX_SIZE); 953 assert(build_state->table_mr != NULL); 954 955 build_state->linker_mr = 956 acpi_add_rom_blob(virt_acpi_build_update, build_state, 957 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0); 958 959 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, 960 acpi_data_len(tables.tcpalog)); 961 962 if (vms->ras) { 963 assert(vms->acpi_dev); 964 acpi_ged_state = ACPI_GED(vms->acpi_dev); 965 acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state, 966 vms->fw_cfg, tables.hardware_errors); 967 } 968 969 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, 970 build_state, tables.rsdp, 971 ACPI_BUILD_RSDP_FILE, 0); 972 973 qemu_register_reset(virt_acpi_build_reset, build_state); 974 virt_acpi_build_reset(build_state); 975 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 976 977 /* Cleanup tables but don't free the memory: we track it 978 * in build_state. 979 */ 980 acpi_build_tables_cleanup(&tables, false); 981 } 982