1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * ARM virt ACPI generation 4 * 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 6 * Copyright (C) 2006 Fabrice Bellard 7 * Copyright (C) 2013 Red Hat Inc 8 * 9 * Author: Michael S. Tsirkin <mst@redhat.com> 10 * 11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 12 * 13 * Author: Shannon Zhao <zhaoshenglong@huawei.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu-common.h" 30 #include "hw/arm/virt-acpi-build.h" 31 #include "qemu/bitmap.h" 32 #include "trace.h" 33 #include "qom/cpu.h" 34 #include "target-arm/cpu.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/loader.h" 40 #include "hw/hw.h" 41 #include "hw/acpi/aml-build.h" 42 #include "hw/pci/pcie_host.h" 43 #include "hw/pci/pci.h" 44 45 #define ARM_SPI_BASE 32 46 #define ACPI_POWER_BUTTON_DEVICE "PWRB" 47 48 typedef struct VirtAcpiCpuInfo { 49 DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT); 50 } VirtAcpiCpuInfo; 51 52 static void virt_acpi_get_cpu_info(VirtAcpiCpuInfo *cpuinfo) 53 { 54 CPUState *cpu; 55 56 memset(cpuinfo->found_cpus, 0, sizeof cpuinfo->found_cpus); 57 CPU_FOREACH(cpu) { 58 set_bit(cpu->cpu_index, cpuinfo->found_cpus); 59 } 60 } 61 62 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) 63 { 64 uint16_t i; 65 66 for (i = 0; i < smp_cpus; i++) { 67 Aml *dev = aml_device("C%03x", i); 68 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 69 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 70 aml_append(scope, dev); 71 } 72 } 73 74 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 75 uint32_t uart_irq) 76 { 77 Aml *dev = aml_device("COM0"); 78 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); 79 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 80 81 Aml *crs = aml_resource_template(); 82 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 83 uart_memmap->size, AML_READ_WRITE)); 84 aml_append(crs, 85 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 86 AML_EXCLUSIVE, &uart_irq, 1)); 87 aml_append(dev, aml_name_decl("_CRS", crs)); 88 89 /* The _ADR entry is used to link this device to the UART described 90 * in the SPCR table, i.e. SPCR.base_address.address == _ADR. 91 */ 92 aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base))); 93 94 aml_append(scope, dev); 95 } 96 97 static void acpi_dsdt_add_rtc(Aml *scope, const MemMapEntry *rtc_memmap, 98 uint32_t rtc_irq) 99 { 100 Aml *dev = aml_device("RTC0"); 101 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0013"))); 102 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 103 104 Aml *crs = aml_resource_template(); 105 aml_append(crs, aml_memory32_fixed(rtc_memmap->base, 106 rtc_memmap->size, AML_READ_WRITE)); 107 aml_append(crs, 108 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 109 AML_EXCLUSIVE, &rtc_irq, 1)); 110 aml_append(dev, aml_name_decl("_CRS", crs)); 111 aml_append(scope, dev); 112 } 113 114 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) 115 { 116 Aml *dev, *crs; 117 hwaddr base = flash_memmap->base; 118 hwaddr size = flash_memmap->size / 2; 119 120 dev = aml_device("FLS0"); 121 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 122 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 123 124 crs = aml_resource_template(); 125 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 126 aml_append(dev, aml_name_decl("_CRS", crs)); 127 aml_append(scope, dev); 128 129 dev = aml_device("FLS1"); 130 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 131 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 132 crs = aml_resource_template(); 133 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); 134 aml_append(dev, aml_name_decl("_CRS", crs)); 135 aml_append(scope, dev); 136 } 137 138 static void acpi_dsdt_add_virtio(Aml *scope, 139 const MemMapEntry *virtio_mmio_memmap, 140 uint32_t mmio_irq, int num) 141 { 142 hwaddr base = virtio_mmio_memmap->base; 143 hwaddr size = virtio_mmio_memmap->size; 144 int i; 145 146 for (i = 0; i < num; i++) { 147 uint32_t irq = mmio_irq + i; 148 Aml *dev = aml_device("VR%02u", i); 149 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); 150 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 151 152 Aml *crs = aml_resource_template(); 153 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 154 aml_append(crs, 155 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 156 AML_EXCLUSIVE, &irq, 1)); 157 aml_append(dev, aml_name_decl("_CRS", crs)); 158 aml_append(scope, dev); 159 base += size; 160 } 161 } 162 163 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, 164 uint32_t irq, bool use_highmem) 165 { 166 Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; 167 int i, bus_no; 168 hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base; 169 hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size; 170 hwaddr base_pio = memmap[VIRT_PCIE_PIO].base; 171 hwaddr size_pio = memmap[VIRT_PCIE_PIO].size; 172 hwaddr base_ecam = memmap[VIRT_PCIE_ECAM].base; 173 hwaddr size_ecam = memmap[VIRT_PCIE_ECAM].size; 174 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 175 176 Aml *dev = aml_device("%s", "PCI0"); 177 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); 178 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); 179 aml_append(dev, aml_name_decl("_SEG", aml_int(0))); 180 aml_append(dev, aml_name_decl("_BBN", aml_int(0))); 181 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 182 aml_append(dev, aml_name_decl("_UID", aml_string("PCI0"))); 183 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); 184 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 185 186 /* Declare the PCI Routing Table. */ 187 Aml *rt_pkg = aml_package(nr_pcie_buses * PCI_NUM_PINS); 188 for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) { 189 for (i = 0; i < PCI_NUM_PINS; i++) { 190 int gsi = (i + bus_no) % PCI_NUM_PINS; 191 Aml *pkg = aml_package(4); 192 aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF)); 193 aml_append(pkg, aml_int(i)); 194 aml_append(pkg, aml_name("GSI%d", gsi)); 195 aml_append(pkg, aml_int(0)); 196 aml_append(rt_pkg, pkg); 197 } 198 } 199 aml_append(dev, aml_name_decl("_PRT", rt_pkg)); 200 201 /* Create GSI link device */ 202 for (i = 0; i < PCI_NUM_PINS; i++) { 203 uint32_t irqs = irq + i; 204 Aml *dev_gsi = aml_device("GSI%d", i); 205 aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); 206 aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0))); 207 crs = aml_resource_template(); 208 aml_append(crs, 209 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 210 AML_EXCLUSIVE, &irqs, 1)); 211 aml_append(dev_gsi, aml_name_decl("_PRS", crs)); 212 crs = aml_resource_template(); 213 aml_append(crs, 214 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 215 AML_EXCLUSIVE, &irqs, 1)); 216 aml_append(dev_gsi, aml_name_decl("_CRS", crs)); 217 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 218 aml_append(dev_gsi, method); 219 aml_append(dev, dev_gsi); 220 } 221 222 method = aml_method("_CBA", 0, AML_NOTSERIALIZED); 223 aml_append(method, aml_return(aml_int(base_ecam))); 224 aml_append(dev, method); 225 226 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 227 Aml *rbuf = aml_resource_template(); 228 aml_append(rbuf, 229 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 230 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, 231 nr_pcie_buses)); 232 aml_append(rbuf, 233 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 234 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio, 235 base_mmio + size_mmio - 1, 0x0000, size_mmio)); 236 aml_append(rbuf, 237 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 238 AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio, 239 size_pio)); 240 241 if (use_highmem) { 242 hwaddr base_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].base; 243 hwaddr size_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].size; 244 245 aml_append(rbuf, 246 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 247 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, 248 base_mmio_high, base_mmio_high, 0x0000, 249 size_mmio_high)); 250 } 251 252 aml_append(method, aml_name_decl("RBUF", rbuf)); 253 aml_append(method, aml_return(rbuf)); 254 aml_append(dev, method); 255 256 /* Declare an _OSC (OS Control Handoff) method */ 257 aml_append(dev, aml_name_decl("SUPP", aml_int(0))); 258 aml_append(dev, aml_name_decl("CTRL", aml_int(0))); 259 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 260 aml_append(method, 261 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 262 263 /* PCI Firmware Specification 3.0 264 * 4.5.1. _OSC Interface for PCI Host Bridge Devices 265 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is 266 * identified by the Universal Unique IDentifier (UUID) 267 * 33DB4D5B-1FF7-401C-9657-7441C03DD766 268 */ 269 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"); 270 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 271 aml_append(ifctx, 272 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 273 aml_append(ifctx, 274 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 275 aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); 276 aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); 277 aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D)), 278 aml_name("CTRL"))); 279 280 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); 281 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08)), 282 aml_name("CDW1"))); 283 aml_append(ifctx, ifctx1); 284 285 ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL")))); 286 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10)), 287 aml_name("CDW1"))); 288 aml_append(ifctx, ifctx1); 289 290 aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3"))); 291 aml_append(ifctx, aml_return(aml_arg(3))); 292 aml_append(method, ifctx); 293 294 elsectx = aml_else(); 295 aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4)), 296 aml_name("CDW1"))); 297 aml_append(elsectx, aml_return(aml_arg(3))); 298 aml_append(method, elsectx); 299 aml_append(dev, method); 300 301 method = aml_method("_DSM", 4, AML_NOTSERIALIZED); 302 303 /* PCI Firmware Specification 3.0 304 * 4.6.1. _DSM for PCI Express Slot Information 305 * The UUID in _DSM in this context is 306 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} 307 */ 308 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 309 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 310 ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0))); 311 uint8_t byte_list[1] = {1}; 312 buf = aml_buffer(1, byte_list); 313 aml_append(ifctx1, aml_return(buf)); 314 aml_append(ifctx, ifctx1); 315 aml_append(method, ifctx); 316 317 byte_list[0] = 0; 318 buf = aml_buffer(1, byte_list); 319 aml_append(method, aml_return(buf)); 320 aml_append(dev, method); 321 322 Aml *dev_rp0 = aml_device("%s", "RP0"); 323 aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0))); 324 aml_append(dev, dev_rp0); 325 aml_append(scope, dev); 326 } 327 328 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, 329 uint32_t gpio_irq) 330 { 331 Aml *dev = aml_device("GPO0"); 332 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); 333 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 334 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 335 336 Aml *crs = aml_resource_template(); 337 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, 338 AML_READ_WRITE)); 339 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 340 AML_EXCLUSIVE, &gpio_irq, 1)); 341 aml_append(dev, aml_name_decl("_CRS", crs)); 342 343 Aml *aei = aml_resource_template(); 344 /* Pin 3 for power button */ 345 const uint32_t pin_list[1] = {3}; 346 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, 347 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, 348 "GPO0", NULL, 0)); 349 aml_append(dev, aml_name_decl("_AEI", aei)); 350 351 /* _E03 is handle for power button */ 352 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); 353 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), 354 aml_int(0x80))); 355 aml_append(dev, method); 356 aml_append(scope, dev); 357 } 358 359 static void acpi_dsdt_add_power_button(Aml *scope) 360 { 361 Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE); 362 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C"))); 363 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 364 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 365 aml_append(scope, dev); 366 } 367 368 /* RSDP */ 369 static GArray * 370 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) 371 { 372 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 373 374 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, 375 true /* fseg memory */); 376 377 memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature)); 378 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, sizeof(rsdp->oem_id)); 379 rsdp->length = cpu_to_le32(sizeof(*rsdp)); 380 rsdp->revision = 0x02; 381 382 /* Point to RSDT */ 383 rsdp->rsdt_physical_address = cpu_to_le32(rsdt); 384 /* Address to be filled by Guest linker */ 385 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, 386 ACPI_BUILD_TABLE_FILE, 387 rsdp_table, &rsdp->rsdt_physical_address, 388 sizeof rsdp->rsdt_physical_address); 389 rsdp->checksum = 0; 390 /* Checksum to be filled by Guest linker */ 391 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 392 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum); 393 394 return rsdp_table; 395 } 396 397 static void 398 build_spcr(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 399 { 400 AcpiSerialPortConsoleRedirection *spcr; 401 const MemMapEntry *uart_memmap = &guest_info->memmap[VIRT_UART]; 402 int irq = guest_info->irqmap[VIRT_UART] + ARM_SPI_BASE; 403 404 spcr = acpi_data_push(table_data, sizeof(*spcr)); 405 406 spcr->interface_type = 0x3; /* ARM PL011 UART */ 407 408 spcr->base_address.space_id = AML_SYSTEM_MEMORY; 409 spcr->base_address.bit_width = 8; 410 spcr->base_address.bit_offset = 0; 411 spcr->base_address.access_width = 1; 412 spcr->base_address.address = cpu_to_le64(uart_memmap->base); 413 414 spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */ 415 spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */ 416 417 spcr->baud = 3; /* Baud Rate: 3 = 9600 */ 418 spcr->parity = 0; /* No Parity */ 419 spcr->stopbits = 1; /* 1 Stop bit */ 420 spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */ 421 spcr->term_type = 0; /* Terminal Type: 0 = VT100 */ 422 423 spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */ 424 spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */ 425 426 build_header(linker, table_data, (void *)spcr, "SPCR", sizeof(*spcr), 2); 427 } 428 429 static void 430 build_mcfg(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 431 { 432 AcpiTableMcfg *mcfg; 433 const MemMapEntry *memmap = guest_info->memmap; 434 int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]); 435 436 mcfg = acpi_data_push(table_data, len); 437 mcfg->allocation[0].address = cpu_to_le64(memmap[VIRT_PCIE_ECAM].base); 438 439 /* Only a single allocation so no need to play with segments */ 440 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 441 mcfg->allocation[0].start_bus_number = 0; 442 mcfg->allocation[0].end_bus_number = (memmap[VIRT_PCIE_ECAM].size 443 / PCIE_MMCFG_SIZE_MIN) - 1; 444 445 build_header(linker, table_data, (void *)mcfg, "MCFG", len, 1); 446 } 447 448 /* GTDT */ 449 static void 450 build_gtdt(GArray *table_data, GArray *linker) 451 { 452 int gtdt_start = table_data->len; 453 AcpiGenericTimerTable *gtdt; 454 455 gtdt = acpi_data_push(table_data, sizeof *gtdt); 456 /* The interrupt values are the same with the device tree when adding 16 */ 457 gtdt->secure_el1_interrupt = ARCH_TIMER_S_EL1_IRQ + 16; 458 gtdt->secure_el1_flags = ACPI_EDGE_SENSITIVE; 459 460 gtdt->non_secure_el1_interrupt = ARCH_TIMER_NS_EL1_IRQ + 16; 461 gtdt->non_secure_el1_flags = ACPI_EDGE_SENSITIVE; 462 463 gtdt->virtual_timer_interrupt = ARCH_TIMER_VIRT_IRQ + 16; 464 gtdt->virtual_timer_flags = ACPI_EDGE_SENSITIVE; 465 466 gtdt->non_secure_el2_interrupt = ARCH_TIMER_NS_EL2_IRQ + 16; 467 gtdt->non_secure_el2_flags = ACPI_EDGE_SENSITIVE; 468 469 build_header(linker, table_data, 470 (void *)(table_data->data + gtdt_start), "GTDT", 471 table_data->len - gtdt_start, 2); 472 } 473 474 /* MADT */ 475 static void 476 build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info, 477 VirtAcpiCpuInfo *cpuinfo) 478 { 479 int madt_start = table_data->len; 480 const MemMapEntry *memmap = guest_info->memmap; 481 const int *irqmap = guest_info->irqmap; 482 AcpiMultipleApicTable *madt; 483 AcpiMadtGenericDistributor *gicd; 484 AcpiMadtGenericMsiFrame *gic_msi; 485 int i; 486 487 madt = acpi_data_push(table_data, sizeof *madt); 488 489 gicd = acpi_data_push(table_data, sizeof *gicd); 490 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR; 491 gicd->length = sizeof(*gicd); 492 gicd->base_address = memmap[VIRT_GIC_DIST].base; 493 494 for (i = 0; i < guest_info->smp_cpus; i++) { 495 AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data, 496 sizeof *gicc); 497 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 498 499 gicc->type = ACPI_APIC_GENERIC_INTERRUPT; 500 gicc->length = sizeof(*gicc); 501 if (guest_info->gic_version == 2) { 502 gicc->base_address = memmap[VIRT_GIC_CPU].base; 503 } 504 gicc->cpu_interface_number = i; 505 gicc->arm_mpidr = armcpu->mp_affinity; 506 gicc->uid = i; 507 if (test_bit(i, cpuinfo->found_cpus)) { 508 gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED); 509 } 510 } 511 512 if (guest_info->gic_version == 3) { 513 AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data, 514 sizeof *gicr); 515 516 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 517 gicr->length = sizeof(*gicr); 518 gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base); 519 gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size); 520 } else { 521 gic_msi = acpi_data_push(table_data, sizeof *gic_msi); 522 gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME; 523 gic_msi->length = sizeof(*gic_msi); 524 gic_msi->gic_msi_frame_id = 0; 525 gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base); 526 gic_msi->flags = cpu_to_le32(1); 527 gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS); 528 gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE); 529 } 530 531 build_header(linker, table_data, 532 (void *)(table_data->data + madt_start), "APIC", 533 table_data->len - madt_start, 3); 534 } 535 536 /* FADT */ 537 static void 538 build_fadt(GArray *table_data, GArray *linker, unsigned dsdt) 539 { 540 AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); 541 542 /* Hardware Reduced = 1 and use PSCI 0.2+ and with HVC */ 543 fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI); 544 fadt->arm_boot_flags = cpu_to_le16((1 << ACPI_FADT_ARM_USE_PSCI_G_0_2) | 545 (1 << ACPI_FADT_ARM_PSCI_USE_HVC)); 546 547 /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */ 548 fadt->minor_revision = 0x1; 549 550 fadt->dsdt = cpu_to_le32(dsdt); 551 /* DSDT address to be filled by Guest linker */ 552 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 553 ACPI_BUILD_TABLE_FILE, 554 table_data, &fadt->dsdt, 555 sizeof fadt->dsdt); 556 557 build_header(linker, table_data, 558 (void *)fadt, "FACP", sizeof(*fadt), 5); 559 } 560 561 /* DSDT */ 562 static void 563 build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 564 { 565 Aml *scope, *dsdt; 566 const MemMapEntry *memmap = guest_info->memmap; 567 const int *irqmap = guest_info->irqmap; 568 569 dsdt = init_aml_allocator(); 570 /* Reserve space for header */ 571 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 572 573 scope = aml_scope("\\_SB"); 574 acpi_dsdt_add_cpus(scope, guest_info->smp_cpus); 575 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], 576 (irqmap[VIRT_UART] + ARM_SPI_BASE)); 577 acpi_dsdt_add_rtc(scope, &memmap[VIRT_RTC], 578 (irqmap[VIRT_RTC] + ARM_SPI_BASE)); 579 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); 580 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], 581 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); 582 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), 583 guest_info->use_highmem); 584 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], 585 (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); 586 acpi_dsdt_add_power_button(scope); 587 588 aml_append(dsdt, scope); 589 590 /* copy AML table into ACPI tables blob and patch header there */ 591 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 592 build_header(linker, table_data, 593 (void *)(table_data->data + table_data->len - dsdt->buf->len), 594 "DSDT", dsdt->buf->len, 2); 595 free_aml_allocator(); 596 } 597 598 typedef 599 struct AcpiBuildState { 600 /* Copy of table in RAM (for patching). */ 601 MemoryRegion *table_mr; 602 MemoryRegion *rsdp_mr; 603 MemoryRegion *linker_mr; 604 /* Is table patched? */ 605 bool patched; 606 VirtGuestInfo *guest_info; 607 } AcpiBuildState; 608 609 static 610 void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables) 611 { 612 GArray *table_offsets; 613 unsigned dsdt, rsdt; 614 VirtAcpiCpuInfo cpuinfo; 615 GArray *tables_blob = tables->table_data; 616 617 virt_acpi_get_cpu_info(&cpuinfo); 618 619 table_offsets = g_array_new(false, true /* clear */, 620 sizeof(uint32_t)); 621 622 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, 623 64, false /* high memory */); 624 625 /* 626 * The ACPI v5.1 tables for Hardware-reduced ACPI platform are: 627 * RSDP 628 * RSDT 629 * FADT 630 * GTDT 631 * MADT 632 * MCFG 633 * DSDT 634 */ 635 636 /* DSDT is pointed to by FADT */ 637 dsdt = tables_blob->len; 638 build_dsdt(tables_blob, tables->linker, guest_info); 639 640 /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */ 641 acpi_add_table(table_offsets, tables_blob); 642 build_fadt(tables_blob, tables->linker, dsdt); 643 644 acpi_add_table(table_offsets, tables_blob); 645 build_madt(tables_blob, tables->linker, guest_info, &cpuinfo); 646 647 acpi_add_table(table_offsets, tables_blob); 648 build_gtdt(tables_blob, tables->linker); 649 650 acpi_add_table(table_offsets, tables_blob); 651 build_mcfg(tables_blob, tables->linker, guest_info); 652 653 acpi_add_table(table_offsets, tables_blob); 654 build_spcr(tables_blob, tables->linker, guest_info); 655 656 /* RSDT is pointed to by RSDP */ 657 rsdt = tables_blob->len; 658 build_rsdt(tables_blob, tables->linker, table_offsets); 659 660 /* RSDP is in FSEG memory, so allocate it separately */ 661 build_rsdp(tables->rsdp, tables->linker, rsdt); 662 663 /* Cleanup memory that's no longer used. */ 664 g_array_free(table_offsets, true); 665 } 666 667 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 668 { 669 uint32_t size = acpi_data_len(data); 670 671 /* Make sure RAM size is correct - in case it got changed 672 * e.g. by migration */ 673 memory_region_ram_resize(mr, size, &error_abort); 674 675 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 676 memory_region_set_dirty(mr, 0, size); 677 } 678 679 static void virt_acpi_build_update(void *build_opaque) 680 { 681 AcpiBuildState *build_state = build_opaque; 682 AcpiBuildTables tables; 683 684 /* No state to update or already patched? Nothing to do. */ 685 if (!build_state || build_state->patched) { 686 return; 687 } 688 build_state->patched = true; 689 690 acpi_build_tables_init(&tables); 691 692 virt_acpi_build(build_state->guest_info, &tables); 693 694 acpi_ram_update(build_state->table_mr, tables.table_data); 695 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 696 acpi_ram_update(build_state->linker_mr, tables.linker); 697 698 699 acpi_build_tables_cleanup(&tables, true); 700 } 701 702 static void virt_acpi_build_reset(void *build_opaque) 703 { 704 AcpiBuildState *build_state = build_opaque; 705 build_state->patched = false; 706 } 707 708 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, 709 GArray *blob, const char *name, 710 uint64_t max_size) 711 { 712 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 713 name, virt_acpi_build_update, build_state); 714 } 715 716 static const VMStateDescription vmstate_virt_acpi_build = { 717 .name = "virt_acpi_build", 718 .version_id = 1, 719 .minimum_version_id = 1, 720 .fields = (VMStateField[]) { 721 VMSTATE_BOOL(patched, AcpiBuildState), 722 VMSTATE_END_OF_LIST() 723 }, 724 }; 725 726 void virt_acpi_setup(VirtGuestInfo *guest_info) 727 { 728 AcpiBuildTables tables; 729 AcpiBuildState *build_state; 730 731 if (!guest_info->fw_cfg) { 732 trace_virt_acpi_setup(); 733 return; 734 } 735 736 if (!acpi_enabled) { 737 trace_virt_acpi_setup(); 738 return; 739 } 740 741 build_state = g_malloc0(sizeof *build_state); 742 build_state->guest_info = guest_info; 743 744 acpi_build_tables_init(&tables); 745 virt_acpi_build(build_state->guest_info, &tables); 746 747 /* Now expose it all to Guest */ 748 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, 749 ACPI_BUILD_TABLE_FILE, 750 ACPI_BUILD_TABLE_MAX_SIZE); 751 assert(build_state->table_mr != NULL); 752 753 build_state->linker_mr = 754 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); 755 756 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 757 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 758 759 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, 760 ACPI_BUILD_RSDP_FILE, 0); 761 762 qemu_register_reset(virt_acpi_build_reset, build_state); 763 virt_acpi_build_reset(build_state); 764 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 765 766 /* Cleanup tables but don't free the memory: we track it 767 * in build_state. 768 */ 769 acpi_build_tables_cleanup(&tables, false); 770 } 771