1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * ARM virt ACPI generation 4 * 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 6 * Copyright (C) 2006 Fabrice Bellard 7 * Copyright (C) 2013 Red Hat Inc 8 * 9 * Author: Michael S. Tsirkin <mst@redhat.com> 10 * 11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 12 * 13 * Author: Shannon Zhao <zhaoshenglong@huawei.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "qapi/error.h" 31 #include "qemu-common.h" 32 #include "hw/arm/virt-acpi-build.h" 33 #include "qemu/bitmap.h" 34 #include "trace.h" 35 #include "qom/cpu.h" 36 #include "target-arm/cpu.h" 37 #include "hw/acpi/acpi-defs.h" 38 #include "hw/acpi/acpi.h" 39 #include "hw/nvram/fw_cfg.h" 40 #include "hw/acpi/bios-linker-loader.h" 41 #include "hw/loader.h" 42 #include "hw/hw.h" 43 #include "hw/acpi/aml-build.h" 44 #include "hw/pci/pcie_host.h" 45 #include "hw/pci/pci.h" 46 47 #define ARM_SPI_BASE 32 48 #define ACPI_POWER_BUTTON_DEVICE "PWRB" 49 50 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) 51 { 52 uint16_t i; 53 54 for (i = 0; i < smp_cpus; i++) { 55 Aml *dev = aml_device("C%03x", i); 56 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 57 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 58 aml_append(scope, dev); 59 } 60 } 61 62 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 63 uint32_t uart_irq) 64 { 65 Aml *dev = aml_device("COM0"); 66 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); 67 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 68 69 Aml *crs = aml_resource_template(); 70 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 71 uart_memmap->size, AML_READ_WRITE)); 72 aml_append(crs, 73 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 74 AML_EXCLUSIVE, &uart_irq, 1)); 75 aml_append(dev, aml_name_decl("_CRS", crs)); 76 77 /* The _ADR entry is used to link this device to the UART described 78 * in the SPCR table, i.e. SPCR.base_address.address == _ADR. 79 */ 80 aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base))); 81 82 aml_append(scope, dev); 83 } 84 85 static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) 86 { 87 Aml *dev = aml_device("FWCF"); 88 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 89 /* device present, functioning, decoding, not shown in UI */ 90 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 91 92 Aml *crs = aml_resource_template(); 93 aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, 94 fw_cfg_memmap->size, AML_READ_WRITE)); 95 aml_append(dev, aml_name_decl("_CRS", crs)); 96 aml_append(scope, dev); 97 } 98 99 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) 100 { 101 Aml *dev, *crs; 102 hwaddr base = flash_memmap->base; 103 hwaddr size = flash_memmap->size / 2; 104 105 dev = aml_device("FLS0"); 106 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 107 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 108 109 crs = aml_resource_template(); 110 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 111 aml_append(dev, aml_name_decl("_CRS", crs)); 112 aml_append(scope, dev); 113 114 dev = aml_device("FLS1"); 115 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 116 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 117 crs = aml_resource_template(); 118 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); 119 aml_append(dev, aml_name_decl("_CRS", crs)); 120 aml_append(scope, dev); 121 } 122 123 static void acpi_dsdt_add_virtio(Aml *scope, 124 const MemMapEntry *virtio_mmio_memmap, 125 uint32_t mmio_irq, int num) 126 { 127 hwaddr base = virtio_mmio_memmap->base; 128 hwaddr size = virtio_mmio_memmap->size; 129 int i; 130 131 for (i = 0; i < num; i++) { 132 uint32_t irq = mmio_irq + i; 133 Aml *dev = aml_device("VR%02u", i); 134 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); 135 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 136 137 Aml *crs = aml_resource_template(); 138 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 139 aml_append(crs, 140 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 141 AML_EXCLUSIVE, &irq, 1)); 142 aml_append(dev, aml_name_decl("_CRS", crs)); 143 aml_append(scope, dev); 144 base += size; 145 } 146 } 147 148 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, 149 uint32_t irq, bool use_highmem) 150 { 151 Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; 152 int i, bus_no; 153 hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base; 154 hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size; 155 hwaddr base_pio = memmap[VIRT_PCIE_PIO].base; 156 hwaddr size_pio = memmap[VIRT_PCIE_PIO].size; 157 hwaddr base_ecam = memmap[VIRT_PCIE_ECAM].base; 158 hwaddr size_ecam = memmap[VIRT_PCIE_ECAM].size; 159 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 160 161 Aml *dev = aml_device("%s", "PCI0"); 162 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); 163 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); 164 aml_append(dev, aml_name_decl("_SEG", aml_int(0))); 165 aml_append(dev, aml_name_decl("_BBN", aml_int(0))); 166 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 167 aml_append(dev, aml_name_decl("_UID", aml_string("PCI0"))); 168 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); 169 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 170 171 /* Declare the PCI Routing Table. */ 172 Aml *rt_pkg = aml_package(nr_pcie_buses * PCI_NUM_PINS); 173 for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) { 174 for (i = 0; i < PCI_NUM_PINS; i++) { 175 int gsi = (i + bus_no) % PCI_NUM_PINS; 176 Aml *pkg = aml_package(4); 177 aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF)); 178 aml_append(pkg, aml_int(i)); 179 aml_append(pkg, aml_name("GSI%d", gsi)); 180 aml_append(pkg, aml_int(0)); 181 aml_append(rt_pkg, pkg); 182 } 183 } 184 aml_append(dev, aml_name_decl("_PRT", rt_pkg)); 185 186 /* Create GSI link device */ 187 for (i = 0; i < PCI_NUM_PINS; i++) { 188 uint32_t irqs = irq + i; 189 Aml *dev_gsi = aml_device("GSI%d", i); 190 aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); 191 aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0))); 192 crs = aml_resource_template(); 193 aml_append(crs, 194 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 195 AML_EXCLUSIVE, &irqs, 1)); 196 aml_append(dev_gsi, aml_name_decl("_PRS", crs)); 197 crs = aml_resource_template(); 198 aml_append(crs, 199 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 200 AML_EXCLUSIVE, &irqs, 1)); 201 aml_append(dev_gsi, aml_name_decl("_CRS", crs)); 202 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 203 aml_append(dev_gsi, method); 204 aml_append(dev, dev_gsi); 205 } 206 207 method = aml_method("_CBA", 0, AML_NOTSERIALIZED); 208 aml_append(method, aml_return(aml_int(base_ecam))); 209 aml_append(dev, method); 210 211 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 212 Aml *rbuf = aml_resource_template(); 213 aml_append(rbuf, 214 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 215 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, 216 nr_pcie_buses)); 217 aml_append(rbuf, 218 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 219 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio, 220 base_mmio + size_mmio - 1, 0x0000, size_mmio)); 221 aml_append(rbuf, 222 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 223 AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio, 224 size_pio)); 225 226 if (use_highmem) { 227 hwaddr base_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].base; 228 hwaddr size_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].size; 229 230 aml_append(rbuf, 231 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 232 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, 233 base_mmio_high, base_mmio_high, 0x0000, 234 size_mmio_high)); 235 } 236 237 aml_append(method, aml_name_decl("RBUF", rbuf)); 238 aml_append(method, aml_return(rbuf)); 239 aml_append(dev, method); 240 241 /* Declare an _OSC (OS Control Handoff) method */ 242 aml_append(dev, aml_name_decl("SUPP", aml_int(0))); 243 aml_append(dev, aml_name_decl("CTRL", aml_int(0))); 244 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 245 aml_append(method, 246 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 247 248 /* PCI Firmware Specification 3.0 249 * 4.5.1. _OSC Interface for PCI Host Bridge Devices 250 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is 251 * identified by the Universal Unique IDentifier (UUID) 252 * 33DB4D5B-1FF7-401C-9657-7441C03DD766 253 */ 254 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"); 255 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 256 aml_append(ifctx, 257 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 258 aml_append(ifctx, 259 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 260 aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); 261 aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); 262 aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL), 263 aml_name("CTRL"))); 264 265 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); 266 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08), NULL), 267 aml_name("CDW1"))); 268 aml_append(ifctx, ifctx1); 269 270 ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL")))); 271 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10), NULL), 272 aml_name("CDW1"))); 273 aml_append(ifctx, ifctx1); 274 275 aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3"))); 276 aml_append(ifctx, aml_return(aml_arg(3))); 277 aml_append(method, ifctx); 278 279 elsectx = aml_else(); 280 aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4), NULL), 281 aml_name("CDW1"))); 282 aml_append(elsectx, aml_return(aml_arg(3))); 283 aml_append(method, elsectx); 284 aml_append(dev, method); 285 286 method = aml_method("_DSM", 4, AML_NOTSERIALIZED); 287 288 /* PCI Firmware Specification 3.0 289 * 4.6.1. _DSM for PCI Express Slot Information 290 * The UUID in _DSM in this context is 291 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} 292 */ 293 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 294 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 295 ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0))); 296 uint8_t byte_list[1] = {1}; 297 buf = aml_buffer(1, byte_list); 298 aml_append(ifctx1, aml_return(buf)); 299 aml_append(ifctx, ifctx1); 300 aml_append(method, ifctx); 301 302 byte_list[0] = 0; 303 buf = aml_buffer(1, byte_list); 304 aml_append(method, aml_return(buf)); 305 aml_append(dev, method); 306 307 Aml *dev_rp0 = aml_device("%s", "RP0"); 308 aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0))); 309 aml_append(dev, dev_rp0); 310 aml_append(scope, dev); 311 } 312 313 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, 314 uint32_t gpio_irq) 315 { 316 Aml *dev = aml_device("GPO0"); 317 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); 318 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 319 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 320 321 Aml *crs = aml_resource_template(); 322 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, 323 AML_READ_WRITE)); 324 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 325 AML_EXCLUSIVE, &gpio_irq, 1)); 326 aml_append(dev, aml_name_decl("_CRS", crs)); 327 328 Aml *aei = aml_resource_template(); 329 /* Pin 3 for power button */ 330 const uint32_t pin_list[1] = {3}; 331 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, 332 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, 333 "GPO0", NULL, 0)); 334 aml_append(dev, aml_name_decl("_AEI", aei)); 335 336 /* _E03 is handle for power button */ 337 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); 338 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), 339 aml_int(0x80))); 340 aml_append(dev, method); 341 aml_append(scope, dev); 342 } 343 344 static void acpi_dsdt_add_power_button(Aml *scope) 345 { 346 Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE); 347 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C"))); 348 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 349 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 350 aml_append(scope, dev); 351 } 352 353 /* RSDP */ 354 static GArray * 355 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) 356 { 357 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 358 359 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, 360 true /* fseg memory */); 361 362 memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature)); 363 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, sizeof(rsdp->oem_id)); 364 rsdp->length = cpu_to_le32(sizeof(*rsdp)); 365 rsdp->revision = 0x02; 366 367 /* Point to RSDT */ 368 rsdp->rsdt_physical_address = cpu_to_le32(rsdt); 369 /* Address to be filled by Guest linker */ 370 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, 371 ACPI_BUILD_TABLE_FILE, 372 rsdp_table, &rsdp->rsdt_physical_address, 373 sizeof rsdp->rsdt_physical_address); 374 rsdp->checksum = 0; 375 /* Checksum to be filled by Guest linker */ 376 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 377 rsdp_table, rsdp, sizeof *rsdp, 378 &rsdp->checksum); 379 380 return rsdp_table; 381 } 382 383 static void 384 build_spcr(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 385 { 386 AcpiSerialPortConsoleRedirection *spcr; 387 const MemMapEntry *uart_memmap = &guest_info->memmap[VIRT_UART]; 388 int irq = guest_info->irqmap[VIRT_UART] + ARM_SPI_BASE; 389 390 spcr = acpi_data_push(table_data, sizeof(*spcr)); 391 392 spcr->interface_type = 0x3; /* ARM PL011 UART */ 393 394 spcr->base_address.space_id = AML_SYSTEM_MEMORY; 395 spcr->base_address.bit_width = 8; 396 spcr->base_address.bit_offset = 0; 397 spcr->base_address.access_width = 1; 398 spcr->base_address.address = cpu_to_le64(uart_memmap->base); 399 400 spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */ 401 spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */ 402 403 spcr->baud = 3; /* Baud Rate: 3 = 9600 */ 404 spcr->parity = 0; /* No Parity */ 405 spcr->stopbits = 1; /* 1 Stop bit */ 406 spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */ 407 spcr->term_type = 0; /* Terminal Type: 0 = VT100 */ 408 409 spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */ 410 spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */ 411 412 build_header(linker, table_data, (void *)spcr, "SPCR", sizeof(*spcr), 2, 413 NULL, NULL); 414 } 415 416 static void 417 build_mcfg(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 418 { 419 AcpiTableMcfg *mcfg; 420 const MemMapEntry *memmap = guest_info->memmap; 421 int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]); 422 423 mcfg = acpi_data_push(table_data, len); 424 mcfg->allocation[0].address = cpu_to_le64(memmap[VIRT_PCIE_ECAM].base); 425 426 /* Only a single allocation so no need to play with segments */ 427 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 428 mcfg->allocation[0].start_bus_number = 0; 429 mcfg->allocation[0].end_bus_number = (memmap[VIRT_PCIE_ECAM].size 430 / PCIE_MMCFG_SIZE_MIN) - 1; 431 432 build_header(linker, table_data, (void *)mcfg, "MCFG", len, 1, NULL, NULL); 433 } 434 435 /* GTDT */ 436 static void 437 build_gtdt(GArray *table_data, GArray *linker) 438 { 439 int gtdt_start = table_data->len; 440 AcpiGenericTimerTable *gtdt; 441 442 gtdt = acpi_data_push(table_data, sizeof *gtdt); 443 /* The interrupt values are the same with the device tree when adding 16 */ 444 gtdt->secure_el1_interrupt = ARCH_TIMER_S_EL1_IRQ + 16; 445 gtdt->secure_el1_flags = ACPI_EDGE_SENSITIVE; 446 447 gtdt->non_secure_el1_interrupt = ARCH_TIMER_NS_EL1_IRQ + 16; 448 gtdt->non_secure_el1_flags = ACPI_EDGE_SENSITIVE | ACPI_GTDT_ALWAYS_ON; 449 450 gtdt->virtual_timer_interrupt = ARCH_TIMER_VIRT_IRQ + 16; 451 gtdt->virtual_timer_flags = ACPI_EDGE_SENSITIVE; 452 453 gtdt->non_secure_el2_interrupt = ARCH_TIMER_NS_EL2_IRQ + 16; 454 gtdt->non_secure_el2_flags = ACPI_EDGE_SENSITIVE; 455 456 build_header(linker, table_data, 457 (void *)(table_data->data + gtdt_start), "GTDT", 458 table_data->len - gtdt_start, 2, NULL, NULL); 459 } 460 461 /* MADT */ 462 static void 463 build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 464 { 465 int madt_start = table_data->len; 466 const MemMapEntry *memmap = guest_info->memmap; 467 const int *irqmap = guest_info->irqmap; 468 AcpiMultipleApicTable *madt; 469 AcpiMadtGenericDistributor *gicd; 470 AcpiMadtGenericMsiFrame *gic_msi; 471 int i; 472 473 madt = acpi_data_push(table_data, sizeof *madt); 474 475 gicd = acpi_data_push(table_data, sizeof *gicd); 476 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR; 477 gicd->length = sizeof(*gicd); 478 gicd->base_address = memmap[VIRT_GIC_DIST].base; 479 480 for (i = 0; i < guest_info->smp_cpus; i++) { 481 AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data, 482 sizeof *gicc); 483 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 484 485 gicc->type = ACPI_APIC_GENERIC_INTERRUPT; 486 gicc->length = sizeof(*gicc); 487 if (guest_info->gic_version == 2) { 488 gicc->base_address = memmap[VIRT_GIC_CPU].base; 489 } 490 gicc->cpu_interface_number = i; 491 gicc->arm_mpidr = armcpu->mp_affinity; 492 gicc->uid = i; 493 gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED); 494 } 495 496 if (guest_info->gic_version == 3) { 497 AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data, 498 sizeof *gicr); 499 500 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 501 gicr->length = sizeof(*gicr); 502 gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base); 503 gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size); 504 } else { 505 gic_msi = acpi_data_push(table_data, sizeof *gic_msi); 506 gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME; 507 gic_msi->length = sizeof(*gic_msi); 508 gic_msi->gic_msi_frame_id = 0; 509 gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base); 510 gic_msi->flags = cpu_to_le32(1); 511 gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS); 512 gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE); 513 } 514 515 build_header(linker, table_data, 516 (void *)(table_data->data + madt_start), "APIC", 517 table_data->len - madt_start, 3, NULL, NULL); 518 } 519 520 /* FADT */ 521 static void 522 build_fadt(GArray *table_data, GArray *linker, unsigned dsdt) 523 { 524 AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); 525 526 /* Hardware Reduced = 1 and use PSCI 0.2+ and with HVC */ 527 fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI); 528 fadt->arm_boot_flags = cpu_to_le16((1 << ACPI_FADT_ARM_USE_PSCI_G_0_2) | 529 (1 << ACPI_FADT_ARM_PSCI_USE_HVC)); 530 531 /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */ 532 fadt->minor_revision = 0x1; 533 534 fadt->dsdt = cpu_to_le32(dsdt); 535 /* DSDT address to be filled by Guest linker */ 536 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 537 ACPI_BUILD_TABLE_FILE, 538 table_data, &fadt->dsdt, 539 sizeof fadt->dsdt); 540 541 build_header(linker, table_data, 542 (void *)fadt, "FACP", sizeof(*fadt), 5, NULL, NULL); 543 } 544 545 /* DSDT */ 546 static void 547 build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 548 { 549 Aml *scope, *dsdt; 550 const MemMapEntry *memmap = guest_info->memmap; 551 const int *irqmap = guest_info->irqmap; 552 553 dsdt = init_aml_allocator(); 554 /* Reserve space for header */ 555 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 556 557 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. 558 * While UEFI can use libfdt to disable the RTC device node in the DTB that 559 * it passes to the OS, it cannot modify AML. Therefore, we won't generate 560 * the RTC ACPI device at all when using UEFI. 561 */ 562 scope = aml_scope("\\_SB"); 563 acpi_dsdt_add_cpus(scope, guest_info->smp_cpus); 564 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], 565 (irqmap[VIRT_UART] + ARM_SPI_BASE)); 566 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); 567 acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); 568 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], 569 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); 570 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), 571 guest_info->use_highmem); 572 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], 573 (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); 574 acpi_dsdt_add_power_button(scope); 575 576 aml_append(dsdt, scope); 577 578 /* copy AML table into ACPI tables blob and patch header there */ 579 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 580 build_header(linker, table_data, 581 (void *)(table_data->data + table_data->len - dsdt->buf->len), 582 "DSDT", dsdt->buf->len, 2, NULL, NULL); 583 free_aml_allocator(); 584 } 585 586 typedef 587 struct AcpiBuildState { 588 /* Copy of table in RAM (for patching). */ 589 MemoryRegion *table_mr; 590 MemoryRegion *rsdp_mr; 591 MemoryRegion *linker_mr; 592 /* Is table patched? */ 593 bool patched; 594 VirtGuestInfo *guest_info; 595 } AcpiBuildState; 596 597 static 598 void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables) 599 { 600 GArray *table_offsets; 601 unsigned dsdt, rsdt; 602 GArray *tables_blob = tables->table_data; 603 604 table_offsets = g_array_new(false, true /* clear */, 605 sizeof(uint32_t)); 606 607 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, 608 64, false /* high memory */); 609 610 /* 611 * The ACPI v5.1 tables for Hardware-reduced ACPI platform are: 612 * RSDP 613 * RSDT 614 * FADT 615 * GTDT 616 * MADT 617 * MCFG 618 * DSDT 619 */ 620 621 /* DSDT is pointed to by FADT */ 622 dsdt = tables_blob->len; 623 build_dsdt(tables_blob, tables->linker, guest_info); 624 625 /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */ 626 acpi_add_table(table_offsets, tables_blob); 627 build_fadt(tables_blob, tables->linker, dsdt); 628 629 acpi_add_table(table_offsets, tables_blob); 630 build_madt(tables_blob, tables->linker, guest_info); 631 632 acpi_add_table(table_offsets, tables_blob); 633 build_gtdt(tables_blob, tables->linker); 634 635 acpi_add_table(table_offsets, tables_blob); 636 build_mcfg(tables_blob, tables->linker, guest_info); 637 638 acpi_add_table(table_offsets, tables_blob); 639 build_spcr(tables_blob, tables->linker, guest_info); 640 641 /* RSDT is pointed to by RSDP */ 642 rsdt = tables_blob->len; 643 build_rsdt(tables_blob, tables->linker, table_offsets, NULL, NULL); 644 645 /* RSDP is in FSEG memory, so allocate it separately */ 646 build_rsdp(tables->rsdp, tables->linker, rsdt); 647 648 /* Cleanup memory that's no longer used. */ 649 g_array_free(table_offsets, true); 650 } 651 652 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 653 { 654 uint32_t size = acpi_data_len(data); 655 656 /* Make sure RAM size is correct - in case it got changed 657 * e.g. by migration */ 658 memory_region_ram_resize(mr, size, &error_abort); 659 660 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 661 memory_region_set_dirty(mr, 0, size); 662 } 663 664 static void virt_acpi_build_update(void *build_opaque) 665 { 666 AcpiBuildState *build_state = build_opaque; 667 AcpiBuildTables tables; 668 669 /* No state to update or already patched? Nothing to do. */ 670 if (!build_state || build_state->patched) { 671 return; 672 } 673 build_state->patched = true; 674 675 acpi_build_tables_init(&tables); 676 677 virt_acpi_build(build_state->guest_info, &tables); 678 679 acpi_ram_update(build_state->table_mr, tables.table_data); 680 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 681 acpi_ram_update(build_state->linker_mr, tables.linker); 682 683 684 acpi_build_tables_cleanup(&tables, true); 685 } 686 687 static void virt_acpi_build_reset(void *build_opaque) 688 { 689 AcpiBuildState *build_state = build_opaque; 690 build_state->patched = false; 691 } 692 693 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, 694 GArray *blob, const char *name, 695 uint64_t max_size) 696 { 697 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 698 name, virt_acpi_build_update, build_state); 699 } 700 701 static const VMStateDescription vmstate_virt_acpi_build = { 702 .name = "virt_acpi_build", 703 .version_id = 1, 704 .minimum_version_id = 1, 705 .fields = (VMStateField[]) { 706 VMSTATE_BOOL(patched, AcpiBuildState), 707 VMSTATE_END_OF_LIST() 708 }, 709 }; 710 711 void virt_acpi_setup(VirtGuestInfo *guest_info) 712 { 713 AcpiBuildTables tables; 714 AcpiBuildState *build_state; 715 716 if (!guest_info->fw_cfg) { 717 trace_virt_acpi_setup(); 718 return; 719 } 720 721 if (!acpi_enabled) { 722 trace_virt_acpi_setup(); 723 return; 724 } 725 726 build_state = g_malloc0(sizeof *build_state); 727 build_state->guest_info = guest_info; 728 729 acpi_build_tables_init(&tables); 730 virt_acpi_build(build_state->guest_info, &tables); 731 732 /* Now expose it all to Guest */ 733 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, 734 ACPI_BUILD_TABLE_FILE, 735 ACPI_BUILD_TABLE_MAX_SIZE); 736 assert(build_state->table_mr != NULL); 737 738 build_state->linker_mr = 739 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); 740 741 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 742 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 743 744 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, 745 ACPI_BUILD_RSDP_FILE, 0); 746 747 qemu_register_reset(virt_acpi_build_reset, build_state); 748 virt_acpi_build_reset(build_state); 749 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 750 751 /* Cleanup tables but don't free the memory: we track it 752 * in build_state. 753 */ 754 acpi_build_tables_cleanup(&tables, false); 755 } 756