1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * ARM virt ACPI generation 4 * 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 6 * Copyright (C) 2006 Fabrice Bellard 7 * Copyright (C) 2013 Red Hat Inc 8 * 9 * Author: Michael S. Tsirkin <mst@redhat.com> 10 * 11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 12 * 13 * Author: Shannon Zhao <zhaoshenglong@huawei.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "qapi/error.h" 31 #include "qemu/bitmap.h" 32 #include "qemu/error-report.h" 33 #include "trace.h" 34 #include "hw/core/cpu.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg_acpi.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/acpi/aml-build.h" 40 #include "hw/acpi/utils.h" 41 #include "hw/acpi/pci.h" 42 #include "hw/acpi/cxl.h" 43 #include "hw/acpi/memory_hotplug.h" 44 #include "hw/acpi/generic_event_device.h" 45 #include "hw/acpi/tpm.h" 46 #include "hw/acpi/hmat.h" 47 #include "hw/cxl/cxl.h" 48 #include "hw/pci/pcie_host.h" 49 #include "hw/pci/pci.h" 50 #include "hw/pci/pci_bus.h" 51 #include "hw/pci-host/gpex.h" 52 #include "hw/arm/virt.h" 53 #include "hw/intc/arm_gicv3_its_common.h" 54 #include "hw/mem/nvdimm.h" 55 #include "hw/platform-bus.h" 56 #include "system/numa.h" 57 #include "system/reset.h" 58 #include "system/tpm.h" 59 #include "migration/vmstate.h" 60 #include "hw/acpi/ghes.h" 61 #include "hw/acpi/viot.h" 62 #include "hw/virtio/virtio-acpi.h" 63 #include "target/arm/multiprocessing.h" 64 65 #define ARM_SPI_BASE 32 66 67 #define ACPI_BUILD_TABLE_SIZE 0x20000 68 69 static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms) 70 { 71 MachineState *ms = MACHINE(vms); 72 uint16_t i; 73 74 for (i = 0; i < ms->smp.cpus; i++) { 75 Aml *dev = aml_device("C%.03X", i); 76 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 77 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 78 aml_append(scope, dev); 79 } 80 } 81 82 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 83 uint32_t uart_irq, int uartidx) 84 { 85 Aml *dev = aml_device("COM%d", uartidx); 86 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); 87 aml_append(dev, aml_name_decl("_UID", aml_int(uartidx))); 88 89 Aml *crs = aml_resource_template(); 90 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 91 uart_memmap->size, AML_READ_WRITE)); 92 aml_append(crs, 93 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 94 AML_EXCLUSIVE, &uart_irq, 1)); 95 aml_append(dev, aml_name_decl("_CRS", crs)); 96 97 aml_append(scope, dev); 98 } 99 100 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) 101 { 102 Aml *dev, *crs; 103 hwaddr base = flash_memmap->base; 104 hwaddr size = flash_memmap->size / 2; 105 106 dev = aml_device("FLS0"); 107 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 108 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 109 110 crs = aml_resource_template(); 111 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 112 aml_append(dev, aml_name_decl("_CRS", crs)); 113 aml_append(scope, dev); 114 115 dev = aml_device("FLS1"); 116 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 117 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 118 crs = aml_resource_template(); 119 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); 120 aml_append(dev, aml_name_decl("_CRS", crs)); 121 aml_append(scope, dev); 122 } 123 124 static void build_acpi0017(Aml *table) 125 { 126 Aml *dev, *scope, *method; 127 128 scope = aml_scope("_SB"); 129 dev = aml_device("CXLM"); 130 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); 131 132 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 133 aml_append(method, aml_return(aml_int(0x0B))); 134 aml_append(dev, method); 135 build_cxl_dsm_method(dev); 136 137 aml_append(scope, dev); 138 aml_append(table, scope); 139 } 140 141 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, 142 uint32_t irq, VirtMachineState *vms) 143 { 144 int ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 145 bool cxl_present = false; 146 PCIBus *bus = vms->bus; 147 bool acpi_pcihp = false; 148 149 if (vms->acpi_dev) { 150 acpi_pcihp = object_property_get_bool(OBJECT(vms->acpi_dev), 151 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 152 NULL); 153 } 154 155 struct GPEXConfig cfg = { 156 .mmio32 = memmap[VIRT_PCIE_MMIO], 157 .pio = memmap[VIRT_PCIE_PIO], 158 .ecam = memmap[ecam_id], 159 .irq = irq, 160 .bus = vms->bus, 161 .pci_native_hotplug = !acpi_pcihp, 162 }; 163 164 if (vms->highmem_mmio) { 165 cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO]; 166 } 167 168 acpi_dsdt_add_gpex(scope, &cfg); 169 QLIST_FOREACH(bus, &vms->bus->child, sibling) { 170 if (pci_bus_is_cxl(bus)) { 171 cxl_present = true; 172 } 173 } 174 if (cxl_present) { 175 build_acpi0017(scope); 176 } 177 } 178 179 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, 180 uint32_t gpio_irq) 181 { 182 Aml *dev = aml_device("GPO0"); 183 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); 184 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 185 186 Aml *crs = aml_resource_template(); 187 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, 188 AML_READ_WRITE)); 189 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 190 AML_EXCLUSIVE, &gpio_irq, 1)); 191 aml_append(dev, aml_name_decl("_CRS", crs)); 192 193 Aml *aei = aml_resource_template(); 194 195 const uint32_t pin = GPIO_PIN_POWER_BUTTON; 196 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, 197 AML_EXCLUSIVE, AML_PULL_UP, 0, &pin, 1, 198 "GPO0", NULL, 0)); 199 aml_append(dev, aml_name_decl("_AEI", aei)); 200 201 /* _E03 is handle for power button */ 202 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); 203 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), 204 aml_int(0x80))); 205 aml_append(dev, method); 206 aml_append(scope, dev); 207 } 208 209 #ifdef CONFIG_TPM 210 static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms) 211 { 212 PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); 213 hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base; 214 SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find()); 215 MemoryRegion *sbdev_mr; 216 hwaddr tpm_base; 217 218 if (!sbdev) { 219 return; 220 } 221 222 tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); 223 assert(tpm_base != -1); 224 225 tpm_base += pbus_base; 226 227 sbdev_mr = sysbus_mmio_get_region(sbdev, 0); 228 229 Aml *dev = aml_device("TPM0"); 230 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 231 aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device"))); 232 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 233 234 Aml *crs = aml_resource_template(); 235 aml_append(crs, 236 aml_memory32_fixed(tpm_base, 237 (uint32_t)memory_region_size(sbdev_mr), 238 AML_READ_WRITE)); 239 aml_append(dev, aml_name_decl("_CRS", crs)); 240 aml_append(scope, dev); 241 } 242 #endif 243 244 #define ID_MAPPING_ENTRY_SIZE 20 245 #define SMMU_V3_ENTRY_SIZE 68 246 #define ROOT_COMPLEX_ENTRY_SIZE 36 247 #define IORT_NODE_OFFSET 48 248 249 /* 250 * Append an ID mapping entry as described by "Table 4 ID mapping format" in 251 * "IO Remapping Table System Software on ARM Platforms", Chapter 3. 252 * Document number: ARM DEN 0049E.f, Apr 2024 253 * 254 * Note that @id_count gets internally subtracted by one, following the spec. 255 */ 256 static void build_iort_id_mapping(GArray *table_data, uint32_t input_base, 257 uint32_t id_count, uint32_t out_ref) 258 { 259 build_append_int_noprefix(table_data, input_base, 4); /* Input base */ 260 /* Number of IDs - The number of IDs in the range minus one */ 261 build_append_int_noprefix(table_data, id_count - 1, 4); 262 build_append_int_noprefix(table_data, input_base, 4); /* Output base */ 263 build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference */ 264 /* Flags */ 265 build_append_int_noprefix(table_data, 0 /* Single mapping (disabled) */, 4); 266 } 267 268 struct AcpiIortIdMapping { 269 uint32_t input_base; 270 uint32_t id_count; 271 }; 272 typedef struct AcpiIortIdMapping AcpiIortIdMapping; 273 274 /* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */ 275 static int 276 iort_host_bridges(Object *obj, void *opaque) 277 { 278 GArray *idmap_blob = opaque; 279 280 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 281 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 282 283 if (bus && !pci_bus_bypass_iommu(bus)) { 284 int min_bus, max_bus; 285 286 pci_bus_range(bus, &min_bus, &max_bus); 287 288 AcpiIortIdMapping idmap = { 289 .input_base = min_bus << 8, 290 .id_count = (max_bus - min_bus + 1) << 8, 291 }; 292 g_array_append_val(idmap_blob, idmap); 293 } 294 } 295 296 return 0; 297 } 298 299 static int iort_idmap_compare(gconstpointer a, gconstpointer b) 300 { 301 AcpiIortIdMapping *idmap_a = (AcpiIortIdMapping *)a; 302 AcpiIortIdMapping *idmap_b = (AcpiIortIdMapping *)b; 303 304 return idmap_a->input_base - idmap_b->input_base; 305 } 306 307 /* Compute ID ranges (RIDs) from RC that are directed to the ITS Group node */ 308 static void create_rc_its_idmaps(GArray *its_idmaps, GArray *smmu_idmaps) 309 { 310 AcpiIortIdMapping *idmap; 311 AcpiIortIdMapping next_range = {0}; 312 313 /* 314 * Based on the RID ranges that are directed to the SMMU, determine the 315 * bypassed RID ranges, i.e., the ones that are directed to the ITS Group 316 * node and do not pass through the SMMU, by subtracting the SMMU-bound 317 * ranges from the full RID range (0x0000–0xFFFF). 318 */ 319 for (int i = 0; i < smmu_idmaps->len; i++) { 320 idmap = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); 321 322 if (next_range.input_base < idmap->input_base) { 323 next_range.id_count = idmap->input_base - next_range.input_base; 324 g_array_append_val(its_idmaps, next_range); 325 } 326 327 next_range.input_base = idmap->input_base + idmap->id_count; 328 } 329 330 /* 331 * Append the last RC -> ITS ID mapping. 332 * 333 * RIDs are 16-bit, according to the PCI Express 2.0 Base Specification, rev 334 * 0.9, section 2.2.6.2, "Transaction Descriptor - Transaction ID Field", 335 * hence the end of the range is 0x10000. 336 */ 337 if (next_range.input_base < 0x10000) { 338 next_range.id_count = 0x10000 - next_range.input_base; 339 g_array_append_val(its_idmaps, next_range); 340 } 341 } 342 343 344 /* 345 * Input Output Remapping Table (IORT) 346 * Conforms to "IO Remapping Table System Software on ARM Platforms", 347 * Document number: ARM DEN 0049E.b, Feb 2021 348 */ 349 static void 350 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 351 { 352 int i, nb_nodes, rc_mapping_count; 353 size_t node_size, smmu_offset = 0; 354 uint32_t id = 0; 355 GArray *rc_smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); 356 GArray *rc_its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); 357 358 AcpiTable table = { .sig = "IORT", .rev = 3, .oem_id = vms->oem_id, 359 .oem_table_id = vms->oem_table_id }; 360 /* Table 2 The IORT */ 361 acpi_table_begin(&table, table_data); 362 363 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 364 object_child_foreach_recursive(object_get_root(), 365 iort_host_bridges, rc_smmu_idmaps); 366 367 /* Sort the smmu idmap by input_base */ 368 g_array_sort(rc_smmu_idmaps, iort_idmap_compare); 369 370 nb_nodes = 2; /* RC and SMMUv3 */ 371 rc_mapping_count = rc_smmu_idmaps->len; 372 373 if (vms->its) { 374 /* 375 * Knowing the ID ranges from the RC to the SMMU, it's possible to 376 * determine the ID ranges from RC that go directly to ITS. 377 */ 378 create_rc_its_idmaps(rc_its_idmaps, rc_smmu_idmaps); 379 380 nb_nodes++; /* ITS */ 381 rc_mapping_count += rc_its_idmaps->len; 382 } 383 } else { 384 if (vms->its) { 385 nb_nodes = 2; /* RC and ITS */ 386 rc_mapping_count = 1; /* Direct map to ITS */ 387 } else { 388 nb_nodes = 1; /* RC only */ 389 rc_mapping_count = 0; /* No output mapping */ 390 } 391 } 392 /* Number of IORT Nodes */ 393 build_append_int_noprefix(table_data, nb_nodes, 4); 394 395 /* Offset to Array of IORT Nodes */ 396 build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4); 397 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 398 399 if (vms->its) { 400 /* Table 12 ITS Group Format */ 401 build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */ 402 node_size = 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */; 403 build_append_int_noprefix(table_data, node_size, 2); /* Length */ 404 build_append_int_noprefix(table_data, 1, 1); /* Revision */ 405 build_append_int_noprefix(table_data, id++, 4); /* Identifier */ 406 build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */ 407 build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */ 408 build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */ 409 /* GIC ITS Identifier Array */ 410 build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4); 411 } 412 413 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 414 int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; 415 int smmu_mapping_count, offset_to_id_array; 416 417 if (vms->its) { 418 smmu_mapping_count = 1; /* ITS Group node */ 419 offset_to_id_array = SMMU_V3_ENTRY_SIZE; /* Just after the header */ 420 } else { 421 smmu_mapping_count = 0; /* No ID mappings */ 422 offset_to_id_array = 0; /* No ID mappings array */ 423 } 424 smmu_offset = table_data->len - table.table_offset; 425 /* Table 9 SMMUv3 Format */ 426 build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type */ 427 node_size = SMMU_V3_ENTRY_SIZE + 428 (ID_MAPPING_ENTRY_SIZE * smmu_mapping_count); 429 build_append_int_noprefix(table_data, node_size, 2); /* Length */ 430 build_append_int_noprefix(table_data, 4, 1); /* Revision */ 431 build_append_int_noprefix(table_data, id++, 4); /* Identifier */ 432 /* Number of ID mappings */ 433 build_append_int_noprefix(table_data, smmu_mapping_count, 4); 434 /* Reference to ID Array */ 435 build_append_int_noprefix(table_data, offset_to_id_array, 4); 436 /* Base address */ 437 build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base, 8); 438 /* Flags */ 439 build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4); 440 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 441 build_append_int_noprefix(table_data, 0, 8); /* VATOS address */ 442 /* Model */ 443 build_append_int_noprefix(table_data, 0 /* Generic SMMU-v3 */, 4); 444 build_append_int_noprefix(table_data, irq, 4); /* Event */ 445 build_append_int_noprefix(table_data, irq + 1, 4); /* PRI */ 446 build_append_int_noprefix(table_data, irq + 3, 4); /* GERR */ 447 build_append_int_noprefix(table_data, irq + 2, 4); /* Sync */ 448 build_append_int_noprefix(table_data, 0, 4); /* Proximity domain */ 449 /* DeviceID mapping index (ignored since interrupts are GSIV based) */ 450 build_append_int_noprefix(table_data, 0, 4); 451 /* Array of ID mappings */ 452 if (smmu_mapping_count) { 453 /* Output IORT node is the ITS Group node (the first node). */ 454 build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET); 455 } 456 } 457 458 /* Table 17 Root Complex Node */ 459 build_append_int_noprefix(table_data, 2 /* Root complex */, 1); /* Type */ 460 node_size = ROOT_COMPLEX_ENTRY_SIZE + 461 ID_MAPPING_ENTRY_SIZE * rc_mapping_count; 462 build_append_int_noprefix(table_data, node_size, 2); /* Length */ 463 build_append_int_noprefix(table_data, 3, 1); /* Revision */ 464 build_append_int_noprefix(table_data, id++, 4); /* Identifier */ 465 /* Number of ID mappings */ 466 build_append_int_noprefix(table_data, rc_mapping_count, 4); 467 /* Reference to ID Array */ 468 build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 4); 469 470 /* Table 14 Memory access properties */ 471 /* CCA: Cache Coherent Attribute */ 472 build_append_int_noprefix(table_data, 1 /* fully coherent */, 4); 473 build_append_int_noprefix(table_data, 0, 1); /* AH: Note Allocation Hints */ 474 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 475 /* Table 15 Memory Access Flags */ 476 build_append_int_noprefix(table_data, 0x3 /* CCA = CPM = DACS = 1 */, 1); 477 478 build_append_int_noprefix(table_data, 0, 4); /* ATS Attribute */ 479 /* MCFG pci_segment */ 480 build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */ 481 482 /* Memory address size limit */ 483 build_append_int_noprefix(table_data, 64, 1); 484 485 build_append_int_noprefix(table_data, 0, 3); /* Reserved */ 486 487 /* Output Reference */ 488 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 489 AcpiIortIdMapping *range; 490 491 /* 492 * Map RIDs (input) from RC to SMMUv3 nodes: RC -> SMMUv3. 493 * 494 * N.B.: The mapping from SMMUv3 to ITS Group node (SMMUv3 -> ITS) is 495 * defined in the SMMUv3 table, where all SMMUv3 IDs are mapped to the 496 * ITS Group node, if ITS is available. 497 */ 498 for (i = 0; i < rc_smmu_idmaps->len; i++) { 499 range = &g_array_index(rc_smmu_idmaps, AcpiIortIdMapping, i); 500 /* Output IORT node is the SMMUv3 node. */ 501 build_iort_id_mapping(table_data, range->input_base, 502 range->id_count, smmu_offset); 503 } 504 505 if (vms->its) { 506 /* 507 * Map bypassed (don't go through the SMMU) RIDs (input) to 508 * ITS Group node directly: RC -> ITS. 509 */ 510 for (i = 0; i < rc_its_idmaps->len; i++) { 511 range = &g_array_index(rc_its_idmaps, AcpiIortIdMapping, i); 512 /* Output IORT node is the ITS Group node (the first node). */ 513 build_iort_id_mapping(table_data, range->input_base, 514 range->id_count, IORT_NODE_OFFSET); 515 } 516 } 517 } else { 518 /* 519 * Map all RIDs (input) to ITS Group node directly, since there is no 520 * SMMU: RC -> ITS. 521 * Output IORT node is the ITS Group node (the first node). 522 */ 523 build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET); 524 } 525 526 acpi_table_end(linker, &table); 527 g_array_free(rc_smmu_idmaps, true); 528 g_array_free(rc_its_idmaps, true); 529 } 530 531 /* 532 * Serial Port Console Redirection Table (SPCR) 533 * Rev: 1.07 534 */ 535 static void 536 spcr_setup(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 537 { 538 AcpiSpcrData serial = { 539 .interface_type = 3, /* ARM PL011 UART */ 540 .base_addr.id = AML_AS_SYSTEM_MEMORY, 541 .base_addr.width = 32, 542 .base_addr.offset = 0, 543 .base_addr.size = 3, 544 .base_addr.addr = vms->memmap[VIRT_UART0].base, 545 .interrupt_type = (1 << 3),/* Bit[3] ARMH GIC interrupt*/ 546 .pc_interrupt = 0, /* IRQ */ 547 .interrupt = (vms->irqmap[VIRT_UART0] + ARM_SPI_BASE), 548 .baud_rate = 3, /* 9600 */ 549 .parity = 0, /* No Parity */ 550 .stop_bits = 1, /* 1 Stop bit */ 551 .flow_control = 1 << 1, /* RTS/CTS hardware flow control */ 552 .terminal_type = 0, /* VT100 */ 553 .language = 0, /* Language */ 554 .pci_device_id = 0xffff, /* not a PCI device*/ 555 .pci_vendor_id = 0xffff, /* not a PCI device*/ 556 .pci_bus = 0, 557 .pci_device = 0, 558 .pci_function = 0, 559 .pci_flags = 0, 560 .pci_segment = 0, 561 }; 562 /* 563 * Passing NULL as the SPCR Table for Revision 2 doesn't support 564 * NameSpaceString. 565 */ 566 build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id, 567 NULL); 568 } 569 570 /* 571 * ACPI spec, Revision 5.1 572 * 5.2.16 System Resource Affinity Table (SRAT) 573 */ 574 static void 575 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 576 { 577 int i; 578 uint64_t mem_base; 579 MachineClass *mc = MACHINE_GET_CLASS(vms); 580 MachineState *ms = MACHINE(vms); 581 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); 582 AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id, 583 .oem_table_id = vms->oem_table_id }; 584 585 acpi_table_begin(&table, table_data); 586 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 587 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 588 589 for (i = 0; i < cpu_list->len; ++i) { 590 uint32_t nodeid = cpu_list->cpus[i].props.node_id; 591 /* 592 * 5.2.16.4 GICC Affinity Structure 593 */ 594 build_append_int_noprefix(table_data, 3, 1); /* Type */ 595 build_append_int_noprefix(table_data, 18, 1); /* Length */ 596 build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */ 597 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ 598 /* Flags, Table 5-76 */ 599 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 600 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 601 } 602 603 mem_base = vms->memmap[VIRT_MEM].base; 604 for (i = 0; i < ms->numa_state->num_nodes; ++i) { 605 if (ms->numa_state->nodes[i].node_mem > 0) { 606 build_srat_memory(table_data, mem_base, 607 ms->numa_state->nodes[i].node_mem, i, 608 MEM_AFFINITY_ENABLED); 609 mem_base += ms->numa_state->nodes[i].node_mem; 610 } 611 } 612 613 build_srat_generic_affinity_structures(table_data); 614 615 if (ms->nvdimms_state->is_enabled) { 616 nvdimm_build_srat(table_data); 617 } 618 619 if (ms->device_memory) { 620 build_srat_memory(table_data, ms->device_memory->base, 621 memory_region_size(&ms->device_memory->mr), 622 ms->numa_state->num_nodes - 1, 623 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 624 } 625 626 acpi_table_end(linker, &table); 627 } 628 629 /* 630 * ACPI spec, Revision 6.5 631 * 5.2.25 Generic Timer Description Table (GTDT) 632 */ 633 static void 634 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 635 { 636 /* 637 * Table 5-117 Flag Definitions 638 * set only "Timer interrupt Mode" and assume "Timer Interrupt 639 * polarity" bit as '0: Interrupt is Active high' 640 */ 641 const uint32_t irqflags = 0; /* Interrupt is Level triggered */ 642 AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id, 643 .oem_table_id = vms->oem_table_id }; 644 645 acpi_table_begin(&table, table_data); 646 647 /* CntControlBase Physical Address */ 648 build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8); 649 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 650 /* 651 * FIXME: clarify comment: 652 * The interrupt values are the same with the device tree when adding 16 653 */ 654 /* Secure EL1 timer GSIV */ 655 build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ, 4); 656 /* Secure EL1 timer Flags */ 657 build_append_int_noprefix(table_data, irqflags, 4); 658 /* Non-Secure EL1 timer GSIV */ 659 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ, 4); 660 /* Non-Secure EL1 timer Flags */ 661 build_append_int_noprefix(table_data, irqflags | 662 1UL << 2, /* Always-on Capability */ 663 4); 664 /* Virtual timer GSIV */ 665 build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ, 4); 666 /* Virtual Timer Flags */ 667 build_append_int_noprefix(table_data, irqflags, 4); 668 /* Non-Secure EL2 timer GSIV */ 669 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ, 4); 670 /* Non-Secure EL2 timer Flags */ 671 build_append_int_noprefix(table_data, irqflags, 4); 672 /* CntReadBase Physical address */ 673 build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8); 674 /* Platform Timer Count */ 675 build_append_int_noprefix(table_data, 0, 4); 676 /* Platform Timer Offset */ 677 build_append_int_noprefix(table_data, 0, 4); 678 if (vms->ns_el2_virt_timer_irq) { 679 /* Virtual EL2 Timer GSIV */ 680 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, 4); 681 /* Virtual EL2 Timer Flags */ 682 build_append_int_noprefix(table_data, irqflags, 4); 683 } else { 684 build_append_int_noprefix(table_data, 0, 4); 685 build_append_int_noprefix(table_data, 0, 4); 686 } 687 acpi_table_end(linker, &table); 688 } 689 690 /* Debug Port Table 2 (DBG2) */ 691 static void 692 build_dbg2(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 693 { 694 AcpiTable table = { .sig = "DBG2", .rev = 0, .oem_id = vms->oem_id, 695 .oem_table_id = vms->oem_table_id }; 696 int dbg2devicelength; 697 const char name[] = "COM0"; 698 const int namespace_length = sizeof(name); 699 700 acpi_table_begin(&table, table_data); 701 702 dbg2devicelength = 22 + /* BaseAddressRegister[] offset */ 703 12 + /* BaseAddressRegister[] */ 704 4 + /* AddressSize[] */ 705 namespace_length /* NamespaceString[] */; 706 707 /* OffsetDbgDeviceInfo */ 708 build_append_int_noprefix(table_data, 44, 4); 709 /* NumberDbgDeviceInfo */ 710 build_append_int_noprefix(table_data, 1, 4); 711 712 /* Table 2. Debug Device Information structure format */ 713 build_append_int_noprefix(table_data, 0, 1); /* Revision */ 714 build_append_int_noprefix(table_data, dbg2devicelength, 2); /* Length */ 715 /* NumberofGenericAddressRegisters */ 716 build_append_int_noprefix(table_data, 1, 1); 717 /* NameSpaceStringLength */ 718 build_append_int_noprefix(table_data, namespace_length, 2); 719 build_append_int_noprefix(table_data, 38, 2); /* NameSpaceStringOffset */ 720 build_append_int_noprefix(table_data, 0, 2); /* OemDataLength */ 721 /* OemDataOffset (0 means no OEM data) */ 722 build_append_int_noprefix(table_data, 0, 2); 723 724 /* Port Type */ 725 build_append_int_noprefix(table_data, 0x8000 /* Serial */, 2); 726 /* Port Subtype */ 727 build_append_int_noprefix(table_data, 0x3 /* ARM PL011 UART */, 2); 728 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 729 /* BaseAddressRegisterOffset */ 730 build_append_int_noprefix(table_data, 22, 2); 731 /* AddressSizeOffset */ 732 build_append_int_noprefix(table_data, 34, 2); 733 734 /* BaseAddressRegister[] */ 735 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3, 736 vms->memmap[VIRT_UART0].base); 737 738 /* AddressSize[] */ 739 build_append_int_noprefix(table_data, 740 vms->memmap[VIRT_UART0].size, 4); 741 742 /* NamespaceString[] */ 743 g_array_append_vals(table_data, name, namespace_length); 744 745 acpi_table_end(linker, &table); 746 }; 747 748 /* 749 * ACPI spec, Revision 6.0 Errata A 750 * 5.2.12 Multiple APIC Description Table (MADT) 751 */ 752 static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size) 753 { 754 build_append_int_noprefix(table_data, 0xE, 1); /* Type */ 755 build_append_int_noprefix(table_data, 16, 1); /* Length */ 756 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 757 /* Discovery Range Base Address */ 758 build_append_int_noprefix(table_data, base, 8); 759 build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */ 760 } 761 762 static void 763 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 764 { 765 int i; 766 const MemMapEntry *memmap = vms->memmap; 767 AcpiTable table = { .sig = "APIC", .rev = 4, .oem_id = vms->oem_id, 768 .oem_table_id = vms->oem_table_id }; 769 770 acpi_table_begin(&table, table_data); 771 /* Local Interrupt Controller Address */ 772 build_append_int_noprefix(table_data, 0, 4); 773 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 774 775 /* 5.2.12.15 GIC Distributor Structure */ 776 build_append_int_noprefix(table_data, 0xC, 1); /* Type */ 777 build_append_int_noprefix(table_data, 24, 1); /* Length */ 778 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 779 build_append_int_noprefix(table_data, 0, 4); /* GIC ID */ 780 /* Physical Base Address */ 781 build_append_int_noprefix(table_data, memmap[VIRT_GIC_DIST].base, 8); 782 build_append_int_noprefix(table_data, 0, 4); /* System Vector Base */ 783 /* GIC version */ 784 build_append_int_noprefix(table_data, vms->gic_version, 1); 785 build_append_int_noprefix(table_data, 0, 3); /* Reserved */ 786 787 for (i = 0; i < MACHINE(vms)->smp.cpus; i++) { 788 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 789 uint64_t physical_base_address = 0, gich = 0, gicv = 0; 790 uint32_t vgic_interrupt = vms->virt ? ARCH_GIC_MAINT_IRQ : 0; 791 uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ? 792 VIRTUAL_PMU_IRQ : 0; 793 794 if (vms->gic_version == VIRT_GIC_VERSION_2) { 795 physical_base_address = memmap[VIRT_GIC_CPU].base; 796 gicv = memmap[VIRT_GIC_VCPU].base; 797 gich = memmap[VIRT_GIC_HYP].base; 798 } 799 800 /* 5.2.12.14 GIC Structure */ 801 build_append_int_noprefix(table_data, 0xB, 1); /* Type */ 802 build_append_int_noprefix(table_data, 80, 1); /* Length */ 803 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 804 build_append_int_noprefix(table_data, i, 4); /* GIC ID */ 805 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ 806 /* Flags */ 807 build_append_int_noprefix(table_data, 1, 4); /* Enabled */ 808 /* Parking Protocol Version */ 809 build_append_int_noprefix(table_data, 0, 4); 810 /* Performance Interrupt GSIV */ 811 build_append_int_noprefix(table_data, pmu_interrupt, 4); 812 build_append_int_noprefix(table_data, 0, 8); /* Parked Address */ 813 /* Physical Base Address */ 814 build_append_int_noprefix(table_data, physical_base_address, 8); 815 build_append_int_noprefix(table_data, gicv, 8); /* GICV */ 816 build_append_int_noprefix(table_data, gich, 8); /* GICH */ 817 /* VGIC Maintenance interrupt */ 818 build_append_int_noprefix(table_data, vgic_interrupt, 4); 819 build_append_int_noprefix(table_data, 0, 8); /* GICR Base Address*/ 820 /* MPIDR */ 821 build_append_int_noprefix(table_data, arm_cpu_mp_affinity(armcpu), 8); 822 /* Processor Power Efficiency Class */ 823 build_append_int_noprefix(table_data, 0, 1); 824 /* Reserved */ 825 build_append_int_noprefix(table_data, 0, 3); 826 } 827 828 if (vms->gic_version != VIRT_GIC_VERSION_2) { 829 build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base, 830 memmap[VIRT_GIC_REDIST].size); 831 if (virt_gicv3_redist_region_count(vms) == 2) { 832 build_append_gicr(table_data, memmap[VIRT_HIGH_GIC_REDIST2].base, 833 memmap[VIRT_HIGH_GIC_REDIST2].size); 834 } 835 836 if (vms->its) { 837 /* 838 * ACPI spec, Revision 6.0 Errata A 839 * (original 6.0 definition has invalid Length) 840 * 5.2.12.18 GIC ITS Structure 841 */ 842 build_append_int_noprefix(table_data, 0xF, 1); /* Type */ 843 build_append_int_noprefix(table_data, 20, 1); /* Length */ 844 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 845 build_append_int_noprefix(table_data, 0, 4); /* GIC ITS ID */ 846 /* Physical Base Address */ 847 build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].base, 8); 848 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 849 } 850 } else { 851 const uint16_t spi_base = vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE; 852 853 /* 5.2.12.16 GIC MSI Frame Structure */ 854 build_append_int_noprefix(table_data, 0xD, 1); /* Type */ 855 build_append_int_noprefix(table_data, 24, 1); /* Length */ 856 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 857 build_append_int_noprefix(table_data, 0, 4); /* GIC MSI Frame ID */ 858 /* Physical Base Address */ 859 build_append_int_noprefix(table_data, memmap[VIRT_GIC_V2M].base, 8); 860 build_append_int_noprefix(table_data, 1, 4); /* Flags */ 861 /* SPI Count */ 862 build_append_int_noprefix(table_data, NUM_GICV2M_SPIS, 2); 863 build_append_int_noprefix(table_data, spi_base, 2); /* SPI Base */ 864 } 865 acpi_table_end(linker, &table); 866 } 867 868 /* FADT */ 869 static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker, 870 VirtMachineState *vms, unsigned dsdt_tbl_offset) 871 { 872 /* ACPI v6.3 */ 873 AcpiFadtData fadt = { 874 .rev = 6, 875 .minor_ver = 3, 876 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, 877 .xdsdt_tbl_offset = &dsdt_tbl_offset, 878 }; 879 880 switch (vms->psci_conduit) { 881 case QEMU_PSCI_CONDUIT_DISABLED: 882 fadt.arm_boot_arch = 0; 883 break; 884 case QEMU_PSCI_CONDUIT_HVC: 885 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT | 886 ACPI_FADT_ARM_PSCI_USE_HVC; 887 break; 888 case QEMU_PSCI_CONDUIT_SMC: 889 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT; 890 break; 891 default: 892 g_assert_not_reached(); 893 } 894 895 build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id); 896 } 897 898 /* DSDT */ 899 static void 900 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 901 { 902 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 903 Aml *scope, *dsdt; 904 MachineState *ms = MACHINE(vms); 905 const MemMapEntry *memmap = vms->memmap; 906 const int *irqmap = vms->irqmap; 907 AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = vms->oem_id, 908 .oem_table_id = vms->oem_table_id }; 909 910 acpi_table_begin(&table, table_data); 911 dsdt = init_aml_allocator(); 912 913 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. 914 * While UEFI can use libfdt to disable the RTC device node in the DTB that 915 * it passes to the OS, it cannot modify AML. Therefore, we won't generate 916 * the RTC ACPI device at all when using UEFI. 917 */ 918 scope = aml_scope("\\_SB"); 919 acpi_dsdt_add_cpus(scope, vms); 920 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], 921 (irqmap[VIRT_UART0] + ARM_SPI_BASE), 0); 922 if (vms->second_ns_uart_present) { 923 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART1], 924 (irqmap[VIRT_UART1] + ARM_SPI_BASE), 1); 925 } 926 if (vmc->acpi_expose_flash) { 927 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); 928 } 929 fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]); 930 virtio_acpi_dsdt_add(scope, memmap[VIRT_MMIO].base, memmap[VIRT_MMIO].size, 931 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), 932 0, NUM_VIRTIO_TRANSPORTS); 933 acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms); 934 if (vms->acpi_dev) { 935 build_ged_aml(scope, "\\_SB."GED_DEVICE, 936 HOTPLUG_HANDLER(vms->acpi_dev), 937 irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY, 938 memmap[VIRT_ACPI_GED].base); 939 } else { 940 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], 941 (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); 942 } 943 944 if (vms->acpi_dev) { 945 uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev), 946 "ged-event", &error_abort); 947 948 if (event & ACPI_GED_MEM_HOTPLUG_EVT) { 949 build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL, 950 AML_SYSTEM_MEMORY, 951 memmap[VIRT_PCDIMM_ACPI].base); 952 } 953 } 954 955 acpi_dsdt_add_power_button(scope); 956 #ifdef CONFIG_TPM 957 acpi_dsdt_add_tpm(scope, vms); 958 #endif 959 960 aml_append(dsdt, scope); 961 962 /* copy AML table into ACPI tables blob */ 963 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 964 965 acpi_table_end(linker, &table); 966 free_aml_allocator(); 967 } 968 969 typedef 970 struct AcpiBuildState { 971 /* Copy of table in RAM (for patching). */ 972 MemoryRegion *table_mr; 973 MemoryRegion *rsdp_mr; 974 MemoryRegion *linker_mr; 975 /* Is table patched? */ 976 bool patched; 977 } AcpiBuildState; 978 979 static void acpi_align_size(GArray *blob, unsigned align) 980 { 981 /* 982 * Align size to multiple of given size. This reduces the chance 983 * we need to change size in the future (breaking cross version migration). 984 */ 985 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 986 } 987 988 static 989 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) 990 { 991 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 992 GArray *table_offsets; 993 unsigned dsdt, xsdt; 994 GArray *tables_blob = tables->table_data; 995 MachineState *ms = MACHINE(vms); 996 997 table_offsets = g_array_new(false, true /* clear */, 998 sizeof(uint32_t)); 999 1000 bios_linker_loader_alloc(tables->linker, 1001 ACPI_BUILD_TABLE_FILE, tables_blob, 1002 64, false /* high memory */); 1003 1004 /* DSDT is pointed to by FADT */ 1005 dsdt = tables_blob->len; 1006 build_dsdt(tables_blob, tables->linker, vms); 1007 1008 /* FADT MADT PPTT GTDT MCFG SPCR DBG2 pointed to by RSDT */ 1009 acpi_add_table(table_offsets, tables_blob); 1010 build_fadt_rev6(tables_blob, tables->linker, vms, dsdt); 1011 1012 acpi_add_table(table_offsets, tables_blob); 1013 build_madt(tables_blob, tables->linker, vms); 1014 1015 if (!vmc->no_cpu_topology) { 1016 acpi_add_table(table_offsets, tables_blob); 1017 build_pptt(tables_blob, tables->linker, ms, 1018 vms->oem_id, vms->oem_table_id); 1019 } 1020 1021 acpi_add_table(table_offsets, tables_blob); 1022 build_gtdt(tables_blob, tables->linker, vms); 1023 1024 acpi_add_table(table_offsets, tables_blob); 1025 { 1026 AcpiMcfgInfo mcfg = { 1027 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, 1028 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, 1029 }; 1030 build_mcfg(tables_blob, tables->linker, &mcfg, vms->oem_id, 1031 vms->oem_table_id); 1032 } 1033 1034 acpi_add_table(table_offsets, tables_blob); 1035 1036 if (ms->acpi_spcr_enabled) { 1037 spcr_setup(tables_blob, tables->linker, vms); 1038 } 1039 1040 acpi_add_table(table_offsets, tables_blob); 1041 build_dbg2(tables_blob, tables->linker, vms); 1042 1043 if (vms->ras) { 1044 acpi_add_table(table_offsets, tables_blob); 1045 acpi_build_hest(tables_blob, tables->hardware_errors, tables->linker, 1046 vms->oem_id, vms->oem_table_id); 1047 } 1048 1049 if (ms->numa_state->num_nodes > 0) { 1050 acpi_add_table(table_offsets, tables_blob); 1051 build_srat(tables_blob, tables->linker, vms); 1052 if (ms->numa_state->have_numa_distance) { 1053 acpi_add_table(table_offsets, tables_blob); 1054 build_slit(tables_blob, tables->linker, ms, vms->oem_id, 1055 vms->oem_table_id); 1056 } 1057 1058 if (ms->numa_state->hmat_enabled) { 1059 acpi_add_table(table_offsets, tables_blob); 1060 build_hmat(tables_blob, tables->linker, ms->numa_state, 1061 vms->oem_id, vms->oem_table_id); 1062 } 1063 } 1064 1065 if (vms->cxl_devices_state.is_enabled) { 1066 cxl_build_cedt(table_offsets, tables_blob, tables->linker, 1067 vms->oem_id, vms->oem_table_id, &vms->cxl_devices_state); 1068 } 1069 1070 if (ms->nvdimms_state->is_enabled) { 1071 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 1072 ms->nvdimms_state, ms->ram_slots, vms->oem_id, 1073 vms->oem_table_id); 1074 } 1075 1076 acpi_add_table(table_offsets, tables_blob); 1077 build_iort(tables_blob, tables->linker, vms); 1078 1079 #ifdef CONFIG_TPM 1080 if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) { 1081 acpi_add_table(table_offsets, tables_blob); 1082 build_tpm2(tables_blob, tables->linker, tables->tcpalog, vms->oem_id, 1083 vms->oem_table_id); 1084 } 1085 #endif 1086 1087 if (vms->iommu == VIRT_IOMMU_VIRTIO) { 1088 acpi_add_table(table_offsets, tables_blob); 1089 build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf, 1090 vms->oem_id, vms->oem_table_id); 1091 } 1092 1093 /* XSDT is pointed to by RSDP */ 1094 xsdt = tables_blob->len; 1095 build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id, 1096 vms->oem_table_id); 1097 1098 /* RSDP is in FSEG memory, so allocate it separately */ 1099 { 1100 AcpiRsdpData rsdp_data = { 1101 .revision = 2, 1102 .oem_id = vms->oem_id, 1103 .xsdt_tbl_offset = &xsdt, 1104 .rsdt_tbl_offset = NULL, 1105 }; 1106 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 1107 } 1108 1109 /* 1110 * The align size is 128, warn if 64k is not enough therefore 1111 * the align size could be resized. 1112 */ 1113 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 1114 warn_report("ACPI table size %u exceeds %d bytes," 1115 " migration may not work", 1116 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 1117 error_printf("Try removing CPUs, NUMA nodes, memory slots" 1118 " or PCI bridges.\n"); 1119 } 1120 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 1121 1122 1123 /* Cleanup memory that's no longer used. */ 1124 g_array_free(table_offsets, true); 1125 } 1126 1127 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 1128 { 1129 uint32_t size = acpi_data_len(data); 1130 1131 /* Make sure RAM size is correct - in case it got changed 1132 * e.g. by migration */ 1133 memory_region_ram_resize(mr, size, &error_abort); 1134 1135 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 1136 memory_region_set_dirty(mr, 0, size); 1137 } 1138 1139 static void virt_acpi_build_update(void *build_opaque) 1140 { 1141 AcpiBuildState *build_state = build_opaque; 1142 AcpiBuildTables tables; 1143 1144 /* No state to update or already patched? Nothing to do. */ 1145 if (!build_state || build_state->patched) { 1146 return; 1147 } 1148 build_state->patched = true; 1149 1150 acpi_build_tables_init(&tables); 1151 1152 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables); 1153 1154 acpi_ram_update(build_state->table_mr, tables.table_data); 1155 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 1156 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 1157 1158 acpi_build_tables_cleanup(&tables, true); 1159 } 1160 1161 static void virt_acpi_build_reset(void *build_opaque) 1162 { 1163 AcpiBuildState *build_state = build_opaque; 1164 build_state->patched = false; 1165 } 1166 1167 static const VMStateDescription vmstate_virt_acpi_build = { 1168 .name = "virt_acpi_build", 1169 .version_id = 1, 1170 .minimum_version_id = 1, 1171 .fields = (const VMStateField[]) { 1172 VMSTATE_BOOL(patched, AcpiBuildState), 1173 VMSTATE_END_OF_LIST() 1174 }, 1175 }; 1176 1177 void virt_acpi_setup(VirtMachineState *vms) 1178 { 1179 AcpiBuildTables tables; 1180 AcpiBuildState *build_state; 1181 AcpiGedState *acpi_ged_state; 1182 1183 if (!vms->fw_cfg) { 1184 trace_virt_acpi_setup(); 1185 return; 1186 } 1187 1188 if (!virt_is_acpi_enabled(vms)) { 1189 trace_virt_acpi_setup(); 1190 return; 1191 } 1192 1193 build_state = g_malloc0(sizeof *build_state); 1194 1195 acpi_build_tables_init(&tables); 1196 virt_acpi_build(vms, &tables); 1197 1198 /* Now expose it all to Guest */ 1199 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, 1200 build_state, tables.table_data, 1201 ACPI_BUILD_TABLE_FILE); 1202 assert(build_state->table_mr != NULL); 1203 1204 build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update, 1205 build_state, 1206 tables.linker->cmd_blob, 1207 ACPI_BUILD_LOADER_FILE); 1208 1209 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, 1210 acpi_data_len(tables.tcpalog)); 1211 1212 if (vms->ras) { 1213 assert(vms->acpi_dev); 1214 acpi_ged_state = ACPI_GED(vms->acpi_dev); 1215 acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state, 1216 vms->fw_cfg, tables.hardware_errors); 1217 } 1218 1219 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, 1220 build_state, tables.rsdp, 1221 ACPI_BUILD_RSDP_FILE); 1222 1223 qemu_register_reset(virt_acpi_build_reset, build_state); 1224 virt_acpi_build_reset(build_state); 1225 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 1226 1227 /* Cleanup tables but don't free the memory: we track it 1228 * in build_state. 1229 */ 1230 acpi_build_tables_cleanup(&tables, false); 1231 } 1232