1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * ARM virt ACPI generation 4 * 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 6 * Copyright (C) 2006 Fabrice Bellard 7 * Copyright (C) 2013 Red Hat Inc 8 * 9 * Author: Michael S. Tsirkin <mst@redhat.com> 10 * 11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 12 * 13 * Author: Shannon Zhao <zhaoshenglong@huawei.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "qapi/error.h" 31 #include "qemu/bitmap.h" 32 #include "trace.h" 33 #include "hw/core/cpu.h" 34 #include "target/arm/cpu.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/acpi/aml-build.h" 40 #include "hw/acpi/utils.h" 41 #include "hw/acpi/pci.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "hw/acpi/generic_event_device.h" 44 #include "hw/pci/pcie_host.h" 45 #include "hw/pci/pci.h" 46 #include "hw/arm/virt.h" 47 #include "hw/mem/nvdimm.h" 48 #include "sysemu/numa.h" 49 #include "sysemu/reset.h" 50 #include "kvm_arm.h" 51 #include "migration/vmstate.h" 52 #include "hw/acpi/ghes.h" 53 54 #define ARM_SPI_BASE 32 55 56 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) 57 { 58 uint16_t i; 59 60 for (i = 0; i < smp_cpus; i++) { 61 Aml *dev = aml_device("C%.03X", i); 62 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 63 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 64 aml_append(scope, dev); 65 } 66 } 67 68 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 69 uint32_t uart_irq) 70 { 71 Aml *dev = aml_device("COM0"); 72 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); 73 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 74 75 Aml *crs = aml_resource_template(); 76 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 77 uart_memmap->size, AML_READ_WRITE)); 78 aml_append(crs, 79 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 80 AML_EXCLUSIVE, &uart_irq, 1)); 81 aml_append(dev, aml_name_decl("_CRS", crs)); 82 83 aml_append(scope, dev); 84 } 85 86 static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) 87 { 88 Aml *dev = aml_device("FWCF"); 89 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 90 /* device present, functioning, decoding, not shown in UI */ 91 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 92 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 93 94 Aml *crs = aml_resource_template(); 95 aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, 96 fw_cfg_memmap->size, AML_READ_WRITE)); 97 aml_append(dev, aml_name_decl("_CRS", crs)); 98 aml_append(scope, dev); 99 } 100 101 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) 102 { 103 Aml *dev, *crs; 104 hwaddr base = flash_memmap->base; 105 hwaddr size = flash_memmap->size / 2; 106 107 dev = aml_device("FLS0"); 108 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 109 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 110 111 crs = aml_resource_template(); 112 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 113 aml_append(dev, aml_name_decl("_CRS", crs)); 114 aml_append(scope, dev); 115 116 dev = aml_device("FLS1"); 117 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 118 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 119 crs = aml_resource_template(); 120 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); 121 aml_append(dev, aml_name_decl("_CRS", crs)); 122 aml_append(scope, dev); 123 } 124 125 static void acpi_dsdt_add_virtio(Aml *scope, 126 const MemMapEntry *virtio_mmio_memmap, 127 uint32_t mmio_irq, int num) 128 { 129 hwaddr base = virtio_mmio_memmap->base; 130 hwaddr size = virtio_mmio_memmap->size; 131 int i; 132 133 for (i = 0; i < num; i++) { 134 uint32_t irq = mmio_irq + i; 135 Aml *dev = aml_device("VR%02u", i); 136 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); 137 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 138 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 139 140 Aml *crs = aml_resource_template(); 141 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 142 aml_append(crs, 143 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 144 AML_EXCLUSIVE, &irq, 1)); 145 aml_append(dev, aml_name_decl("_CRS", crs)); 146 aml_append(scope, dev); 147 base += size; 148 } 149 } 150 151 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, 152 uint32_t irq, bool use_highmem, bool highmem_ecam) 153 { 154 int ecam_id = VIRT_ECAM_ID(highmem_ecam); 155 Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; 156 int i, slot_no; 157 hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base; 158 hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size; 159 hwaddr base_pio = memmap[VIRT_PCIE_PIO].base; 160 hwaddr size_pio = memmap[VIRT_PCIE_PIO].size; 161 hwaddr base_ecam = memmap[ecam_id].base; 162 hwaddr size_ecam = memmap[ecam_id].size; 163 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 164 165 Aml *dev = aml_device("%s", "PCI0"); 166 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); 167 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); 168 aml_append(dev, aml_name_decl("_SEG", aml_int(0))); 169 aml_append(dev, aml_name_decl("_BBN", aml_int(0))); 170 aml_append(dev, aml_name_decl("_UID", aml_string("PCI0"))); 171 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); 172 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 173 174 /* Declare the PCI Routing Table. */ 175 Aml *rt_pkg = aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS); 176 for (slot_no = 0; slot_no < PCI_SLOT_MAX; slot_no++) { 177 for (i = 0; i < PCI_NUM_PINS; i++) { 178 int gsi = (i + slot_no) % PCI_NUM_PINS; 179 Aml *pkg = aml_package(4); 180 aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF)); 181 aml_append(pkg, aml_int(i)); 182 aml_append(pkg, aml_name("GSI%d", gsi)); 183 aml_append(pkg, aml_int(0)); 184 aml_append(rt_pkg, pkg); 185 } 186 } 187 aml_append(dev, aml_name_decl("_PRT", rt_pkg)); 188 189 /* Create GSI link device */ 190 for (i = 0; i < PCI_NUM_PINS; i++) { 191 uint32_t irqs = irq + i; 192 Aml *dev_gsi = aml_device("GSI%d", i); 193 aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); 194 aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i))); 195 crs = aml_resource_template(); 196 aml_append(crs, 197 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 198 AML_EXCLUSIVE, &irqs, 1)); 199 aml_append(dev_gsi, aml_name_decl("_PRS", crs)); 200 crs = aml_resource_template(); 201 aml_append(crs, 202 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 203 AML_EXCLUSIVE, &irqs, 1)); 204 aml_append(dev_gsi, aml_name_decl("_CRS", crs)); 205 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 206 aml_append(dev_gsi, method); 207 aml_append(dev, dev_gsi); 208 } 209 210 method = aml_method("_CBA", 0, AML_NOTSERIALIZED); 211 aml_append(method, aml_return(aml_int(base_ecam))); 212 aml_append(dev, method); 213 214 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 215 Aml *rbuf = aml_resource_template(); 216 aml_append(rbuf, 217 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 218 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, 219 nr_pcie_buses)); 220 aml_append(rbuf, 221 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 222 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio, 223 base_mmio + size_mmio - 1, 0x0000, size_mmio)); 224 aml_append(rbuf, 225 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 226 AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio, 227 size_pio)); 228 229 if (use_highmem) { 230 hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base; 231 hwaddr size_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].size; 232 233 aml_append(rbuf, 234 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 235 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, 236 base_mmio_high, 237 base_mmio_high + size_mmio_high - 1, 0x0000, 238 size_mmio_high)); 239 } 240 241 aml_append(method, aml_return(rbuf)); 242 aml_append(dev, method); 243 244 /* Declare an _OSC (OS Control Handoff) method */ 245 aml_append(dev, aml_name_decl("SUPP", aml_int(0))); 246 aml_append(dev, aml_name_decl("CTRL", aml_int(0))); 247 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 248 aml_append(method, 249 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 250 251 /* PCI Firmware Specification 3.0 252 * 4.5.1. _OSC Interface for PCI Host Bridge Devices 253 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is 254 * identified by the Universal Unique IDentifier (UUID) 255 * 33DB4D5B-1FF7-401C-9657-7441C03DD766 256 */ 257 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"); 258 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 259 aml_append(ifctx, 260 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 261 aml_append(ifctx, 262 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 263 aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); 264 aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); 265 266 /* 267 * Allow OS control for all 5 features: 268 * PCIeHotplug SHPCHotplug PME AER PCIeCapability. 269 */ 270 aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F), 271 aml_name("CTRL"))); 272 273 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); 274 aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08), 275 aml_name("CDW1"))); 276 aml_append(ifctx, ifctx1); 277 278 ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL")))); 279 aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10), 280 aml_name("CDW1"))); 281 aml_append(ifctx, ifctx1); 282 283 aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3"))); 284 aml_append(ifctx, aml_return(aml_arg(3))); 285 aml_append(method, ifctx); 286 287 elsectx = aml_else(); 288 aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4), 289 aml_name("CDW1"))); 290 aml_append(elsectx, aml_return(aml_arg(3))); 291 aml_append(method, elsectx); 292 aml_append(dev, method); 293 294 method = aml_method("_DSM", 4, AML_NOTSERIALIZED); 295 296 /* PCI Firmware Specification 3.0 297 * 4.6.1. _DSM for PCI Express Slot Information 298 * The UUID in _DSM in this context is 299 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} 300 */ 301 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 302 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 303 ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0))); 304 uint8_t byte_list[1] = {1}; 305 buf = aml_buffer(1, byte_list); 306 aml_append(ifctx1, aml_return(buf)); 307 aml_append(ifctx, ifctx1); 308 aml_append(method, ifctx); 309 310 byte_list[0] = 0; 311 buf = aml_buffer(1, byte_list); 312 aml_append(method, aml_return(buf)); 313 aml_append(dev, method); 314 315 Aml *dev_res0 = aml_device("%s", "RES0"); 316 aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); 317 crs = aml_resource_template(); 318 aml_append(crs, 319 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 320 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_ecam, 321 base_ecam + size_ecam - 1, 0x0000, size_ecam)); 322 aml_append(dev_res0, aml_name_decl("_CRS", crs)); 323 aml_append(dev, dev_res0); 324 aml_append(scope, dev); 325 } 326 327 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, 328 uint32_t gpio_irq) 329 { 330 Aml *dev = aml_device("GPO0"); 331 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); 332 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 333 334 Aml *crs = aml_resource_template(); 335 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, 336 AML_READ_WRITE)); 337 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 338 AML_EXCLUSIVE, &gpio_irq, 1)); 339 aml_append(dev, aml_name_decl("_CRS", crs)); 340 341 Aml *aei = aml_resource_template(); 342 /* Pin 3 for power button */ 343 const uint32_t pin_list[1] = {3}; 344 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, 345 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, 346 "GPO0", NULL, 0)); 347 aml_append(dev, aml_name_decl("_AEI", aei)); 348 349 /* _E03 is handle for power button */ 350 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); 351 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), 352 aml_int(0x80))); 353 aml_append(dev, method); 354 aml_append(scope, dev); 355 } 356 357 static void acpi_dsdt_add_power_button(Aml *scope) 358 { 359 Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE); 360 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C"))); 361 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 362 aml_append(scope, dev); 363 } 364 365 static void 366 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 367 { 368 int nb_nodes, iort_start = table_data->len; 369 AcpiIortIdMapping *idmap; 370 AcpiIortItsGroup *its; 371 AcpiIortTable *iort; 372 AcpiIortSmmu3 *smmu; 373 size_t node_size, iort_node_offset, iort_length, smmu_offset = 0; 374 AcpiIortRC *rc; 375 376 iort = acpi_data_push(table_data, sizeof(*iort)); 377 378 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 379 nb_nodes = 3; /* RC, ITS, SMMUv3 */ 380 } else { 381 nb_nodes = 2; /* RC, ITS */ 382 } 383 384 iort_length = sizeof(*iort); 385 iort->node_count = cpu_to_le32(nb_nodes); 386 /* 387 * Use a copy in case table_data->data moves during acpi_data_push 388 * operations. 389 */ 390 iort_node_offset = sizeof(*iort); 391 iort->node_offset = cpu_to_le32(iort_node_offset); 392 393 /* ITS group node */ 394 node_size = sizeof(*its) + sizeof(uint32_t); 395 iort_length += node_size; 396 its = acpi_data_push(table_data, node_size); 397 398 its->type = ACPI_IORT_NODE_ITS_GROUP; 399 its->length = cpu_to_le16(node_size); 400 its->its_count = cpu_to_le32(1); 401 its->identifiers[0] = 0; /* MADT translation_id */ 402 403 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 404 int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; 405 406 /* SMMUv3 node */ 407 smmu_offset = iort_node_offset + node_size; 408 node_size = sizeof(*smmu) + sizeof(*idmap); 409 iort_length += node_size; 410 smmu = acpi_data_push(table_data, node_size); 411 412 smmu->type = ACPI_IORT_NODE_SMMU_V3; 413 smmu->length = cpu_to_le16(node_size); 414 smmu->mapping_count = cpu_to_le32(1); 415 smmu->mapping_offset = cpu_to_le32(sizeof(*smmu)); 416 smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base); 417 smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE); 418 smmu->event_gsiv = cpu_to_le32(irq); 419 smmu->pri_gsiv = cpu_to_le32(irq + 1); 420 smmu->gerr_gsiv = cpu_to_le32(irq + 2); 421 smmu->sync_gsiv = cpu_to_le32(irq + 3); 422 423 /* Identity RID mapping covering the whole input RID range */ 424 idmap = &smmu->id_mapping_array[0]; 425 idmap->input_base = 0; 426 idmap->id_count = cpu_to_le32(0xFFFF); 427 idmap->output_base = 0; 428 /* output IORT node is the ITS group node (the first node) */ 429 idmap->output_reference = cpu_to_le32(iort_node_offset); 430 } 431 432 /* Root Complex Node */ 433 node_size = sizeof(*rc) + sizeof(*idmap); 434 iort_length += node_size; 435 rc = acpi_data_push(table_data, node_size); 436 437 rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX; 438 rc->length = cpu_to_le16(node_size); 439 rc->mapping_count = cpu_to_le32(1); 440 rc->mapping_offset = cpu_to_le32(sizeof(*rc)); 441 442 /* fully coherent device */ 443 rc->memory_properties.cache_coherency = cpu_to_le32(1); 444 rc->memory_properties.memory_flags = 0x3; /* CCA = CPM = DCAS = 1 */ 445 rc->pci_segment_number = 0; /* MCFG pci_segment */ 446 447 /* Identity RID mapping covering the whole input RID range */ 448 idmap = &rc->id_mapping_array[0]; 449 idmap->input_base = 0; 450 idmap->id_count = cpu_to_le32(0xFFFF); 451 idmap->output_base = 0; 452 453 if (vms->iommu == VIRT_IOMMU_SMMUV3) { 454 /* output IORT node is the smmuv3 node */ 455 idmap->output_reference = cpu_to_le32(smmu_offset); 456 } else { 457 /* output IORT node is the ITS group node (the first node) */ 458 idmap->output_reference = cpu_to_le32(iort_node_offset); 459 } 460 461 /* 462 * Update the pointer address in case table_data->data moves during above 463 * acpi_data_push operations. 464 */ 465 iort = (AcpiIortTable *)(table_data->data + iort_start); 466 iort->length = cpu_to_le32(iort_length); 467 468 build_header(linker, table_data, (void *)(table_data->data + iort_start), 469 "IORT", table_data->len - iort_start, 0, NULL, NULL); 470 } 471 472 static void 473 build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 474 { 475 AcpiSerialPortConsoleRedirection *spcr; 476 const MemMapEntry *uart_memmap = &vms->memmap[VIRT_UART]; 477 int irq = vms->irqmap[VIRT_UART] + ARM_SPI_BASE; 478 int spcr_start = table_data->len; 479 480 spcr = acpi_data_push(table_data, sizeof(*spcr)); 481 482 spcr->interface_type = 0x3; /* ARM PL011 UART */ 483 484 spcr->base_address.space_id = AML_SYSTEM_MEMORY; 485 spcr->base_address.bit_width = 8; 486 spcr->base_address.bit_offset = 0; 487 spcr->base_address.access_width = 1; 488 spcr->base_address.address = cpu_to_le64(uart_memmap->base); 489 490 spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */ 491 spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */ 492 493 spcr->baud = 3; /* Baud Rate: 3 = 9600 */ 494 spcr->parity = 0; /* No Parity */ 495 spcr->stopbits = 1; /* 1 Stop bit */ 496 spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */ 497 spcr->term_type = 0; /* Terminal Type: 0 = VT100 */ 498 499 spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */ 500 spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */ 501 502 build_header(linker, table_data, (void *)(table_data->data + spcr_start), 503 "SPCR", table_data->len - spcr_start, 2, NULL, NULL); 504 } 505 506 static void 507 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 508 { 509 AcpiSystemResourceAffinityTable *srat; 510 AcpiSratProcessorGiccAffinity *core; 511 AcpiSratMemoryAffinity *numamem; 512 int i, srat_start; 513 uint64_t mem_base; 514 MachineClass *mc = MACHINE_GET_CLASS(vms); 515 MachineState *ms = MACHINE(vms); 516 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); 517 518 srat_start = table_data->len; 519 srat = acpi_data_push(table_data, sizeof(*srat)); 520 srat->reserved1 = cpu_to_le32(1); 521 522 for (i = 0; i < cpu_list->len; ++i) { 523 core = acpi_data_push(table_data, sizeof(*core)); 524 core->type = ACPI_SRAT_PROCESSOR_GICC; 525 core->length = sizeof(*core); 526 core->proximity = cpu_to_le32(cpu_list->cpus[i].props.node_id); 527 core->acpi_processor_uid = cpu_to_le32(i); 528 core->flags = cpu_to_le32(1); 529 } 530 531 mem_base = vms->memmap[VIRT_MEM].base; 532 for (i = 0; i < ms->numa_state->num_nodes; ++i) { 533 if (ms->numa_state->nodes[i].node_mem > 0) { 534 numamem = acpi_data_push(table_data, sizeof(*numamem)); 535 build_srat_memory(numamem, mem_base, 536 ms->numa_state->nodes[i].node_mem, i, 537 MEM_AFFINITY_ENABLED); 538 mem_base += ms->numa_state->nodes[i].node_mem; 539 } 540 } 541 542 if (ms->device_memory) { 543 numamem = acpi_data_push(table_data, sizeof *numamem); 544 build_srat_memory(numamem, ms->device_memory->base, 545 memory_region_size(&ms->device_memory->mr), 546 ms->numa_state->num_nodes - 1, 547 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 548 } 549 550 build_header(linker, table_data, (void *)(table_data->data + srat_start), 551 "SRAT", table_data->len - srat_start, 3, NULL, NULL); 552 } 553 554 /* GTDT */ 555 static void 556 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 557 { 558 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 559 int gtdt_start = table_data->len; 560 AcpiGenericTimerTable *gtdt; 561 uint32_t irqflags; 562 563 if (vmc->claim_edge_triggered_timers) { 564 irqflags = ACPI_GTDT_INTERRUPT_MODE_EDGE; 565 } else { 566 irqflags = ACPI_GTDT_INTERRUPT_MODE_LEVEL; 567 } 568 569 gtdt = acpi_data_push(table_data, sizeof *gtdt); 570 /* The interrupt values are the same with the device tree when adding 16 */ 571 gtdt->secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_S_EL1_IRQ + 16); 572 gtdt->secure_el1_flags = cpu_to_le32(irqflags); 573 574 gtdt->non_secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ + 16); 575 gtdt->non_secure_el1_flags = cpu_to_le32(irqflags | 576 ACPI_GTDT_CAP_ALWAYS_ON); 577 578 gtdt->virtual_timer_interrupt = cpu_to_le32(ARCH_TIMER_VIRT_IRQ + 16); 579 gtdt->virtual_timer_flags = cpu_to_le32(irqflags); 580 581 gtdt->non_secure_el2_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ + 16); 582 gtdt->non_secure_el2_flags = cpu_to_le32(irqflags); 583 584 build_header(linker, table_data, 585 (void *)(table_data->data + gtdt_start), "GTDT", 586 table_data->len - gtdt_start, 2, NULL, NULL); 587 } 588 589 /* MADT */ 590 static void 591 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 592 { 593 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 594 int madt_start = table_data->len; 595 const MemMapEntry *memmap = vms->memmap; 596 const int *irqmap = vms->irqmap; 597 AcpiMultipleApicTable *madt; 598 AcpiMadtGenericDistributor *gicd; 599 AcpiMadtGenericMsiFrame *gic_msi; 600 int i; 601 602 madt = acpi_data_push(table_data, sizeof *madt); 603 604 gicd = acpi_data_push(table_data, sizeof *gicd); 605 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR; 606 gicd->length = sizeof(*gicd); 607 gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base); 608 gicd->version = vms->gic_version; 609 610 for (i = 0; i < vms->smp_cpus; i++) { 611 AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data, 612 sizeof(*gicc)); 613 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 614 615 gicc->type = ACPI_APIC_GENERIC_CPU_INTERFACE; 616 gicc->length = sizeof(*gicc); 617 if (vms->gic_version == 2) { 618 gicc->base_address = cpu_to_le64(memmap[VIRT_GIC_CPU].base); 619 gicc->gich_base_address = cpu_to_le64(memmap[VIRT_GIC_HYP].base); 620 gicc->gicv_base_address = cpu_to_le64(memmap[VIRT_GIC_VCPU].base); 621 } 622 gicc->cpu_interface_number = cpu_to_le32(i); 623 gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity); 624 gicc->uid = cpu_to_le32(i); 625 gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED); 626 627 if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 628 gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ)); 629 } 630 if (vms->virt) { 631 gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ)); 632 } 633 } 634 635 if (vms->gic_version == 3) { 636 AcpiMadtGenericTranslator *gic_its; 637 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 638 AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data, 639 sizeof *gicr); 640 641 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 642 gicr->length = sizeof(*gicr); 643 gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base); 644 gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size); 645 646 if (nb_redist_regions == 2) { 647 gicr = acpi_data_push(table_data, sizeof(*gicr)); 648 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; 649 gicr->length = sizeof(*gicr); 650 gicr->base_address = 651 cpu_to_le64(memmap[VIRT_HIGH_GIC_REDIST2].base); 652 gicr->range_length = 653 cpu_to_le32(memmap[VIRT_HIGH_GIC_REDIST2].size); 654 } 655 656 if (its_class_name() && !vmc->no_its) { 657 gic_its = acpi_data_push(table_data, sizeof *gic_its); 658 gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR; 659 gic_its->length = sizeof(*gic_its); 660 gic_its->translation_id = 0; 661 gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base); 662 } 663 } else { 664 gic_msi = acpi_data_push(table_data, sizeof *gic_msi); 665 gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME; 666 gic_msi->length = sizeof(*gic_msi); 667 gic_msi->gic_msi_frame_id = 0; 668 gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base); 669 gic_msi->flags = cpu_to_le32(1); 670 gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS); 671 gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE); 672 } 673 674 build_header(linker, table_data, 675 (void *)(table_data->data + madt_start), "APIC", 676 table_data->len - madt_start, 3, NULL, NULL); 677 } 678 679 /* FADT */ 680 static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker, 681 VirtMachineState *vms, unsigned dsdt_tbl_offset) 682 { 683 /* ACPI v5.1 */ 684 AcpiFadtData fadt = { 685 .rev = 5, 686 .minor_ver = 1, 687 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, 688 .xdsdt_tbl_offset = &dsdt_tbl_offset, 689 }; 690 691 switch (vms->psci_conduit) { 692 case QEMU_PSCI_CONDUIT_DISABLED: 693 fadt.arm_boot_arch = 0; 694 break; 695 case QEMU_PSCI_CONDUIT_HVC: 696 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT | 697 ACPI_FADT_ARM_PSCI_USE_HVC; 698 break; 699 case QEMU_PSCI_CONDUIT_SMC: 700 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT; 701 break; 702 default: 703 g_assert_not_reached(); 704 } 705 706 build_fadt(table_data, linker, &fadt, NULL, NULL); 707 } 708 709 /* DSDT */ 710 static void 711 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 712 { 713 Aml *scope, *dsdt; 714 MachineState *ms = MACHINE(vms); 715 const MemMapEntry *memmap = vms->memmap; 716 const int *irqmap = vms->irqmap; 717 718 dsdt = init_aml_allocator(); 719 /* Reserve space for header */ 720 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 721 722 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. 723 * While UEFI can use libfdt to disable the RTC device node in the DTB that 724 * it passes to the OS, it cannot modify AML. Therefore, we won't generate 725 * the RTC ACPI device at all when using UEFI. 726 */ 727 scope = aml_scope("\\_SB"); 728 acpi_dsdt_add_cpus(scope, vms->smp_cpus); 729 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], 730 (irqmap[VIRT_UART] + ARM_SPI_BASE)); 731 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); 732 acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); 733 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], 734 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); 735 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), 736 vms->highmem, vms->highmem_ecam); 737 if (vms->acpi_dev) { 738 build_ged_aml(scope, "\\_SB."GED_DEVICE, 739 HOTPLUG_HANDLER(vms->acpi_dev), 740 irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY, 741 memmap[VIRT_ACPI_GED].base); 742 } else { 743 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], 744 (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); 745 } 746 747 if (vms->acpi_dev) { 748 uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev), 749 "ged-event", &error_abort); 750 751 if (event & ACPI_GED_MEM_HOTPLUG_EVT) { 752 build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL, 753 AML_SYSTEM_MEMORY, 754 memmap[VIRT_PCDIMM_ACPI].base); 755 } 756 } 757 758 acpi_dsdt_add_power_button(scope); 759 760 aml_append(dsdt, scope); 761 762 /* copy AML table into ACPI tables blob and patch header there */ 763 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 764 build_header(linker, table_data, 765 (void *)(table_data->data + table_data->len - dsdt->buf->len), 766 "DSDT", dsdt->buf->len, 2, NULL, NULL); 767 free_aml_allocator(); 768 } 769 770 typedef 771 struct AcpiBuildState { 772 /* Copy of table in RAM (for patching). */ 773 MemoryRegion *table_mr; 774 MemoryRegion *rsdp_mr; 775 MemoryRegion *linker_mr; 776 /* Is table patched? */ 777 bool patched; 778 } AcpiBuildState; 779 780 static 781 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) 782 { 783 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 784 GArray *table_offsets; 785 unsigned dsdt, xsdt; 786 GArray *tables_blob = tables->table_data; 787 MachineState *ms = MACHINE(vms); 788 789 table_offsets = g_array_new(false, true /* clear */, 790 sizeof(uint32_t)); 791 792 bios_linker_loader_alloc(tables->linker, 793 ACPI_BUILD_TABLE_FILE, tables_blob, 794 64, false /* high memory */); 795 796 /* DSDT is pointed to by FADT */ 797 dsdt = tables_blob->len; 798 build_dsdt(tables_blob, tables->linker, vms); 799 800 /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */ 801 acpi_add_table(table_offsets, tables_blob); 802 build_fadt_rev5(tables_blob, tables->linker, vms, dsdt); 803 804 acpi_add_table(table_offsets, tables_blob); 805 build_madt(tables_blob, tables->linker, vms); 806 807 acpi_add_table(table_offsets, tables_blob); 808 build_gtdt(tables_blob, tables->linker, vms); 809 810 acpi_add_table(table_offsets, tables_blob); 811 { 812 AcpiMcfgInfo mcfg = { 813 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, 814 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, 815 }; 816 build_mcfg(tables_blob, tables->linker, &mcfg); 817 } 818 819 acpi_add_table(table_offsets, tables_blob); 820 build_spcr(tables_blob, tables->linker, vms); 821 822 if (vms->ras) { 823 build_ghes_error_table(tables->hardware_errors, tables->linker); 824 acpi_add_table(table_offsets, tables_blob); 825 acpi_build_hest(tables_blob, tables->linker); 826 } 827 828 if (ms->numa_state->num_nodes > 0) { 829 acpi_add_table(table_offsets, tables_blob); 830 build_srat(tables_blob, tables->linker, vms); 831 if (ms->numa_state->have_numa_distance) { 832 acpi_add_table(table_offsets, tables_blob); 833 build_slit(tables_blob, tables->linker, ms); 834 } 835 } 836 837 if (ms->nvdimms_state->is_enabled) { 838 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 839 ms->nvdimms_state, ms->ram_slots); 840 } 841 842 if (its_class_name() && !vmc->no_its) { 843 acpi_add_table(table_offsets, tables_blob); 844 build_iort(tables_blob, tables->linker, vms); 845 } 846 847 /* XSDT is pointed to by RSDP */ 848 xsdt = tables_blob->len; 849 build_xsdt(tables_blob, tables->linker, table_offsets, NULL, NULL); 850 851 /* RSDP is in FSEG memory, so allocate it separately */ 852 { 853 AcpiRsdpData rsdp_data = { 854 .revision = 2, 855 .oem_id = ACPI_BUILD_APPNAME6, 856 .xsdt_tbl_offset = &xsdt, 857 .rsdt_tbl_offset = NULL, 858 }; 859 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 860 } 861 862 /* Cleanup memory that's no longer used. */ 863 g_array_free(table_offsets, true); 864 } 865 866 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 867 { 868 uint32_t size = acpi_data_len(data); 869 870 /* Make sure RAM size is correct - in case it got changed 871 * e.g. by migration */ 872 memory_region_ram_resize(mr, size, &error_abort); 873 874 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 875 memory_region_set_dirty(mr, 0, size); 876 } 877 878 static void virt_acpi_build_update(void *build_opaque) 879 { 880 AcpiBuildState *build_state = build_opaque; 881 AcpiBuildTables tables; 882 883 /* No state to update or already patched? Nothing to do. */ 884 if (!build_state || build_state->patched) { 885 return; 886 } 887 build_state->patched = true; 888 889 acpi_build_tables_init(&tables); 890 891 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables); 892 893 acpi_ram_update(build_state->table_mr, tables.table_data); 894 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 895 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 896 897 acpi_build_tables_cleanup(&tables, true); 898 } 899 900 static void virt_acpi_build_reset(void *build_opaque) 901 { 902 AcpiBuildState *build_state = build_opaque; 903 build_state->patched = false; 904 } 905 906 static const VMStateDescription vmstate_virt_acpi_build = { 907 .name = "virt_acpi_build", 908 .version_id = 1, 909 .minimum_version_id = 1, 910 .fields = (VMStateField[]) { 911 VMSTATE_BOOL(patched, AcpiBuildState), 912 VMSTATE_END_OF_LIST() 913 }, 914 }; 915 916 void virt_acpi_setup(VirtMachineState *vms) 917 { 918 AcpiBuildTables tables; 919 AcpiBuildState *build_state; 920 AcpiGedState *acpi_ged_state; 921 922 if (!vms->fw_cfg) { 923 trace_virt_acpi_setup(); 924 return; 925 } 926 927 if (!virt_is_acpi_enabled(vms)) { 928 trace_virt_acpi_setup(); 929 return; 930 } 931 932 build_state = g_malloc0(sizeof *build_state); 933 934 acpi_build_tables_init(&tables); 935 virt_acpi_build(vms, &tables); 936 937 /* Now expose it all to Guest */ 938 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, 939 build_state, tables.table_data, 940 ACPI_BUILD_TABLE_FILE, 941 ACPI_BUILD_TABLE_MAX_SIZE); 942 assert(build_state->table_mr != NULL); 943 944 build_state->linker_mr = 945 acpi_add_rom_blob(virt_acpi_build_update, build_state, 946 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0); 947 948 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, 949 acpi_data_len(tables.tcpalog)); 950 951 if (vms->ras) { 952 assert(vms->acpi_dev); 953 acpi_ged_state = ACPI_GED(vms->acpi_dev); 954 acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state, 955 vms->fw_cfg, tables.hardware_errors); 956 } 957 958 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, 959 build_state, tables.rsdp, 960 ACPI_BUILD_RSDP_FILE, 0); 961 962 qemu_register_reset(virt_acpi_build_reset, build_state); 963 virt_acpi_build_reset(build_state); 964 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 965 966 /* Cleanup tables but don't free the memory: we track it 967 * in build_state. 968 */ 969 acpi_build_tables_cleanup(&tables, false); 970 } 971